Nitride semiconductor device

Abstract

This nitride semiconductor device (1) comprises: a substrate (10); a first nitride semiconductor layer (20) provided above the substrate (10); and a second nitride semiconductor layer (40) provided so as to cover a groove provided in the first nitride semiconductor layer (20). When a portion (P1a or P1b) in which the groove extends in a first direction parallel to an off-direction of the substrate (10) is defined as a first portion, and a portion (P2a or P2b) in which the groove extends in a second direction perpendicular to the off-direction of the substrate (10) is defined as a second portion, the cross-sectional area of the groove at the second portion orthogonal to the first direction is smaller than the cross-sectional area of the groove at the first portion orthogonal to the second direction.

Description

nitride semiconductor devices

[0001] The present disclosure relates to nitride semiconductor devices.

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-gap semiconductors with a large band gap, and are characterized by a large dielectric breakdown field and a higher saturated drift velocity of electrons than GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors, etc. For this reason, research and development is being conducted on power transistors using nitride semiconductors, which are advantageous for achieving high output and high breakdown voltage.

[0003] For example, Patent Document 1 discloses a semiconductor device formed on a GaN-based stack. The semiconductor device described in Patent Document 1 is a vertical field effect transistor (FET) including a regrowth layer made of an electron transit layer and an electron supply layer positioned so as to cover an opening formed in the GaN-based stack, and a gate electrode positioned on and along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer, resulting in a FET with high mobility and low on-resistance.

[0004] Patent No. 7017579

[0005] In a field effect transistor having a trench such as a gate opening, when regrowth is performed to fill the trench, abnormal growth may occur along the off-direction of the substrate.

[0006] Therefore, the present disclosure provides a nitride semiconductor device in which abnormal growth is suppressed.

[0007] A nitride semiconductor device according to one aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer provided above the substrate, and a second nitride semiconductor layer provided so as to cover a groove provided in the first nitride semiconductor layer, wherein a first portion is a portion where the groove extends in a first direction parallel to an off-direction of the substrate, and a second portion is a portion where the groove extends in a second direction perpendicular to the off-direction of the substrate, and a cross-sectional area of ​​the groove in the second portion, perpendicular to the first direction, is smaller than a cross-sectional area of ​​the groove in the first portion, perpendicular to the second direction.

[0008] According to the present disclosure, it is possible to provide a nitride semiconductor device in which abnormal growth is suppressed.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment. FIG. 2 is a plan view showing a planar layout of the nitride semiconductor device according to the embodiment. FIG. 3 is a plan view for explaining abnormal growth occurring due to an off-angle of the substrate in a nitride semiconductor device according to a comparative example. FIG. 4 is an enlarged plan view showing the shape of a gate opening in region IV of FIG. 2. FIG. 5 is a plan view showing the planar layout of a nitride semiconductor device according to a modification of the embodiment. FIG. 6 is an enlarged plan view showing the shape of a gate opening in region VI of FIG. 5. FIG. 7A is a cross-sectional view showing a nitride semiconductor lamination step in a method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 7B is a cross-sectional view showing a resist patterning step in the method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 7C is a cross-sectional view showing a gate opening formation step in the method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 7D is a cross-sectional view showing a nitride semiconductor regrowth step in the method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 7E is a cross-sectional view showing a gate electrode formation step in the method for manufacturing a nitride semiconductor device according to an embodiment. FIG. 7F is a cross-sectional view showing a source electrode formation step in the method for manufacturing a nitride semiconductor device according to an embodiment.

[0010] (Summary of the Present Disclosure) The present inventors have found that the following problems occur with the conventional semiconductor devices described in the "Background Art" section.

[0011] In conventional semiconductor devices, the substrate has an off-axis angle. The off-axis angle is the angle between the main surface of the substrate and a crystal plane (specifically, the c-plane). In conventional semiconductor devices, an abnormal growth region due to the off-axis angle of the substrate was observed in the region adjacent to the gate opening. Specifically, abnormal growth occurred in the semiconductor layer provided to cover the gate opening, resulting in a thin region on the downstream side of the off-axis direction of the substrate.

[0012] Therefore, an object of the present disclosure is to provide a nitride semiconductor device in which abnormal growth is suppressed.

[0013] A nitride semiconductor device according to a first aspect of the present disclosure comprises a substrate, a first nitride semiconductor layer provided above the substrate, and a second nitride semiconductor layer provided so as to cover a groove provided in the first nitride semiconductor layer, wherein a first portion is a portion where the groove extends in a first direction parallel to an off-direction of the substrate, and a second portion is a portion where the groove extends in a second direction perpendicular to the off-direction of the substrate, and a cross-sectional area of ​​the groove in the second portion, perpendicular to the first direction, is smaller than a cross-sectional area of ​​the groove in the first portion, perpendicular to the second direction.

[0014] This allows the grooves to be filled more quickly during regrowth, thereby suppressing abnormal growth.

[0015] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect, wherein the width of the groove in the second portion is narrower than the width of the groove in the first portion.

[0016] The width of the trench can be easily and precisely adjusted, for example, by changing the shape of the etching mask used to form the trench. This makes it easier to fill the trench during regrowth as expected, thereby improving the effect of suppressing abnormal growth.

[0017] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first or second aspect, wherein the groove is an annular groove.

[0018] Therefore, if a groove has an end portion, abnormal growth is likely to occur at the end portion, but since an annular groove does not have an end portion, abnormal growth can be suppressed.

[0019] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects, wherein the first nitride semiconductor layer includes a third nitride semiconductor layer of a first conductivity type, and a fourth nitride semiconductor layer of a second conductivity type opposite to the first conductivity type, provided above the third nitride semiconductor layer.

[0020] As a result, a depletion layer can be formed near the interface by the pn junction between the third nitride semiconductor layer and the fourth nitride semiconductor layer. For example, when the nitride semiconductor device functions as a device that passes current in the vertical direction of the substrate, the depletion layer can suppress leakage current, thereby increasing the breakdown voltage of the device.

[0021] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to the fourth aspect, comprising: a gate electrode provided above the second nitride semiconductor layer so as to overlap the first portion in a planar view of the substrate; a source electrode provided above the substrate and spaced apart from the gate electrode; and a drain electrode provided below the substrate, wherein the trench penetrates the fourth nitride semiconductor layer, and the second nitride semiconductor layer is in contact with the third nitride semiconductor layer at the bottom of the trench.

[0022] This makes it possible to realize a vertical FET. A vertical FET is an FET in which the direction of drain current flow is mainly perpendicular to the main surface of the substrate. Furthermore, since a depletion layer can be formed near the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer, it is possible to suppress the occurrence of leakage current between the source electrode and the drain electrode. Therefore, a vertical FET with a high breakdown voltage can be realized.

[0023] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to the fifth aspect, wherein the source electrode is in contact with the third nitride semiconductor layer at the bottom of an opening that penetrates the second nitride semiconductor layer.

[0024] This allows a source potential to be supplied to the third nitride semiconductor layer. The stabilization of the potential of the third nitride semiconductor layer can improve the off-state characteristics of the vertical FET. For example, a depletion layer can be formed near the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer by applying a voltage between the source electrode and the drain electrode. The formation of the depletion layer can suppress the occurrence of leakage current between the source and drain, thereby increasing the breakdown voltage of the nitride semiconductor device.

[0025] A nitride semiconductor device according to a seventh aspect of the present disclosure is the nitride semiconductor device according to the fifth or sixth aspect, wherein the source electrode has an elongated shape in the first direction when viewed in a plan view of the substrate.

[0026] This reduces wasted space in the planar layout, thereby enabling the nitride semiconductor device to be miniaturized.

[0027] A nitride semiconductor device according to an eighth aspect of the present disclosure is the nitride semiconductor device according to the seventh aspect, wherein the groove includes two straight portions extending along the first direction with the source electrode sandwiched therebetween, a first connection portion connecting first ends of each of the two straight portions in the first direction in an arch shape, and a second connection portion connecting second ends of each of the two straight portions opposite the first ends in an arch shape, wherein the first portion is included in each of the two straight portions and the second portion is included in each of the first connection portion and the second connection portion.

[0028] As a result, both ends of the two straight portions are connected by the first connecting portion and the second connecting portion, respectively, to form an annular groove. Eliminating the end of the groove makes it possible to suppress abnormal growth and thereby reduce leakage current. Note that, when the groove outline is polygonal in plan view, its apex becomes a singular point, making abnormal growth more likely to occur. In the nitride semiconductor device according to this aspect, the occurrence of singular points for abnormal growth can be suppressed by curving each of the first connecting portion and the second connecting portion in an arch shape.

[0029] A nitride semiconductor device according to a ninth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, wherein the width of the first connection portion monotonically increases from the second portion included in the first connection portion to the first end, and the width of the second connection portion monotonically increases from the second portion included in the second connection portion to the second end.

[0030] This makes it possible to suppress abrupt changes in the width of the groove, and to suppress the occurrence of singular points of abnormal growth.

[0031] A nitride semiconductor device according to a tenth aspect of the present disclosure is the nitride semiconductor device according to the eighth aspect, wherein the first connecting portion and the second connecting portion both have a uniform width.

[0032] This allows the width of each of the first connecting portion and the second connecting portion to be uniformly reduced over the entire area, thereby reducing the abnormal growth region.

[0033] A nitride semiconductor device according to an eleventh aspect of the present disclosure is a nitride semiconductor device according to any one of the eighth to tenth aspects, wherein the first portion is a portion where a first virtual line passing through the center of the source electrode in a planar view of the substrate and extending in the second direction intersects with the groove, and the second portion is a portion where a second virtual line passing through the center of the source electrode in a planar view of the substrate and extending in the first direction intersects with the groove.

[0034] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to any one of the eighth to eleventh aspects, comprising three or more source electrodes, two or more grooves arranged side by side in the second direction, the three or more source electrodes arranged side by side in the second direction, and the source electrodes arranged between adjacent grooves.

[0035] This allows the distance between adjacent source and gate electrodes to be easily shortened, and multiple channels with short channel lengths can be provided within the plane, thereby achieving high output power for the nitride semiconductor device.

[0036] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to twelfth aspects, wherein the second nitride semiconductor layer includes a stacked structure of a GaN layer and an AlGaN layer.

[0037] This allows the two-dimensional electron gas generated in the vicinity of the heterointerface between the AlGaN layer and the GaN layer to be used as a current path, thereby realizing a low resistance current path.

[0038] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0039] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0040] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0041] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangular or circular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0042] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0043] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. When the planar shape of the substrate is rectangular, the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0044] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided is considered to be "upper" or "upper side", and the side of the substrate on which the drain electrode is provided is considered to be "lower" or "lower side".

[0045] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0046] In addition, in this specification, a groove portion means a point on the groove. The extension direction of the groove is the direction in which the center line of the groove extends in a plan view. If the center line is curved, the extension direction of the groove is defined as the tangent direction to the center line. The center line is a line that continuously connects the center points of the groove in the width direction along the groove. The width of a groove at one portion is expressed as the distance (i.e., the length of a line segment) between the intersection points of the shortest line between the intersection point with the inner contour of the groove and the intersection point with the outer contour of the groove among the countless straight lines that pass through that portion (i.e., one point) in the groove in a plan view.

[0047] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0048] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN.

[0049] (Embodiment) [Configuration] First, the configuration of a nitride semiconductor device according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view of a nitride semiconductor device 1 according to the embodiment. Figure 2 is a plan view showing the planar layout of the nitride semiconductor device 1 according to the embodiment. Here, Figure 1 shows a cross-section of the nitride semiconductor device 1 according to the embodiment taken along line II in Figure 2.

[0050] In this embodiment, the nitride semiconductor device 1 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film.

[0051] In a heterostructure of an AlGaN film and a GaN film, spontaneous polarization or piezoelectric polarization on the c-plane, which is represented by the (0001) plane, generates a high concentration of two-dimensional electron gas (2DEG) at the heterointerface. Therefore, even in an undoped state, a high concentration of 1×10 １３ cm －２ The sheet carrier concentration can be obtained as above.

[0052] 1, the nitride semiconductor device 1 includes a substrate 10, a first nitride semiconductor layer 20, and a second nitride semiconductor layer 40. The nitride semiconductor device 1 further includes a threshold control layer 60, a gate electrode 62, a source electrode 64, a drain electrode 66, and an insulating layer 70. Furthermore, as shown in FIG. 2, the nitride semiconductor device 1 includes a gate electrode pad 72 and a source electrode pad 74.

[0053] Each of the components included in the nitride semiconductor device 1 will be described in detail below.

[0054] The substrate 10 is made of a nitride semiconductor and has a first major surface 10a and a second major surface 10b that face each other. The first major surface 10a is the major surface on the side where the drift layer 22 is formed and corresponds to the upper surface or front surface of the substrate 10. Specifically, the first major surface 10a has a predetermined off angle with respect to the c-plane. The second major surface 10b is the major surface on the side where the drain electrode 66 is formed and corresponds to the lower surface or back surface of the substrate 10.

[0055] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm －３ The substrate is made of n-type GaN, where n-type and p-type indicate the conductivity types of semiconductors. In this embodiment, n-type is an example of a first conductivity type of a nitride semiconductor. P-type is an example of a second conductivity type having a polarity different from that of the first conductivity type.

[0056] The first nitride semiconductor layer 20 is provided above the substrate 10. As shown in Fig. 1, the first nitride semiconductor layer 20 includes a drift layer 22, a first underlayer 24, a second underlayer 26, and a third underlayer 28. Furthermore, a gate opening 30 is provided in the first nitride semiconductor layer 20.

[0057] The drift layer 22 is an example of a third nitride semiconductor layer of the first conductivity type provided above the first major surface 10a of the substrate 10. The drift layer 22 has a thickness of 8 μm and a carrier concentration of 1×10 １６ cm －３The drift layer 22 is a film made of n-type GaN, where n is a GaN film. The drift layer 22 is provided in contact with the first main surface 10 a of the substrate 10 .

[0058] The first underlayer 24 is an example of a fourth nitride semiconductor layer of the second conductivity type provided above the drift layer 22. The first underlayer 24 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The first underlayer 24 is a film made of p-type GaN, where p-type GaN is a p-type GaN film. The first underlayer 24 is provided in contact with the upper surface of the drift layer 22.

[0059] The first underlayer 24 suppresses leakage current between the source electrode 64 and the drain electrode 66. For example, when a reverse voltage is applied to the pn junction formed between the first underlayer 24 and the drift layer 22, specifically when the drain electrode 66 has a higher potential than the source electrode 64, a depletion layer extends into the drift layer 22. This allows the nitride semiconductor device 1 to have a high breakdown voltage.

[0060] The second underlayer 26 is provided above the first underlayer 24. The second underlayer 26 is formed of an insulating or semi-insulating nitride semiconductor. The second underlayer 26 is, for example, a film made of undoped GaN with a thickness of 200 nm. The second underlayer 26 is provided in contact with the first underlayer 24.

[0061] Here, "undoped" means that the GaN is not doped with a dopant such as silicon (Si) or magnesium (Mg) that changes the polarity of the GaN to n-type or p-type. In this embodiment, the second underlayer 26 is doped with carbon. Specifically, the carbon concentration of the second underlayer 26 is higher than the carbon concentration of the first underlayer 24.

[0062] The second underlayer 26 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the second underlayer 26 is, for example, 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ The silicon concentration or oxygen concentration of the second underlayer 26 may be, for example, 5×10１６ cm －３ The following is 2 x 10 １６ cm －３ The following is also acceptable.

[0063] If the nitride semiconductor device 1 does not include the second underlayer 26, a stacked structure of n-type electron supply layer 44 and electron transit layer 42 / p-type first underlayer 24 / n-type drift layer 22 is formed between the source electrode 64 and the drain electrode 66. This stacked structure forms a parasitic bipolar transistor having a parasitic npn structure.

[0064] When the nitride semiconductor device 1 is in an off state, if a current flows through the first underlayer 24, this parasitic bipolar transistor may turn on, reducing the breakdown voltage of the nitride semiconductor device 1. In this case, the nitride semiconductor device 1 is likely to malfunction.

[0065] The second underlayer 26 suppresses the formation of this parasitic npn structure, thereby reducing malfunction of the nitride semiconductor device 1 due to the formation of the parasitic npn structure. Note that if the current flowing through the first underlayer 24 is sufficiently suppressed, the nitride semiconductor device 1 does not need to include the second underlayer 26.

[0066] The third underlayer 28 is provided above the second underlayer 26. The third underlayer 28 is, for example, an Al 2000 sintered body having a thickness of 20 nm. ０．２ Ga ０．８ The third underlayer 28 is a film made of N. The third underlayer 28 is provided in contact with the second underlayer 26 .

[0067] The third underlayer 28 suppresses the diffusion of p-type impurities such as Mg from the first underlayer 24. If Mg diffuses into the channel in the electron transit layer 42, the carrier concentration of the two-dimensional electron gas may decrease, resulting in an increase in on-resistance. The degree of Mg diffusion varies depending on the growth conditions of the epitaxial growth, etc. Therefore, if the diffusion of Mg is suppressed, the nitride semiconductor device 1 does not need to include the third underlayer 28.

[0068] The third underlayer 28 may also have a function of supplying electrons to a channel formed at the interface between the electron transit layer 42 and the electron supply layer 44. The third underlayer 28 has a band gap larger than that of the electron supply layer 44, for example.

[0069] The gate opening 30 is an example of a groove provided in the first nitride semiconductor layer 20. The gate opening 30 penetrates the first underlayer 24 and reaches the drift layer 22. Specifically, the gate opening 30 penetrates from the upper surface of the third underlayer 28, through the third underlayer 28, the second underlayer 26, and the first underlayer 24 in this order, and reaches the drift layer 22. A bottom 30a of the gate opening 30 is part of the upper surface of the drift layer 22. In this embodiment, as shown in FIG. 1 , the bottom 30a of the gate opening 30 is located below the interface between the drift layer 22 and the first underlayer 24.

[0070] In this embodiment, the gate opening 30 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the sidewall 30b of the gate opening 30 is inclined obliquely. For example, the cross-sectional shape of the gate opening 30 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0071] The second nitride semiconductor layer 40 is provided so as to cover the groove provided in the first nitride semiconductor layer 20. Specifically, the second nitride semiconductor layer 40 is provided so as to cover the gate opening 30. The second nitride semiconductor layer 40 is a regrown layer formed by regrowth after crystal growth for forming the first nitride semiconductor layer 20. As shown in FIG. 1 , the second nitride semiconductor layer 40 includes a stacked structure of an electron transit layer 42 and an electron supply layer 44. Furthermore, a source opening 50 is provided in the second nitride semiconductor layer 40.

[0072] The electron transit layer 42 is a first regrown layer that includes a portion located above the first underlayer 24 and a portion provided along the inner surface of the gate opening 30. Specifically, the electron transit layer 42 is formed so as to cover the upper surface of the third underlayer 28 and the sidewall 30b and bottom 30a of the gate opening 30. For example, the electron transit layer 42 is formed from GaN with a thickness of 100 nm.

[0073] The electron transit layer 42 is in contact with the drift layer 22 at the bottom 30a of the gate opening 30. The electron transit layer 42 is in contact with the side surfaces of the first underlying layer 24, the second underlying layer 26, and the third underlying layer 28 at the sidewalls 30b of the gate opening 30. Furthermore, the electron transit layer 42 is in contact with the top surface of the third underlying layer 28.

[0074] The electron transit layer 42 has a channel. Specifically, two-dimensional electron gas is generated near the interface between the electron transit layer 42 and the electron supply layer 44. The two-dimensional electron gas functions as the channel of the electron transit layer 42. The electron transit layer 42 is undoped, but may be made n-type by doping with Si or the like.

[0075] Although not shown, in this embodiment, an AlN film having a thickness of approximately 1 nm is provided as a second regrown layer between the electron transit layer 42 and the electron supply layer 44. The AlN film can suppress alloy scattering and improve channel mobility. Note that the AlN film does not necessarily have to be provided, and the electron transit layer 42 and the electron supply layer 44 may be in direct contact with each other.

[0076] The electron supply layer 44 is a third regrown layer including a portion located above the first underlayer 24 and a portion provided along the inner surface of the gate opening 30. The electron transit layer 42 and the electron supply layer 44 are provided in this order from the substrate 10 side. The electron supply layer 44 is, for example, an undoped Al layer having a thickness of 50 nm. ０．２ Ga ０．８ It is a film made of N.

[0077] The electron supply layer 44 supplies electrons to the channel formed in the electron transit layer 42. As described above, in this embodiment, the third underlayer 28 also has an electron supply function. Both the electron supply layer 44 and the third underlayer 28 are formed of AlGaN, but the Al composition ratio therein is not particularly limited. For example, the Al composition ratio of the electron supply layer 44 may be 20%, and the Al composition ratio of the third underlayer 28 may be 25%. The Al composition ratio refers to the ratio of the number of Al atoms to one or more elements other than nitrogen contained in the nitride semiconductor.

[0078] The source opening 50 is an example of an opening that penetrates the second nitride semiconductor layer 40. Specifically, the source opening 50 penetrates the electron supply layer 44 and the electron transit layer 42 at a position away from the gate electrode 62. More specifically, the source opening 50 penetrates the electron supply layer 44, the electron transit layer 42, the third underlayer 28, and the second underlayer 26 in this order, and reaches the first underlayer 24. In this embodiment, as shown in FIG. 1 , a bottom 50 a of the source opening 50 is part of the upper surface of the first underlayer 24. The bottom 50 a is located below the interface between the first underlayer 24 and the second underlayer 26. The source opening 50 is located at a position away from the gate opening 30 in a plan view.

[0079] 1 , the source opening 50 is formed with a substantially constant opening area. Specifically, the sidewalls 50b of the source opening 50 are substantially parallel to the thickness direction of the substrate 10. For example, the cross-sectional shape of the source opening 50 is rectangular. Alternatively, the cross-sectional shape of the source opening 50 may be an inverted trapezoid, similar to the gate opening 30.

[0080] The threshold control layer 60 is a fourth regrown layer provided between the gate electrode 62 and the electron supply layer 44. The threshold control layer 60 is provided on the electron supply layer 44 and is in contact with the electron supply layer 44 and the gate electrode 62. The threshold control layer 60 has a thickness of 100 nm and a carrier concentration of 1×10 １７ cm －３ p-type Al ０．２ Ga ０．８ It is a nitride semiconductor layer made of N.

[0081] The potential of the conduction band edge of the channel portion is raised by the threshold control layer 60. This makes it possible to increase the threshold voltage of the nitride semiconductor device 1, and to realize the nitride semiconductor device 1 as a normally-off type FET.

[0082] The threshold control layer 60 may be an insulating film such as a silicon oxide film, a silicon nitride film, etc. The threshold control layer 60 does not necessarily have to be provided.

[0083] The gate electrode 62 is provided above the second nitride semiconductor layer 40 and so as to overlap at least a portion of the gate opening 30 in a plan view of the substrate 10. In the present embodiment, the gate electrode 62 is formed to a shape that conforms to the upper surface of the threshold control layer 60, and to a substantially uniform thickness in contact with the upper surface of the threshold control layer 60. If the threshold control layer 60 is not provided, the gate electrode 62 is provided in contact with the upper surface of the electron supply layer 44.

[0084] The gate electrode 62 is formed using a conductive material such as a metal. For example, the gate electrode 62 is formed using palladium (Pd). Note that the material of the gate electrode 62 can be a material that can be Schottky-connected to an n-type semiconductor, such as a nickel (Ni)-based material, tungsten silicide (WSi), or gold (Au).

[0085] The gate electrode 62 is formed to be spaced apart in a plan view so as not to come into contact with the source electrode 64. Specifically, as shown in Fig. 2, the gate electrode 62 is provided so as to surround the source electrode 64 in a plan view. More specifically, the gate electrode 62 is formed in the shape of a single plate in which a plurality of openings corresponding to the source electrodes 64 are provided.

[0086] The source electrode 64 is provided above the substrate 10 and spaced apart from the gate electrode 62. In this embodiment, the source electrode 64 is provided in the source opening 50. Specifically, the source electrode 64 is provided so as to fill the inside of the source opening 50. The source electrode 64 is in contact with the first underlayer 24 at the bottom 50 a of the source opening 50. Specifically, the source electrode 64 is in contact with each end face of the electron supply layer 44, the electron transit layer 42, the third underlayer 28, and the second underlayer 26. The source electrode 64 is in ohmic contact with the electron transit layer 42 and the electron supply layer 44.

[0087] The source electrode 64 is formed using a conductive material such as a metal, and may be made of a material that forms an ohmic contact with the n-type semiconductor layer, such as Ti / Al.

[0088] Since the source electrode 64 is connected to the first underlayer 24, the potential of the first underlayer 24 can be fixed. This stabilizes the operation of the nitride semiconductor device 1. The Al contained in the source electrode 64 is Schottky-contacted to the first underlayer 24 made of a p-type nitride semiconductor. Therefore, a metal material with a large work function, such as Pd or Ni, which provides low contact resistance with the p-type nitride semiconductor, may be provided in the lower layer of the source electrode 64. This further stabilizes the potential of the first underlayer 24.

[0089] The drain electrode 66 is provided below the substrate 10. Specifically, the drain electrode 66 is provided in contact with the second main surface 10b of the substrate 10. The drain electrode 66 is formed using a conductive material such as a metal. As with the material of the source electrode 64, the material of the drain electrode 66 may be a material that forms an ohmic contact with the n-type semiconductor layer, such as Ti / Al.

[0090] The insulating layer 70 is provided to electrically insulate the gate electrode 62 from the source electrode pad 74 and the source electrode 64. The insulating layer 70 is, for example, a silicon oxide film or a silicon nitride film.

[0091] The gate electrode pad 72 is electrically connected to the gate electrode 62. The gate electrode pad 72 is provided, for example, above the gate electrode 62. In this embodiment, the gate electrode 62 is formed in the shape of a single plate, and therefore, as shown in Fig. 2, the gate electrode pad 72 is provided in only a partial region in a plan view of the nitride semiconductor device 1. A power supply for controlling the gate electrode 62 is connected to the gate electrode pad 72 from outside.

[0092] The source electrode pad 74 is electrically connected to each of the plurality of source electrodes 64. The source electrode pad 74 is provided above the source electrodes 64. In the present embodiment, each of the plurality of source electrodes 64 is formed in an island shape. Therefore, the source electrode pad 74 is provided in most of the region excluding the gate electrode pad 72 in a plan view of the nitride semiconductor device 1 so as to cover each of the plurality of source electrodes 64.

[0093] As described above, in the nitride semiconductor device 1 according to this embodiment, the interface between the electron transit layer 42 and the electron supply layer 44 is an AlGaN / GaN heterointerface. This generates two-dimensional electron gas in the electron transit layer 42, forming a channel. The two-dimensional electron gas has a high carrier concentration, which increases the mobility of the channel and reduces the on-resistance.

[0094] [Planar Layout] The planar layout of the nitride semiconductor device 1 according to this embodiment will be described with reference to FIG.

[0095] 2, the nitride semiconductor device 1 includes a plurality of source electrodes 64 and a plurality of gate openings 30. Note that in Fig. 2, the outline of the gate opening 30 is represented by a dashed line. The dashed line shown in Fig. 2 corresponds to the upper end portion of the gate opening 30, i.e., the upper end portion of the sidewall portion 30b.

[0096] In this embodiment, the m-axis direction and the a-axis direction of the GaN constituting the substrate 10 are respectively assigned to the x-axis direction and the y-axis direction shown in each figure. The m-axis direction is represented by [1-100], and the a-axis direction is represented by [11-20]. The c-axis direction is represented by

[0001] . The c-axis direction and the z-axis direction do not coincide with each other, but intersect at a predetermined angle. This angle corresponds to the off-angle of the substrate 10.

[0097] The off-angle is the angle between the c-plane of GaN, i.e., the (0001) plane, and the first main surface 10a of the substrate 10. The off-angle is, for example, greater than 0° and not more than 5°. The off-angle may be 0.1° or greater. The off-angle may be 1° or less, or may be 0.5° or less.

[0098] The multiple source electrodes 64 are elongated in a first direction. In this embodiment, the first direction is the y-axis direction shown in FIG. 2 , which is the a-axis direction of GaN constituting the substrate 10. Note that the first direction, i.e., the longitudinal direction, may be a direction intersecting the a-axis direction. In this case, the angle formed between the first direction and the a-axis direction may be, for example, 1° or less.

[0099] The source electrode 64 extends linearly and thinly along the a-axis direction. The source electrode 64 has a planar shape that is a sufficiently long rectangle, for example, with the longitudinal length being at least 10 times the lateral length. The planar shapes of the multiple source electrodes 64 are substantially the same. Note that in the region where the gate electrode pad 72 is provided, the length of the source electrode 64 is shortened to avoid contact with the gate electrode pad 72.

[0100] The multiple source electrodes 64 are aligned in a direction perpendicular to the a-axis direction, i.e., along the m-axis direction, along which each of the source electrodes 64 extends. Furthermore, the multiple source electrodes 64 are also aligned in the a-axis direction. In the example shown in FIG. 2 , the nitride semiconductor device 1 includes a total of 18 source electrodes 64 arranged in a matrix of 2 rows and 9 columns. Note that two source electrodes 64 aligned along the a-axis direction may be configured as one long source electrode.

[0101] In a plan view, the gate electrode 62 surrounds the source electrode 64. Specifically, the gate electrode 62 is a single conductive layer provided on the entire surface of the substrate 10, and has openings provided in regions corresponding to the multiple source electrodes 64. The multiple openings provided in the gate electrode 62 expose the source electrodes 64 so as to be electrically connected to the source electrode pads 74.

[0102] In plan view, one gate opening 30 has an elongated O-shape or a racetrack shape along the a-axis direction. Specifically, as shown in FIG. 2 , the gate opening 30 includes two linear portions 31 and 32 and connecting portions 33 and 34.

[0103] When the first main surface 10a of the substrate 10 is viewed in plan, the two linear portions 31 and 32 extend linearly along the first direction (y-axis direction) with the source electrode 64 sandwiched therebetween. Specifically, the two linear portions 31 and 32 are parallel to each other and extend linearly along the a-axis direction of GaN.

[0104] The connection portion 33 is an example of a first connection portion that connects the first ends of the two straight portions 31 and 32 in an arch shape. The first ends are the ends on the positive side in the y-axis direction of each of the straight portions 31 and 32. The connection portion 33 is provided so as to surround one end of the source electrode 64 in the longitudinal direction (the end on the positive side in the y-axis direction).

[0105] The connection portion 34 is an example of a second connection portion that connects the second ends of the two straight portions 31 and 32 in an arch shape. The second ends are opposite to the first ends, and are the negative ends in the y-axis direction of each of the straight portions 31 and 32. The connection portion 34 is provided to surround the other end of the source electrode 64 in the longitudinal direction (the negative end in the y-axis direction).

[0106] Note that "arch-shaped" refers to a shape that is convex toward either the positive or negative side in the y-axis direction. For example, both the inner and outer peripheral contours of connection portion 33 are convex toward the positive side in the y-axis direction. Both the inner and outer peripheral contours of connection portion 34 are convex toward the negative side in the y-axis direction. In this embodiment, connection portion 33 has a shape that is the inverse of connection portion 34 with respect to the x-axis direction. The shape of connection portion 34 will be described later using FIG. 4.

[0107] The multiple gate openings 30 are aligned in a direction perpendicular to the direction in which the linear portions 31 and 32 extend (specifically, the a-axis direction), i.e., along the m-axis direction. In the example shown in Fig. 2, five gate openings 30 are provided. The linear portions 31 and 32 of the multiple gate openings 30 and the multiple source electrodes 64 are aligned alternately one by one in the m-axis direction.

[0108] In this embodiment, since the longitudinal direction of the gate opening 30 is the a-axis direction, most of the sidewall 30b of the gate opening 30 can be made of the GaN m-plane. This suppresses the occurrence of GaN crystal facets on the sidewall 30b of the gate opening 30. This makes it possible to achieve good electrode contact with the gate electrode 62 and low resistance in the channel along the sidewall 30b.

[0109] The longitudinal direction of the gate opening 30 does not necessarily have to be the a-axis direction. For example, the longitudinal direction of the gate opening 30 may be the m-axis direction. In this case, the flatness of the surface of the nitride semiconductor layer crystal-grown on the substrate 10 is improved. This increases the stability of processes such as exposure, making it possible to realize a nitride semiconductor device 1 with excellent quality and improving the yield.

[0110] Abnormal growth occurring due to the off-angle of the substrate 10 in the nitride semiconductor device 1 according to the present embodiment will be described with reference to FIG. 3 . FIG. 3 is a plan view illustrating abnormal growth occurring due to the off-angle of the substrate in a nitride semiconductor device according to a comparative example. Of the components constituting the nitride semiconductor device according to the comparative example, FIG. 3 illustrates only the gate opening 30x. The nitride semiconductor device according to the comparative example differs from the nitride semiconductor device 1 shown in FIGS. 1 and 2 only in the shape of the gate opening. As shown in FIG. 3 , the gate opening 30x according to the comparative example has a uniform width.

[0111] In this embodiment, the first major surface 10a of the substrate 10 has an off-angle tilted along the y-axis direction (specifically, the a-axis direction). Specifically, the first major surface 10a of the substrate 10 is tilted so that it decreases as it approaches the [11-20] direction with respect to the c-plane of GaN. The off-angle in this case is, for example, about 0.4°. In the plan view of FIG. 3, the negative side in the y-axis direction is higher and the positive side in the y-axis direction is lower. The height of the first major surface 10a is defined as the positive side in the z-axis direction being "high" and the negative side in the z-axis direction being "low."

[0112] The off-angle of the first main surface 10 a of the substrate 10 promotes crystal growth on the first main surface 10 a, making it possible to form a drift layer 22 with excellent film quality. On the other hand, the off-angle causes abnormal growth in the regrowth layer formed to cover the gate opening 30 x.

[0113] The source material supplied in the regrowth process tends to move from a high-gradient position to a low-gradient position along the off-axis direction. For example, some of the source material supplied to region 46x exits toward the lower gradient (the positive side of the y-axis). Meanwhile, the connection portion 34x of the gate opening 30x is formed at a higher gradient than region 46x, i.e., on the negative side of region 46x in the y-axis direction. Therefore, the source material does not enter region 46x from the gate opening 30x. As a result, the source material that can contribute to growth in region 46x decreases, resulting in abnormal growth in region 46x, where the regrown layer becomes thinner.

[0114] In addition, in a region 45x adjacent to the connecting portion 33x, the supply of raw material from the connecting portion 33x is reduced, and the thickness of the regrown layer in the region 45x also becomes thinner. That is, abnormal growth of the regrown layer occurs in the region 45x as in the region 46x.

[0115] In this embodiment, the second nitride semiconductor layer 40 and the threshold control layer 60 are formed as regrown layers. The second nitride semiconductor layer 40 includes a channel, and the threshold control layer 60 controls the channel. Therefore, if the film thickness of at least one of the second nitride semiconductor layer 40 and the threshold control layer 60 becomes thin, the characteristics of the nitride semiconductor device 1 deteriorate. For this reason, it is not preferable to form, for example, a source electrode 64 in the regions 45x and 46x including abnormal growth. By avoiding using the regions 45x and 46x as the effective regions of the FET, the effective area for operating as a FET is reduced.

[0116] Therefore, in this embodiment, the shape of the gate opening 30 is made different depending on the portion so that the region including abnormal growth is made smaller. Figure 2 shows portions P1a, P1b, P2a, and P2b as characteristic portions of the gate opening 30.

[0117] The portions P1a and P1b are portions where the gate opening 30 extends in a first direction (y-axis direction) parallel to the off-direction of the substrate 10. FIG. 2 shows an imaginary straight line VL1 extending in a second direction (x-axis direction) perpendicular to the off-direction of the substrate 10. The imaginary straight line VL1 is an example of a first imaginary straight line, and is an imaginary line that passes through the center of one of the multiple source electrodes 64 in a planar view. The portions where the imaginary straight line VL1 and the gate opening 30 intersect are defined as portions P1a and P1b. The portion P1a is included in the straight line portion 31. The portion P1b is included in the straight line portion 32.

[0118] The portions P2a and P2b are portions where the gate opening 30 extends in a second direction (x-axis direction) perpendicular to the off-direction of the substrate 10. FIG. 2 shows an imaginary line VL2 extending in a first direction (y-axis direction) parallel to the off-direction of the substrate 10. The imaginary line VL2 is an example of a second imaginary line, and is an imaginary line that passes through the center, in a plan view, of one of the multiple source electrodes 64. The portions where the imaginary line VL2 and the gate opening 30 intersect are defined as portions P2a and P2b. The portion P2a is included in the connection portion 33. The portion P2b is included in the connection portion 34.

[0119] In addition, in Figure 2, virtual straight lines VL1 and VL2 are shown that pass through the bottom left source electrode 64 (the source electrode located on the most negative side of each of the x-axis and y-axis) among the multiple source electrodes 64, but the centers of the other source electrodes 64 may also be used as references.

[0120] In this embodiment, the cross-sectional area of ​​the gate opening 30 at each of the portions P2a and P2b, taken perpendicular to the x-axis direction, is smaller than the cross-sectional area of ​​the gate opening 30 at each of the portions P1a and P1b, taken perpendicular to the y-axis direction. Specifically, the width of the gate opening 30 at each of the portions P2a and P2b is narrower than the width of the gate opening 30 at each of the portions P1a and P1b. More specifically, the widths of the connection portions 33 and 34 of the gate opening 30 are narrower than the widths of the linear portions 31 and 32 of the gate opening 30.

[0121] Fig. 4 is an enlarged plan view showing the shape of the gate opening 30 in region IV in Fig. 2. Note that Fig. 4 illustrates only the gate opening 30 among the components of the nitride semiconductor device 1. Specifically, the outline of the upper end of the gate opening 30 is indicated by a solid line.

[0122] At least a portion of the inner peripheral contour 34a and the outer peripheral contour 34b of the connecting portion 34 are along a circular arc or an elliptical arc. In the present embodiment, at least a portion of the contours 34a and 34b coincide with a circular arc or an elliptical arc.

[0123] 4, at least a portion of the contour 34a corresponds to an arc of a circle C1 having a radius R1 and a center at point Q1. For example, at least a portion of the contour 34a corresponds to half the circumference of the circle C1, i.e., a semicircular arc. For example, the diameter of the circle C1 (2×R1) is equal to the distance between the two adjacent straight line portions 31 and 32.

[0124] The contour 34b corresponds to an arc of a circle C2 having a center at point Q2 and a radius R2 (R2>R1). For example, the contour 34b corresponds to half the circumference of the circle C2, i.e., a semicircular arc.

[0125] The width of the gate opening 30 is widest at each of the linear portions 31 and 32, and the width is W1 = R2 - R1. The width of the gate opening 30 narrows from the position where the linear portions 31 and 32 connect with the connection portion 34, and is narrowest at the tip of the gate opening 30 (portion P2b). The width W2 of the gate opening 30 at this time satisfies W2 < R2 - R1 = d1. In other words, the width of the connection portion 34 monotonically increases from portion P2b to the end of each of the linear portions 31 and 32 (the end on the negative side in the y-axis direction). The rate of increase in width may be constant or may vary. Furthermore, the connection portion 34 may include a section where the width does not change.

[0126] With this configuration, in the regrowth process, the connection portion 34 is filled with material supplied to the connection portion 34 along the off-direction in addition to material supplied directly to the connection portion 34. The filling process progresses faster when the width of the connection portion 34 is narrow. Once the connection portion 34 is filled, material is supplied from the connection portion 34 to the region 46, thereby preventing a shortage of material in the region 46. By preventing a decrease in the film thickness in the region 46, the abnormal growth region becomes narrower, and the effective area of ​​the FET becomes larger.

[0127] Like the connection portion 34, the width of the connection portion 33 also increases monotonically from the portion P2a toward the ends (the ends on the positive side in the y-axis direction) of the linear portions 31 and 32. The rate of increase in width may be constant or may vary. Furthermore, the connection portion 33 may include a section in which the width does not change. This suppresses a shortage of raw material in the region adjacent to the outer periphery of the connection portion 33, thereby making it possible to reduce the abnormal growth region.

[0128] As described above, according to the present embodiment, it is possible to realize the nitride semiconductor device 1 in which abnormal growth is suppressed. By reducing the abnormal growth region, it is possible to increase the effective area of ​​the FET, which enables, for example, a larger current and a higher breakdown voltage.

[0129] Furthermore, in this embodiment, an example has been shown in which the width of each of the connection portions 33 and 34 is narrowed to speed up the filling, but this is not limiting. The depth of at least one of the connection portions 33 and 34 may be shallower. Note that the depth is the distance in the z-axis direction from the top end of the gate opening 30 to the bottom portion 30a. A gate opening having different depths depending on the location can be formed, for example, by multi-stage etching. The cross-sectional area of ​​the connection portions 33 and 34 may be reduced by a method other than varying the width or depth.

[0130] [Modifications] Next, modifications of the embodiment will be described.

[0131] In this modification, the shape of the gate opening in plan view is different from that of the above embodiment. The following description will focus on the differences from the embodiment. Points in this modification that are not particularly described are the same as those in the embodiment.

[0132] 5 is a plan view showing the planar layout of a nitride semiconductor device 2 according to this modification. As shown in FIG. 5, the nitride semiconductor device 2 differs from the nitride semiconductor device 1 according to the embodiment in that it includes a gate opening 130 instead of the gate opening 30. The gate opening 130 has a different shape in a plan view from the gate opening 30, but the cross-sectional shape is the same as that of the gate opening 30. For example, the cross section taken along line II in FIG. 5 is the same as the cross section of the nitride semiconductor device 1 shown in FIG. 1.

[0133] The gate opening 130 according to this modification includes two linear portions 31 and 32 and connecting portions 133 and 134. The shapes of the connecting portions 133 and 134 in a plan view are different from the shapes of the connecting portions 33 and 34 of the gate opening 30 in a plan view.

[0134] As in the above-described embodiment, the connection portion 133 is an example of a first connection portion that connects the first ends (the ends on the positive side in the y-axis direction) of the two straight portions 31 and 32 together in an arch shape. The connection portion 134 is an example of a second connection portion that connects the second ends (the ends on the negative side in the y-axis direction) of the two straight portions 31 and 32 together. In this modification, both the connection portions 133 and 134 have the same width. The connection portion 133 has a shape that is the inverse of the connection portion 134 with respect to the x-axis direction. The shape of the connection portion 134 will be described below with reference to FIG. 6 .

[0135] Fig. 6 is an enlarged plan view showing the shape of the gate opening 130 in region VI of Fig. 5. Note that Fig. 6 illustrates only the gate opening 130 out of the configuration of the nitride semiconductor device 2. Specifically, the outline of the upper end of the gate opening 130 is indicated by a solid line.

[0136] At least a portion of the inner peripheral contour 134a and the outer peripheral contour 134b of the connecting portion 134 are along a circular arc or an elliptical arc. In this modification, at least a portion of the contours 134a and 134b coincide with a circular arc or an elliptical arc.

[0137] 6, the contour 134a coincides with an arc of a circle C3 having a radius R3 and a center Q3. For example, the contour 134a coincides with half the circumference of the circle C3, i.e., a semicircular arc.

[0138] The contour 134b corresponds to the arc of a circle C4 having a center at point Q3 and a radius R4 (R4>R3). For example, the contour 134b corresponds to half the circumference of the circle C4, i.e., a semicircular arc. The contours 134b and 134a are formed concentrically.

[0139] In this modification, the width of the connection portion 134 is uniform at width W2 at portion P2b. The width of the gate opening 130 changes at the boundary where the linear portions 31 and 32 are connected to the connection portion 134. If the width of each of the linear portions 31 and 32 is W1, then W2 = R4 - R3 < W1.

[0140] In this modification, the same effects as those of the embodiment can be obtained, that is, a nitride semiconductor device 2 in which abnormal growth is suppressed can be realized.

[0141] [Manufacturing Method] Next, a manufacturing method of the nitride semiconductor device 1 according to this embodiment will be described with reference to Figures 7A to 7F. Figures 7A to 7F are cross-sectional views showing each step of the manufacturing method of the nitride semiconductor device 1 according to this embodiment.

[0142] The following describes a case where each nitride semiconductor layer constituting the nitride semiconductor device 1 is formed by metal organic vapor phase epitaxy (MOVPE). However, the method for forming the nitride semiconductor layers is not limited to this, and the nitride semiconductor layers may be formed by, for example, molecular beam epitaxy (MBE) or other epitaxial growth methods.

[0143] An n-type nitride semiconductor is formed by adding, for example, silicon (Si), and a p-type nitride semiconductor is formed by adding magnesium (Mg). Note that the n-type impurities and p-type impurities are not limited to these.

[0144] First, a substrate 10 is prepared, which is made of n-type GaN and has a first main surface 10a that is a (0001) plane, i.e., a c-plane. As shown in Fig. 7A, a first nitride semiconductor film 21 is formed on the first main surface 10a of the substrate 10. Specifically, an n-type GaN film 23 doped with Si as an n-type impurity, a p-type GaN film 25 doped with Mg as a p-type impurity, an undoped GaN film 27, and an undoped Al ０．２ Ga ０．８ An undoped AlGaN film 29 made of N is formed in this order. The n-type GaN film 23, the p-type GaN film 25, the undoped GaN film 27, and the undoped AlGaN film 29 are patterned into predetermined shapes to become the drift layer 22, the first underlayer 24, the second underlayer 26, and the third underlayer 28 shown in FIG. 1 , respectively.

[0145] The thickness and carrier concentration of each layer are, for example, as follows: The n-type GaN film 23 has a thickness of 8 μm and a carrier concentration of 1×10 １６ cm －３ The p-type GaN film 25 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The undoped GaN film 27 has a thickness of 200 nm. The undoped AlGaN film 29 has a thickness of 20 nm. These values ​​are merely examples.

[0146] 7B , a resist is applied onto the undoped AlGaN film 29, and the applied resist is patterned by photolithography to form a resist mask 90. ​​The resist mask 90 is a mask for forming the gate opening 30, and has an opening 91 corresponding to the shape of the gate opening 30 in a plan view.

[0147] Next, as shown in FIG. 7C , a gate opening 30 is formed by dry etching. The gate opening 30 penetrates the undoped AlGaN film 29, the undoped GaN film 27, and the p-type GaN film 25, exposing the drift layer 22 (n-type GaN film 23). At this time, a bottom 30a of the gate opening 30 is parallel to the first main surface 10a of the substrate 10. A sidewall 30b of the gate opening 30 is inclined at a predetermined inclination angle with respect to the bottom 30a. The inclination angle is, for example, in the range of 20° to 80°.

[0148] 7D , the resist mask 90 is removed, and then a second nitride semiconductor film 41 and a p-type GaN film 61 are formed. Specifically, an undoped GaN film 43, an undoped AlN film (not shown), an undoped AlGaN film 45, and a p-type GaN film 61 are formed in this order over the entire surface along the shape of the gate opening 30 by MOVPE. The undoped GaN film 43, the undoped AlGaN film 45, and the p-type GaN film 61 are patterned into predetermined shapes to become the electron transit layer 42, the electron supply layer 44, and the threshold control layer 60, respectively.

[0149] The thickness of each layer is as follows: the undoped GaN film 43 is 200 nm; the undoped AlN film is 1 nm; the undoped AlGaN film 45 is 50 nm; and the p-type GaN film 61 is 200 nm. Note that these values ​​are merely examples.

[0150] Next, a gate metal film made of Pd is formed by evaporation, sputtering, or the like so as to cover the gate opening 30. As shown in Fig. 7E, the formed gate metal film is patterned to form a gate electrode 62.

[0151] 7F , a source opening 50 is formed at a position away from the gate electrode 62. Specifically, similar to the gate opening 30, photolithography and dry etching are used to penetrate the p-type GaN film 61, the undoped AlGaN film 45, the undoped AlN film (not shown), the undoped GaN film 43, the undoped AlGaN film 29, and the undoped GaN film 27, thereby exposing the p-type GaN film 25, thereby forming the source opening 50. The p-type GaN film 61, the undoped AlGaN film 45, the undoped GaN film 43, the undoped AlGaN film 29, the undoped GaN film 27, and the p-type GaN film 25 are patterned, respectively, thereby forming the threshold control layer 60, the electron supply layer 44, the electron transit layer 42, the third underlayer 28, the second underlayer 26, and the first underlayer 24.

[0152] Next, a source metal film made of Ti and Au is formed by vapor deposition, sputtering, or the like so as to fill the source opening 50, and is patterned to form a source electrode 64. Furthermore, a drain metal film made of Ti and Al is formed on the second main surface 10b of the substrate 10 by vapor deposition, sputtering, or the like, and is patterned as necessary to form a drain electrode 66.

[0153] Through the above steps, the nitride semiconductor device 1 shown in FIG. 1 is formed.

[0154] After the gate electrode 62 and the source electrode 64 are formed, an insulating layer 70 is formed, and contact holes are formed in the formed insulating film to expose a portion of each of the plurality of source electrodes 64 and a portion of the gate electrode 62. Thereafter, a metal film is formed and patterned to form a gate electrode pad 72 and a source electrode pad 74.

[0155] The method for manufacturing the nitride semiconductor device 2 according to the modification is similar to the method for manufacturing the above-described nitride semiconductor device 1. As shown in Fig. 7B, in the step of forming a resist mask 90 for forming the gate opening 30, the shape of the opening 91 of the resist mask 90 may be adjusted to match the shape of the gate opening 130.

[0156] While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0157] For example, in the above embodiment, the source opening 50 is provided so as to reach the first underlayer 24, but this is not limiting. For example, the source opening 50 may be an opening that reaches the electron transit layer 42. Furthermore, the source electrode 64 may be connected to the electron transit layer 42, but not to the first underlayer 24.

[0158] Furthermore, for example, the threshold control layer 60 and the gate electrode 62 are provided at positions overlapping the bottom 30a of the gate opening 30 in a plan view, but this is not limiting. The threshold control layer 60 and the gate electrode 62 may overlap the sidewall 30b without overlapping the bottom 30a in a plan view. Alternatively, the threshold control layer 60 and the gate electrode 62 may be provided so as not to overlap the gate opening 30 in a plan view. Specifically, the threshold control layer 60 and the gate electrode 62 may be provided at positions overlapping the upper surface of the first nitride semiconductor layer 20 outside the gate opening 30 in a plan view. The threshold control layer 60 and the gate electrode 62 may be arranged on both sides of the gate opening 30 so as to sandwich the gate opening 30 therebetween in a plan view, like the source electrode 64. The threshold control layer 60 does not have to be provided.

[0159] In this case, the electron supply layer 44 may be provided with a gate recess at a position overlapping the gate electrode 62 in a plan view. The gate recess is a recess provided in the upper surface of the electron supply layer 44. Since the thickness of the electron supply layer 44 is smaller at the bottom of the gate recess, it becomes easier to suppress the generation of 2DEG during off-state operation, and a normally-off state can be easily achieved. A threshold control layer 60 is provided so as to cover the gate recess. If the threshold control layer 60 is not provided, the gate electrode 62 is provided so as to cover the gate recess.

[0160] In this case, a first electrode electrically isolated from the threshold control layer 60 and the gate electrode 62 may be provided above the second nitride semiconductor layer 40 at a position overlapping the bottom 30a of the gate opening 30 in a plan view. The first electrode is supplied with, for example, the same potential as that applied to the source electrode 64. For example, a through-hole may be provided in an insulating layer covering the first electrode, and a conductive via may be provided to electrically connect the source electrode pad 74 and the first electrode. A p-type nitride semiconductor layer may be provided between the first electrode and the second nitride semiconductor layer 40. The p-type nitride semiconductor layer is electrically isolated from the threshold control layer 60 and the gate electrode 62. For example, the first electrode and the p-type nitride semiconductor layer are ohmically connected.

[0161] With this configuration, electric field lines extending from the drain electrode 66 can be terminated at the first electrode and the p-type nitride semiconductor layer, thereby reducing the parasitic capacitance Cgd between the gate and the drain. This shortens the rise and fall times of the voltage and current, thereby reducing switching loss. Furthermore, a nitride semiconductor device capable of high-speed operation can be realized. Since total loss is suppressed even during high-speed operation, a low-loss power device can be realized.

[0162] Furthermore, for example, the nitride semiconductor device does not have to be a vertical FET, but may be a lateral FET or a diode, etc. In this case, the groove provided in the first nitride semiconductor layer does not have to be the gate opening 30. For example, the groove may be provided as an element isolation region.

[0163] Furthermore, the groove does not have to be a circular groove. The groove may be composed of a plurality of grooves. For example, the groove may include a first groove including a first portion and a second groove including a second portion. The first groove and the second groove may be connected to or intersect with each other, or may be spaced apart from each other.

[0164] The contour of the connection may be a polygonal line. When all bending points included in the polygonal line are located on a circular arc or an elliptical arc, the contour can be considered to be along a circular arc or an elliptical arc.

[0165] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0166] The present disclosure can be used as a nitride semiconductor device with low leakage current and high breakdown voltage, and can be used, for example, as a power device used in the power supply circuits of consumer appliances such as televisions.

[0167] REFERENCE SIGNS LIST 1, 2 Nitride semiconductor device 10 Substrate 10a First principal surface 10b Second principal surface 20 First nitride semiconductor layer 21 First nitride semiconductor film 22 Drift layer 23 n-type GaN film 24 First underlayer 25, 61 P-type GaN film 26 Second underlayer 27, 43 Undoped GaN film 28 Third underlayer 29, 45 Undoped AlGaN film 30, 30x, 130 Gate opening 30a, 50a Bottom 30b, 50b Sidewall 31, 32 Linear portion 33, 33x, 34, 34x, 133, 134 Connection 34a, 34b, 134a, 134b Contour 40 Second nitride semiconductor layer 41 Second nitride semiconductor film 42 Electron transit layer 44 Electron supply layer 45x, 46, 46x Region 50 Source opening 60 Threshold control layer 62 Gate electrode 64 Source electrode 66 Drain electrode 70 Insulating layer 72 Gate electrode pad 74 Source electrode pad 90 Resist mask 91 Opening

Claims

1. circuit board and A first nitride semiconductor layer provided above the substrate, The present invention comprises a second nitride semiconductor layer provided so as to cover a groove provided in the first nitride semiconductor layer, If the portion of the substrate in which the groove extends in a first direction parallel to the off-direction is defined as the first portion, and the portion of the substrate in which the groove extends in a second direction perpendicular to the off-direction is defined as the second portion, then the cross-sectional area of ​​the groove in the second portion perpendicular to the second direction is smaller than the cross-sectional area of ​​the groove in the first portion perpendicular to the first direction. Nitride semiconductor equipment.

2. The width of the groove in the second portion is narrower than the width of the groove in the first portion. The nitride semiconductor device according to claim 1.

3. The groove is an annular groove. The nitride semiconductor device according to claim 2.

4. The first nitride semiconductor layer is A third nitride semiconductor layer of the first conductivity type, The present invention includes a fourth nitride semiconductor layer having a second conductivity type opposite in polarity to the first conductivity type, which is provided above the third nitride semiconductor layer. A nitride semiconductor device according to any one of claims 1 to 3.

5. A gate electrode is provided above the second nitride semiconductor layer, such that it overlaps the first portion of the substrate in a plan view, A source electrode is provided above the substrate, away from the gate electrode, The substrate comprises a drain electrode provided below the substrate, The groove penetrates the fourth nitride semiconductor layer, The second nitride semiconductor layer is in contact with the third nitride semiconductor layer at the bottom of the groove. The nitride semiconductor device according to claim 4.

6. The source electrode is in contact with the fourth nitride semiconductor layer at the bottom of an opening that penetrates the second nitride semiconductor layer. The nitride semiconductor device according to claim 5.

7. The source electrode has an elongated shape in the first direction when viewed in plan of the substrate. The nitride semiconductor device according to claim 5.

8. The groove is Two straight sections extending along the first direction with the source electrode sandwiched in between, A first connecting portion that connects the first ends of each of the two straight sections in the first direction in an arch shape, It includes a second connecting portion that connects the second ends of each of the two straight sections, opposite to the first end, in an arch shape, The first portion is included in each of the two straight sections, The second part is included in each of the first and second connection parts, The nitride semiconductor device according to claim 7.

9. The width of the first connection portion increases monotonically from the second portion included in the first connection portion to the first end portion. The width of the second connection portion increases monotonically from the second portion included in the second connection portion to the second end portion. The nitride semiconductor device according to claim 8.

10. Both the first and second connecting portions have a uniform width. The nitride semiconductor device according to claim 8.

11. The first portion is the portion where the groove intersects with a first virtual straight line that passes through the center of the source electrode in a plan view of the substrate and extends in the second direction, The second portion is the portion where the groove intersects with a second virtual straight line that passes through the center of the source electrode in a plan view of the substrate and extends in the first direction. The nitride semiconductor device according to claim 8.

12. The source electrodes comprise three or more, Two or more of the grooves are provided, arranged side by side in the second direction. The three or more source electrodes are arranged in line in the second direction, The source electrode is positioned between adjacent grooves. The nitride semiconductor device according to claim 8.

13. The second nitride semiconductor layer includes a stacked structure of a GaN layer and an AlGaN layer. A nitride semiconductor device according to any one of claims 1 to 3.