Semiconductor device

Abstract

Provided is a semiconductor device that makes it possible to suppress decrease in a threshold value while leaving a barrier metal on an interlayer insulating film. The semiconductor device comprises: a first semiconductor layer (1) of a first conductivity type; a gate insulating film (7) in contact with the first semiconductor layer (1); a gate electrode (8); an interlayer insulating film (9); a contact hole (20); an upper surface electrode (11); and a sealing film (31). Among a first region (43) covered by the sealing film (31), a second region (42) that is adjacent to the first region (43) and in which the upper surface electrode (11) is not covered by the sealing film (31), and a third region (41) that is not adjacent to the first region (43), is adjacent to the second region (42), and in which the upper surface electrode (11) is not covered by the sealing film (31), the second region (42) is provided with a first barrier metal (25) including a first metal between the upper surface electrode (11) and the interlayer insulating film (9), and the first barrier metal (25) is not provided between the upper surface electrode (11) and the interlayer insulating film (9) in the third region (41).

Description

Semiconductor Devices

[0001] This disclosure relates to semiconductor devices.

[0002] Conventionally, a technique has been known in which an electrode pad and wiring are formed on an interlayer insulating film via a barrier metal film, and the barrier metal film is left around the electrode pad, thereby forming a barrier metal removal region in the barrier metal film where the barrier metal film under the electrode pad is removed (see, for example, Patent Document 1 below).

[0003] Japanese Patent Application Laid-Open No. 2004-363173

[0004] In conventional semiconductor devices, a barrier metal including a Ti (titanium) film is left on an interlayer insulating film. When Ti remains, Ti absorbs hydrogen, which causes a problem of a decrease in the threshold voltage of the semiconductor device. The purpose of this disclosure is to provide a semiconductor device that can suppress a decrease in the threshold voltage while leaving the barrier metal on the interlayer insulating film.

[0005] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: The semiconductor device includes a first semiconductor layer of a first conductivity type, a gate insulating film in contact with the first semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor layer, an interlayer insulating film provided on the gate electrode, a contact hole penetrating the interlayer insulating film to a surface of the second semiconductor layer, a top electrode selectively formed on the surface of the interlayer insulating film and in the contact hole, and a sealing film selectively formed on the top electrode and on the surface of the interlayer insulating film, wherein the semiconductor device includes a first barrier metal containing a first metal between the top electrode and the interlayer insulating film in a first region covered by the sealing film, a second region in which the top electrode is not covered by the sealing film and adjacent to the first region, and a third region in which the top electrode is not covered by the sealing film and is adjacent to the second region but not to the first region.

[0006] According to the above disclosure, the barrier metal is left only near the polyimide film, rather than on the entire surface of the semiconductor device. This leaves less Ti in the barrier metal remaining on the interlayer insulating film, reducing hydrogen absorption by Ti and mitigating threshold voltage drops. This allows semiconductor devices to be manufactured with desirable characteristics and yields.

[0007] The semiconductor device according to the present disclosure has the effect of being able to suppress a decrease in threshold voltage while leaving the barrier metal on the interlayer insulating film.

[0008] FIG. 1 is a top view of a semiconductor device according to an embodiment. FIG. 2 is an A-A' cross-sectional view of the semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view showing a structure of the semiconductor device according to the embodiment. FIG. 4 is a top view of Example 1 of the semiconductor device according to the embodiment. FIG. 5 is a top view of Example 2 of the semiconductor device according to the embodiment. FIG. 6 is a top view of Example 3 of the semiconductor device according to the embodiment. FIG. 7A is an enlarged top view of a region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 7B is a different example of an enlarged top view of a region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 7C is a different example of an enlarged top view of a region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 7D is a different example of an enlarged top view of a region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 7E is a different example of an enlarged top view of a region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 8 is a top view of Example 4 of the semiconductor device according to the embodiment. FIG. 9A is an enlarged top view of a region S1 of Example 4 of the semiconductor device according to the embodiment. FIG. 9B is an enlarged top view of a region S1 of a semiconductor device according to a second example of the embodiment. FIG. 9C is an enlarged top view of a region S2 of a semiconductor device according to a fourth example of the embodiment. FIG. 9D is an enlarged top view of a region S1 of a semiconductor device according to a second example of the embodiment. FIG. 10 is a top view of another structure of a semiconductor device according to the embodiment. FIG. 11A is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 1). FIG. 11B is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 2). FIG. 11C is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 3). FIG. 11D is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 4). FIG. 11E is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 5). FIG. 11F is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 6). FIG. 11G is an A-A' cross-sectional view of another structure of a semiconductor device according to the embodiment (part 7). FIG. 11H is a cross-sectional view taken along the line AA′ of another structure of the semiconductor device according to the embodiment (part 8).11I is an A-A' cross-sectional view (part 9) of another structure of the semiconductor device according to the embodiment. FIG. 11J is an A-A' cross-sectional view (part 10) of another structure of the semiconductor device according to the embodiment. FIG. 12 is a top view of the semiconductor device according to the embodiment when mounted. FIG. 13A is a cross-sectional view (part 1) showing a structure in the vicinity of a gate electrode pad of the semiconductor device according to the embodiment. FIG. 13B is a cross-sectional view (part 2) showing a structure in the vicinity of a gate electrode pad of the semiconductor device according to the embodiment. FIG. 13C is a cross-sectional view (part 3) showing a structure in the vicinity of a gate electrode pad of the semiconductor device according to the embodiment. FIG. 14 is a top view of a conventional semiconductor device. FIG. 15 is an A-A' cross-sectional view of the conventional semiconductor device.

[0009] <Outline of Embodiments of the Present Disclosure> In order to solve the above-described problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: The semiconductor device includes a first semiconductor layer of a first conductivity type, a gate insulating film in contact with the first semiconductor layer, a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the first semiconductor layer, an interlayer insulating film provided on the gate electrode, a contact hole penetrating the interlayer insulating film to a surface of the second semiconductor layer, a top electrode selectively formed on a surface of the interlayer insulating film and in the contact hole, and a sealing film selectively formed on the top electrode and on a surface of the interlayer insulating film. In a first region covered with the sealing film, a second region in which the top electrode is not covered with the sealing film and is adjacent to the first region, and a third region in which the top electrode is not covered with the sealing film and is not adjacent to the first region but is adjacent to the second region, a first barrier metal containing a first metal is provided between the top electrode and the interlayer insulating film in the second region, and the first barrier metal is not provided between the top electrode and the interlayer insulating film in the third region.

[0010] According to the above disclosure, the barrier metal is left only near the polyimide film, rather than on the entire surface of the semiconductor device. This leaves less Ti in the barrier metal remaining on the interlayer insulating film, reducing hydrogen absorption by Ti and mitigating threshold voltage drops. This allows semiconductor devices to be manufactured with desirable characteristics and yields.

[0011] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, a second barrier metal having a smaller hydrogen absorption capacity than the first barrier metal is provided between the upper electrode and the interlayer insulating film in the third region.

[0012] Furthermore, in the semiconductor device according to the present disclosure, the second barrier metal does not contain the first metal or contains less of the first metal than the first barrier metal.

[0013] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the second barrier metal is made of a compound film of the first metal.

[0014] Furthermore, in the semiconductor device according to the present disclosure, the compound film of the first metal is a nitride film.

[0015] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the compound film of the first metal includes a compound film with a semiconductor material.

[0016] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first barrier metal includes a single film of the first metal, and the second barrier metal does not include a single film of the first metal or includes less of the single film of the first metal than the first barrier metal.

[0017] In addition, in the semiconductor device according to the present disclosure, the second barrier metal has a simple substance or compound film of a second metal different from the first metal.

[0018] Moreover, in the semiconductor device according to the present disclosure, the first metal is titanium.

[0019] Furthermore, the semiconductor device according to the present disclosure, in the above disclosure, further comprises a transistor region including a second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer, and a second semiconductor region of a first conductivity type selectively provided in the surface layer of the second semiconductor layer.

[0020] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the transistor region is provided in the third region and not in the second region.

[0021] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it includes a lifetime control region.

[0022] Moreover, in the semiconductor device according to the present disclosure, in the above disclosure, the lifetime control region is not provided in the transistor region in the second region.

[0023] Moreover, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it further comprises a diode region.

[0024] Furthermore, the semiconductor device according to the present disclosure, in the above disclosure, is characterized in that the second region includes an ineffective region between the diode region and the transistor region that does not have the lifetime control region.

[0025] Moreover, in the semiconductor device disclosed above, the diode region is provided in the third region and not in the second region.

[0026] Moreover, in the semiconductor device disclosed above, the diode region is provided in the second region and not in the third region.

[0027] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it includes a lifetime control region.

[0028] Moreover, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it further comprises a diode region.

[0029] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it further comprises a trench reaching the first semiconductor layer 1, and the gate electrode is provided inside the trench via the gate insulating film.

[0030] Moreover, in the above-described semiconductor device according to the present disclosure, the semiconductor device further comprises the first barrier metal between the upper electrode and the interlayer insulating film in the first region.

[0031] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, it further comprises a fourth region in the region covered with the sealing film, which is in contact with the first region and not adjacent to the second region, and the fourth region does not comprise the first barrier metal between the upper electrode and the interlayer insulating film.

[0032] <Findings that Form the Basis of the Present Disclosure> First, the problems of conventional semiconductor devices will be described. FIG. 14 is a top view of a conventional semiconductor device. FIG. 15 is a cross-sectional view of the conventional semiconductor device taken along the line A-A'. Conventionally, semiconductor devices include a MOS (Metal Oxide Semiconductor) gate on the front surface side of a semiconductor substrate (semiconductor chip) 130. The MOS gate is composed of a gate insulating film 107 and a gate electrode 108 in a trench 106. An interlayer insulating film 109 is provided on the gate electrode 108 to insulate the front electrode 111 from the gate electrode 108. The front electrode 111 is composed of, for example, an Al film, an Al alloy film such as Al-Si or Al-Si-Cu, or copper (Cu).

[0033] A contact hole 120 is provided in the interlayer insulating film 109 to electrically connect the front surface electrode 111 and the semiconductor substrate 130. A plug electrode 115 made of tungsten (W) or copper (Cu) is buried in the contact hole 120, and a barrier metal 125 is provided on the interlayer insulating film 109 to prevent ion diffusion from the front surface electrode 111 toward the gate insulating film 107 and gate electrode 108. The barrier metal 125 is made of, for example, a Ti film and a TiN film.

[0034] A polyimide film (passivation film) 131 is formed around the front electrode 111 as a protective film for preventing ion diffusion into the semiconductor device and insulating the semiconductor device.

[0035] As described above, in conventional semiconductor devices, the barrier metal 125 remains on the interlayer insulating film 109. During assembly of the resin encapsulation of the semiconductor device, stress migration can cause defects 134 in the front electrode 111. If ions reach the gate insulating film 107 and gate electrode 108 via the defects 134, this can lead to assembly defects and reduced reliability. If the barrier metal 125 remains on the interlayer insulating film 109, ions will not reach the gate insulating film 107 and gate electrode 108, leading to reduced assembly defects and improved reliability.

[0036] On the other hand, when hydrogen or helium is irradiated to create a lifetime killer control region, the gate insulating film 107 is damaged and defects are generated. These defects are repaired by supplying heat and hydrogen (H) to the defective parts during subsequent annealing. However, if the barrier metal is left on the entire surface of the gate insulating film 107 and the interlayer insulating film 109, the hydrogen that would be supplied to the defective parts during annealing is absorbed by Ti in the barrier metal and does not reach the defects, preventing the defects from repairing and resulting in a decrease in the threshold voltage.

[0037] Preferred embodiments of a semiconductor device according to the present disclosure that solve the problems of conventional semiconductor devices described above will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0038] (Embodiment) Fig. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. The structure of the semiconductor device according to the embodiment will be described using a trench-type RC-IGBT 150 as an example. The semiconductor device according to the embodiment shown in Fig. 3 is an RC-IGBT 150 in which an IGBT with a trench structure and a diode connected in anti-parallel to the IGBT are integrated on the same semiconductor substrate (semiconductor chip). The RC-IGBT 150 includes an active region, which is a region through which current flows when the RC-IGBT is on, and an edge termination region that surrounds the periphery of the active region; however, Fig. 3 shows only the active region.

[0039] The RC-IGBT 150 has an IGBT region (transistor region) 21 that serves as the operating region of the IGBT and an FWD region (diode region) 22 that serves as the operating region of the diode, which are provided in parallel on the same semiconductor substrate as the active region.

[0040] Within the semiconductor body 30 of the active region, n - An n-type accumulation layer 5 may be provided in the surface layer of the front surface (first main surface) of the n-type drift layer (first semiconductor layer of the first conductivity type) 1. The n-type accumulation layer 5 is a so-called charge storage layer (CSL) that reduces the spreading resistance of carriers. A p-type base region (second semiconductor layer of the second conductivity type) 2 is provided on the n-type accumulation layer 5, extending from the IGBT region 21 to the FWD region 22. The p-type base region 2 functions as a p-type anode region in the FWD region 22. A p-type anode region (a second semiconductor layer of the second conductivity type) 2 extends through the p-type base region 2. - A trench 6 is provided in the IGBT region 21 and the FWD region 22, and in the IGBT region 21, n-type +In the FWD region 22, a p-type emitter region (first semiconductor region of a first conductivity type) 3 is provided. The trenches 6 are arranged at predetermined intervals, for example, in a striped planar layout, and separate the p-type base region 2 into multiple regions (mesa portions). Inside the trench 6, a gate insulating film 7 is provided along the inner wall of the trench 6, and a gate electrode 8 is provided inside the gate insulating film 7. The gate electrode 8 is connected to a gate pad and is given a gate potential from an external circuit connected to the gate pad. Note that some of the trenches 6 may be dummy trenches in which the internal gate electrode 8 is not connected to the gate pad and is fixed to the potential of the emitter electrode. In this example, if a dummy trench is not necessary, it may also be described as a trench 6. In another example, the trench 6 may not be provided in the FWD region 22.

[0041] In the IGBT region 21, inside the p-type base region 2, n-type + The n-type emitter region 3 is selectively provided. + The emitter region 3 faces the gate electrode 8 across a gate insulating film 7 provided on the inner wall of the trench 6. + In this case, n + type emitter region 3 and p + The contact regions 4 are in contact with each other. + type emitter region 3 and p + However, the n-type contact regions 4 are arranged in a line, and are not limited to this. + type emitter region 3 and p + In the FWD region 22, the p-type base region 2 may have n-type contact regions 4 arranged alternately. + type emitter region 3 and p + The n-type contact region 4 is not provided. The front surface electrode (upper surface electrode) 11 is connected to the n-type contact region 4 via the contact hole 20. +The mesa contacts the emitter region 3 and is electrically insulated from the gate electrode 8 by an interlayer insulating film 9. Some of the mesas may not have a contact hole 20 formed above them. The sidewalls of the contact hole 20 may be vertical or tapered. + An opening may be selectively provided in the p-type emitter region 3, and the front surface electrode 11 and the p-type base region 2 may be electrically connected through the opening. + When the contact region 4 is provided, the front electrode 11 and the p + The p-type contact region 4 may be electrically connected to the p-type base region 2. The front surface electrode 11 functions as an emitter electrode in the IGBT region 21, and as an anode electrode in the FWD region 22. A Ti film 17 and a TiN film 18 are provided between the front surface electrode 11 and the interlayer insulating film 9 as a barrier metal 25 that prevents ions from diffusing from the front surface electrode 11 to the gate electrode 8 side. The Ti film 17 at the bottom of the contact hole 20 may form an alloy with the semiconductor substrate 10 and exist as a titanium silicide film 55. + The mold contact region 4 may have a plug region (not shown) in which the impurity concentration is further increased in at least a part of the region directly below the contact hole 20 .

[0042] Alternatively, a structure may be employed in which contact plugs are embedded in contact holes 20 formed in the interlayer insulating film 9. The contact plugs are formed, for example, of a metal film made of tungsten (W) or copper (Cu), which have high embedding properties. The front surface electrodes 11 are formed of an Al film, an Al alloy film such as Al-Si or Al-Si-Cu, or copper (Cu). When the cell pitch is wide, a structure in which the contact holes 20 are filled with the front surface electrodes 11 without forming contact plugs may be employed. Hereinafter, the contact plugs or the front surface electrodes 11 in the contact holes 20 are referred to as plug electrodes 15. A polyimide film (passivation film, sealing film) 31 is formed around the front surface electrodes 11 as a protective film to prevent ion diffusion into the semiconductor device and to insulate the semiconductor device.

[0043] n -An n-type field stop (FS) layer 12 is provided on the rear surface of the substrate inside the drift layer 1. The n-type FS layer 12 is connected to the p-type base region 2 and the n-type - The pn junction between the p-type drift layer 1 and the + This has the function of suppressing the extension of the depletion layer toward the collector region 13 .

[0044] Also, n - In the n-type drift layer 1, the FWD region 22 has a larger n-type conductivity than the n-type FS layer 12. - A lifetime control region 26 may be provided at a shallow position from the front surface of the type drift layer 1, where lattice defects (indicated by x marks) such as vacancies (V) that act as lifetime killers are introduced by irradiation with hydrogen (H) or helium (He). The lifetime control region 26 may also be considered to be formed at a shallow position from the front surface when lattice defects are formed over a wide range in the thickness direction of the semiconductor substrate 30 by irradiation with an electron beam, etc. Forming the lifetime control region 26 can reduce losses and surges during switching in the device. In particular, the n of the FWD region 22 + The p-type cathode region 14 and the adjacent p-type base region 2 and p + The lifetime control region 26 has a function of reducing holes injected from the type contact region 4. Therefore, the lifetime control region 26 may be provided in a range centered on the FWD region 22. In this example, it extends from the FWD region 22 to the IGBT region 21 near the boundary with the FWD region 22. In another example, the lifetime control region 26 does not have to be provided in part of or the entire FWD region 22, or may be provided over the entire IGBT region 21, or may not be provided over the entire IGBT region 21, and the lifetime control region 26 may extend to the chip end of the edge termination region. The lifetime control region 26 does not have to be provided.

[0045] n - The surface layer on the rear surface (second main surface) side of the n-type drift layer 1 is more n-type than the n-type FS layer 12. - At a shallow position from the rear surface of the drift layer 1, p + The collector region 13 is provided in the FWD region 22. +A cathode region 14 is provided. + The cathode region 14 is p + The back electrode 24 is adjacent to the p-type collector region 13. + collector region 13 and n + The back electrode 24 functions as a collector electrode in the IGBT region 21 and as a cathode electrode in the FWD region 22.

[0046] 1 is a top view of a semiconductor device according to a first embodiment. FIG. 2 is an A-A' cross-sectional view of the semiconductor device according to the embodiment. As shown in FIGS. 1 and 2, the semiconductor device according to the embodiment is configured, in a top view, with a first region 43 covered with a polyimide film 31, a second region 42 in which the front surface electrode 11 is not covered with the polyimide film 31 and is adjacent to the first region 43, and a third region 41 in which the front surface electrode 11 is not covered with the polyimide film 31 and is not adjacent to the first region 43 but is adjacent to the second region 42.

[0047] As shown in FIG. 2 , in the first region 43 and the second region 42, the front surface electrode 11 includes a barrier metal 25 on the surface of the interlayer insulating film 9, whereas in the third region 41, the front surface electrode 11 does not include a barrier metal 25 on the surface of the interlayer insulating film 9. As described above, in the embodiment, the barrier metal 25 is not left over the entire surface of the semiconductor device, but only near the polyimide film 31, where defects 34 are likely to occur. In the third region 41, if a plug electrode 15 is formed simultaneously with the front surface electrode 11 and has the same composition, the contact hole 20 does not need to include a barrier metal 25, and the bottom surface of the contact hole 20 may or may not include silicide. The interlayer insulating film 9 may have a step at the boundary between the second region 42 and the adjacent third region 41. In the first region 43, the region not covered by the front surface electrode 11 does not need to be covered with the barrier metal 25.

[0048] In FIG. 1, the outer shapes of the second region 42 and the third region 41 are approximately rectangular, but in cases where the polyimide film 31 has a convex shape, such as when a gate runner, a runner for a temperature sensing diode, an auxiliary pad, or the like, which are formed in the same layer as the front surface electrode 11, protrude into the active region, or when the polyimide film 31 is provided not only on the periphery of the chip but also across the center of the chip or when the polyimide film 31 is scattered inside the chip, the barrier metal 25 on the interlayer insulating film 9 is left around the convex shape and the polyimide film 31 inside the chip.

[0049] As a result, the amount of Ti remaining in the barrier metal 25 on the interlayer insulating film 9 is small, which reduces hydrogen absorption by Ti and alleviates the threshold voltage drop. This allows semiconductor devices to be manufactured with desirable characteristics and yield. This configuration is particularly effective for products in which the lifetime control region 26, which is more susceptible to damage, is formed in the gate electrode 8.

[0050] FIG. 4 is a top view of Example 1 of a semiconductor device according to an embodiment. In FIG. 4 , the RC-IGBT 150 has rectangular IGBT regions 21 and FWD regions 22 arranged along the longitudinal direction (y direction) of the trenches 6, alternating in the repeating direction (x direction) of the trenches 6. The lifetime control region 26 is provided in all of the FWD regions 22 and in part of the IGBT region 21. In the top views of FIG. 4 and subsequent figures, thick dashed lines indicate boundaries between regions where the lifetime control region 26 is provided. In this example, the lifetime control region 26 is provided in the region surrounded by the thick dashed line. The region surrounded by the thin dashed line is the third region 41, the region outside that is the second region 42, and the outermost region is the first region 43. In this structure, the gate electrode 8 and the gate electrode pad 33 can be connected by a peripheral gate runner (not shown) provided in the first region 43.

[0051] 4, the IGBT region 21 and the FWD region 22 are depicted in the third region 41 and the second region 42, but are not depicted in the first region 43. However, the IGBT region 21 or the FWD region 22 may also be formed in the first region 43. The same applies to the top views shown below. The end of the trench 6 is located in the first region 43 and is connected to a peripheral gate runner (not shown).

[0052] The lifetime control region 26 is provided in the entire FWD region 22 and in a part of the IGBT region 21 near the FWD region 22, and the boundary of the lifetime control region 26 in the y direction from the FWD region 22 is provided at the boundary between the second region 42 and the first region 43, but is not limited to this. The boundary of the lifetime control region 26 may be provided at the first region 43 or the second region 42. + The cathode region 14 is formed on the outer periphery of the gate runner and the p of the edge termination region. + In order to improve the reverse recovery characteristics by separating the FWD region 22 from the p-type well region 29, a part of the end portion in the y direction of the FWD region 22 may be an ineffective region. The ineffective region is a region that does not function as an IGBT or an FWD. For example, the front surface is a p-type base region 2 and the back surface is a p-type well region 29. + The lifetime control region 26 is a region of the collector region 13. By widening the invalid region, + It is also possible not to provide the barrier metal 25 in the region where the mold well region 29 is present. Although the gate insulating film 7 may be damaged by irradiation with hydrogen or helium when forming the lifetime control region 26, the area covered with the barrier metal 25 is reduced compared to when the barrier metal 25 is left on the entire surface, and therefore the decrease in threshold voltage is reduced.

[0053] However, it is conceivable that a threshold voltage drop is likely to occur near the barrier metal 25, which may result in different threshold voltages for each region, which may cause problems. In this case, the operation timing may be adjusted. The IGBT region 21 having the lifetime control region 26 in the second region 42 may have a higher impurity concentration in the p-type base region 2 or a thicker gate insulating film 7 than the other IGBT regions 21, thereby compensating for the threshold voltage. Alternatively, a gate signal different from that applied to the other IGBT regions 21 may be applied to adjust the turn-on and turn-off operation timing. The threshold voltage and operation timing may be gradually adjusted depending on the degree of influence. Alternatively, in the second region 42 where the barrier metal 25 remains, the IGBT region 21 having the lifetime control region 26 may be formed as an ineffective region. These adjustments are not limited to the IGBT region 21 in the second region 42, but may also be applied to the IGBT region 21 in the third region 41 in areas affected by its proximity to the second region 42. Also, in the second region 42, it may not be applied to a portion where the influence is minor because it is close to the third region 41.

[0054] Furthermore, the decrease in threshold value may be reduced by not providing the IGBT region 21 having the lifetime control region 26 in the second region 42. In the examples shown below, when the lifetime control region 26 is provided in the FWD region 22 and in a part of the IGBT region 21 adjacent to the FWD region 22, an example will be described in which each region is arranged so that the IGBT region 21 having the lifetime control region 26 is not provided in the second region 42. Note that even in these examples, the IGBT region 21 having the lifetime control region 26 may not be provided in a part of the IGBT region 21 in the third region 41 that is affected by being close to the second region 42, and the IGBT region 21 having the lifetime control region 26 may be provided in a part of the second region 42 that is only slightly affected by being close to the third region 41.

[0055] FIG. 5 is a top view of Example 2 of a semiconductor device according to an embodiment. As in the example shown in FIG. 4 , the RC-IGBT 150 has rectangular IGBT regions 21 and FWD regions 22 arranged along the longitudinal direction (y direction) of the trenches 6, alternating in the repeating direction (x direction) of the trenches 6. The lifetime control regions 26 are provided in the area surrounded by the thick dashed line, and are provided in all of the FWD regions 22 and part of the IGBT region 21. In this example, no lifetime killer is inserted in the IGBT region 21 in the second region 42 directly below the barrier metal 25 or in the vicinity thereof, even in the vicinity of the FWD region 22, and no lifetime control regions 26 are formed. The IGBT region 21 in the third region 41 is provided with a lifetime adjustment region 26. This arrangement can improve reverse recovery characteristics while reducing threshold voltage drop.

[0056] FIG. 6 is a top view of Example 3 of a semiconductor device according to an embodiment. In FIG. 6, an RC-IGBT 150 has rectangular FWD regions 22 aligned along the longitudinal direction of the trenches 6, arranged alternately in the direction in which the trenches 6 are repeated, and an IGBT region 21 is provided outside the FWD regions 22. In FIG. 6, lifetime control regions 26 are provided in all of the FWD regions 22 and in part of the IGBT region 21. No FWD regions 22 are formed in the second region 42, and no lifetime control regions 26 are provided in the IGBT region 21. As a result, in the second region 42, the lifetime control regions 26 are not provided in the IGBT region 21, thereby reducing a decrease in threshold voltage. In this structure, the gate electrode 8 and the gate electrode pad 33 can be connected by a peripheral gate runner (not shown) provided in the first region 43.

[0057] 7A is an enlarged top view of region S1 of Example 3 of the semiconductor device according to the embodiment. Fig. 7A omits the illustration of front surface electrode 11 and interlayer insulating film 9, and only shows contact hole 20, illustrating the structure below them. Fig. 7A is a top view of a structure in which poly runner 27 is provided at the boundary between IGBT region 21 and FWD region 22 in the y direction, connecting gate electrode 8 and gate runner.

[0058] The trench 6 in the IGBT region 21 is connected to the poly runner 27. The poly runner 27 is p+ The dummy trench 28 is provided on the well region 29 via an insulating film. The insulating film may be formed by depositing the gate insulating film 7 and leaving it on the semiconductor substrate 10. The poly runner 27 may be deposited simultaneously with the gate electrode 8 and left on the semiconductor substrate 10. The dummy trench 28 has an end portion that is p + The poly runner 27 extends to the well region 29. The upper surface of the poly runner 27 is covered with an interlayer insulating film 9, which is in turn covered with a front surface electrode 11 that is connected to the IGBT region 21 and the FWD region 22. + The mold well region 29 may not be formed.

[0059] A boundary region may be provided in the IGBT region 21 adjacent to the FWD region 22 in the x direction. The boundary region is a structure for connecting the different structures of the IGBT region 21 and the FWD region 22 with good characteristics, and a structure different from that of a normal IGBT region may be provided. In this example, the boundary region is a region sandwiched between dummy trenches 28 on both sides, and the front surface is p + By providing the n-type contact region 4 + No type emitter region 3 is provided, and the back surface is p + In another example, the front surface is a p-type base region 2 and the rear surface is a p-type collector region 13. + It may be a mold collector region 13, or may be formed in a region sandwiched between a plurality of trenches 6 or dummy trenches 28, or may not be provided at all.

[0060] The lifetime control region 26 may be provided up to the IGBT region 21 adjacent in the x and y directions. + type cathode region 14 (p + well region 29 and n + The ineffective region (the front surface is the p-type base region 2 and the back surface is the p-type cathode region 14) is + collector region 13) + The lifetime control region 26 does not extend to the type well region 29, or +The lifetime control region 26 may extend to the type well region 29, and the lifetime control region 26 may not be provided in the IGBT region 21 adjacent in the y direction. In such a case, the IGBT region 21 may not be provided in the third region 41. In other words, the boundary between the IGBT region 21 and the FWD region 22 may coincide with the boundary between the third region 41 and the second region 42.

[0061] 7B is a different example of an enlarged top view of region S1 of Example 3 of the semiconductor device according to the embodiment. Fig. 7B is a top view of a structure in which a poly runner 27 that connects the gate electrode 8 and the gate runner is provided at the boundary in the y direction between the IGBT region 21 and the FWD region 22. Fig. 7B shows a structure in which the trench 6 is shared between regions of the IGBT region 21 adjacent to each other in the y direction with the poly runner 27 sandwiched therebetween. As a structure in which the poly runner 27 is not extended to regions of the IGBT region 21 adjacent to each other in the y direction, p + n-type well region 29 + type emitter region 3 and p + The effective region may be formed by providing a mold contact region 4. The other structures may be the same as those in the example described with reference to FIG.

[0062] 7C is a different example of an enlarged top view of region S1 of Example 3 of the semiconductor device according to the embodiment. FIG. 7C is a top view of a structure in which a poly runner 27 is provided at the boundary between the IGBT region 21 and the FWD region 22 in the y direction, connecting the gate electrode 8 and the gate runner. FIG. 7C shows an example in which the poly runner 27 is formed by connecting the ends of trenches 6 adjacent in the x direction. The connection of the trenches 6 is not limited to a T-shape, and may be a cross or other structure. Similarly, the dummy trenches 28 may be connected at locations that can be connected in the x direction. The other structures may be the same as those of the example described using FIG. 7A.

[0063] 7D is a top view of a different example of an enlarged region S1 of Example 3 of the semiconductor device according to the embodiment. This is a top view of a structure in which the poly runner 27 is not provided but the trench 6 is isolated. The IGBT region 21 that is not adjacent to the FWD region 22 in the y direction is p +The well region 29 is not formed, the ends of the trench 6 and the dummy trench 28 are not provided, and the n + type emitter region 3 and p + The effective region may be formed by providing a mold contact region 4. The other structures may be the same as those in the example described with reference to FIG.

[0064] 7E is a different example of an enlarged top view of region S1 of Example 3 of the semiconductor device according to the embodiment. Fig. 7E is a top view of a structure in which the trench 6 is not isolated. In this manner, the IGBT region 21 and the FWD region 22 may have the same trench 6 and dummy trench 28. However, the FWD is affected by gate operation. The other structure may be the same as the example described with reference to Fig. 7A.

[0065] The region in contact with the FWD region 22 in the y direction may not be a normal IGBT region 21, but may be entirely formed as an ineffective region. In this case, there is no need to provide a trench 6 connected to the gate runner, and all may be dummy trenches 28. In this case, there is no need to separate the dummy trenches 28 at the boundary of the FWD region 22, i.e., the boundary between the effective FWD region and the ineffective region, and the p + It may extend to the mold well region 29 .

[0066] FIG. 8 is a top view of Example 4 of the semiconductor device according to the embodiment. In FIG. 8, the RC-IGBT 150 has rectangular IGBT regions 21 aligned along the longitudinal direction of the trenches 6, alternately arranged in the direction in which the trenches 6 are repeated, and an FWD region 22 is provided outside the IGBT region 21. In FIG. 8, in this example, the lifetime control region 26 is provided in the active region except for the region surrounded by the thick dashed line, and is provided in all of the FWD region 22 and part of the IGBT region 21, and no IGBT region 21 is provided in the second region 42. As a result, an IGBT region 21 having a lifetime control region 26 is not provided in the second region 42, thereby reducing a decrease in the threshold voltage.

[0067] 9A is an enlarged top view of a region S1 of a semiconductor device according to a fourth example embodiment. Fig. 9A is a top view of a structure in which a poly-runner 27 that connects the gate electrode 8 and the gate runner is provided at the boundary in the y direction between the IGBT region 21 and the FWD region 22. This example corresponds to the example described using Fig. 7A in the second example embodiment, and a description of the same points as those in Fig. 7A will be omitted.

[0068] The lifetime control region 26 may be provided up to the IGBT region 21 adjacent to the FWD region 22 in the x and y directions. + well region 29 and n + The ineffective region (the front surface is the p-type base region 2 and the back surface is the p-type cathode region 14) is + collector region 13) + The lifetime control region 26 does not extend to the type well region 29, or + The lifetime control region 26 may extend over the region up to the type well region 29, and the lifetime control region 26 may not be provided in the IGBT region 21 adjacent in the y direction. Also, the FWD region 22 may not be provided in the third region 41. That is, the boundary between the IGBT region 21 and the FWD region 22 may coincide with the boundary between the third region 41 and the second region 42. In another example, the lifetime control region 26 may be provided over the entire surface of the IGBT region 21, and in this case too, the absence of the IGBT region 21 in the second region 42 suppresses a decrease in the threshold voltage.

[0069] 8 , if dummy trench 28 is provided in FWD region 22 but no trench 6 is provided, the peripheral gate runner provided in first region 43 cannot connect gate electrode 8 in IGBT region 21 in third region 41 to gate electrode pad 33. By extending poly runner 27 shown in FIG. 9A to first region 43 and connecting it to the peripheral gate runner, it is possible to connect gate electrode 8 in IGBT region 21 in third region 41 to gate electrode pad 33. In FIG. 9A , the same configuration of poly runner 27, trench 6, and dummy trench 28 as shown in FIG. 7C may also be used.

[0070] 9B is a top view of a different example of an enlarged region S1 of Example 2 of the semiconductor device according to the embodiment. Fig. 9B is a top view of a structure in which the poly runner 27 is not provided but the trench 6 is separated. The FWD region 22 that is not adjacent to the IGBT region 21 in the y direction is p + Alternatively, the p-type well region 29 may not be formed, the ends of the trench 6 and the dummy trench 28 may not be provided, and the p-type base region 2 may be placed and made active.

[0071] 8 , if dummy trenches 28 are provided in FWD region 22 but no trenches 6 are provided, the peripheral gate runner provided in first region 43 cannot connect gate electrode 8 in IGBT region 21 in third region 41 to gate electrode pad 33. As shown in FIG. 9C , if poly runner 27 is provided between IGBT region 21 and FWD region 22 and is not extended to first region 43 to connect to the peripheral gate runner, poly runner 27 is placed in IGBT region 21 and extended to first region 43 to connect to the peripheral gate runner.

[0072] FIG. 9C is an enlarged top view of region S2 of Example 4 of the semiconductor device according to the embodiment. As described above, a structure in which poly runner 27 is placed within IGBT region 21 may be used. However, this is not limiting. For example, IGBT regions 21 arranged in the y direction with poly runner 27 sandwiched therebetween may have the same configurations of poly runner 27, trench 6, and dummy trench 28 as those shown in FIGS. 7B and 7C , or other configurations. Furthermore, the structure in which poly runner 27 is placed within IGBT region 21 is not limited to cases in which a trench is not used to separate IGBT region 21 and FWD region 22, and poly runner 27 is not placed therebetween. It may also be applied to cases where a different boundary exists. Furthermore, this is not limited to Example 4 shown in FIG. 8 , but may also be applied to the examples shown in FIGS. 1 , 4 , 5 , and 6 .

[0073] 9D is a different example of an enlarged top view of region S1 of Example 2 of the semiconductor device according to the embodiment. FIG. 9D is a top view of a structure in which the trench 6 is not isolated. In this manner, the IGBT region 21 and the FWD region 22 may have the same trench 6 and dummy trench 28. However, the FWD is affected by gate operation. In this case, the gate electrode 8 in the IGBT region 21 can be connected to the gate electrode pad 33 without disposing a poly runner 27 in the IGBT region 21 as shown in FIG. 9C.

[0074] The region in contact with the IGBT region 21 in the y direction may be entirely formed as an ineffective region, rather than as a normal FWD region 22. In this case, it is not necessary to separate the trench 6 at the boundary of the IGBT region 21, i.e., at the boundary between the effective IGBT region and the ineffective region, and the trench 6 may be extended and connected to the gate runner provided in the first region 43 on the periphery.

[0075] As an example of a semiconductor device according to another embodiment, the second region 42 and the first region 43 may not be provided with an effective IGBT region 21 regardless of the lifetime control region 26. That is, only the dummy trench 28 is formed on the front surface, and the n-type IGBT region 21 is not formed on the front surface. + The p-type base region 2 or p-type emitter region 3 is not provided. + The back surface is p + In the third region 41, an effective IGBT region 21 may not be provided in a region close to the second region 42 that is heavily influenced by the barrier metal, and an effective IGBT region 21 may be provided in a region close to the third region 41 that is lightly influenced by the barrier metal. In addition, an effective FWD region 22 may not be provided in the second region 42.

[0076] 10 is a top view of another structure of a semiconductor device according to an embodiment. In this example, a plurality of third regions 41 are provided in the opening of the emitter electrode pad, with second regions 42 provided between them. That is, each second region 42 is not provided in a ring shape, but in a mesh shape. In this case, too, the provision of the third regions 41 reduces the amount of barrier metal and hydrogen absorption, thereby suppressing a decrease in the threshold voltage.

[0077] (Manufacturing Method of Semiconductor Device According to the Embodiment) Next, a manufacturing method of a semiconductor device according to the embodiment will be described. The manufacturing method shown below is an example and is not limited to the contents thereof. The order of steps may be changed as appropriate, or the materials used may be changed as appropriate. In addition, if a temperature sensing diode or the like is provided, other appropriate manufacturing steps may be added. First, n-type semiconductor substrate 30 is formed. - n-type semiconductor wafer 10 - Forming the n-type drift region 1. - n-type drift region 1 - A molded semiconductor wafer 10 may be prepared. The material of the semiconductor wafer 10 may be silicon (Si), diamond (C), or a compound semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or digallium trioxide (GaO). The following description will be given taking the case where the semiconductor wafer 10 is a silicon wafer as an example.

[0078] First, the front surface of the semiconductor wafer 10 is thermally oxidized to form a field oxide film covering the front surface of the semiconductor wafer 10 in the edge termination region. Next, a set of photolithography and ion implantation steps is repeatedly performed under different conditions to form a surface device structure including a MOS structure on the front surface side of the semiconductor wafer 10. For example, first, the p-type base region 2 of the IGBT, n-type + type emitter region 3 and p + The p-type contact region 4 is formed on the n-type semiconductor layer 1. The p-type base region 2 is formed on the entire surface of the active region, from the IGBT region 21 to the FWD region 22. The p-type base region 2 also serves as a p-type anode region in the FWD region 22. + type emitter region 3 and p+ The p-type contact region 4 is selectively formed inside the p-type base region 2 in the IGBT region 21. In addition, p-type contact regions are formed in the edge termination region, the poly runner 27, the termination of the trench 6, etc. + A mold well region 29 may be selectively formed.

[0079] The semiconductor wafer 10 has a p-type base region 2 and an n-type field stop (FS) layer 12 (described later), + collector region 13 and n + The portion other than the cathode region 14 is n - In the IGBT region 21, - An n-type accumulation layer 5 may be formed between the n-type drift region 1 and the p-type base region 2. The n-type accumulation layer 5 accumulates n-type charge when the IGBT is turned on. - It acts as a barrier to minority carriers (holes) in the n-type drift region 1, - The type drift region 1 has a function of accumulating minority carriers.

[0080] Next, photolithography and etching are performed to form n-type GaN films in the IGBT region 21. + The n-type emitter region 3, the p-type base region 2, and the n-type accumulation layer 5 are - Trenches 6 are formed so as to reach the type drift region 1. When viewed from the front surface side of the semiconductor wafer 10, the trenches 6 are arranged in a stripe-like layout extending in a direction (depth direction in FIG. 3 ) perpendicular to the direction in which the IGBT region 21 and the FWD region 22 are aligned (horizontal direction in FIG. 3 ).

[0081] The trenches 6 are also formed in the FWD region 22 in the same layout as in the IGBT region 21. In the FWD region 22, the trenches 6 penetrate the p-type base region 2 (p-type anode region) to form n-type trenches. - The gate insulating film 7 reaches the mold drift region 1. Next, the gate insulating film 7 is formed along the inner wall of the trench 6 by, for example, thermal oxidation.

[0082] Next, a polysilicon (poly-Si) film is formed on the front surface of the semiconductor wafer 10 so as to fill the trenches 6. Next, this polysilicon film is etched back, for example, to leave the portion that will become the gate electrodes 8 inside the trenches 6. Alternatively, photolithography and etching may be used to leave the poly runners 27 and the underlying gate insulating film 7 on the front surface of the semiconductor wafer 10. After this etching, channel ions may be implanted into the p-type base regions 2.

[0083] Next, n + type emitter region 3, p + An n-type contact region 4 and an n-type accumulation layer 5 may be formed. + The n-type emitter region 3 may be disposed in at least one mesa region between adjacent trenches 6 (mesa regions). + There may be a mesa region in which the n-type emitter region 3 is not disposed. + The emitter regions 3 may be selectively arranged at predetermined intervals in the direction in which the trenches 6 extend in a stripe shape.

[0084] Next, after forming the surface device structure, an interlayer insulating film 9 made of two layers, for example, a BPSG film and an HTO film, is formed on the front surface of the semiconductor wafer 10 so as to cover the gate electrode 8. Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes 20 penetrating the interlayer insulating film 9 in the depth direction. The depth direction is the direction from the front surface to the back surface of the semiconductor wafer 10. The contact holes 20 in the IGBT region 21 are provided with n + type emitter region 3 and p + The p-type contact region 4 is exposed. The p-type base region 2 is exposed in the contact hole 20 of the FWD region 22. + A high concentration p-type plug region may be formed on the top surface of the p-type contact region 4 and the p-type base region 2 by further ion implantation.

[0085] Next, a Ti film 17 is formed uniformly in the contact hole 20 and on the surface of the interlayer insulating film 9 by sputtering. Next, a TiN film 18 is formed on the surface of the Ti film 17 by sputtering. As a result, a barrier metal 25 is stacked on the interlayer insulating film 9 and in the contact hole 20. Next, the Ti film 17 on the bottom surface of the contact hole 20 is silicided by heat treatment (annealing) to form a titanium silicide film 55.

[0086] Next, the surface of the TiN film 18 and the inside of the contact hole 20 are filled with a contact plug by, for example, CVD. Next, the contact plug outside the contact hole 20 is removed by etching, and a plug electrode 15 is formed inside the contact hole 20. Note that this step may be omitted if the plug electrode 15 is formed with the same composition as the front surface electrode 11 to be formed later.

[0087] Next, the barrier metal 25 on the interlayer insulating film 9 is patterned so as to remain only near the polyimide film 31 to be formed later. As a result, the barrier metal 25 remains on the interlayer insulating film 9 in the second region 42 and the first region 43, but does not remain on the interlayer insulating film 9 in the third region 41. At this time, the interlayer insulating film 9 may also be partially etched in the third region 41. If the interlayer insulating film 9 also contains a region into which impurity ions forming a plug region have been implanted, this region may also be removed. The contact plug may be left above the interlayer insulating film 9, and patterning may be performed simultaneously with the contact plug and the barrier metal 25, or may be performed separately. If the contact plug is not formed in the contact hole 20, the barrier metal 25 in the contact hole 20 may also be removed in the third region 41, and the silicide at the bottom of the contact hole 20 may or may not remain.

[0088] Next, an Al metal film that will become the front electrode 11 is formed by, for example, sputtering. The Al metal film may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the Al metal film is patterned. Next, the patterned Al metal film is annealed in a hydrogen atmosphere to form the front electrode 11.

[0089] The front surface electrode 11 is connected to the p-type base region 2 and the n-type + type emitter region 3 and p + The front surface electrode 11 is electrically connected to the p-type contact region 4 and functions as an emitter electrode. The front surface electrode 11 is electrically connected to the p-type base region 2 in the FWD region 22 and functions as an anode electrode. + The p-type emitter region 3 may be electrically connected to the p-type base region 2 in the mesa region where the p-type emitter region 3 is not disposed.

[0090] Next, the semiconductor wafer 10 is ground from the backside to a thickness corresponding to the thickness of the semiconductor device. Next, a set of photolithography and ion implantation processes is repeatedly performed under different conditions to form a backside device structure on the backside of the semiconductor wafer 10. For example, an n-type field stop (FS) layer 12, an n-type field stop (FS) layer 13, and an n-type field stop (FS) layer 14 are formed on the backside of the semiconductor wafer 10. + type cathode region 14 and p + A mold collector region 13 is formed.

[0091] p + The n-type collector region 13 is formed in the surface layer of the back surface of the semiconductor wafer 10 after grinding, over the entire back surface of the semiconductor wafer 10. The n-type field stop layer 12 is formed in the p-type field stop layer 12 from the back surface of the semiconductor wafer 10 after grinding. + The n-type field stop layer 12 is formed at a position deeper than the p-type collector region 13. The n-type field stop layer 12 is formed at least from the IGBT region 21 to the FWD region 22. The n-type field stop layer 12 is formed at a position deeper than the p-type collector region 13. + It may be in contact with the mold collector region 13 .

[0092] Next, p + The part of the collector region 13 corresponding to the FWD region 22 is n + By changing it to the type + The n-type cathode region 14 is formed. + The cathode region 14 has a p-type + contacts the collector region 13. +The cathode region 14 may be in contact with the n-type field stop layer 12 in the depth direction. + collector region 13,n + type cathode region 14 and n + This activates the ion field-stop layer 12. Annealing may be performed separately for each ion implantation.

[0093] Next, a polyimide film (passivation film) 31 is formed on the front surface of the semiconductor wafer 10. Next, the passivation film is patterned to expose the emitter electrode pad and each electrode pad. The polyimide film 31 may cover an edge termination region, etc. The polyimide film 31 is selectively left in the region where the barrier metal 25 remains on the interlayer insulating film 9, so as to recede a predetermined width from the boundary where the barrier metal 25 does not remain on the interlayer insulating film 9. As a result, a first region 43, a second region 42, and a third region 41 are formed. Instead of the polyimide film 31, a silicon nitride film or the like may be used as the passivation film.

[0094] Next, a photoresist film (not shown) having openings corresponding to the lifetime control regions 26 is formed on the front surface of the semiconductor wafer 10. Using this photoresist film as a mask (shielding film), helium is irradiated with high acceleration energy and a deep range to form n - A lifetime control region 26 may be formed by introducing (forming) lattice defects that act as lifetime killers into the mold drift region 1. In another example, lifetime control may be performed on the entire wafer or a part of the wafer by irradiating the backside of the semiconductor wafer 10 with helium at a high acceleration energy and a deep range, or lifetime control may be performed on the entire wafer by using a particle beam, such as an electron beam, that easily penetrates the semiconductor wafer 10.

[0095] Then, the photoresist film is removed by ashing. Annealing may be performed to partially repair defects in the lifetime control region 26 and adjust the lifetime. Next, a back electrode 24 is formed on the entire back surface of the semiconductor wafer 10. The back electrode 24 is p + collector region 13 and n +The back electrode 24 functions as a collector electrode and also as a cathode electrode. The semiconductor wafer 10 is then cut (diced) into individual chips, thereby completing the RC-IGBT 150 chips (semiconductor chips).

[0096] 11A to 11J are cross-sectional views along the line A-A' of another structure of a semiconductor device according to an embodiment. FIG. 11A shows an example of a method for reducing Ti in the exposed portion (third region 41) of the front electrode 11 away from the boundary of the polyimide film 31. A barrier metal 25 consisting of a titanium silicide film 55 and a TiN film 18 is provided on the interlayer insulating film 9. Polysilicon or a thin Ti film may be formed in contact with the titanium silicide film 55. An alloy film with other semiconductor materials may also be used. When a metal other than Ti that absorbs hydrogen is used, an alloy film of the other metal may also be used. In the structure of FIG. 11A, the titanium silicide film 55 is formed by reacting a Ti film 17 with polysilicon or the like on the surface of the interlayer insulating film 9. In this case, the amount of elemental Ti in the barrier metal 25 remaining on the interlayer insulating film 9 is small, resulting in less hydrogen absorption by Ti and a reduced threshold voltage drop. Note that a Ti film 17 may be formed on the sidewall of the contact hole 20 in the third region 41. In another example, a titanium silicide film 55 may be provided on the sidewall of the contact hole 20 in the third region 41 instead of the Ti film 17 .

[0097] The structure of FIG. 11A can be fabricated as follows. Differences from the manufacturing method of the structure of FIG. 2 described above will be described below, and similar steps will be omitted. First, an interlayer insulating film 9 is formed. Next, polysilicon is deposited. Next, the polysilicon is patterned and removed from the second region 42 and the first region 43. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a high-concentration p-type plug region. Next, a Ti film 17 and a TiN film 18 are formed by sputtering and then annealed. In the third region 41, since polysilicon is also present on the interlayer insulating film 9, the Ti film 17 reacts with Si to form a titanium silicide film 55. Unreacted polysilicon or the Ti film 17 may be left. Next, a contact plug is formed in the contact hole 20 and on the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, the front surface electrode 11 is formed. Alternatively, after forming the interlayer insulating film 9, the contact hole 20 may be formed, and then polysilicon may be deposited and patterned to remove the polysilicon in the second region 42 and the first region 43. In this case, since polysilicon is also present on the side wall of the contact hole 20 in the third region 41, a titanium silicide film 55 is formed on the side wall of the contact hole 20.

[0098] 11A, if the titanium silicide film 55 and the TiN film 18 on the interlayer insulating film 9 in the third region 41 are removed, the structure becomes the same as that in Fig. 2. If the titanium silicide film 55 is formed on the sidewall of the contact hole 20 in the third region 41 without the Ti film 17, the amount of Ti in the third region 41 can be further reduced.

[0099] 11B shows an example of a method for eliminating Ti in the exposed portion (third region 41) of the front surface electrode 11 away from the boundary of the polyimide film 31. In the third region 41, no barrier metal 25 is provided on the interlayer insulating film 9, and a barrier metal 25 made of a titanium silicide film 55 and a TiN film 18 is provided in the second region 42. That is, the configuration of the second region 42 in the structure of FIG. 11B is the same as the configuration of the third region 41 in the structure of FIG. 11A. In this case, too, because there is little Ti in the barrier metal 25 remaining on the interlayer insulating film 9, hydrogen absorption by Ti is reduced, and the threshold voltage drop is alleviated.

[0100] The structure of FIG. 11B can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, polysilicon is deposited. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a high-concentration p-type plug region. Next, a Ti film 17 and a TiN film 18 are formed by sputtering and annealed. The Ti film 17 reacts with Si to form a titanium silicide film 55. Next, a contact plug is formed on the contact hole 20 and the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, the titanium silicide film 55 and the TiN film 18 are patterned, and the titanium silicide film 55 and the TiN film 18 are removed by etching in the third region 41. Next, a front electrode 11 is formed. Note that polysilicon deposition may be performed after the formation of the contact hole 20, as described in the fabrication method of the structure of FIG. 11A.

[0101] A similar structure can be formed, except for the structure inside the contact hole 20 in the third region 41, by forming the barrier metal 25 composed of the titanium silicide film 55 and the TiN film 18 on the interlayer insulating film 9 in the second region 42 and then removing the Ti film 17 and the TiN film 18 on the interlayer insulating film 9 in the third region 41. Even if only the TiN film 18 on the interlayer insulating film 9 in the third region 41 is removed and the titanium silicide film 55 remains, the amount of Ti in the barrier metal 25 remaining on the interlayer insulating film 9 is small, resulting in less hydrogen absorption by Ti and a reduction in threshold voltage drop. In this case, an oxide film or the like may be formed on the surface of the titanium silicide film 55 on the interlayer insulating film 9 in the third region 41 due to the removal of the TiN film 18.

[0102] FIG. 11C shows an example of a method for reducing Ti in the exposed portion (third region 41) of the front electrode 11 away from the boundary of the polyimide film 31. A barrier metal 25 consisting of only a TiN film 18 is provided on the interlayer insulating film 9. Furthermore, the sidewall of the contact hole 20 in the third region 41 is provided with only the TiN film 18, without the Ti film 17. In the structure shown in FIG. 11C, the Ti film 17 reacts with silicon at the bottom of the contact hole 20 to form a titanium silicide film 55, and then the Ti film 17 is removed from the third region 41. This also results in less elemental Ti remaining in the barrier metal 25 on the interlayer insulating film 9, resulting in less hydrogen absorption by Ti and a reduced threshold voltage drop. In the third region 41, an oxide film or the like may be formed on the surface of the titanium silicide film 55 at the bottom of the contact hole 20 following the removal of the Ti film 17.

[0103] The structure of FIG. 11C can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a high-concentration p-type plug region. Next, a Ti film 17 is formed by sputtering and annealed. Next, the Ti film 17 is patterned, and in the third region 41, the Ti film 17 on the interlayer insulating film 9 and in the contact hole 20 is removed by etching, leaving behind the titanium silicide film 55 at the bottom of the contact hole 20. Next, a TiN film 18 is formed by sputtering. Next, a contact plug is formed in the contact hole 20 and on the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, a front electrode 11 is formed.

[0104] 11C, if the TiN film 18 on the interlayer insulating film 9 in the third region 41 is removed, the structure will be the same as that in FIG. 2, except that there is no Ti film 17 on the sidewall of the contact hole 20 in the third region 41. This structure may be used when it is desired to reduce Ti as much as possible in the third region 41.

[0105] 11D shows an example of a method for eliminating Ti in the exposed portion (third region 41) of the front surface electrode 11 away from the boundary of the polyimide film 31, in which no barrier metal 25 is provided in the third region 41, and a barrier metal 25 made of a TiN film 18 is provided in the second region 42. That is, the configuration of the second region 42 in the structure of FIG. 11D is the same as the configuration of the third region 41 in the structure of FIG. 11C. In this case as well, because there is little elemental Ti in the barrier metal 25 remaining on the interlayer insulating film 9, hydrogen absorption by Ti is reduced, and the threshold voltage drop is alleviated.

[0106] The structure of FIG. 11D can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a high-concentration p-type plug region. Next, a Ti film 17 is formed by sputtering and annealed. Next, the Ti film 17 on the interlayer insulating film 9 and in the contact hole 20 is removed by etching, leaving the titanium silicide film 55 at the bottom of the contact hole 20. Next, a TiN film 18 is formed by sputtering. Next, a contact plug is formed on the TiN film 18 in the contact hole 20 and on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, the TiN film 18 is patterned, and the TiN film 18 in the third region 41 is removed by etching. Next, a front electrode 11 is formed.

[0107] In the second region 42, the Ti film 17 is removed and a TiN film 18 is formed on the interlayer insulating film 9, and in the third region 41, the Ti film 17 and the TiN film 18 on the interlayer insulating film 9 are removed, thereby forming a similar structure except for the configuration inside the contact hole 20 in the third region 41.

[0108] 11E shows an example of a method for reducing Ti in the exposed portion (third region 41) of the front electrode 11 away from the boundary of the polyimide film 31. A barrier metal 25 consisting of only a TiN film 18 is provided on the interlayer insulating film 9. In this case, too, the amount of elemental Ti remaining in the barrier metal 25 on the interlayer insulating film 9 is small, so hydrogen absorption by Ti is reduced, and the threshold voltage drop is alleviated. In the structure of FIG. 11E , the Ti film 17 and the TiN film 18 are formed on the interlayer insulating film 9, and then the Ti film 17 and the TiN film 18 are removed in the third region 41, and the TiN film 18 is formed again. The TiN film 18 may or may not be formed on the plug electrode 15. In the second region 42, a barrier metal 25 consisting of the Ti film 17 and the thick TiN film 18 is provided on the interlayer insulating film 9. 11E is one of the structures that is effective when, when forming a barrier metal 25 in the second region 42 to prepare for defects in the front surface electrode 11, it is desired to provide a certain amount of barrier metal 25 in the third region 41 to prevent the front surface electrode 11 from diffusing into the semiconductor wafer 10. Note that, in Figures 11A and 11C as well, the TiN film 18 is provided in the third region 41, thereby achieving the same effect.

[0109] The structure of FIG. 11E can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a high-concentration p-type plug region. Next, a Ti film 17 and a TiN film 18 are formed by sputtering and annealed. Next, a contact plug is formed on the contact hole 20 and the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, the Ti film 17 and the TiN film 18 are patterned, and the TiN film 18 on the interlayer insulating film 9 in the third region 41 is removed by etching. Next, a TiN film 18 is formed by sputtering. Next, a front surface electrode 11 is formed. The TiN film 18 on the plug electrode 15 may be removed before the front surface electrode 11 is formed.

[0110] 11F shows the structure of FIG. 11E from which the TiN film 18 re-deposited in the second region 42 has been removed. If the Ti film 17 and TiN film 18 deposited before the formation of the plug electrode 15 in the second region 42 provide sufficient ion shielding capability, the re-deposited TiN film 18 may be removed to further reduce hydrogen absorption. The TiN film 18 may or may not be formed on the plug electrode 15 in the third region 41. The TiN film 18 on the plug electrode 15 in the third region 41 may be removed when etching the TiN film 18 on the interlayer insulating film 9 in the second region 42. On the other hand, FIG. 11G shows the structure of FIG. 11E from which the TiN film 18 re-deposited in the third region 41 has been removed. If the barrier metal 25 is not required on the interlayer insulating film 9 in the third region 41, but a thick barrier metal 25 is desired to be formed in the second region 42, hydrogen absorption may be reduced by leaving the TiN film 18 deposited again only in the second region 42. The TiN film 18 may or may not be formed on the plug electrode 15 in the second region 42. The TiN film 18 on the plug electrode 15 in the second region 42 may be removed simultaneously with the TiN film 18 on the interlayer insulating film 9 in the third region 41.

[0111] 11H shows that in the exposed portion (third region 41) of the front surface electrode 11 away from the boundary of the polyimide film 31, a barrier metal 25 made of a thin Ti film 17 and a TiN film 18 is provided on the interlayer insulating film 9. In this example, as in the example shown in FIG. 11E , the Ti film 17 and the TiN film 18 may or may not be formed on the plug electrode 15. In the second region 42, a barrier metal 25 is provided on the interlayer insulating film 9, in which the Ti film 17, the TiN film 18, the Ti film 17, and the TiN film 18 are stacked in this order. For example, the thickness of the thin Ti film 17 on the interlayer insulating film 9 in the third region 41 is preferably 50% or less of the thickness of the lowest Ti film 17 on the interlayer insulating film 9 in the second region 42. For example, the thickness of the Ti film 17 on the interlayer insulating film 9 in the third region 41 is preferably 20 nm or less. In this case, too, the amount of elemental Ti in the barrier metal 25 remaining on the interlayer insulating film 9 is small, so hydrogen absorption by Ti is reduced, and the threshold voltage drop is alleviated. The structure of Figure 11H includes the Ti film 17, so it can improve ion shielding ability compared to the structure of Figure 11E in which only the TiN film 18 is formed again. Also, the TiN film 18 may be formed before the Ti film 17 is formed again, i.e., the films may be formed in the order TiN / Ti / TiN.

[0112] The structure shown in FIG. 11H can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a highly-doped p-type plug region. Next, a Ti film 17 and a TiN film 18 are formed by sputtering and annealed. Next, a contact plug is formed on the contact hole 20 and the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, the Ti film 17 and the TiN film 18 are patterned, and in the third region 41, the Ti film 17 and the TiN film 18 are removed by etching on the interlayer insulating film 9. Next, thin Ti films 17 and TiN films 18 are formed by sputtering. Next, a front surface electrode 11 is formed. The Ti film 17 and the TiN film 18 on the plug electrode 15 may be removed before the front surface electrode 11 is formed.

[0113] 11H , the Ti film 17 and TiN film 18 deposited again in the second region 42 may be removed. That is, a structure in which thin Ti film 17 and TiN film 18 are formed instead of the TiN film 18 deposited again in FIG. 11F may be used. If the Ti film 17 and TiN film 18 deposited before the formation of the plug electrode 15 in the second region 42 provide sufficient ion shielding capability, the thin Ti film 17 and TiN film 18 deposited again may be removed to further reduce hydrogen absorption. On the other hand, the Ti film 17 and TiN film 18 deposited again in the third region 41 may be removed from the structure in FIG. 11H , that is, a structure in which Ti film 17 and TiN film 18 are formed instead of the TiN film 18 deposited again in FIG. 11G may be used. If the barrier metal 25 is not required on the interlayer insulating film 9 in the third region 41, but a thick barrier metal 25 is desired to be formed in the second region 42, hydrogen absorption may be reduced by leaving the Ti film 17 and TiN film 18 deposited again only in the second region 42. Since a problem may occur at the bottom of the contact hole 20 if the Ti film 17 deposited before the formation of the plug electrode 15 is made too thick, this problem can be avoided by depositing the Ti film 17 again after the formation of the plug electrode 15. In this case, the thickness of the Ti film 17 deposited again after the formation of the plug electrode 15 may be thicker than the thickness of the Ti film 17 deposited before the formation of the plug electrode 15.

[0114] FIG. 11I shows an example of a method for reducing Ti in the exposed portion (third region 41) of the front electrode 11 away from the boundary of the polyimide film 31. In this example, as in the example shown in FIG. 11E , the TiN film 18 and the tungsten film 56 may or may not be formed on the plug electrode 15. As another example, metals such as Ta and Ni may be used, or their nitrides may be used. The structure of FIG. 11I includes the tungsten film 56, thereby improving ion shielding capability compared to the structure of FIG. 11E , in which only the TiN film 18 is formed again. Alternatively, hydrogen absorption may be reduced by forming only the tungsten film 56 without forming the TiN film 18. In this case, too, the amount of elemental Ti in the barrier metal 25 remaining on the interlayer insulating film 9 is small, resulting in less hydrogen absorption by Ti and a reduced threshold voltage drop.

[0115] The structure shown in FIG. 11I can be fabricated as follows. First, an interlayer insulating film 9 is formed. Next, a contact hole 20 is formed. Next, impurity ions may be implanted into the bottom of the contact hole 20 and annealed to form a highly-doped p-type plug region. Next, a Ti film 17 and a TiN film 18 are formed by sputtering and annealed. Next, a contact plug is formed on the contact hole 20 and the TiN film 18 on the interlayer insulating film 9. Next, the contact plug on the interlayer insulating film 9 is removed, and a plug electrode 15 is formed in the contact hole 20. Next, in the third region 41, the Ti film 17 and the TiN film 18 on the interlayer insulating film 9 are removed by etching, and the TiN film 18 and a tungsten film 56 are formed by sputtering. Next, a front electrode 11 is formed. The TiN film 18 and the tungsten film 56 on the plug electrode 15 may be removed before the front electrode 11 is formed.

[0116] 11I, the TiN film 18 and the tungsten film 56 formed in the second region 42 may be removed. That is, the TiN film 18 and the tungsten film 56 may be formed instead of the TiN film 18 formed again in FIG. 11F. If the Ti film 17 and the TiN film 18 formed before the formation of the plug electrode 15 in the second region 42 provide sufficient ion shielding capability, the TiN film 18 and the tungsten film 56 may be removed to further reduce hydrogen absorption. On the other hand, the TiN film 18 and the tungsten film 56 formed in the third region 41 may be removed from the structure of FIG. 11I. That is, the TiN film 18 and the tungsten film 56 may be formed instead of the TiN film 18 formed again in FIG. 11G. In the third region 41, no barrier metal 25 is required on the interlayer insulating film 9, but if it is desired to form a thick barrier metal 25 in the second region 42, hydrogen absorption can be reduced by leaving the TiN film 18 and tungsten film 56 formed only in the second region 42.

[0117] 11J shows that in a fourth region 44 below the polyimide film 31 and away from the boundary of the polyimide film 31, i.e., in the fourth region 44 below the polyimide film 31 and not adjacent to the second region 42, similar to the exposed portion (third region 41) of the front surface electrode 11 away from the boundary of the polyimide film 31, no barrier metal 25 is provided on the surface of the interlayer insulating film 9 covered by the front surface electrode 11. In this case, too, the amount of elemental Ti in the barrier metal 25 remaining on the interlayer insulating film 9 is small, so that hydrogen absorption by Ti is reduced and the threshold voltage drop is alleviated. Examples of methods for reducing Ti in the third region 41 and the fourth region 44 may be the examples of methods for reducing Ti in the third region 41 described using FIG. 2 and FIGS. 11A to 11I.

[0118] In addition, the structure of Figure 11J can be produced by the above-mentioned manufacturing method by not forming the Ti film 17 in the fourth region 44, as in the third region 41, or by forming a Ti film 17 that is thinner than those in the first region 43 and the second region 42.

[0119] FIG. 12 is a top view of a semiconductor device according to an embodiment when mounted. As shown in FIG. 12 , in this example, a region of the emitter electrode pad where a connection portion 62 to which a wire wiring portion 61 is connected (hereinafter referred to as a bonding region) is provided is provided in the third region 41, not in the second region 42. The connection portion 62 may be a part of the wire wiring portion 61. The wire wiring portion 61 may be ultrasonically bonded to the upper surface of the front electrode 11 at the connection portion 62. In FIG. 12 , as in FIG. 4 , the second region 42 is provided in an annular shape in the opening of one emitter electrode pad, and one third region 41 is provided inside the second region 42. However, this is not limiting, and for example, even in a semiconductor device arranged as shown in FIG. 10 , the bonding region may be provided in the third region 41, not in the second region 42.

[0120] In the second region 42, a Ti film 17 is present between the front surface electrode 11 and the interlayer insulating film 9, but the adhesion between the Ti film 17 and the interlayer insulating film 9 is poor. Therefore, when bonding is performed in the second region 42, the Ti film 17 may peel off due to an impact caused by a wire wiring, which may result in peeling of the front surface electrode 11. In another example, in the second region 42, the implantation of impurity ions to form a plug region is also performed in the interlayer insulating film 9 in some places, which may result in poor adhesion between the barrier metal 25 and the interlayer insulating film 9. Therefore, when bonding is performed in the second region 42, the barrier metal 25 may peel off due to an impact caused by a wire wiring, which may result in peeling of the front surface electrode 11. Furthermore, even if the front surface electrode 11 does not peel off, peeling of the barrier metal 25 may cause a defect 34, resulting in a decrease in the threshold voltage.

[0121] In the third region 41, the front surface electrode 11 is formed directly on the interlayer insulating film 9, which improves adhesion between the front surface electrode 11 and the interlayer insulating film 9 compared to when the front surface electrode 11 is formed via the Ti film 17, and prevents peeling of the front surface electrode 11 due to impacts associated with wire wiring. In another example, the Ti film 17 is not present in the third region 41, and the TiN film 18 is formed on the interlayer insulating film 9, which improves adhesion between the TiN film 18 and the interlayer insulating film 9 compared to when the TiN film 18 is formed via the Ti film 17, and prevents peeling of the barrier metal 25 and the front surface electrode 11 due to impacts associated with wire wiring. In another example, the third region 41 undergoes a process of removing the barrier metal on the interlayer insulating film 9, and the portions of the interlayer insulating film 9 where the implantation of impurity ions to form the plug region is also performed are removed during this process. As a result, the adhesion between the barrier metal 25 or the front surface electrode 11 and the interlayer insulating film 9 is improved compared to when the front surface electrode 11 is formed via the Ti film 17 formed before the formation of the plug electrode 15, and peeling of the barrier metal 25 or the front surface electrode 11 due to impacts associated with wire wiring does not occur.

[0122] As described above, by providing the bonding region in the third region 41 and not in the second region 42, peeling of the barrier metal 25 and the front surface electrode 11 and a decrease in the threshold voltage due to the impact caused by the wire wiring do not occur.

[0123] 13A to 13C are cross-sectional views showing the structure in the vicinity of the gate electrode pad 33 of the semiconductor device according to the embodiment. The structures in the vicinity of pads other than the front surface electrode pads through which the main current flows (e.g., emitter electrode pads and source electrode pads) are shown. A similar structure may be used when a pad other than the gate electrode pad, such as a pad for the temperature sensing / protection diode wiring, is included.

[0124] 13A shows the structure in the vicinity of the gate electrode pad 33. In this example, no contact hole 20 is provided in the interlayer insulating film 9 under the gate electrode pad 33, and the semiconductor wafer 10 and the front surface electrode 11 are not connected. In this example, the front surface electrode 11 may be a gate runner. In the gate electrode pad 33, too, a barrier metal 25 is provided between the interlayer insulating film 9 and the front surface electrode 11 in a second region 42 close to the polyimide film 31, but a barrier metal 25 is not required between the interlayer insulating film 9 and the front surface electrode 11 in a third region 41 away from the boundary of the polyimide film 31. As a result, hydrogen absorption by the barrier metal 25 can be reduced, thereby suppressing a decrease in the threshold voltage.

[0125] 13B shows another structure near the gate electrode pad 33. In this example, a contact hole 20 is provided in the interlayer insulating film 9 below the gate electrode pad 33, and the front electrode 11 is connected to a polysilicon (polycrystalline portion) runner 27 provided on the semiconductor wafer 10 via an insulating film 19. The insulating film 19 and the polysilicon runner 27 may be formed simultaneously with the gate insulating film 7 and the gate electrode 8, or may be formed separately. In the gate electrode pad 33 of this example, a barrier metal 25 is provided between the interlayer insulating film 9 and the front electrode 11 in a second region 42 close to the polyimide film 31, but the barrier metal 25 is not required between the interlayer insulating film 9 and the front electrode 11 in a third region 41 away from the boundary of the polyimide film 31. As a result, hydrogen absorption by the barrier metal 25 is reduced, thereby suppressing a decrease in the threshold voltage.

[0126] 13C shows another structure near the gate electrode pad 33. In this example, a contact hole 20 is provided in the interlayer insulating film 9 below the gate electrode pad 33, and the front electrode 11 is connected to a gate electrode 8 made of polysilicon (polycrystalline portion) provided within a trench 6 provided in the semiconductor wafer 10 via a gate insulating film 7. The trench 6 may extend directly to the active region, or it may not extend to the active region. In this example, the gate electrode pad 33 also has a barrier metal 25 between the interlayer insulating film 9 and the front electrode 11 in a second region 42 close to the polyimide film 31, but does not need to have a barrier metal 25 between the interlayer insulating film 9 and the front electrode 11 in a third region 41 away from the boundary of the polyimide film 31. As a result, hydrogen absorption by the barrier metal 25 can be reduced, thereby suppressing a decrease in the threshold voltage.

[0127] The examples shown in Figures 13A to 13C are described using examples of structures similar to the structure near the active region shown in Figure 2, but structures similar to the structures described using Figures 11A to 11J may also be applied to the vicinity of the gate electrode pad 33.

[0128] The example shown in FIGS. 13A to 13C may be fabricated in the same manner as the fabrication method of the structure in the vicinity of the active region shown in FIGS. 2 and 11A to 11J.

[0129] Similarly, in the gate electrode pad 33, the region to be bonded during mounting may be provided in the third region 41 rather than in the second region 42. As a result, the adhesion between the front surface electrode 11 or the barrier metal 25 and the interlayer insulating film 9 is improved in the vicinity of the connection portion 62, and peeling of the front surface electrode 11 or the barrier metal 25 is prevented.

[0130] As described above, according to the embodiment, the barrier metal that absorbs hydrogen is not left over the entire surface between the interlayer insulating film and the front electrode of the semiconductor device, but is left only near the polyimide film, or is left less in areas away from the polyimide film. As a result, there is less Ti in the barrier metal remaining on the interlayer insulating film, which reduces hydrogen absorption by Ti and alleviates threshold voltage drops. This allows semiconductor devices to be manufactured with desirable characteristics and yields.

[0131] In the above, the present disclosure has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon substrate. However, this is not a limitation, and various changes are possible for the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, and the like. Furthermore, while the embodiments of the present disclosure have been described using a trench IGBT as an example, this is not a limitation, and the present disclosure is applicable to semiconductor devices with various configurations, such as MOS semiconductor devices such as trench MOSFETs. Furthermore, in each embodiment of the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0132] As described above, the semiconductor device according to the present disclosure is useful as a high-voltage semiconductor device used in power conversion devices and power supply devices for various industrial machines.

[0133] 1, 101 n - n-type drift region 2, 102 p-type base region 3 + Type emitter region 4p + 1. Type contact region 5: n-type accumulation layer 6, 106: trench 7, 107: gate insulating film 8, 108: gate electrode 9, 109: interlayer insulating film 10: semiconductor wafer 11, 111: front electrode 12: n-type field stop layer 13: p + Mold collector region 14 n + 1. Mold cathode region 15, 115 Plug electrode 17 Ti film 18 TiN film 19 Insulating film 20, 120 Contact hole 21 IGBT region 22 FWD region 24 Back electrode 25, 125 Barrier metal 26 Lifetime control region 27 Poly runner 28 Dummy trench 29 p + Mold well region 30, 130 Semiconductor substrate 31, 131 Polyimide film 33, 133 Gate electrode pad 34, 134 Defect 41 Third region (region where no barrier metal is left) 42 Second region (region where barrier metal is left) 43 First region (polyimide film region) 44 Fourth region (polyimide film region) 55 Titanium silicide film 56 Tungsten film 61 Wire wiring portion 62 Connection portion 150 RC-IGBT

Claims

a contact hole penetrating the interlayer insulating film to the surface of the first semiconductor layer; a top electrode selectively formed on the surface of the interlayer insulating film and in the contact hole; and a sealing film selectively formed on the top electrode and the surface of the interlayer insulating film, wherein a first barrier metal containing a first metal is provided between the top electrode and the interlayer insulating film in a first region covered by the sealing film, a second region in which the top electrode is not covered by the sealing film and adjacent to the first region, and a third region in which the top electrode is not covered by the sealing film and is not adjacent to the first region but adjacent to the second region, and wherein the first barrier metal is not provided between the top electrode and the interlayer insulating film in the third region.

2. The semiconductor device according to claim 1, further comprising a second barrier metal between the upper electrode and the interlayer insulating film in the third region, the second barrier metal having a smaller hydrogen absorbing capacity than the first barrier metal.

3. The semiconductor device according to claim 2, wherein the second barrier metal does not contain the first metal or contains a smaller amount of the first metal than the first barrier metal.

4. The semiconductor device according to claim 3, wherein the second barrier metal is made of a compound film of the first metal.

5. The semiconductor device according to claim 4, wherein the compound film of the first metal is a nitride film.

6. A semiconductor device according to claim 4, wherein the compound film of the first metal includes a compound film with a semiconductor material.

7. The semiconductor device according to claim 3, wherein the first barrier metal includes a single film of the first metal, and the second barrier metal does not include a single film of the first metal or includes less of the first metal than the first barrier metal.

8. The semiconductor device according to claim 3, wherein the second barrier metal comprises a simple substance or compound film of a second metal different from the first metal.

9. A semiconductor device according to any one of claims 1 to 8, wherein the first metal is titanium.

10. The semiconductor device according to claim 1, further comprising a transistor region including: a second semiconductor layer of a second conductivity type provided on the surface of the first semiconductor layer; and a second semiconductor region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer.

11. The semiconductor device according to claim 10, wherein the transistor region is provided in the third region and not in the second region.

12. The semiconductor device according to claim 10, further comprising a lifetime control region.

13. The semiconductor device according to claim 12, wherein the lifetime control region is not provided in the transistor region in the second region.

14. The semiconductor device according to claim 13, further comprising a diode region.

15. The semiconductor device according to claim 14, further comprising an ineffective region in the second region between the diode region and the transistor region not having the lifetime control region.

16. The semiconductor device according to claim 14, wherein the diode region is provided in the third region and not in the second region.

17. The semiconductor device according to claim 14, wherein the diode region is provided in the second region and not in the third region.

18. The semiconductor device according to claim 11, further comprising a lifetime control region.

19. The semiconductor device according to any one of claims 10, 11, 12 and 18, further comprising a diode region.

20. A semiconductor device according to any one of claims 1 and 10 to 18, further comprising a trench reaching the first semiconductor layer, wherein the gate electrode is provided inside the trench via the gate insulating film.

21. The semiconductor device according to claim 1, wherein the first barrier metal is provided between the upper electrode and the interlayer insulating film in the first region.

22. The semiconductor device according to claim 21, further comprising a fourth region in contact with the first region but not adjacent to the second region in the region covered with the sealing film, wherein the first barrier metal is not provided between the upper electrode and the interlayer insulating film in the fourth region.