Semiconductor device

Abstract

A semiconductor device according to some embodiments of the concept of the present invention comprises: a first source / drain pattern and a second source / drain pattern; a first power line disposed at a lower level than the first and second source / drain patterns and electrically connected to the first source / drain pattern; an upper active contact on the second source / drain pattern; a channel structure connected to at least one of the first and second source / drain patterns; and a first pad electrically connected to the first source / drain pattern through the first power line.

Description

Technology Field

[0001] Embodiments of the concept of the present invention relate to a semiconductor device, and more specifically, to a semiconductor device including pads. Background Technology

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. The problem to be solved

[0003] Embodiments of the concept of the present invention aim to provide a semiconductor device with improved electrical characteristics and reliability and a method for manufacturing the same. means of solving the problem

[0004] A semiconductor device according to some embodiments comprises: a first source / drain pattern and a second source / drain pattern; a first power line disposed at a level lower than the first and second source / drain patterns and electrically connected to the first source / drain pattern; an upper active contact on the second source / drain pattern; a channel structure connected to at least one of the first and second source / drain patterns; and a first pad electrically connected to the first source / drain pattern through the first power line, wherein the level of the upper surface of the first pad is higher than the level of the upper surface of the upper active contact, and the level of the lower surface of the first pad may be lower than the level of the lowest portions of the first and second source / drain patterns.

[0005] A semiconductor device according to some embodiments comprises: a source / drain pattern; power lines disposed at a level lower than the source / drain pattern; an upper active contact on the source / drain pattern; a channel structure connected to the source / drain pattern; and pads electrically connected to the power lines, wherein the power lines extend in a first direction and the power lines are spaced apart from each other in a second direction, and the pads may include: a first pad and a second pad spaced apart from each other in the first direction with the power lines in between; and a third pad and a fourth pad spaced apart from each other in a second direction intersecting the first direction with the power lines in between.

[0006] A semiconductor device according to some embodiments comprises: a first source / drain pattern and a second source / drain pattern; semiconductor patterns connected to at least one of the first and second source / drain patterns; a gate electrode overlapping the semiconductor patterns; a power line positioned at a lower level than the first and second source / drain patterns; an upper active contact on the second source / drain pattern; a bump positioned at a lower level than the power line and electrically connected to the power line; a lower active contact connecting the power line and the first source / drain pattern; an upper via on the upper active contact; an upper line on the upper via; and a pad electrically connected to the first source / drain pattern through the power line and the lower active contact, wherein the distance between the upper surface and the lower surface of the pad may be greater than the distance between the upper surface of the upper line and the upper surface of the power line.

[0007] A method for manufacturing a semiconductor device according to some embodiments comprises: forming a pin pattern; forming a device isolation film on a sidewall of the pin pattern; forming a source / drain pattern on the pin pattern; forming an interlayer insulating film on the source / drain pattern; forming a lower active contact connected to the source / drain pattern; forming a power line connected to the lower active contact; forming a pad electrically connected to the power line; positioning the pad, the power line, and the source / drain pattern between a probe pin and a measuring part; applying a voltage to the pad through the probe pin; and measuring a hot electron with the measuring part, wherein the pad penetrates the interlayer insulating film and the device isolation film.

[0008] A method for manufacturing a semiconductor device, further comprising measuring the hot electrons and forming a bump electrically connected to the power line.

[0009] A method for manufacturing a semiconductor device comprising: forming a bump electrically connected to the power line; and removing the bump, wherein forming the bump and removing the bump are performed before placing the pad, the power line, and the source / drain pattern between the probe pin and the measuring part.

[0010] A method for manufacturing a semiconductor device comprising: forming an upper active contact penetrating the interlayer insulating film; forming upper lines electrically connected to the upper active contact; and further comprising removing at least some of the upper lines, wherein removing at least some of the upper lines is performed before forming the pad. Effects of the invention

[0011] A semiconductor device according to embodiments of the concept of the present invention may include a pad electrically connected to a power line positioned at a level lower than the source / drain patterns. Accordingly, a voltage can be applied to the power line positioned at a level lower than the source / drain patterns using a probe pin in contact with the pad, and hot electrons generated by the voltage can be measured. Brief explanation of the drawing

[0012] FIG. 1a is a plan view of a semiconductor device according to some embodiments. Figure 1b is an enlarged view of the Q1 region of Figure 1a. Figure 1c is an enlarged view of the Q2 region of Figure 1a. Figure 1d is a cross-sectional view along the line A-A' of Figure 1b. Figure 1e is a cross-sectional view along the line B-B' of Figure 1c. FIGS. 2a and 2b are cross-sectional views for explaining a method of manufacturing a semiconductor device according to FIGS. 1a to 1e. FIGS. 3a, 3b, 3c and 3d are cross-sectional views illustrating a test method for a semiconductor device according to some embodiments. FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments. Specific details for implementing the invention

[0013] FIG. 1a is a plan view of a semiconductor device according to some embodiments. FIG. 1b is an enlarged view of the Q1 region of FIG. 1a. FIG. 1c is an enlarged view of the Q2 region of FIG. 1a. FIG. 1d is a cross-sectional view along the line A-A' of FIG. 1b. FIG. 1e is a cross-sectional view along the line B-B' of FIG. 1c.

[0014] Referring to FIG. 1a, a semiconductor device may include a first region (R1) and a second region (R2). The second region (R2) may surround the first region (R1). The first region (R1) and the second region (R2) may be distinguished in a planar view defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions that are orthogonal to each other.

[0015] A semiconductor device may include power lines (PL). Power lines (PL) may be placed in a first region (R1). Power lines (PL) may extend in a second direction (D2). Power lines (PL) may be arranged in a first direction (D1). A power voltage (VDD) or a ground voltage (VSS) may be provided to the power lines (PL). Power lines (PL) may include a conductive material.

[0016] A semiconductor device may include pads (PDs). Pads (PDs) may be placed in a second region (R2). Pads (PDs) may surround a first region (R1). Pads (PDs) may surround power lines (PL). Pads (PDs) may be electrically connected to power lines (PL). Pads (PDs) may include a conductive material. For example, pads (PDs) may include tungsten.

[0017] The semiconductor device may include connection lines (CL). The connection lines (CL) may extend from the second region (R2) to the first region (R1). The connection lines (CL) may electrically connect the pad (PD) and the power line (PL). The connection lines (CL) may include a conductive material.

[0018] The pads (PD) may include a first pad (PD1), a second pad (PD2), a third pad (PD3), a fourth pad (PD4), a fifth pad (PD5), a sixth pad (PD6), a seventh pad (PD7), an eighth pad (PD8), a ninth pad (PD9), a tenth pad (PD10), an eleventh pad (PD11), and a twelfth pad (PD12).

[0019] The first pad (PD1) and the second pad (PD2) may be spaced apart from each other in a second direction (D2) with power lines (PL) in between. Power lines (PL) and a first area (R1) may be positioned between the first pad (PD1) and the second pad (PD2).

[0020] The third pad (PD3) and the fourth pad (PD4) may be spaced apart from each other in a first direction (D1) with power lines (PL) in between. Power lines (PL) and a first region (R1) may be positioned between the third pad (PD3) and the fourth pad (PD4).

[0021] The power lines (PL) may include a first power line (PL1) electrically connected to a first pad (PD), a second power line (PL2) electrically connected to a second pad (PD2), a third power line (PL3) electrically connected to a third pad (PD3), and a fourth power line (PL4) electrically connected to a fourth pad (PD4).

[0022] A ground voltage may be provided to the first power line (PL1). A power voltage may be provided to the second power line (PL2). A ground voltage may be provided to the third power line (PL3). A power voltage may be provided to the fourth power line (PL4).

[0023] Each of the 1st, 3rd, 6th, 8th, 10th, and 12th pads (PD1, PD3, PD6, PD8, PD10, PD12) can be electrically connected to a power line (PL) to which a ground voltage is provided. Each of the 2nd, 4th, 5th, 7th, 9th, and 11th pads (PD2, PD4, PD5, PD7, PD9, PD11) can be electrically connected to a power line (PL) to which a power voltage is provided.

[0024] Power lines (PL) to which ground voltage is provided may be electrically connected to each other. The power voltages may include a first power voltage (VDD_0), a second power voltage (VDD_1), a third power voltage (VDD_2), a fourth power voltage (VDD_3), a fifth power voltage (VDD_4), and a sixth power voltage (VDD_5). A power line (PL) to which the first power voltage is provided may be electrically isolated from a power line (PL) to which a power voltage different from the first power voltage is provided. For example, a power line (PL) to which the first power voltage is provided may be electrically isolated from a power line (PL) to which the second power voltage is provided.

[0025] In some embodiments, the seventh pad (PD7) may be electrically connected to a power line (PL) that provides a first power voltage, the fifth pad (PD5) may be electrically connected to a power line (PL) that provides a second power voltage, the fourth pad (PD4) may be electrically connected to a power line (PL) that provides a third power voltage, the eleventh pad (PD11) may be electrically connected to a power line (PL) that provides a fourth power voltage, the second pad (PD2) may be electrically connected to a power line (PL) that provides a fifth power voltage, and the ninth pad (PD9) may be electrically connected to a power line (PL) that provides a sixth power voltage. In this case, the second power line (PL2) may be electrically disconnected from the fourth power line (PL4).

[0026] The connection lines (CL) may include a first connection line (CL1) that electrically connects a first pad (PD1) and a first power line (PL1), a second connection line (CL2) that electrically connects a second pad (PD2) and a second power line (PL2), a third connection line (CL3) that electrically connects a third pad (PD3) and a third power line (PL3), and a fourth connection line (CL4) that electrically connects a fourth pad (PD4) and a fourth power line (PL4).

[0027] The first and second connecting lines (CL1, CL2) can be extended in the second direction (D2). The third and fourth connecting lines (CL3, CL4) can be extended in the first direction (D1).

[0028] Referring to FIGS. 1b, 1c, 1d and 1e, the semiconductor device may include a first lower insulating film (101), a second lower insulating film (102), a third lower insulating film (103), a fourth lower insulating film (104), and a fifth lower insulating film (105). A fourth lower insulating film (104) may be provided on a fifth lower insulating film (105). A third lower insulating film (103) may be provided on a fourth lower insulating film (104). A second lower insulating film (102) may be provided on a third lower insulating film (103). A first lower insulating film (101) may be provided on a second lower insulating film (102). The lower insulating films (101, 102, 103, 104, 105) may include an insulating material. In some embodiments, each of the lower insulating films (101, 102, 103, 104, 105) may be a multilayer film comprising a plurality of insulating films.

[0029] A lower pad (LP) may be disposed within the fifth lower insulating layer (105). The lower pad (LP) may be disposed at a level lower than the power line (PL). The lower pad (LP) may include a conductive material. A bump (BP) in contact with the lower pad (LP) may be provided. The bump (BP) may be disposed at a level lower than the power line (PL). The bump (BP) may include a conductive material.

[0030] Lower vias (LV) may be provided within the fourth lower insulating layer (104). Connection lines (CL) and lower lines (LL) may be provided within the third lower insulating layer (103). Lower vias (LV) and connection vias (CV) may be provided within the second lower insulating layer (102). Power lines (PL) may be provided within the first lower insulating layer (101).

[0031] The lower via (LV), lower line (LL), and lower pad (LP) can electrically connect the power line (PL) and the bump (BP). The connecting via (CV) and connecting line (CL) can electrically connect the power line (PL) and the pad (PD).

[0032] The lower vias (LV), lower lines (LL), and connecting vias (CV) may contain a conductive material.

[0033] Pin patterns (FP) may be provided on power lines (PL). In some embodiments, pin patterns (FP) may be provided on a first lower insulating film (101). Pin patterns (FP) may extend in a second direction (D2). Pin patterns (FP) may be spaced apart from each other in a first direction (D1). Pin patterns (FP) may comprise an insulating material. For example, pin patterns (FP) may comprise a nitride.

[0034] In some embodiments, the pin patterns (FP) may comprise a semiconductor material. The semiconductor material may be, for example, silicon. In some embodiments, a semiconductor substrate may be provided on the first lower insulating film (101), and the pin patterns (FP) may be portions protruding in a third direction (D3) of the semiconductor substrate. In this case, the pin patterns (FP) may be connected to each other by the lower portion of the semiconductor substrate. The third direction (D3) may intersect the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be a vertical direction orthogonal to the first direction (D1) and the second direction (D2).

[0035] A device isolation layer (111) may be provided. The device isolation layer (111) may surround pin patterns (FP). The pin patterns (FP) may be separated by the device isolation layer (111). The device isolation layer (111) may be provided on the sidewalls of the pin patterns (FP). The device isolation layer (111) may be in contact with the sidewalls of the pin patterns (FP). The device isolation layer (111) may include an insulating material. For example, the device isolation layer (111) may include an oxide. In some embodiments, the device isolation layer (111) may be a multilayer film comprising a plurality of insulating films.

[0036] Lower active contacts (LAC) may be provided. Lower active contacts (LAC) may be provided on a power line (PL). Lower active contacts (LAC) may be electrically connected to the power line (PL). The lower surface of the lower active contact (LAC) may be in contact with the upper surface (PL_U) of the power line (PL). The lower active contact (LAC) may penetrate the pin pattern (FP) in a third direction (D3). The lower active contact (LAC) may include a conductive material.

[0037] A source / drain pattern (SD) may be provided on a pin pattern (FP). The source / drain pattern (SD) may be epitaxial patterns formed by a Selective Epitaxial Growth (SEG) process. The source / drain pattern (SD) may include a semiconductor material. The source / drain pattern (SD) may include at least one of silicon (Si), silicon-germanium (SiGe), or germanium (Ge). The source / drain pattern (SD) may be doped with impurities.

[0038] A channel structure (CH) connected to a source / drain pattern (SD) may be provided. The channel structure (CH) may be provided between source / drain patterns (SD) that are adjacent to each other in a second direction (D2). The channel structure (CH) may include semiconductor patterns (SP) that overlap each other in a third direction (D3). The semiconductor patterns (SP) may be connected to the source / drain pattern (SD). The semiconductor patterns (SP) may include, for example, silicon, silicon-germanium, or germanium.

[0039] A gate electrode (GE) intersecting with a pin pattern (FP) may be provided. The gate electrode (GE) may overlap with the pin pattern (FP) in a third direction (D3). The gate electrode (GE) may extend in a first direction (D1). The gate electrode (GE) may overlap with semiconductor patterns (SP) in a third direction (D3). The gate electrode (GE) may form a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) with the semiconductor patterns (SP).

[0040] A gate insulating film (GI) in contact with a gate electrode (GE) may be provided. The gate insulating film (GI) may separate the gate electrode (GE) from the semiconductor pattern (SP). The gate insulating film (GI) may separate the gate electrode (GE) from the source / drain pattern (SD). The gate insulating film (GI) may include an insulating material. For example, the gate insulating film (GI) may include an oxide.

[0041] A pair of gate spacers (GS) may be disposed on both sides of the gate electrode (GE). The gate spacers (GS) may extend in a first direction (D1). The gate spacers (GS) may include an insulating material.

[0042] Gate capping patterns (GP) may be provided on the gate electrode (GE). The gate capping pattern (GP) may extend in a first direction (D1). The gate capping pattern (GP) may include an insulating material.

[0043] A first interlayer insulating film (121) may be provided. The first interlayer insulating film (121) may be provided on a source / drain pattern (SD) and a gate spacer (GS). A second interlayer insulating film (122) may be provided on the first interlayer insulating film (121). The second interlayer insulating film (122) may be provided on the first interlayer insulating film (121), the gate spacers (GS), and the gate capping patterns (GP). The first and second interlayer insulating films (121, 122) may comprise an insulating material. For example, the first and second interlayer insulating films (121, 122) may comprise an oxide.

[0044] Upper active contacts (UACs) may be provided. The upper active contacts (UACs) may penetrate the first and second interlayer insulating films (121, 122). The upper active contacts (UACs) may include a conductive material.

[0045] Upper insulating films (130) may be provided on the second interlayer insulating film (122). The upper insulating films (130) may be laminated in a third direction (D3) on the second interlayer insulating film (122). The upper insulating films (130) may include a first upper insulating film (131) on the second interlayer insulating film (122) and a second upper insulating film (132) on the first upper insulating film (131). The upper insulating films (130) may include an insulating material.

[0046] Upper vias (UV) and upper lines (UL) may be provided within the upper insulating films (130). The upper vias (UV) and upper lines (UL) may be electrically connected to an upper active contact (UAC). At least one of the upper lines (UL) may be a signal line. The upper vias (UV) and upper lines (UL) may include a conductive material.

[0047] The pad (PD) can penetrate the upper insulating films (130), the second interlayer insulating film (122), the first interlayer insulating film (121), the device isolation film (111), the first lower insulating film (101), and the second lower insulating film (102) in a third direction (D3). The pad (PD) can be surrounded by the upper insulating films (130), the second interlayer insulating film (122), the first interlayer insulating film (121), the device isolation film (111), the first lower insulating film (101), and the second lower insulating film (102).

[0048] A cover insulating film (140) may be provided on the uppermost upper insulating film (130) among the upper insulating films (130) and on the pad (PD). The entire upper surface (PD_U) of the pad (PD) may be in contact with the lower surface of the cover insulating film (140). The cover insulating film (140) may include an insulating material. For example, the cover insulating film (140) may include an oxide.

[0049] In some embodiments, the cover insulating film (140) may be a multilayer film comprising a plurality of insulating films. In some embodiments, a portion of the upper lines (UL) and a portion of the upper vias (UV) may be provided within the cover insulating film (140). In some embodiments, the cover insulating film (140) may be a molding film covering a semiconductor chip. In this case, the molding film may comprise a polymer material.

[0050] Referring to FIG. 1b, the power lines (PL) may further include a fifth power line (PL5) spaced apart from the first power line (PL1) in a first direction (D1). The fifth power line (PL5) may be electrically connected to the first pad (PD1) through a connection line (CL). A ground voltage may be applied to the fifth power line (PL5).

[0051] The first connection line (CL1) may include a first side wall (CL_S1) and a second side wall (CL_S2) opposite to the first side wall (CL_S1). The first side wall (CL_S1) and the second side wall (CL_S2) may be spaced apart from each other in a second direction (D2). The first pad (PD1) may be positioned between the first side wall (CL_S1) and the second side wall (CL_S2) of the first connection line (CL1). The second side wall (CL_S2) of the first connection line (CL1) may overlap with the first power line (PL1) in a third direction (D3). The distance in the second direction (D2) between the first side wall (CL_S1) and the second side wall (CL_S2) of the first connection line (CL1) may be greater than the width (L2) of the first pad (PD1) in the second direction (D2).

[0052] Referring to FIG. 1c, the power lines (PL) may further include a sixth power line (PL6) spaced apart from the third power line (PL3) in the first direction (D1). The sixth power line (PL6) may be electrically connected to the third pad (PD3) through a connection line (CL). A ground voltage may be applied to the sixth power line (PL6).

[0053] Referring to FIG. 1d, the width of the connecting via (CV) and the lower via (LV) in the second direction (D2) can increase as the level decreases. The width of the upper via (UV) in the second direction (D2) can decrease as the level decreases.

[0054] Source / drain patterns (SD) may include a first source / drain pattern (SD1) electrically connected to a first power line (PL1) and a second source / drain pattern (SD2) electrically connected to an upper active contact (UAC). An upper active contact (UAC) may be provided on the second source / drain pattern (SD2).

[0055] The first power line (PL1) may be positioned at a lower level than the first and second source / drain patterns (SD1, SD2). The first power line (PL1) may be electrically connected to the first source / drain pattern (SD1) through a lower active contact (LAC). The lower active contact (LAC) may be connected to the first source / drain pattern (SD1) and the first power line (PL1). The lower active contact (LAC) may be in contact with the first source / drain pattern (SD1) and the first power line (PL1).

[0056] The first pad (PD1) can be electrically connected to the first source / drain pattern (SD1) through the first connection line (CL1), connection via (CV), first power line (PL1) and lower active contact (LAC).

[0057] The level of the upper surface (PD_U) of the first pad (PD1) may be higher than the level of the upper surface (UAC_U) of the upper active contact (UAC). The level of the lower surface (PD_L) of the first pad (PD1) may be lower than the level of the lowest portions (SD_L) of the first and second source / drain patterns (SD1, SD2).

[0058] The lower surface (CV_L) of the connecting via (CV) connecting the first power line (PL1) and the first connecting line (CL1) can be in contact with the upper surface (CL_U) of the first connecting line (CL1). The upper surface (CV_U) of the connecting via (CV) connecting the first power line (PL1) and the first connecting line (CL1) can be in contact with the lower surface (PL_L) of the first power line (PL1).

[0059] The lower surface (PD_L) of the first pad (PD1) may be in contact with the upper surface (CL_U) of the first connection line (CL1). The level of the lower surface (PD_L) of the first pad (PD1) may be lower than the level of the lower surface (PL1_L) of the first power line (PL1).

[0060] The distance (L1) in the third direction (D3) between the upper surface (PD_U) and the lower surface (PD_L) of the first pad (PD1) may be greater than the width (L2) in the second direction (D2) and the width (L3, FIG. 1B) in the first direction (D1) of the first pad (PD1). The width (L2) in the second direction (D2) and the width (L3) in the first direction (D1) of the first pad (PD1) may decrease as the level decreases. The distance (L1) in the third direction (D3) between the upper surface (PD_U) and the lower surface (PD_L) of the first pad (PD1) may be, for example, 70 μm to 100 μm. The width in the second direction (D2) and the width in the first direction (D1) of the upper surface (PD_U) of the first pad (PD1) may be, for example, 10 μm.

[0061] The upper vias (UV) may include a first upper via (UV1) on an upper active contact (UAC) that contacts a second source / drain pattern (SD2). The upper lines (UL) may include a first upper line (UL1) on the first upper via (UV1).

[0062] The distance (L1) in the third direction (D3) between the upper surface (PD_U) and the lower surface (PD_L) of the first pad (PD1) may be greater than the distance (L4) in the third direction (D3) between the upper surface (PL_U) of the first power line (PL1) and the upper surface (UL_U) of the first upper line (UL1).

[0063] The distance in the second direction (D2) between the first sidewall (CL_S1) of the first connection line (CL1) and the first power line (PL1) can be, for example, 20 μm.

[0064] Referring to FIG. 1e, the source / drain patterns (SD) may include a third source / drain pattern (SD3) electrically connected to a third power line (PL3).

[0065] The third power line (PL3) may be positioned at a lower level than the third source / drain pattern (SD3). The third power line (PL3) may be electrically connected to the third source / drain pattern (SD3) through a lower active contact (LAC). The lower active contact (LAC) may be in contact with the third source / drain pattern (SD3) and the third power line (PL3).

[0066] The third pad (PD3) can be electrically connected to the third source / drain pattern (SD3) through the third connection line (CL3), connection via (CV), third power line (PL3) and lower active contact (LAC).

[0067] A semiconductor device according to some embodiments may include a pad (PD) electrically connected to a power line (PL) positioned at a level lower than the source / drain patterns (SD). Accordingly, a voltage can be applied to the power line (PL) positioned at a level lower than the source / drain patterns (SD) using a probe pin in contact with the pad (PD), and hot electrons generated by the voltage can be measured.

[0069] FIGS. 2a and 2b are cross-sectional views for illustrating a method of manufacturing a semiconductor device according to FIGS. 1a to 1e. FIGS. 2a and 2b may correspond to FIG. 1d. The method of manufacturing a semiconductor device may include a method of testing a semiconductor device.

[0070] Referring to FIG. 2a, pin patterns (FP), device isolation layer (111), channel structures (CH), source / drain patterns (SD), gate insulating layers (GI), gate electrodes (GE), gate capping patterns (GP), gate spacers (GS), first interlayer insulating layer (121), second interlayer insulating layer (122), and upper active contacts (UAC) can be formed.

[0071] Upper insulating films (130) can be formed on the second interlayer insulating film (122). Upper vias (UV) and upper lines (UL) can be formed within the upper insulating films (130).

[0072] Lower active contacts (LAC) can be formed. A first lower insulating film (101) and power lines (PL) can be formed. A second lower insulating film (102), lower vias (LV) and connecting vias (CV) can be formed. A third lower insulating film (103), lower lines (LL) and connecting lines (CL) can be formed.

[0073] Through holes (PH) penetrating the upper insulating films (130), the second interlayer insulating film (122), the first interlayer insulating film (121), the device isolation film (111), the first lower insulating film (101), and the second lower insulating film (102) in a third direction (D3) can be formed. The through holes (PH) can be formed, for example, by an ion milling process using an ion beam.

[0074] The upper surface (CL_U) of the connection line (CL) can be exposed by the through hole (PH).

[0075] Referring to FIG. 2b, a pad (PD) can be formed within a through hole (PH). Forming the pad (PD) may include depositing a conductive material (e.g., tungsten) within the through hole (PH).

[0076] A semiconductor device can be tested using pads (PDs). In some embodiments, a semiconductor device can be tested using hot electron analysis (HEA). In some embodiments, the HEA analysis device may include probe pins (150) and a measurement unit (160), and in the semiconductor device test process, the semiconductor device may be placed between the probe pins (150) and the measurement unit (160). Pads (PDs), power lines (PL), source / drain patterns (SD), lower active contacts (LAC), upper active contacts (UAC), and connection lines (CL) may be placed between the probe pins (150) and the measurement unit (160).

[0077] The probe pin (150) can be brought into contact with the upper surface of the pad (PD). Voltage can be applied to the pad (PD) through the probe pin (150). For example, a DC voltage can be applied to the pad (PD) through the probe pin (150). Hot electrons can be generated from a defect in the semiconductor device by the voltage applied through the probe pin (150).

[0078] A measuring unit (160) may be placed below the connection line (CL). The measuring unit (160) may measure photons (PO) produced by hot electrons of the semiconductor device. In some embodiments, the measuring unit (160) may measure heat produced by hot electrons. In some embodiments, the measuring unit (160) may measure hot electrons using a laser.

[0079] Based on the hot electrons measured by the measuring unit (160), it is possible to test whether there are defects in the semiconductor device.

[0080] A first region (R1, FIG. 1a) of a semiconductor device may include a plurality of block regions. Each of the block regions may be electrically connected to an adjacent pad (PD). A pad (PD) adjacent to the block region can be used to test whether there is a defect in the block region. For example, a first pad (PD1) can be used to test whether there is a defect in the block region adjacent to the first pad (PD1).

[0081] In some embodiments, a pad (PD) may be formed on some of the connection lines (CL) and may not be formed on other of the connection lines (CL). In other words, some of the first to twelfth pads (PD1-PD12) may be omitted.

[0082] Referring to FIGS. 1a to 1e, a cover insulating film (140) can be formed on the pads (PD).

[0083] A fourth lower insulating film (104) can be formed on the third lower insulating film (103). Lower vias (LV) can be formed within the fourth lower insulating film (104). A fifth lower insulating film (105) can be formed on the fourth lower insulating film (104). A lower pad (LP) can be formed within the fifth lower insulating film (105). A bump (BP) can be formed on the lower pad (LP).

[0084] A method for manufacturing a semiconductor device according to some embodiments may test the semiconductor device using a pad (PD) before forming a fourth lower insulating film (104), a fifth lower insulating film (105), a lower via (LV), a lower pad (LP), and a bump (BP). By testing the semiconductor device with the lower wiring of the semiconductor device minimized, the phenomenon of photons (PO) being blocked by the lower wiring can be prevented or limited. Accordingly, even if a probe pin (150) is placed on the semiconductor device and a measuring unit (160) is placed below the semiconductor device, the accuracy of defect measurement of the semiconductor device can be improved.

[0086] FIGS. 3a, 3b, 3c and 3d are cross-sectional views illustrating a test method for a semiconductor device according to some embodiments.

[0087] Referring to FIG. 3a, pin patterns (FP), device isolation layer (111), channel structures (CH), source / drain patterns (SD), gate insulating layers (GI), gate electrodes (GE), gate capping patterns (GP), gate spacers (GS), first interlayer insulating layer (121), second interlayer insulating layer (122), and upper active contacts (UAC) can be formed.

[0088] Upper insulating films (130) can be formed on the second interlayer insulating film (122). Upper vias (UV) and upper lines (UL) can be formed within the upper insulating films (130).

[0089] A first substrate (210) can be formed on the upper insulating films (130). The first substrate (210) may be, for example, a silicon substrate.

[0090] Lower active contacts (LAC) can be formed. A first lower insulating film (101) and power lines (PL) can be formed. A second lower insulating film (102), lower vias (LV), and connecting vias (CV) can be formed. A third lower insulating film (103), lower lines (LL), and connecting lines (CL) can be formed. A fourth lower insulating film (104) and lower vias (LV) can be formed. A fifth lower insulating film (105) and a lower pad (LP) can be formed. A bump (BP) can be formed.

[0091] Referring to FIG. 3b, the bump (MP), lower pad (LP), lower via (LV), fifth lower insulating film (105), and fourth lower insulating film (104) can be removed. The fourth lower insulating film (104) can be removed so that the third lower insulating film (103), connection line (CL), and lower line (LL) are exposed.

[0092] A second substrate (220) can be formed on the third lower insulating film (103), the connecting line (CL), and the lower line (LL). The second substrate (220) may be, for example, a silicon substrate.

[0093] In some embodiments, the process of removing the bump (MP), lower pad (LP), lower via (LV), fifth lower insulating film (105) and fourth lower insulating film (104) and the process of forming the second substrate (220) can be performed while the first substrate (210) is fixed.

[0094] Referring to FIG. 3c, at least a portion of the first substrate (210), the upper insulating films (130), at least a portion of the upper lines (UL), and at least a portion of the upper vias (UV) can be removed. At least a portion of the first substrate (210), the upper insulating films (130), at least a portion of the upper lines (UL), and at least a portion of the upper vias (UV) can be removed, for example, by a lapping process.

[0095] Although the number of upper insulating films (130) remaining after the removal process is depicted as 6, the number of upper insulating films (130) remaining after the removal process may not be limited thereto. In some embodiments, the number of upper insulating films (130) remaining after the removal process may be 5 or fewer, or 7 or more.

[0096] Through holes (PHa) can be formed. The through holes (PHa) can penetrate the upper insulating films (130), the second interlayer insulating film (122), the first interlayer insulating film (121), the device isolation film (111), the first lower insulating film (101), and the second lower insulating film (102) in a third direction (D3).

[0097] Referring to FIG. 3d, pads (PDa) can be formed. The length of the pad (PDa) in the third direction (D3) may be smaller than the width of the pad (PDa) in the second direction (D2) and the width of the pad (PDa) in the first direction (D1). For example, the length of the pad (PDa) in the third direction (D3) may be 2.5 μm, and the length of the pad (PDa) in the third direction (D3) may be 10 μm, the maximum width of the pad (PDa) in the second direction (D2) and the maximum width of the pad (PDa) in the first direction (D1).

[0098] A semiconductor device can be tested using a pad (PDa). Voltage can be applied to the pad (PDa) through the probe pin (150). A measuring unit (160) can be placed below the connection line (CL). The measuring unit (160) can measure photons (PO) produced by the hot electrons of the semiconductor device.

[0099] In some embodiments, the process of removing at least a portion of the upper insulating films (130), at least a portion of the upper lines (UL), and at least a portion of the upper vias (UV), the process of forming pads (PDa), and the process of testing the semiconductor device may be performed with the second substrate (220) fixed.

[0100] A test method for a semiconductor device according to some embodiments can test the semiconductor device using a pad (PDa) with the lower wiring minimized by removing the bump (BP), lower pad (LP), and lower via (LV). Accordingly, the phenomenon of photons (PO) being blocked by the lower wiring can be prevented or limited. Accordingly, even if a probe pin (150) is placed on the semiconductor device and a measuring unit (160) is placed below the semiconductor device, the accuracy of defect measurement of the semiconductor device can be improved.

[0102] FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 4 may be similar to the semiconductor device according to FIG. 1a to 1e, except as described below.

[0103] Referring to FIG. 4, a first upper insulating film (331), a second upper insulating film (332), a third upper insulating film (333), a fourth upper insulating film (334), a fifth upper insulating film (335), a sixth upper insulating film (336), a seventh upper insulating film (337), an eighth upper insulating film (338), a ninth upper insulating film (339), and a tenth upper insulating film (340) may be provided sequentially along the third direction (D3) on the second interlayer insulating film (122).

[0104] A power via (PVb) may be provided on the upper active contact (UAC). The power via (PVb) may be provided within the first upper insulating film (331). The power via (PVb) may include a conductive material. A power line (PLb) may be provided on the power via (PVb). The power line (PLb) may be provided within the second upper insulating film (332).

[0105] A connection via (CVb) may be provided on the power line (PLb). The connection via (CVb) may be provided within the third upper insulating layer (333). A connection line (CLb) may be provided on the connection via (CVb). The connection line (CLb) may be provided within the fourth upper insulating layer (334).

[0106] A first pad (PD1b) may be provided on a connection line (CLb). The first pad (PD1b) may be provided within the fifth upper insulating film (335). A first pad via (AV1b) may be provided on the first pad (PD1b). The first pad via (AV1b) may be provided within the sixth upper insulating film (336).

[0107] A second pad (PD2b) may be provided on the first pad via (AV1b). The second pad (PD2b) may be provided within the seventh upper insulating film (337). A second pad via (AV2b) may be provided on the second pad (PD2b). The second pad via (AV2b) may be provided within the eighth upper insulating film (338).

[0108] A third pad (PD3b) may be provided on the second pad via (AV2b). The third pad (PD3b) may be provided within the ninth upper insulating film (339). The first pad via (AV1b) and the second pad via (AV2b) may include a conductive material.

[0109] Upper vias (UVb) and upper lines (ULb) may be provided within the third to tenth upper insulating films (333-340).

[0110] The first pad (PD1b) may be placed at a lower level than the second pad (PD2b). The second pad (PD2b) may be placed at a lower level than the third pad (PD3b). The width of the first pad (PD1b) in the second direction (D2) may be smaller than the width of the second pad (PD2b) in the second direction (D2). The width of the second pad (PD2b) in the second direction (D2) may be smaller than the width of the third pad (PD3b) in the second direction (D2).

[0111] Each of the first to third pads (PD1b, PD2b, PD3b) can be placed at the same level as the upper via (UVb).

[0112] In the process of manufacturing a semiconductor device, the semiconductor device can be tested using the first to third pads (PD1b, PD2b, PD3b). After forming the fifth upper insulating film (335) and the first pad (PD1b), the semiconductor device can be tested by contacting a probe pin to the first pad (PD1b). After forming the seventh upper insulating film (337) and the second pad (PD2b), the semiconductor device can be tested by contacting a probe pin to the second pad (PD2b). After forming the ninth upper insulating film (339) and the third pad (PD3b), the semiconductor device can be tested by contacting a probe pin to the third pad (PD3b).

[0113] As the semiconductor device is tested using the first to third pads (PD1b, PD2b, PD3b), defects in the semiconductor device can be detected before the manufacturing process of the semiconductor device is completed.

[0115] FIG. 5 is a cross-sectional view of a semiconductor device according to some embodiments. The semiconductor device according to FIG. 5 may be similar to the semiconductor device according to FIG. 1a to 1e, except as described below.

[0116] Referring to FIG. 5, the semiconductor device may include a pin pattern (FPc). A device isolation film (411) surrounding the pin pattern (FPc) may be provided.

[0117] Semiconductor patterns (SPc) and upper semiconductor patterns (USPc) that overlap the pin pattern (FPc) in a third direction (D3) may be provided. The upper semiconductor patterns (USPc) may be placed at a higher level than the semiconductor patterns (SPc).

[0118] Source / drain patterns (SDc) may be provided on the pin pattern (FPc). Upper source / drain patterns (USDc) that overlap the source / drain patterns (SDc) in a third direction (D3) may be provided. The upper source / drain pattern (USDc) may be an epitaxial pattern formed by a Selective Epitaxial Growth (SEG) process.

[0119] The source / drain pattern (SDc) can be in contact with the semiconductor pattern (SPc). The upper source / drain pattern (USDc) can be in contact with the upper semiconductor pattern (USPc).

[0120] Interposed insulation patterns (412) may be provided. The interposed insulation pattern (412) may be placed between the source / drain pattern (SDc) and the upper source / drain pattern (USDc). The interposed insulation pattern (412) may include an insulating material.

[0121] Gate electrodes (GEc) may be provided. The gate electrodes (GEc) may surround the semiconductor patterns (SPc) and the upper semiconductor patterns (USPc).

[0122] Gate insulating films (GIc) may be provided. The gate insulating film (GIc) may separate the gate electrode (GEc) from the semiconductor patterns (SPc) and the upper semiconductor patterns (USPc). Gate spacers (GSc) may be provided on both sides of the gate electrode (GEd). A gate capping pattern (GPc) may be provided on the gate electrode (GEc).

[0123] A first interlayer insulating film (421) may be provided. A second interlayer insulating film (422) may be provided on the first interlayer insulating film (421).

[0124] Upper active contacts (UACc) may be provided. The upper active contacts (UACc) may be in contact with the upper source / drain pattern (USDc). Lower active contacts (LACc) may be provided. The lower active contacts (LACc) may be in contact with the source / drain pattern (SDc).

[0125] Upper insulating films (430) may be provided on the second interlayer insulating film (422). A power via (PVc) may be provided on the upper active contact (UACc). An upper power line (UPLc) may be provided on the power via (PVc). Upper vias (UVc) and upper lines (ULc) electrically connected to the upper power line (UPLc) may be provided.

[0126] A first pad (PD1c) may be provided on the upper power line (UPLc). The lower surface of the first pad (PD1c) may be in contact with the upper surface of the upper power line (UPLc). The first pad (PD1c) may penetrate a portion of the upper insulating films (130) in a third direction (D3).

[0127] A first lower insulating film (401) in contact with the element isolation film (411), a second lower insulating film (402) in contact with the first lower insulating film (401), and a third lower insulating film (403) in contact with the second lower insulating film (402) may be provided.

[0128] A lower power line (LPLc) in contact with a lower active contact (LACc) may be provided. A second pad (PD2c) may be provided on the lower power line (LPLc). The lower surface of the second pad (PD2c) may be in contact with the upper surface of the lower power line (LPLc).

[0129] A cover insulating film (440) may be provided on the first pad (PD1c) and the second pad (PD2c). The entire upper surface of the first pad (PD1c) and the entire upper surface of the second pad (PD2c) may come into contact with the cover insulating film (440).

[0130] A lower via (LVc) in contact with a lower power line (LPLc) may be provided. A lower pad (LPc) in contact with the lower via (LVc) may be provided. A bump (BPc) in contact with the lower pad (LPc) may be provided.

[0131] A semiconductor device according to some embodiments can test the semiconductor device using a first pad (PD1c) and an upper power line (UPLc), and can test the semiconductor device using a second pad (PD2c) and a lower power line (LPLc).

[0133] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising: a first source / drain pattern and a second source / drain pattern; a first power line disposed at a level lower than the first and second source / drain patterns and electrically connected to the first source / drain pattern; an upper active contact on the second source / drain pattern; a channel structure connected to at least one of the first and second source / drain patterns; and a first pad electrically connected to the first source / drain pattern through the first power line, wherein the level of the upper surface of the first pad is higher than the level of the upper surface of the upper active contact and the level of the lower surface of the first pad is lower than the level of the lowest portions of the first and second source / drain patterns. Claim 2 A semiconductor device according to claim 1, further comprising a cover insulating film on the first pad, wherein the entire upper surface of the first pad is in contact with the cover insulating film. Claim 3 A semiconductor device according to claim 1, further comprising: a connecting via in contact with the lower surface of the first power line; and a connecting line in contact with the lower surface of the connecting via, wherein the lower surface of the first pad is in contact with the upper surface of the connecting line. Claim 4 A semiconductor device according to claim 3, wherein the level of the lower surface of the first pad is lower than the level of the lower surface of the first power line. Claim 5 A semiconductor device according to claim 1, further comprising: a first interlayer insulating film on the first and second source / drain patterns; a second interlayer insulating film on the first interlayer insulating film; a first upper insulating film on the second interlayer insulating film; a second upper insulating film on the first upper insulating film; an upper via in the first upper insulating film; and an upper line in the second upper insulating film, wherein the upper active contact penetrates the first and second interlayer insulating films, the upper via contacts the upper surface of the upper active contact, the upper line contacts the upper surface of the upper via, and the first pad penetrates the first and second interlayer insulating films and the first and second upper insulating films. Claim 6 A semiconductor device according to claim 1, further comprising a second power line spaced apart from the first power line in a first direction and electrically connected to the first pad. Claim 7 A semiconductor device according to claim 1, further comprising: a third source / drain pattern; a second power line disposed at a lower level than the third source / drain pattern and electrically connected to the second source / drain pattern; and a second pad electrically connected to the third source / drain pattern through the second power line, wherein the first power line and the second power line are disposed between the first pad and the second pad. Claim 8 A semiconductor device according to claim 1, wherein the distance between the upper surface and the lower surface of the first pad is greater than the width of the first pad. Claim 9 A semiconductor device comprising: a source / drain pattern; power lines positioned at a lower level than the source / drain pattern; an upper active contact on the source / drain pattern; a channel structure connected to the source / drain pattern; and pads electrically connected to the power lines, wherein the power lines extend in a first direction and the power lines are spaced apart from each other in a second direction, and the pads include: a first pad and a second pad spaced apart from each other in the first direction with the power lines in between; and a third pad and a fourth pad spaced apart from each other in a second direction intersecting the first direction with the power lines in between. Claim 10 A semiconductor device according to claim 9, wherein the power lines further comprise: a first power line electrically connected to the first pad; a second power line electrically connected to the second pad; a third power line electrically connected to the third pad; and a fourth power line electrically connected to the fourth pad, and further comprises a first connection line electrically connecting the first pad and the first power line; a second connection line electrically connecting the second pad and the second power line; a third connection line electrically connecting the third pad and the third power line; and a fourth connection line electrically connecting the fourth pad and the fourth power line, wherein the first and second connection lines extend in the first direction and the third and fourth connection lines extend in the second direction.

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