Image Sensing Device and Imaging Device including the same

Abstract

An image sensing device according to one embodiment includes: a driver transistor comprising a first electrode to which a power supply voltage is applied, a gate electrode connected to a floating diffusion region, and another electrode; a first low-selection transistor comprising a first electrode connected to the other electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; a second low-selection transistor comprising a first electrode connected to the other electrode of the first low-selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line; and a boosting capacitor between the other electrode of the first low-selection transistor and the floating diffusion region.

Description

Technology Field

[0001] This specification relates to an image sensing device and a shooting device including the same. Background Technology

[0002] With the development of the information and communication industry and the digitalization of electronic devices, high-performance image sensors are being used in various fields, such as digital cameras, camcorders, mobile phones, PCS (personal communication systems), game consoles, security cameras, and medical micro cameras. Generally, an image sensor has a pixel area containing a photodiode and a peripheral circuit area. A unit pixel includes a photodiode and a transfer transistor. The transfer transistor is placed between the photodiode and the floating diffusion region to transfer the charge generated by the photodiode to the floating diffusion region. The problem to be solved

[0003] The problem that this specification aims to solve is to provide an image sensing device capable of selectively controlling the capacitance of a boosting capacitor (or the capacitance of a floating diffusion region).

[0004] Another problem that this specification aims to solve is to provide a method of operation for an image sensing device capable of selectively controlling the capacitance of a boosting capacitor (or the capacitance of a floating diffusion region).

[0005] The problems of this specification are not limited to those mentioned above, and other technical problems may be inferred from the following embodiments. means of solving the problem

[0006] An image sensing device according to one embodiment for solving the above problem comprises: a driver transistor including a first electrode to which a power supply voltage is applied, a gate electrode connected to a floating diffusion region, and another electrode; a first low-selection transistor including a first electrode connected to the other electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; a second low-selection transistor including a first electrode connected to the other electrode of the first low-selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line; and a boosting capacitor between the other electrode of the first low-selection transistor and the floating diffusion region.

[0007] A method of operation of an image sensing device according to one embodiment for solving the above problem comprises: a first period in which a reset transistor and a transfer transistor are turned on and a photodetector is reset; a second period in which a photocharge accumulates in the photodetector; a third period in which a floating diffusion region is reset; a fourth period in which a low-select transistor is turned on and a reverse low-select transistor is turned off and a voltage of the reset floating diffusion region is output; a fifth period in which the transfer transistor is turned on and the photocharge of the photodetector moves to the floating diffusion region; and a sixth period in which the low-select transistor is turned on and the reverse low-select transistor is turned off and a voltage of the floating diffusion region in which the photocharge has accumulated is output.

[0008] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0009] According to the embodiments, during the period of transferring photocharges from the photodetector to the floating diffusion region, a boosting capacitor and a boosting control line may be additionally arranged to further form capacitance in the floating diffusion region. As a result, during the period of transferring photocharges to the floating diffusion region, the capacitance of the floating diffusion region is increased, and as a result, smooth transfer of photocharges from the photodetector to the floating diffusion region may be possible.

[0010] However, during the period of reading out photocharges from the floating diffusion region, the capacitance of the floating diffusion region may increase due to the boosting capacitor even if a boosting control signal is not applied. As a result, it may be difficult to implement the HCG mode.

[0011] However, according to the embodiments, by including a first row select transistor connected to a driver transistor, a second row select transistor connected to an output signal line and an inverse row select transistor connected to the first and second row select transistors, the capacitance of the floating diffusion region can be lowered by controlling the boosting capacitor to have Miller capacitance during the period of reading out the photocharge of the floating diffusion region.

[0012] As a result, the implementation of HCG mode may be possible.

[0013] However, the effects obtainable in this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which this specification belongs from the description below. Brief explanation of the drawing

[0014] FIG. 1 is a block diagram showing a shooting system according to a first embodiment. Figure 2 is a drawing showing the image sensing device illustrated in Figure 1 in more detail. Figure 3 is a block diagram of the image sensing device of Figure 1. Figure 4 is a circuit diagram of a pixel of the pixel array of Figure 3. FIG. 5 is a timing diagram of a plurality of pixels according to one embodiment. Figure 6 is a timing diagram of one pixel of Figure 5. Figure 7 is a timing diagram including the first period of Figure 6. Figure 8 is a circuit diagram showing the operation of transistors during the first period. Figure 9 is a timing diagram including the second period of Figure 6. Figure 10 is a circuit diagram showing the operation of transistors in the second period. FIG. 11 is a timing diagram including the third period of FIG. 6. Figure 12 is a circuit diagram showing the operation of transistors in the third period. FIG. 13 is a timing diagram including the fourth period of FIG. 6. Figure 14 is a circuit diagram showing the operation of transistors in the fourth period. FIG. 15 is a timing diagram including the fifth period of FIG. 6. Figure 16 is a circuit diagram showing the operation of transistors in the fifth period. FIG. 17 is a timing diagram including the sixth period of FIG. 6. Figure 18 is a circuit diagram showing the operation of transistors in the sixth period. Specific details for implementing the invention

[0015] Hereinafter, embodiments are described with reference to the drawings. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "joined" to another component, it means that it may be directly connected / joined to the other component or that a third component may be placed between them.

[0016] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all of one or more combinations that the associated components may define.

[0017] Terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0018] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0019] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0020] FIG. 1 is a block diagram showing a shooting system according to one embodiment.

[0021] Referring to FIG. 1, the shooting system (1) may refer to a device such as a digital still camera that captures still images or a digital video camera that captures video, as well as a device that detects motion. For example, the shooting device (10) may be implemented as a Digital Single Lens Reflex (DSLR), a mirrorless camera, or a mobile phone (especially a smartphone), but is not limited thereto. The shooting device (10) may be a concept that includes a device capable of capturing a subject and generating an image by including a lens and an image element.

[0022] The imaging system (1) may include an imaging device (10) and a host device (20).

[0023] The shooting device (10) may include an image sensing device (100), a line memory (200), an image signal processor (ISP, 300), an input / output interface (I / O interface, 400), and a data memory (500).

[0024] The image sensing device (100) may be a Complementary Metal Oxide Semiconductor Image Sensor (CIS) that converts an optical signal into an electrical signal. The overall operation of the image sensing device (100), such as on / off, operation mode, operation timing, and sensitivity, may be controlled by an ISP (300). The image sensing device (100) may transmit image data, converted from an optical signal into an electrical signal according to the control of the ISP (300), to a line memory (200).

[0025] The line memory (200) may include volatile memory (e.g., DRAM, SRAM) and / or non-volatile memory (e.g., flash memory).

[0026] The line memory (200) can receive and store image data from the image sensing device (100), and can transmit the stored image data to the ISP (300) under the control of the ISP (300).

[0027] The ISP (300) can perform image signal processing on image data stored in the line memory (200). The ISP (300) can reduce noise on the image data and perform image signal processing for image quality improvement, such as gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, and lens distortion correction.

[0028] To generate an HDR image, the ISP (300) may include a gain processing unit (310) and an image compositing unit (320).

[0029] The gain processing unit (310) can determine the gain to be operated on (e.g., multiplication operation) the image data. The gain processing unit (310) can determine the gain based on the difference in conversion gain between the HCG (high conversion gain) mode and the LCG (low conversion gain) mode and provide it to the image synthesis unit (320).

[0030] Each pixel of the pixel array (110) can operate in either an HCG mode or an LCG mode, and the mode of each pixel can be determined by the intensity (or illuminance) of light incident on each pixel.

[0031] The image synthesis unit (320) can synthesize an HDR image corresponding to a high dynamic range using image data of a pixel operating in HCG mode and / or image data of a pixel operating in LCG mode.

[0032] The ISP (300) can transmit video signal-processed image data (i.e., HDR image) to the input / output interface (400).

[0033] According to another embodiment, the gain processing unit (310) and image synthesis unit (320) for generating an HDR image may be included in an image sensing device (100) rather than an ISP (300).

[0034] The input / output interface (400) performs communication with the host device (20) and can transmit image data processed from video signals to the host device (20).

[0035] The host device (20) may be a processor that processes image data processed from an image signal received from a shooting device (10) (e.g., an application processor), a memory that stores image data (e.g., a non-volatile memory), or a display device that visually outputs image data (e.g., an LCD (liquid crystal display)).

[0036] The data memory (500) can store digital image data (Data_PX) converted from the analog-to-digital converter (140).

[0037] Figure 2 is a drawing showing the image sensing device illustrated in Figure 1 in more detail.

[0038] Referring to FIG. 2, the image sensing device (100) may include a pixel array (110), a row driver (120), a Correlate Double Sampler (CDS, 130), an Analog-Digital Converter (ADC, 140), an output buffer (150), a column driver (160), and a timing controller (170). Here, each component of the image sensing device (100) is merely exemplary, and at least some components may be added or omitted as needed.

[0039] A pixel array (110) may include a plurality of image pixels arranged in a plurality of rows and a plurality of columns. In one embodiment, the plurality of image pixels may be arranged in a two-dimensional pixel array including rows and columns. In another embodiment, the plurality of image pixels may be arranged in a three-dimensional pixel array. The plurality of image pixels may convert an optical signal into an electrical signal on a pixel-by-pixel basis or on a pixel group basis, and image pixels within a pixel group may share at least a specific internal circuit. The pixel array (110) may receive a pixel control signal including a row selection signal, a pixel reset signal, and a transmission signal from a row driver (120), and the corresponding pixel of the pixel array (110) may be activated by the pixel control signal to perform an operation corresponding to the row selection signal, the pixel reset signal, and the transmission signal. Each of the image pixels may detect incident light by generating a photocharge corresponding to the intensity (or illuminance) of the incident light and generating an electrical signal having a magnitude corresponding to the amount of the generated photocharge. For the sake of convenience of explanation, image pixels may also be referred to as pixels.

[0040] The row driver (120) can activate the pixel array (110) to perform specific operations on the pixels included in the row based on commands and control signals supplied by the timing controller (170).

[0041] In one embodiment, the correlation double sampler (130) can sequentially sample and hold a reference signal and an image signal provided to each of a plurality of column lines from the pixel array (110). That is, the correlation double sampler (130) can sample and hold the levels of the reference signal and the image signal corresponding to each of the columns of the pixel array (110).

[0042] The correlation double sampler (130) can transmit the reference signal and image signal of each column to the ADC (140) as a correlation double sampling signal based on a control signal from the timing controller (170).

[0043] The ADC (140) can output image data by converting the correlated double sampling signal for each column output from the correlated double sampler (130) into a digital signal. In one embodiment, the ADC (140) can output the correlated double sampling signal generated by the correlated double sampler (130) for each column by converting it into a digital signal.

[0044] The ADC (140) may include a plurality of column counters corresponding to each of the columns of the pixel array (110). Each column of the pixel array (110) is connected to each column counter, and image data may be generated by converting a correlated double sampling signal corresponding to each of the columns into a digital signal using the column counters.

[0045] The output buffer (150) can temporarily hold and output image data in each column unit provided by the ADC (140). The output buffer (150) can temporarily store image data output from the ADC (140) based on a control signal from the timing controller (170).

[0046] The column driver (160) can select a column of the output buffer (150) based on a control signal from the timing controller (170) and control the output buffer (150) so that image data temporarily stored in the selected column of the output buffer (150) is output sequentially.

[0047] The timing controller (170) can control at least one of the row driver (120), the correlated dual sampler (130), the ADC (140), the output buffer (150), and the column driver (160).

[0048] The timing controller (170) can provide clock signals required for the operation of each component of the image sensing device (100), control signals for timing control, and address signals for selecting a row or column to at least one of a row driver (120), a correlated dual sampler (130), an ADC (140), an output buffer (150), and a column driver (160). According to one embodiment, the timing controller (170) may include a logic control circuit, a phase lock loop (PLL) circuit, a timing control circuit, and a communication interface circuit, etc.

[0049] Figure 3 is a block diagram of the image sensing device of Figure 1.

[0050] Referring to FIG. 3, the pixel array (110) may include a plurality of pixels (PX). The pixels (PX) may be arranged in a matrix manner along the row direction and column direction, but the embodiments of the present specification are not limited thereto. The pixels (PX) may include red pixels, green pixels, and blue pixels, but the embodiments of the present specification are not limited thereto and may further include white pixels or infrared pixels.

[0051] Multiple pixels (PX) may be electrically connected to a row driver (120). Multiple pixels (PX) may each be connected to control lines extending from the row driver (120). The control lines may be transmission lines or boosting control lines as shown in FIG. 3, but the embodiments of this specification are not limited thereto.

[0052] The timing controller (170), correlated dual sampler (130), and ADC (140) shown in FIG. 3 are described in FIG. 2, so a redundant description will be omitted.

[0053] Figure 4 is a circuit diagram of a pixel of the pixel array of Figure 3.

[0054] Referring to FIG. 4, the circuit diagram of a pixel may correspond to the equivalent circuit of each pixel (PX) included in the pixel array (see 110 in FIG. 3).

[0055] The pixel (PX) may include a photodetector (PD), a transfer transistor (TT), a reset transistor (RT), a floating diffusion region (FD), a driver transistor (DT), and a select transistor (ST). That is, the pixel may have a structure of a 4TR (4-transistor) pixel.

[0056] A photodetector (PD) can generate and accumulate photocharges corresponding to the intensity of incident light. For example, the photodetector (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. When the photodetector (PD) is implemented as a photodiode, it may be a region doped with impurities of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type).

[0057] Each transistor (TT, RT, DT, ST1, ST2, SBT) may have a first electrode and a second electrode, and below, the first electrode and the second electrode may each be referred to as a source electrode or a drain electrode.

[0058] A transfer transistor (TT) can be connected between a photodetector (PD) and a floating diffusion region (FD). The transfer transistor (TT) can be turned on or turned off in response to a transfer control signal (TX) applied to its gate electrode, and the turned-on transfer transistor (TT) can transfer photocharges accumulated in the photodetector (PD) to the floating diffusion region (FD). The source electrode of the transfer transistor (TT) can be connected to the photodetector (PD), and the drain electrode can be connected to the floating diffusion region (FD).

[0059] A reset transistor (RT) is connected between the power supply voltage (VDD) and the floating diffusion region (FD), and can reset the voltage of the floating diffusion region (FD) to the power supply voltage (VDD) in response to a reset control signal (RX) applied to the gate electrode. The power supply voltage (VDD) is applied to the source electrode of the reset transistor (RT), and the drain electrode can be connected to the floating diffusion region (FD).

[0060] The floating diffusion region (FD) can accumulate photocharges transferred from the transfer transistor (TT). For example, the floating diffusion region (FD) may be a region doped with impurities of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type), and the substrate and the impurity-doped region may be modeled as a junction capacitor. The floating diffusion region (FD) may be connected to the gate electrode of the driver transistor (DT), the drain electrode of the transfer transistor (TT), and the drain electrode of the reset transistor (RT). A floating diffusion electrode may be placed in the floating diffusion region (FD).

[0061] The driver transistor (DT) is connected between the power supply voltage (VDD) and the select transistor (ST), and can amplify the change in the electrical potential of the floating diffusion region (FD), which receives the photocharge accumulated in the photodetector (PD), and transfer it to the select transistor (ST). The gate electrode of the driver transistor (DT) is connected to the floating diffusion region (FD), the power supply voltage (VDD) is applied to the source electrode, and the drain electrode can be connected to the source electrode of the select transistor (ST).

[0062] There may be two selection transistors (ST1, ST2). The first selection transistor (ST1) may be placed between the driver transistor (DT) and the boosting capacitor (CFDB), between the driver transistor (DT) and the second selection transistor (ST2), and between the driver transistor (DT) and the reverse selection transistor (SXT). The first selection transistor (ST1) may be turned on by a first selection control signal (SX1) applied to its gate electrode to output an electrical signal transmitted from the driver transistor (DT) to the second selection transistor (ST2). The source electrode of the first selection transistor (ST1) may be connected to the drain electrode of the driver transistor (DT). The source electrode of the first selection transistor (ST1) may be connected to the source electrode of the second selection transistor (ST2).

[0063] The second selection transistor (ST2) can be connected to the output signal line of the first selection transistor (ST1). The second selection transistor (ST2) can be turned on by a second selection control signal (SX2) applied to its gate electrode to output an electrical signal transmitted from the first selection transistor (ST2) to the output signal line. The source electrode of the second selection transistor (ST2) can be connected to the drain electrode of the first selection transistor (ST1). The drain electrode of the second selection transistor (ST2) can be connected to the output signal line.

[0064] For example, the first selection control signal (SX1) and the second selection control signal (SX2) may be the same signal. In this case, the first selection transistor (ST1) and the second selection transistor (ST2) may be turned on or turned off simultaneously. However, the embodiments of this specification are not limited thereto.

[0065] The reverse selection transistor (SXT) can be connected to the first selection transistor (ST1) and the boosting control line. The reverse selection transistor (SXT) can be turned on by a reverse selection control signal (SXB) applied to its gate electrode to provide a boosting control signal (FDB) to the boosting capacitor (CFDB). The source electrode of the reverse selection transistor (SXT) can be connected to the boosting control line. The drain electrode of the reverse selection transistor (SXT) can be connected to the other electrode of the boosting capacitor (CFDB).

[0066] A boosting capacitor (CFDB) can be placed between the floating diffusion region (FD) and the node between the first selection transistor (ST1) and the second selection transistor (ST2). One electrode of the boosting capacitor (CFDB) is connected to the floating diffusion region (FD), and the other electrode of the boosting capacitor (CFDB) can be connected to the node between the first selection transistor (ST1) and the second selection transistor (ST2).

[0067] The voltage of the floating diffusion region (FD) can be determined by the amount of photocharge transferred through the transfer transistor (TT), and the voltage of the floating diffusion region (FD) may decrease as the amount of photocharge increases. The floating diffusion region (FD) (or floating diffusion electrode) may be connected to a boosting capacitor (CFDB). The capacitance of the floating diffusion region (FD) may be equal to the sum of the parasitic capacitance between the floating diffusion region (FD) (or floating diffusion electrode) and surrounding electrodes and the boosting capacitance of the boosting capacitor (CFDB). Furthermore, the boosting capacitance of the boosting capacitor (CFDB) may vary depending on the parasitic capacitance between the boosting capacitor (CFDB) and adjacent electrodes and the magnitude of the boosting control signal (FDB). For example, if the boosting control signal (FDB) increases, the boosting capacitance of the boosting capacitor (CFDB) can increase. The portion of the capacitance in the floating diffusion region (FD) occupied by the boosting capacitance of the boosting capacitor (CFDB) can be large. Additionally, the capacitance of the floating diffusion region (FD) is inversely proportional to the conversion gain (CG).

[0068] FIG. 5 is a timing diagram of a plurality of pixels according to one embodiment.

[0069] Referring to FIG. 5, the timing diagram of each pixel row (R1, R2, *?*?*, Rn-1, Rn) of a pixel array (see 110 in FIG. 3) is shown. In FIG. 5, for example, the time at which the timing of all pixel rows begins and ends is shown as a 1-frame period (1-frame time).

[0070] As illustrated in FIG. 5, the pixel operation of the pixels of the first pixel row (R1) may include a reset time, an int. time, a read time, and an idle time. From the first pixel row (R1) to the nth pixel row (Rn), the above-described reset time, initialization time, read time, and idle time may proceed sequentially.

[0071] FIG. 6 is a timing diagram of a single pixel of FIG. 5. For convenience of explanation, the reset period is referred to as the first period (T1), the light irradiation period as the second period (T2), and the read periods as the third to sixth periods (T3, T4, T5, T6). The third period (T3) may be the FD reset period, the fourth period (T4) may be the first read-out period, the fifth period (T5) may be the boosting period, and the sixth period (T6) may be the second read-out period. The first period (T1) may be the PD reset period.

[0072] Referring to FIGS. 4 and 6, the voltages of a first selection control signal (SX1), a second selection control signal (SX2), a reset control signal (RX), a transmission control signal (TX), a boosting control signal (FDB), a reverse selection control signal (SBX), and a floating diffusion region (FD) are illustrated to explain the operation of a pixel (PX) over time. Each of the first selection control signal (SX1), the second selection control signal (SX2), the reset control signal (RX), the transmission control signal (TX), and the reverse selection control signal (SBX) may have an activation voltage (or high voltage) or an inactivation voltage (or low voltage). When each of the first selection control signal (SX1), the second selection control signal (SX2), the reset control signal (RX), the transmission control signal (TX), and the reverse selection control signal (SBX) has an activation voltage, the corresponding transistors (ST1, ST2, RT, TT, S) may be turned on. Conversely, when the first selection control signal (SX1), the second selection control signal (SX2), the reset control signal (RX), and the transmission control signal (TX) each have an inactive voltage, the corresponding transistors (ST1, ST2, RT, TT, SBT) can be turned off.

[0073] Below, the operation of the pixel (PX) during each period (T1~T6) will be explained based on the circuit diagram and waveform diagram of the pixel (PX).

[0074] FIG. 7 is a timing diagram including the first period of FIG. 6. FIG. 8 is a circuit diagram showing the operation of transistors in the first period.

[0075] Referring to FIGS. 7 and 8, in the first period (T1), the reset control signal (RX) and the transmission control signal (TX) have an activation voltage, and the reset transistor (RT) and the transmission transistor (TT) are turned on. The voltage of the photodetector (PD) can be reset to the power supply voltage (VDD). In the first period (T1), the first and second selection control signals (SX1, SX2) have an inactivation voltage, and the first and second selection transistors (ST1, ST2) can be turned off, respectively. The first and second selection control signals (SX1, SX2) can be the same in periods (T1 to T6). That is, the first and second selection transistors (ST1, ST2) can be turned on or turned off simultaneously. The reverse selection control signal (SXB) has an activation voltage, and the reverse selection transistor (SXT) can be turned on. The reverse selection control signal (SXB) and the first selection control signal (SX1) may have opposite phases. That is, when the reverse selection transistor (SXT) is turned on, the first selection transistor (ST1) may be turned off, and when the reverse selection transistor (SXT) is turned off, the first selection transistor (ST1) may be turned on, but the embodiments of this specification are not limited thereto. In some embodiments, during the first period (T1), the reverse selection control signal (SXB) may have an inactivation voltage and the reverse selection transistor (SXT) may be turned off.

[0077] FIG. 9 is a timing diagram including the second period of FIG. 6. FIG. 10 is a circuit diagram showing the operation of transistors in the second period.

[0078] Referring to FIGS. 9 and 10, during the second period (T2), the remaining signals (TX, SX1, SX2), excluding the reset control signal (RX) and the reverse selection control signal (SXB), may have an inactive voltage. The reset control signal (RX) and the reverse selection control signal (SXB) may have an active voltage.

[0079] In the second period (T2), the transfer transistor (TT) and the first and second selection transistors (ST1, ST2) can be turned off. Since the transfer transistor (TT) is turned off, photocharge can accumulate in the photodetector (PD).

[0080] In some embodiments, during the second period (T2), the reset control signal (RX) and the reverse selection control signal (SXB) may also have an inactivation voltage.

[0082] FIG. 11 is a timing diagram including the third period of FIG. 6. FIG. 12 is a circuit diagram showing the operation of transistors in the third period.

[0083] Referring to FIGS. 11 and 12, in the third period (T3), the reset control signal (RX) and the reverse selection control signal (SXB) each have an activation voltage, and the transmission control signal (TX) and the first and second selection control signals (SX1, SX2) may have an inactivation voltage. In the third period (T3), the boosting control signal (FDB) may not have a voltage. In the third period (T3), the reset transistor (RT) and the reverse selection transistor (SXT) may be turned on, and the transmission transistor (TT) and the first and second selection transistors (ST1, ST2) may be turned off.

[0084] In the third period (T3), as the reset transistor (RT) is turned on, the voltage of the floating diffusion region (FD) can be reset to the power supply voltage (VDD).

[0085] In some embodiments, the first and second selection control signals (SX1, SX2) may have an activation voltage, and the reverse selection control signal (SXB) may have an inactivation voltage.

[0087] FIG. 13 is a timing diagram including the fourth period of FIG. 6. FIG. 14 is a circuit diagram showing the operation of transistors in the fourth period.

[0088] Referring to FIGS. 13 and 14, in the fourth period (T4), the select control signals (SX1, SX2) may have an enable voltage, and the transfer control signal (TX), the reverse select control signal (SXB), and the reset control signal (RX) may have an disable voltage. In the fourth period (T4), the boosting control signal (FDB) may not have a voltage. In the fourth period (T4), the first and second select transistors (ST1, ST2) may be turned on, and the reset transistor (RT), the reverse select transistor (SXT), and the transfer transistor (TT) may be turned off.

[0089] In the fourth period (T4), the first and second selection transistors (ST1, ST2) are turned on, allowing the voltage level of the floating diffusion region (FD) to be read out. More specifically, the output voltage output as the pixel signal (Vout) can change according to the voltage of the floating diffusion region (FD). That is, the voltage of the floating diffusion region (FD) can be calculated based on the output voltage. At this time, the driver transistor (DT) can operate as a source follower circuit.

[0090] Calculating the voltage of the floating diffusion region (FD) based on the output voltage may mean that the electrical signal transmitted from the driver transistor (DT) is output to the output signal line through the first selection transistor (ST1) and the second selection transistor (ST2).

[0091] In the fourth period (T4), the reverse selection transistor (SXT) is turned off, so the boosting control signal (FDB) is not applied to the boosting capacitor (CFDB), but parasitic capacitance can be formed between the electrodes surrounding the boosting capacitor (CFDB) (one electrode and the other electrode). Since the boosting capacitance of the boosting capacitor (CFDB) occupies a large portion of the capacitance of the floating diffusion region (FD), it is desirable to lower the capacitance of the boosting capacitor (CFDB) in the fourth period (T4).

[0092] According to one embodiment, since the boosting capacitor (CFDB) is placed between the gate electrode of the driver transistor (DT) and the drain electrode (or source electrode) of the driver transistor (DT), the boosting capacitor (CFDB) is subject to the Miller effect. The capacitance of the boosting capacitor (CFDB) subject to the Miller effect may have a Miller capacitance. The Miller capacitance can be calculated by the following equation.

[0093] [ceremony]

[0094]

[0095] (Here, CP(FDB) represents the capacitance of the boosting capacitor (CFDB) (before the Miller effect), CP(FDB_M) represents the Miller capacitance, and ASFG represents the source follower gain.) The source follower gain (ASFG) is an intrinsic characteristic of the source follower circuit and can be a rational number greater than 0 and less than 1.

[0096] According to the above equation, the Miller capacitance (CP(FDB_M)) can be smaller than the capacitance (CP(FDB)) of the boosting capacitor (CFDB) that is not affected by the Miller effect. Therefore, in the fourth period (T4), the capacitance of the boosting capacitor (CFDB) can be lowered, making it possible to implement the HCG mode.

[0097] In the fourth period (T4), the voltage of the floating diffusion region (FD) is provided to a dual-correlation sampler (see 130 in Fig. 2).

[0099] FIG. 15 is a timing diagram including the fifth period of FIG. 6. FIG. 16 is a circuit diagram showing the operation of transistors in the fifth period.

[0100] Referring to FIGS. 15 and 16, in the fifth period (T5), the selection control signals (SX1, SX2) and the reset control signal (RX) may have an inactive voltage, and the transmission control signal (TX) and the reverse selection control signal (SXB) may have an active voltage. In the fifth period (T5), the boosting control signal (FDB) may have a predetermined voltage. In the fifth period (T5), the first and second selection transistors (ST1, ST2) and the reset transistor (RT) may be turned off, and the reverse selection transistor (SXT) and the transmission transistor (TT) may be turned on. The period during which the reverse selection control signal (SXB) is applied may be longer than the period during which the boosting control signal (FDB) is applied, and the period during which the boosting control signal (FDB) is applied may be included within the period during which the reverse selection control signal (SXB) is applied, but the embodiments of this specification are not limited thereto.

[0101] In the fifth period (T5), the transfer transistor (TT) and the reverse selection transistor (SXT) may be turned on, and the reset transistor (RT) and the first and second selection transistors (ST1, ST2) may be turned off. In the fifth period (T5), the photocharge of the photodetector (PD) may move to the floating diffusion region (FD). Accordingly, the voltage of the floating diffusion region (FD) may change according to the amount of photocharge moving. Additionally, as the movement of the photocharge is completed, the voltage of the floating diffusion region (FD) may have a voltage corresponding to the amount of photocharge.

[0102] Meanwhile, the voltage of the floating diffusion region (FD) is boosted by the boosting control signal (FDB) before the photocharge enters (at the time when the fifth period (T5) begins). Since the boosting control signal (FDB) is provided to the other electrode of the boosting capacitor (CFDB), the voltage of the floating diffusion region (FD) connected to one electrode of the boosting capacitor (CFDB) is boosted instantaneously. As the voltage of the floating diffusion region (FD) is boosted, the potential of the floating diffusion region (FD) can be lowered. Because the potential of the floating diffusion region (FD) is lowered, it is possible to improve the retention (Lag) of some photocharge in the photodetector (PD) when photocharge moves from the photodetector (PD) to the floating diffusion region (FD).

[0104] FIG. 15 is a timing diagram including the fifth period of FIG. 6. FIG. 16 is a circuit diagram showing the operation of transistors in the fifth period.

[0105] Referring to FIGS. 15 and 16, in the sixth period (T6), the select control signals (SX1, SX2) may have an enable voltage, and the transfer control signal (TX), the reverse select control signal (SXB), and the reset control signal (RX) may have an disable voltage. In the sixth period (T6), the boosting control signal (FDB) may not have a voltage. In the sixth period (T6), the first and second select transistors (ST1, ST2) may be turned on, and the reset transistor (RT), the reverse select transistor (SXT), and the transfer transistor (TT) may be turned off.

[0106] In the sixth period (T6), the first and second selection transistors (ST1, ST2) are turned on, allowing the voltage level of the floating diffusion region (FD) to be read out. More specifically, the output voltage output as the pixel signal (Vout) can change according to the voltage of the floating diffusion region (FD). That is, based on the output voltage, the voltage of the floating diffusion region (FD) where photocharges have accumulated can be calculated. At this time, the driver transistor (DT) can operate as a source follower circuit.

[0107] As described in the fourth period (T4) during the sixth period (T6), since the boosting capacitor (CFDB) is placed between the gate electrode of the driver transistor (DT) and the drain electrode (or source electrode) of the driver transistor (DT), the boosting capacitor (CFDB) is subject to the Miller effect. The capacitance of the boosting capacitor (CFDB) subject to the Miller effect can have Miller capacitance. Therefore, during the sixth period (T6), the capacitance of the boosting capacitor (CFDB) can be lowered, making it possible to implement the HCG mode.

[0108] In the sixth period (T6), the voltage of the floating diffusion region (FD) is provided to a dual correlation sampler (see 130 in Fig. 2).

[0109] A dual-correlation sampler (see 130 in FIG. 2) calculates the difference between the voltage of the floating diffusion region (FD) in the sixth period (T6) and the voltage of the floating diffusion region (FD) in the fourth period (T4) and provides it to an ADC (see 140 in FIG. 2). The difference between the voltage of the floating diffusion region (FD) in the sixth period (T6) and the voltage of the floating diffusion region (FD) in the fourth period (T4) may correspond to the amount of photocharge applied to a photodetector (PD).

[0111] An image sensing device according to various embodiments of the present specification may be described as follows.

[0112] According to an image sensing device according to various embodiments of the present specification, the device comprises: a driver transistor including a first electrode to which a power supply voltage is applied, a gate electrode connected to a floating diffusion region, and another electrode; a first selection transistor including a first electrode connected to the other electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; a second selection transistor including a first electrode connected to the other electrode of the first selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line; and a boosting capacitor between the other electrode of the first selection transistor and the floating diffusion region.

[0113] According to an image sensing device according to various embodiments of the present specification, the first selection control signal and the second selection control signal may be the same.

[0114] According to an image sensing device according to various embodiments of the present specification, the first selection transistor and the second selection transistor may be turned on or turned off simultaneously.

[0115] According to an image sensing device according to various embodiments of the present specification, it may further include a reverse selection transistor comprising a first electrode connected to another electrode of the first selection transistor, a gate electrode to which a reverse selection control signal is applied, and another electrode to which a boosting control signal is applied.

[0116] According to an image sensing device according to various embodiments of the present specification, if the first selection control signal has an activation voltage, the inverse selection control signal has an inactive voltage, and if the first selection control signal has an inactive voltage, the inverse selection control signal may have an activation voltage.

[0117] According to an image sensing device according to various embodiments of the present specification, the application time of the reverse selection control signal may be longer than the application time of the boosting control signal.

[0118] According to an image sensing device according to various embodiments of the present specification, the voltage of the floating diffusion region can be boosted when the boosting control signal is applied.

[0119] According to an image sensing device according to various embodiments of the present specification, the capacitance of the boosting capacitor may decrease when the reverse selection transistor is turned off and the first selection transistor is turned on.

[0120] According to an image sensing device according to various embodiments of the present specification, when the reverse selection transistor is turned off and the first selection transistor is turned on, the boosting capacitor may have a Miller capacitance.

[0121] According to an image sensing device according to various embodiments of the present specification, it may further include a reset transistor comprising a first electrode connected to one electrode of the driver transistor, a gate electrode to which a reset control signal is applied, and another electrode connected to the floating diffusion region.

[0122] According to various embodiments of the present specification, an image sensing device may further include a transfer transistor comprising one electrode connected to a photodetector, a gate electrode to which a transfer control signal is applied, and another electrode connected to the floating diffusion region.

[0123] According to an image sensing device according to various embodiments of the present specification, it comprises: a first period in which a reset transistor and a transfer transistor are turned on and a photodetector is reset; a second period in which a photocharge accumulates in the photodetector; a third period in which a floating diffusion region is reset; a fourth period in which a selection transistor is turned on and a reverse selection transistor is turned off and a voltage of the reset floating diffusion region is output; a fifth period in which the transfer transistor is turned on and the photocharge of the photodetector moves to the floating diffusion region; and a sixth period in which the selection transistor is turned on and the reverse selection transistor is turned off and a voltage of the floating diffusion region in which the photocharge has accumulated is output.

[0124] According to an image sensing device according to various embodiments of the present specification, a boosting control signal may be applied to a boosting capacitor between the floating diffusion region and the reverse selection transistor during the fifth period.

[0125] According to an image sensing device according to various embodiments of the present specification, the selection transistor may include: a first selection transistor comprising a first electrode connected to another electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; and a second selection transistor comprising a first electrode connected to another electrode of the first selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line.

[0126] According to an image sensing device according to various embodiments of the present specification, the first selection control signal and the second selection control signal may be the same.

[0127] According to an image sensing device according to various embodiments of the present specification, the first selection transistor and the second selection transistor may be turned on or turned off simultaneously.

[0128] According to an image sensing device according to various embodiments of the present specification, the reverse selection transistor may include a first electrode connected to another electrode of the first selection transistor, a gate electrode to which a reverse selection control signal is applied, and another electrode to which a boosting control signal is applied.

[0129] According to an image sensing device according to various embodiments of the present specification, if the first selection control signal has an activation voltage, the inverse selection control signal has an inactive voltage, and if the first selection control signal has an inactive voltage, the inverse selection control signal may have an activation voltage.

[0130] According to an image sensing device according to various embodiments of the present specification, the application time of the inverse selection control signal in the fifth period may be longer than the application time of the boosting control signal.

[0131] According to an image sensing device according to various embodiments of the present specification, the boosting capacitor may have a Miller capacitance during the fifth period.

[0132] Although an embodiment has been described above with reference to the attached drawings, those skilled in the art to which this specification pertains will understand that the above-described technical configuration may be implemented in other specific forms without altering the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope is defined by the claims set forth below rather than by the detailed description above. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope. Explanation of the symbols

[0133] 1: Shooting System 10: Recording device 100: Image sensing device RT: Reset transistor DT: Driver Transistor ST: Select Transistor

Claims

Claim 1 An image sensing device comprising: a driver transistor including a first electrode to which a power supply voltage is applied, a gate electrode connected to a floating diffusion region, and another electrode; a first selection transistor including a first electrode connected to the other electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; a second selection transistor including a first electrode connected to the other electrode of the first selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line; and a boosting capacitor between the other electrode of the first selection transistor and the floating diffusion region. Claim 2 In claim 1, the first selection control signal and the second selection control signal are the same image sensing device. Claim 3 In claim 1, the image sensing device wherein the first selection transistor and the second selection transistor are simultaneously turned on or turned off. Claim 4 An image sensing device according to claim 1, further comprising a reverse selection transistor including a first electrode connected to another electrode of the first selection transistor, a gate electrode to which a reverse selection control signal is applied, and another electrode to which a boosting control signal is applied. Claim 5 An image sensing device according to claim 4, wherein if the first selection control signal has an activation voltage, the reverse selection control signal has an inactivation voltage, and if the first selection control signal has an inactivation voltage, the reverse selection control signal has an activation voltage. Claim 6 In claim 4, the image sensing device in which the application time of the reverse selection control signal is longer than the application time of the boosting control signal. Claim 7 In claim 4, the voltage of the floating diffusion region is boosted when the boosting control signal is applied to the image sensing device. Claim 8 An image sensing device according to claim 4, wherein the capacitance of the boosting capacitor decreases when the reverse selection transistor is turned off and the first selection transistor is turned on. Claim 9 In claim 4, when the reverse selection transistor is turned off and the first selection transistor is turned on, the boosting capacitor is an image sensing device having Miller capacitance. Claim 10 An image sensing device according to claim 1, further comprising a reset transistor including a first electrode connected to a first electrode of the driver transistor, a gate electrode to which a reset control signal is applied, and another electrode connected to the floating diffusion region. Claim 11 An image sensing device according to claim 1, further comprising a transfer transistor including one electrode connected to a photodetector, a gate electrode to which a transfer control signal is applied, and another electrode connected to the floating diffusion region. Claim 12 A method of operation of an image sensing device comprising: a first period in which a reset transistor and a transfer transistor are turned on and a photodetector is reset; a second period in which a photocharge accumulates in the photodetector; a third period in which a floating diffusion region is reset; a fourth period in which a select transistor is turned on and a reverse select transistor is turned off and a voltage of the reset floating diffusion region is output; a fifth period in which the transfer transistor is turned on and the photocharge of the photodetector moves to the floating diffusion region; and a sixth period in which the select transistor is turned on and the reverse select transistor is turned off and a voltage of the floating diffusion region in which the photocharge has accumulated is output. Claim 13 A method of operation of an image sensing device according to claim 12, wherein the boosting control signal is applied to the boosting capacitor between the floating diffusion region and the reverse selection transistor during the fifth period. Claim 14 A method of operation of an image sensing device according to claim 12, wherein the selection transistor comprises: a first selection transistor including a first electrode connected to another electrode of the driver transistor, a gate electrode to which a first selection control signal is applied, and another electrode; and a second selection transistor including a first electrode connected to another electrode of the first selection transistor, a gate electrode to which a second selection control signal is applied, and another electrode connected to an output signal line. Claim 15 In claim 14, the first selection control signal and the second selection control signal are the same method of operation of an image sensing device. Claim 16 In claim 14, a method of operation of an image sensing device in which the first selection transistor and the second selection transistor are simultaneously turned on or turned off. Claim 17 In claim 14, the method of operation of an image sensing device comprising: a reverse selection transistor, a first electrode connected to the other electrode of the first selection transistor, a gate electrode to which a reverse selection control signal is applied, and another electrode to which a boosting control signal is applied. Claim 18 A method of operation of an image sensing device according to claim 17, wherein if the first selection control signal has an activation voltage, the reverse selection control signal has an inactivation voltage, and if the first selection control signal has an inactivation voltage, the reverse selection control signal has an activation voltage. Claim 19 A method of operation of an image sensing device in which, in the fifth period, the application time of the reverse selection control signal is longer than the application time of the boosting control signal. Claim 20 In claim 17, the boosting capacitor in the fifth period is a method of operation of an image sensing device having Miller capacitance.

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