Memory device including pass transistors

Abstract

A memory device according to embodiments of the present disclosure may include: a laminate comprising a plurality of electrode layers and a plurality of interlayer insulating layers that are alternately stacked along a vertical direction and extending in a first horizontal direction; a first semiconductor layer comprising a plurality of contact plugs that penetrate the laminate and are each connected to the plurality of electrode layers; and a second semiconductor layer comprising a plurality of pass transistors each connected to the plurality of contact plugs. The plurality of pass transistors and the plurality of contact plugs may be arranged in a plurality of connection regions arranged along the first horizontal direction, wherein the number of pass transistors and the number of contact plugs in each of the plurality of connection regions may be equal.

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