Memory device and manufacturing method of the memory device

Abstract

A memory device according to an embodiment of the present invention may include cell plugs penetrating a stack, selection plugs each connected to the cell plugs on the stack, selection lines surrounding the selection plugs on the stack, and a separation structure that separates the selection lines from each other and contacts the selection plugs.

Description

Technology Field

[0001] The present invention relates to a memory device and a method for manufacturing the same, and more specifically, to a memory device including a memory block having a three-dimensional structure and a method for manufacturing the same. Background Technology

[0002] A memory device may include a non-volatile memory device in which stored data is retained even when the power supply is cut off. Non-volatile memory devices can be classified into two-dimensional or three-dimensional structures depending on the arrangement of memory cells. Memory cells of a non-volatile memory device having a two-dimensional structure can be arranged in a single layer on a substrate, while memory cells of a non-volatile memory device having a three-dimensional structure can be stacked vertically on a substrate. Since the integration density of a non-volatile memory device having a three-dimensional structure is higher than that of a non-volatile memory device having a two-dimensional structure, the number of electronic devices using non-volatile memory devices having a three-dimensional structure has recently been increasing. In addition, various technologies are being proposed to reduce the volume of non-volatile memory devices having a three-dimensional structure. The problem to be solved

[0003] An embodiment of the present invention provides a memory device capable of reducing the volume of the memory device and a method for manufacturing the same. means of solving the problem

[0004] A memory device according to an embodiment of the present invention may include cell plugs penetrating a stack, selection plugs each connected to the cell plugs on the stack, selection lines surrounding the selection plugs on the stack, and a separation structure that separates the selection lines from each other and contacts the selection plugs.

[0005] A method for manufacturing a memory device according to an embodiment of the present invention may include the steps of: forming cell plugs penetrating a stack; forming selection plugs on the stack that are each connected to the cell plugs; forming a first upper insulating film covering the stack and the selection plugs; removing a portion of the first upper insulating film to form a separation structure in contact with the selection plugs; and forming selection lines on the stack that are separated from each other by the separation structure and each contact with the selection plugs. Effects of the invention

[0006] This technology can reduce the volume of a memory device compared to existing ones by improving the structure of the selection lines and separation structure. Brief explanation of the drawing

[0007] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention. FIG. 2 is a diagram for schematically explaining a memory device according to an embodiment of the present invention. FIGS. 3a to 3d are drawings for explaining the structure of a memory device according to an embodiment of the present invention. FIGS. 4a to 4q are drawings for explaining a method of manufacturing a memory device according to an embodiment of the present invention. FIG. 5 is a drawing for explaining a memory card system to which the memory device of the present invention is applied. FIG. 6 is a diagram illustrating a Solid State Drive (SSD) system to which the memory device of the present invention is applied. Specific details for implementing the invention

[0008] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0009] Hereinafter, in order to explain in detail enough for a person skilled in the art to implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the attached drawings.

[0011] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention.

[0012] Referring to FIG. 1, a memory device (100) may include a memory cell array (110), a peripheral circuit (170), and a control circuit (180).

[0013] The memory cell array (110) may include first to i-th memory blocks (BLK1 to BLKi). Each of the first to i-th memory blocks (BLK1 to BLKi) may include memory cells capable of storing data. Drain select lines (DSL), word lines (WL), source select lines (SSL), and source lines (SC) may be connected to each of the first to i-th memory blocks (BLK1 to BLKi), and bit lines (BL) may be connected in common to the first to i-th memory blocks (BLK1 to BLKi).

[0014] The first to i-th memory blocks (BLK1 to BLKi) may be formed in a three-dimensional structure. Memory blocks having a three-dimensional structure may include memory cells stacked vertically on a substrate. The structure of the memory blocks (e.g., the first to i-th memory blocks (BLK1 to BLKi)) will be described later with reference to FIGS. 3a and 3b.

[0015] Memory cells can store 1 bit or 2 or more bits of data depending on the programming method. For example, the method of storing 1 bit of data in a single memory cell is called the single-level cell method, and the method of storing 2 bits of data is called the multi-level cell method. The method of storing 3 bits of data in a single memory cell is called the triple-level cell method, and the method of storing 4 bits of data is called the quad-level cell method. In addition, 5 bits or more of data may be stored in a single memory cell.

[0016] The peripheral circuit (170) may be configured to perform a program operation for storing data in the memory cell array (110), a read operation for outputting data stored in the memory cell array (110), and an erase operation for erasing data stored in the memory cell array (110). For example, the peripheral circuit (170) may include a voltage generator (120), a row decoder (130), a page buffer group (140), a column decoder (150), and an input / output circuit (160).

[0017] The voltage generator (120) can generate various operating voltages (Vop) used for program operation, read operation, or erase operation in response to the operation code (OPCD). For example, the voltage generator (120) can be configured to generate program voltages, turn-on voltages, turn-off voltages, negative voltages, precharge voltages, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code (OPCD). The operating voltages (Vop) generated by the voltage generator (120) can be applied to the drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SC) of the memory block selected through the row decoder (130).

[0018] Program voltages are voltages applied to a selected word line among the word lines (WL) during a program operation, and can be used to raise the threshold voltage of the memory cells connected to the selected word line. Turn-on voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn on drain select transistors or source select transistors. Turn-off voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn off drain select transistors or source select transistors. For example, the turn-off voltage can be set to 0V. Precharge voltages are voltages higher than 0V and can be applied to bit lines during a read operation. Verification voltages can be used during a verification operation to determine whether the threshold voltage of the selected memory cells has been raised to a target level. Verification voltages can be set to various levels depending on the target level and can be applied to the selected word line.

[0019] Read voltages may be applied to selected word lines during a read operation of selected memory cells. For example, read voltages may be set to various levels depending on the programming method of the selected memory cells. Pass voltages are voltages applied to unselected word lines among the word lines (WL) during a program or read operation, and may be used to turn on memory cells connected to the unselected word lines. Erase voltages may be used during an erase operation to erase memory cells included in a selected memory block, and may be applied to the source line (SC).

[0020] The row decoder (130) may be configured to transmit operating voltages (Vop) to drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SC) connected to a memory block selected according to a row address (RADD). For example, the row decoder (130) may be connected to a voltage generator (120) via global lines and to first to i-th memory blocks (BLK1 to BLKi) via drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SC).

[0021] A page buffer group (140) may include page buffers (not shown) each connected to the first to i-th memory blocks (BLK1 to BLKi). Each of the page buffers (not shown) may be connected to the first to i-th memory blocks (BLK1 to BLKi) via bit lines (BL). During a read operation, the page buffers (not shown) may sense the current or voltage of the bit lines, which vary according to the threshold voltages of the selected memory cells, in response to page buffer control signals (PBSIG), and temporarily store the sensed data.

[0022] A column decoder (150) may be configured to transmit data between a page buffer group (140) and an input / output circuit (160) in response to a column address (CADD). For example, the column decoder (150) may be connected to the page buffer group (140) via column lines (CL) and may transmit enable signals via column lines (CL). Page buffers (not shown) included in the page buffer group (140) may receive or output data via data lines (DL) in response to the enable signals.

[0023] The input / output circuit (160) may be configured to receive or output commands (CMD), addresses (ADD), or data through input / output lines (I / O). For example, the input / output circuit (160) may transmit commands (CMD) and addresses (ADD) received from an external controller through input / output lines (I / O) to the control circuit (180), and transmit data received from an external controller through input / output lines (I / O) to the page buffer group (140). Alternatively, the input / output circuit (160) may output data received from the page buffer group (140) to an external controller through input / output lines (I / O).

[0024] The control circuit (180) can output at least one of an operation code (OPCD), a row address (RADD), page buffer control signals (PBSIG), or a column address (CADD) in response to a command (CMD) and an address (ADD). For example, if the command (CMD) input to the control circuit (180) is a command corresponding to a program operation, the control circuit (180) can control the peripheral circuit (170) to perform a program operation of the memory block selected by the address (ADD). If the command (CMD) input to the control circuit (180) is a command corresponding to a read operation, the control circuit (180) can control the peripheral circuit (170) to perform a read operation of the memory block selected by the address and output the read data. If the command (CMD) input to the control circuit (180) is a command corresponding to an erase operation, the control circuit (180) can control the peripheral circuit (170) so that the erase operation of the selected memory block is performed.

[0026] FIG. 2 is a diagram for schematically explaining a memory device according to an embodiment of the present invention.

[0027] Referring to FIG. 2, the memory device (100) may include a peripheral circuit structure (PC) disposed on a substrate (SST) and first to i-th memory blocks (BLK1 to BLKi). The first to i-th memory blocks (BLK1 to BLKi) may be superimposed on the peripheral circuit structure (PC).

[0028] The substrate (SST) may be a single-crystal semiconductor film. For example, the substrate (SST) may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed through a selective epitaxial growth method.

[0029] The peripheral circuit structure (PC) may include a row decoder (130), a column decoder (150), a page buffer group (140), and a control circuit (180), etc., which constitute a circuit for controlling the operation of the first to i-th memory blocks (BLK1 to BLKi). For example, the peripheral circuit structure (PC) may include an NMOS transistor, a PMOS transistor, a resistor, and a capacitor, etc., which are electrically connected to the first to i-th memory blocks (BLK1 to BLKi). The peripheral circuit structure (PC) may be placed between the substrate (SST) and the first to i-th memory blocks (BLK1 to BLKi).

[0030] Each of the first to i-th memory blocks (BLK1 to BLKi) may include a source structure, bit lines, cell strings electrically connected to the source structure and bit lines, word lines electrically connected to the cell strings, and select lines electrically connected to the cell strings. Each cell string may include memory cells and select transistors connected in series by a cell plug. Each of the select lines may be used as the gate electrode of the corresponding select transistor, and each of the word lines may be used as the gate electrode of the corresponding memory cell. The first to i-th memory blocks (BLK1 to BLKi) may be separated from one another by a slit. The select lines included in each of the first to i-th memory blocks (BLK1 to BLKi) may be separated horizontally by a separation structure. The slit and the separation structure will be described later with reference to FIGS. 3a to 3c.

[0031] As another embodiment, the substrate (SST), the peripheral circuit structure (PC), and the first to i-th memory blocks (BLK1 to BLKi) may be stacked in reverse order of the order shown in FIG. 2. For example, the peripheral circuit structure (PC) may be placed on the first to i-th memory blocks (BLK1 to BLKi).

[0032] As another embodiment, unlike that shown in FIG. 2, the peripheral circuit structure (PC) may be placed on a portion of the substrate (SST) that does not overlap with the first to i-th memory blocks (BLK1 to BLKi). For example, the peripheral circuit structure (PC) and the first to i-th memory blocks (BLK1 to BLKi) may each be placed on areas on the substrate (SST) that do not overlap with each other.

[0034] FIGS. 3a to 3d are drawings for explaining the structure of a memory device according to an embodiment of the present invention. FIG. 3a is a plan view showing the layout of a memory device according to one embodiment of the present invention. FIG. 3b is a cross-sectional view showing the AA' section of FIG. 3a. FIG. 3c is an enlarged view of C of FIG. 3b. FIG. 3d is a plan view for explaining a separation structure according to another embodiment of the present invention.

[0035] FIG. 3a illustrates any two adjacent memory blocks among the first to i-th memory blocks (BLK1 to BLKi) of FIG. 2. FIG. 3a illustrates a part of the n-th memory block (BLKn) and a part of the n+1-th memory block (BLK(n+1)). Hereinafter, the n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) will be described with reference to FIG. 3a, but the following description may also apply to the remaining memory blocks among the first to i-th memory blocks (BLK1 to BLKi).

[0036] The n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) may be arranged adjacently in the Y direction. The n+1-th memory block (BLK(n+1)) may be located in the Y direction of the n-th memory block (BLKn). The n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) may each extend in the X direction. The n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) may be separated from each other by a slit (SI). The n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) may be adjacent to each other with the slit (SI) in between. The slit (SI) may insulate the n-th memory block (BLKn) and the n+1-th memory block (BLK(n+1)) from each other. The slits (SI) may be located in the Y direction and the direction opposite to the Y direction of the nth memory block (BLKn), respectively. Additionally, the slits (SI) may be located in the Y direction and the direction opposite to the Y direction of the n+1th memory block (BLK(n+1)), respectively. The slits (SI) may each extend in the X direction. The slits (SI) may be filled with a single film or multiple films. For example, the slits (SI) may each include an insulating film. As another example, the slits (SI) may each include a conductive film and an insulating film surrounding the conductive film.

[0037] The nth memory block (BLKn) and the n+1th memory block (BLK(n+1)) may each include a cell region (CR) and a contact region (CTR). The contact regions (CTR) may be located in the X direction of each of the cell regions (CR). The contact region (CTR) may extend from the cell region (CR) in the X direction. Unlike the illustration in FIG. 3a, the contact region (CTR) may extend from the cell region (CR) in the opposite direction of the X direction, or extend in the X direction and the opposite direction of the X direction, i.e., to both sides of the cell region (CR). In addition, the cell region (CR) and the contact region (CTR) may be arranged in various ways.

[0038] Cell plugs and select plugs (SPL) may be placed within the cell area (CR). Although only select plugs (SPL) are shown in FIG. 3a, it can be understood that select plugs (SPL) are placed in the Z direction of each cell plug. The structure of the cell plugs will be described later with reference to FIG. 3b.

[0039] Select plugs (SPLs) can be arranged along the X and Y directions. For example, the centers of each of the select plugs (SPLs) included in the odd-numbered rows and even-numbered rows can be positioned offset from each other. Select plugs (SPLs) can be spaced apart from each other in the X and Y directions. Each of the select plugs (SPLs) can extend in the Z direction. Each of the select plugs (SPLs) can be electrically connected to a bit line (e.g., bit line (BL) in FIG. 1) and a source line (e.g., source line (SC) in FIG. 1) through a wiring structure.

[0040] Each of the select plugs (SPL) may include a channel pillar (CHP), a gate insulating film (GI), and a barrier film (BA). The channel pillar (CHP) may have a cylindrical shape. The gate insulating film (GI) may wrap around the channel pillar (CHP). The gate insulating film (GI) may have a cylindrical shape that contacts the side of the channel pillar (CHP). The channel pillar (CHP) may fill the interior of the gate insulating film (GI). The barrier film (BA) may wrap around the gate insulating film (GI). The barrier film (BA) may contact the side of the gate insulating film (GI). The barrier film (BA) may have a cylindrical shape.

[0041] Channel pillars (CHP) can be formed from undoped silicon films or doped silicon films. For example, some parts of the channel pillars (CHP) may be undoped silicon films, and others may be doped silicon films. The gate insulating film (GI) may be an oxide film (e.g., silicon oxide). The barrier film (BA) may be a nitride film (e.g., titanium nitride).

[0042] Each of the selection lines (SL) may extend in the X direction. The selection lines (SL) may extend from the cell region (CR) to the contact region (CTR). The selection lines (SL) may be arranged along the Y direction. The selection lines (SL) may be placed adjacent to each other in the Y direction. For example, the selection line (SL) of the nth memory block (BLKn) and the selection line (SL) of the n+1th memory block (BLK(n+1)) may be placed adjacent to each other in the Y direction with a slit (SI) in between. Additionally, the nth memory block (BLKn) and the n+1th memory block (BLK(n+1)) may each include two or more selection lines (SL). For example, two selection lines (SL) adjacent in the Y direction may be located inside the nth memory block (BLKn). The selection lines (SL) may include a conductive material such as tungsten (W).

[0043] Select lines (SL) can be separated by a separation structure (IS). For example, two or more select lines (SL) contained within a single memory block (e.g., the nth memory block (BLKn)) can be insulated from each other by a separation structure (IS). The separation structure (IS) can extend in the X direction. One or more separation structures (IS) can be placed between adjacent slits (SI) in the Y direction. The number of select lines (SL) contained in a single memory block can be determined by the number of separation structures (IS) located between adjacent slits (SI) in the Y direction. For example, the nth memory block (BLKn) may include one separation structure (IS) and two select lines (SL). The separation structure (IS) may include an insulating material such as an oxide.

[0044] Selection lines (SL) can surround selection plugs (SPL). Selection lines (SL) can be located between selection plugs (SPL) in a cell area (CR). For example, selection lines (SL) can fill the space between adjacent selection plugs (SPL). Selection lines (SL) can be in contact with the barrier membrane (BA) of the selection plugs (SPL).

[0045] The separation structure (IS) may be in contact with the selection plugs (SPL). The separation structure (IS) may be located between some of the selection plugs (SPL) in the cell region (CR). For example, the separation structure (IS) may be placed between selection plugs (SPL) surrounded by different selection lines (SL) among the selection plugs (SPL). The separation structure (IS) may fill the space between some of the selection plugs (SPL). The separation structure (IS) may be in contact with the barrier membrane (BA) of some of the selection plugs (SPL).

[0046] In one embodiment, the width of the separation structure (IS) (e.g., length in the Y direction) may correspond to the distance between the selection plugs (SPL). For example, the separation structure (IS) included in the nth memory block (BLKn) in FIG. 3a may have a width that contacts the selection plugs (SPL) of the second row and the selection plugs (SPL) of the third row included in the nth memory block (BLKn), respectively. In another embodiment, the width of the separation structure (IS) may be formed wider than that in FIG. 3a. An embodiment in which the width of the separation structure (IS) is different will be described later with reference to FIG. 3d.

[0047] A barrier film (BA) included in each of the selection plugs (SPL) may include at least one of a first portion (P1) in contact with the selection lines (SL) and a second portion (P2) in contact with the separation structure (IS). For example, in FIG. 3a, the selection plug (SPL) in contact with the separation structure (IS) may include the first portion (P1) and the second portion (P2). Also, in FIG. 3a, the selection plug (SPL) located near the slit (SI) may include the first portion (P1) and not include the second portion (P2).

[0048] Select line contacts (SCT) and word line contacts (WCT) may be placed within a contact area (CTR). Multiple contacts may be placed within the contact area (CTR), and FIG. 3a illustrates only some of the select line contacts (SCT) and some of the word line contacts (WCT).

[0049] Select line contacts (SCTs) can be connected to each of the select lines (SL). Select line contacts (SCTs) can be in contact with each of the select lines (SL). Word line contacts (WCTs) can penetrate the first upper insulation pattern (UIP1). Word line contacts (WCTs) can be spaced apart from each other along the X direction. For example, within the nth memory block (BLKn), word line contacts (WCTs) can be arranged along the X direction. In addition, word line contacts (WCTs) can be arranged in various ways within the contact area (CTR). For example, word line contacts (WCTs) may not be arranged parallel along the X direction, but may be arranged in a zigzag shape. Each of the select line contacts (SCTs) and word line contacts (WCTs) can extend in the Z direction. The select line contacts (SCT) and word line contacts (WCT) may include a conductive material such as tungsten. The specific structure of the select line contacts (SCT), word line contacts (WCT), and the first upper insulating pattern (UIP1) will be described later with reference to FIG. 3b.

[0050] FIG. 3b is a cross-sectional view corresponding to the AA' section of FIG. 3a. Also, FIG. 3a is a plan view corresponding to the BB' section of FIG. 3b.

[0051] The laminate (STK) may include conductive films (CD) and interlayer insulating films (IL). The conductive films (CD) and interlayer insulating films (IL) may be stacked alternately along the Z direction. The conductive films (CD) may be insulated from one another by the interlayer insulating films (IL). The conductive films (CD) may be formed from at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The conductive films (CD) may correspond to the word line (WL) or source select line (SSL) of FIG. 1. The interlayer insulating films (IL) may be formed from an oxide film (e.g., silicon oxide).

[0052] In the contact region (CTR), the laminate (STK) may include a stepped structure. The laminate (STK) may include a plurality of steps formed within the contact region (CTR). Each of the plurality of steps may consist of a pair of conductive films (CD) and an interlayer insulating film (IL). For example, each of the plurality of steps may include a layer of conductive film (CD) and an interlayer insulating film (IL) on the conductive film (CD). As another example, unlike the illustration in FIG. 3b, each of the plurality of steps may include a layer of conductive film (CD) and an interlayer insulating film (IL) underneath the conductive film (CD). FIG. 3b illustrates steps arranged along the X direction, but the form of the stepped structure is not limited by the illustration in FIG. 3b. For example, the laminate (STK) may include steps arranged along the Y direction within the contact region (CTR). As another example, the laminate (STK) may include steps arranged along the X and Y directions within the contact region (CTR).

[0053] The laminate (STK) may further include a first cover film (CV1), a second cover film (CV2), and a step insulating film (SIL) formed sequentially on a step structure within a contact region (CTR). The first cover film (CV1) may be in direct contact with the step structure of the laminate (STK). The first cover film (CV1) may be formed conformally along the surface of the steps. The first cover film (CV1) may include an insulating material. The second cover film (CV2) may be formed on the first cover film (CV1). The second cover film (CV2) may extend along the surface of the first cover film (CV1). The second cover film (CV2) may be formed thicker than the first cover film (CV1). The second cover film (CV2) may include SiCN. The step insulating film (SIL) may be located on the second cover film (CV2). The upper surface of the step insulation layer (SIL) may be located at a level equivalent to the upper surface of the uppermost interlayer insulation layer (IL). The step insulation layer (SIL) may contain an oxide material.

[0054] Support structures (SS) may be disposed within a contact region (CTR). The support structures (SS) may penetrate the laminate (STK) within the contact region (CTR). The support structures (SS) may penetrate at least some of the interlayer insulating film (IL), the conductive film (CD), the first cover film (CV1), the second cover film (CV2), and the step insulating film (SIL). The height of each support structure (SS) may correspond to the height of the laminate (STK). The upper surface of the support structures (SS) may be located at a level equivalent to the upper surface of the laminate (STK). In one embodiment, the support structures (SS) may be disposed to penetrate each step. In another embodiment, more or fewer support structures (SS) may be disposed compared to the illustration in FIG. 3b. The support structures (SS) may comprise an insulating material.

[0055] Select lines (SL) may be located on a laminate (STK). Select lines (SL) may cover a portion of the laminate (STK). Select lines (SL) may include a conductive material such as tungsten (W). Select lines (SL) may correspond to drain select lines (DSL) of FIG. 1. According to the present disclosure, since a select line (SL) acting as a drain select line (DSL) is formed separately on the laminate (STK), the conductive films (CD) within the laminate (STK) may act as word lines (WL) or source select lines (SSL).

[0056] The thickness of the select lines (SL) (e.g., length in the Z direction) can be formed to be thicker than the conductive films (CD). Since each select line (SL) is formed to be thicker than the conductive films (CD), even if multiple layers of conductive films are not used as drain select lines (DSL), a single layer of select lines (SL) can deliver a voltage sufficient to operate the drain select transistor.

[0057] A separation structure (IS) may be disposed between selection lines (SL). The separation structure (IS) may be in direct contact with the selection plugs (SPL). The separation structure (IS) may fill the space between adjacent selection plugs (SPL) with the separation structure (IS) in between. Thus, the separation structure (IS) may be formed even when the spacing between the selection plugs (SPL) is relatively narrow. That is, according to the present disclosure, the length in the Y direction of each of the memory blocks may be reduced.

[0058] The height of the separation structure (IS) (e.g., length in the Z direction) may be higher than the height of the select lines (SL). By making the height of the separation structure (IS) higher than that of the select lines (SL), leakage between different select lines (SL) can be prevented or reduced. Additionally, the height of the separation structure (IS) may be lower than the height of the select plugs (SPL).

[0059] Cell plugs (CPL) can penetrate the cell region (CR) of the stack (STK). Each cell plug (CPL) may include a blocking membrane (BX), a charge trap membrane (CT), a tunneling membrane (TX), a channel membrane (CH), a capping membrane (CAP), and a core pillar (CO). The blocking membrane (BX), the charge trap membrane (CT), and the tunneling membrane (TX) may each have a cylindrical shape. The blocking membrane (BX) may have a cylindrical shape in contact with the stack (STK). The charge trap membrane (CT) may extend along the inner surface of the blocking membrane (BX). The tunneling membrane (TX) may extend along the inner surface of the charge trap membrane (CT). The channel membrane (CH) may extend along the inner surface of the tunneling membrane (TX). The core pillar (CO) may fill the interior of the channel membrane (CH). The core pillar (CO) may have a cylindrical shape surrounded by the channel membrane (CH). The capping membrane (CAP) can be connected to the channel membrane (CH) on the core pillar (CO).

[0060] The blocking film (BX) and tunneling film (TX) may be formed of an oxide film (e.g., silicon oxide) or an oxynitride film (e.g., silicon oxynitride), or a combination thereof. The charge trap film (CT) may include a nitride film or a variable resistance material. The channel film (CH) and capping film (CAP) may be formed of an undoped silicon film or a doped silicon film. The core pillar (CO) may be formed of an insulating film (e.g., an oxide film) or a conductive film.

[0061] Memory cells and select transistors can be formed at points where cell plugs (CPL) intersect conductive films (CD), respectively. The cell plugs (CPL) can be used as channel regions of a cell string. For example, memory cells (MC) and source select transistors (SSL) of FIG. 1 can be formed at points where cell plugs (CPL) and conductive films (CD) intersect, respectively.

[0062] Selective plugs (SPL) can be formed on the laminate (STK). Selective plugs (SPL) can be connected to cell plugs (CPL), respectively. Selective plugs (SPL) can be located in the Z direction of the laminate (STK). For example, selective plugs (SPL) can be located in the Z direction relative to the conductive films (CD) and interlayer insulating films (IL).

[0063] Each of the select plugs (SPL) may include a channel pillar (CHP) in contact with the capping membrane (CAP) of the cell plugs (CPL). The channel pillars (CHP) may have a cylindrical shape extending in the Z direction. The channel pillars (CHP) may include doping regions (DP). For example, doping regions (DP) may be formed on the top of each of the channel pillars (CHP). The doping regions (DP) may be regions where impurities are injected into the channel pillars (CHP).

[0064] Each of the select plugs (SPL) may include a gate insulating film (GI) in contact with the side of the channel pillar (CHP). The gate insulating film (GI) may be located between the channel pillar (CHP) and the select line (SL). The gate insulating film (GI) may surround at least a portion of the channel pillar (CHP). For example, the gate insulating film (GI) may completely surround the remaining portion of the channel pillar (CHP) excluding the doping region (DP). Additionally, the gate insulating film (GI) may surround at least a portion of the side of the doping region (DP). The upper surface of the gate insulating film (GI) may be located between the upper surface of the doping region (DP) and the lower surface of the doping region (DP).

[0065] Each of the select plugs (SPL) may include a barrier film (BA) in contact with the side of the gate insulating film (GI). The barrier film (BA) may be located between the gate insulating film (GI) and the select line (SL). The barrier film (BA) may surround at least a portion of the channel pillar (CHP) and at least a portion of the gate insulating film (GI). The height of the barrier film (BA) may be lower than that of the channel pillar (CHP) and the gate insulating film (GI).

[0066] Referring to FIG. 3a and FIG. 3b together, a first portion (P1) of the barrier membrane (BA) may be located between the channel column (CHP) and the selection line (SL). The first portion (P1) may not protrude upward relative to the selection lines (SL). For example, the upper surface of the first portion (P1) may be located at an equivalent level to the upper surface of the selection lines (SL). Additionally, a second portion (P2) of the barrier membrane (BA) may be located between the channel column (CHP) and the separation structure (IS). The second portion (P2) may not protrude upward relative to the separation structure (IS). For example, the upper surface of the second portion (P2) may be located at an equivalent level to the upper surface of the separation structure (IS).

[0067] The height of the first part (P1) of the barrier membrane (BA) (e.g., length in the Z direction) may be lower than the height of the second part (P2). Because the height of the separation structure (IS) is higher than the height of the selection lines (SL), the height of the second part (P2) may be higher than the height of the first part (P1). The upper surface of the second part (P2) may be located higher than the upper surface of the first part (P1). Additionally, the lower surface of the first part (P1) and the lower surface of the second part (P2) may be located at the same level.

[0068] The liner film (LL) may extend along the upper surface of the stack (SKT). ​​The liner film (LL) may extend from the gate insulating films (GI) of the select plugs (SPL). The liner film (LL) may have a thickness equal to or greater than that of the gate insulating films (GI). The liner film (LL) may be in contact with the lower surface of the select lines (SL), the lower surface of the barrier films (BA), and the lower surface of the isolation structure (IS). The select plugs (SPL) may protrude through the stack (STK) relative to the isolation structure (IS) and the select lines (SL). Since the isolation structure (IS) and the select lines (SL) are located on the liner film (LL) and the select plugs (SPL) are in direct contact with the cell plugs (CPL), the lower surface of the select plugs (SPL) may be located below the lower surface of the isolation structure (IS) and the select lines (SL). FIG. 3b illustrates the boundary between the liner film (LL) and the gate insulating film (GI), but this is for convenience of explanation and the interface between the liner film (LL) and the gate insulating film (GI) may not be observed in the actual product.

[0069] Cell contacts (CCTs) can each be connected to select plugs (SPLs). Cell contacts (CCTs) can be in direct contact with channel pillars (CHPs). For example, cell contacts (CCTs) can be in contact with doping regions (DPs). The width of the cell contacts (CCTs) (e.g., length in the X direction) can be wider than the width of the channel pillars (CHPs). Cell contacts (CCTs) can be in contact with the upper surface of the gate insulating film (GI). Doping regions (DPs) can extend into the interior of the cell contacts (CCTs). Cell contacts (CCTs) can be electrically connected to cell plugs (CPLs) and select plugs (SPLs) to a bit line (e.g., bit line (BL) in FIG. 1). Cell contacts (CCTs) may include a conductive material such as tungsten.

[0070] The slit (SI) can penetrate the stack (STK) and the select line (SL). The slit (SI) can penetrate the interlayer insulating films (IL) and conductive films (CD) of the stack (STK). Select lines (SL) included in different memory blocks can be insulated from each other by the slit (SI). Although the cell region (CR) and the contact region (CTR) are shown as being separated by the slit (SI) in FIG. 3b, when referred to in conjunction with FIG. 3a, the slit (SI) can be placed between different memory blocks (e.g., the nth memory block (BLKn) and the n+1th memory block (BLK(n+1))). That is, since FIG. 3b illustrates the cell region (CR) of the n+1 memory block (BLK(n+1)) and the contact region (CTR) of the n memory block (BLKn), the slit (SI) appears to be located between the cell region (CR) and the contact region (CTR), but the slit (SI) does not separate the cell region (CR) and the contact region (CTR).

[0071] Select line contacts (SCT) and word line contacts (WCT) may be placed within a contact area (CTR). The select line contact (SCT) may be in contact with the upper surface of the select line (SL). The select line contact (SCT) may extend in the Z direction from the select line (SL). The select line contact (SCT) may be electrically connected to the select line (SL). Referring to FIGS. 3a and 3b, the select line contacts (SCT) may be connected to the select lines (SL) in a 1:1 manner, respectively.

[0072] Word line contacts (WCTs) can be in contact with conductive films (CDs). Word line contacts (WCTs) can extend in the Z direction from the conductive films (CDs). Word line contacts (WCTs) can be electrically connected to each of the conductive films (CDs). Within the contact region (CTR), the conductive films (CDs) included in the steps of the laminate (STK) and the word line contacts (WCTs) can be connected to each other. For example, the word line contacts (WCTs) can be in contact with any one of the conductive films (CDs) by penetrating the liner film (LL), the step insulating film (SIL), the second cover film (CV2), the first cover film (CV1), and the interlayer insulating film (IL). The word line contacts (WCTs) illustrated in FIG. 3b are only partially illustrated, and a memory block (e.g., the nth memory block (BLKn)) may include word line contacts (WCTs) corresponding to the number of layers of conductive films (CD). Additionally, a memory block (e.g., the nth memory block (BLKn)) may further include source select line contacts connected to a conductive film (CD) used as a source select line (SSL).

[0073] Word line contacts (WCT) can penetrate the first upper insulation pattern (UIP1) and the second upper insulation pattern (UIP2). The first upper insulation pattern (UIP1) can be located on the contact area (CTR) of the laminate (STK). The first upper insulation pattern (UIP1) can be superimposed on the stepped structure of the laminate (STK). The first upper insulation pattern (UIP1) can be in contact with the liner film (LL). The height of the first upper insulation pattern (UIP1) (e.g., length in the Z direction) can correspond to the height of the separation structure (IS). The first upper insulation pattern (UIP1) can be in contact with the side of the selection line (SL). The first upper insulation pattern (UIP1) can be composed of the same material as the separation structure (IS). For example, the first upper insulation pattern (UIP1) may include an oxide material.

[0074] The second upper insulating pattern (UIP2) can cover the stack (STK), select lines (SL), slit (SI), and the first upper insulating pattern (UIP1). The second upper insulating pattern (UIP2) can be in contact with the gate insulating films (GI) of the select plugs (SPL). The second upper insulating pattern (UIP2) can surround the cell contacts (CCT). The cell contacts (CCT) can be insulated from each other by the second upper insulating pattern (UIP2). The second upper insulating pattern (UIP2) can be in contact with the upper surface of the select lines (SL). The second upper insulating pattern (UIP2) can be in contact with the upper surface of the slit (SI) and with some of its sides. The select line contacts (SCT) and word line contacts (WCT) can pass through the second upper insulating pattern (UIP2). The second upper insulating pattern (UIP2) may include an insulating material (e.g., an oxide).

[0075] FIG. 3c is an enlarged view of area C of FIG. 3b. Among the configurations shown in FIG. 3c, the configurations described with reference to FIG. 3a and FIG. 3b may be briefly described or omitted.

[0076] Referring to FIG. 3c, the upper width of the select plugs (SPL) may be narrower than or equal to the lower width. For example, as shown in FIG. 3b, the upper and lower widths of the select plugs (SPL) may be substantially equal. As another example, as shown in FIG. 3c, the width of the select plugs (SPL) may vary with height.

[0077] The channel pillars (CHP) may have a truncated cone shape that narrows toward the top. For example, the lower width of each channel pillar (CHP) may be 85 nm and the upper width may be 64 nm. The smaller the difference between the upper and lower widths of the channel pillars (CHP), the better the operating performance of the drain select transistor can be. The gate insulating films (GI) may be formed with a constant thickness (e.g., 10 nm) along the sides of the channel pillars (CHP). The barrier films (BA) may be formed with a constant thickness (e.g., 10 nm) along the sides of the gate insulating films (GI). The first portion (P1) of the barrier films (BA) may have a lower height than the second portion (P2).

[0078] Gate insulating films (GI) can be extended from the liner film (LL). The liner film (LL) can be formed of the same material as the gate insulating films (GI).

[0079] Referring to FIG. 3b, a residual portion (RP) may be formed on the liner membrane (LL). The residual portion (RP) may be located between the liner membrane (LL) and the select line (SL). The residual portion (RP) may be formed of the same material as the separation structure (IS). The reason for the formation of the residual portion (RP) will be described later with reference to FIG. 4h.

[0080] Referring to FIG. 3d, the width (e.g., length in the Y direction) of the separation structure (IS) can be formed wider than that of FIG. 3a. The width of the separation structure (IS) shown in FIG. 3d may be the maximum width that the separation structure (IS) can have. For example, the separation structure (IS) may have various widths as long as the barrier membranes (BA) included in the selection plugs (SPL) of the second and third rows in FIG. 3d can come into contact with the selection lines (SL).

[0082] FIGS. 4a to 4q are drawings for explaining a method of manufacturing a memory device according to an embodiment of the present invention. FIGS. 4a to 4q are cross-sectional views corresponding to the AA' section of FIG. 3a.

[0083] Referring to FIG. 4a, a pre-laminated structure (pSTK) may be formed on a substrate (SUB). The pre-laminated structure (pSTK) may include sacrificial films (SF) and interlayer insulating films (IL). The sacrificial films (SF) and interlayer insulating films (IL) may be stacked alternately along the Z direction.

[0084] The interlayer insulating films (IL) can be formed from an insulating material. For example, the interlayer insulating films (IL) can be formed from an oxide film. The interlayer insulating films (IL) may include a silicon oxide film or an equivalent oxide material. The sacrificial films (SF) can be formed from a material that can be selectively removed in a subsequent process. Thus, the sacrificial films (SF) can be formed from a material with an etch selectivity different from that of the interlayer insulating films (IL). The sacrificial films (SF) may include a nitride material. For example, the sacrificial films (SF) can be formed from a silicon nitride film.

[0085] Subsequently, cell plugs (CPL) penetrating the prefabricated laminate (pSTK) may be formed. The cell plugs (CPL) may extend into the substrate (SUB) by penetrating the interlayer insulating films (IL) and sacrificial films (SF) of the prefabricated laminate (pSTK). The cell plugs (CPL) may include a blocking film (BX), a charge trap film (CT), a tunneling film (TX), a channel film (CH), a core pillar (CO), and a capping film (CAP). The capping film (CAP) may be formed from an undoped silicon film.

[0086] Subsequently, parts of the interlayer insulating films (IL) and sacrificial films (SF) may be etched to form a step structure. For example, a step structure may be formed so that a pre-laminated structure (pSTK) may include steps within the contact region (CTR) of FIGS. 3a and 3b.

[0087] Referring to FIG. 4b, a first cover film (CV1), a second cover film (CV2), and a step insulation film (SIL) can be sequentially formed on interlayer insulation films (IL) and sacrificial films (SF) formed in a step structure. The first cover film (CV1) can be formed conformally along the surfaces of the interlayer insulation films (IL) and sacrificial films (SF). The second cover film (CV2) can be formed conformally along the surface of the first cover film (CV1). After the step insulation film (SIL) is formed on the second cover film (CV2), a planarization process can be performed.

[0088] Referring to FIG. 4c, a portion of the first cover film (CV1), a portion of the second cover film (CV2), and a portion of the step insulating film (SIL) can be removed so that the upper surface of the cell plugs (CPL) is exposed. For example, the upper portion of the prefabricated laminate (pSTK) can be removed through a planarization process until the upper surface of the cell plugs (CPL) is exposed.

[0089] Subsequently, support structures (SS) penetrating the prefabricated laminate (pSTK) may be formed. The support structures (SS) may penetrate the prefabricated laminate (pSTK) and extend into the interior of the substrate (SUB).

[0090] Referring to FIG. 4d, a first semiconductor film (SM1), a barrier insulating film (BI), a second semiconductor film (SM2), and a hard mask (HM) may be sequentially formed on a prefabricated laminate (pSTK). The first semiconductor film (SM1) may be in contact with the upper surface of the prefabricated laminate (pSTK). The first semiconductor film (SM1) may be formed thicker than the second semiconductor film (SM2). For example, the height of the first semiconductor film (SM1) may be 250 nm, and the height of the second semiconductor film (SM2) may be 50 nm. The first semiconductor film (SM1) and the second semiconductor film (SM2) may comprise equivalent materials. For example, the first semiconductor film (SM1) and the second semiconductor film (SM2) may comprise polysilicon. The barrier insulating film (BI) may extend between the first semiconductor film (SM1) and the second semiconductor film (SM2). A barrier insulating film (BI) may be placed between the first semiconductor film (SM1) and the second semiconductor film (SM2) to protect the first semiconductor film (SM1). The barrier insulating film (BI) may be formed to be thin, approximately 5 nm. The barrier insulating film (BI) may include an oxide material. A hard mask (HM) may cover the first semiconductor film (SM1), the barrier insulating film (BI), and the second semiconductor film (SM2). The hard mask (HM) may include a nitride material.

[0091] Referring to FIG. 4e, a first semiconductor film (SM1), a second semiconductor film (SM2), and a hard mask (HM) can be patterned to form first semiconductor patterns (SP1), second semiconductor patterns (SP2), and hard mask patterns (HMP). A portion of each of the first semiconductor film (SM1), barrier insulating film (BI), second semiconductor film (SM2), and hard mask (HM) can be etched using a self-aligning etching process. The first semiconductor patterns (SP1), barrier insulating film (BI), second semiconductor patterns (SP2), and hard mask patterns (HM) can be superimposed on cell plugs (CPL). The first semiconductor patterns (SP1) can each be in contact with the cell plugs (CPL).

[0092] Referring to FIG. 4f, an oxidation process can be performed to oxidize the surfaces of the first semiconductor patterns (SP1) and the second semiconductor patterns (SP2). The residual region remaining after the surface of the first semiconductor patterns (SP1) is oxidized can be referred to as channel pillars (CHP). The oxide film formed by the oxidation of the surface of the first semiconductor patterns (SP1) can be referred to as a gate insulating film (GI). The channel pillars (CHP) can each be connected to cell plugs (CPL). The surface of the second semiconductor patterns (SP2) can also be oxidized to form a gate insulating film (GI). The gate insulating film (GI) can surround the sides of the channel pillars (CHP) and the second semiconductor patterns (SP2). The upper surface of the gate insulating film (GI) can be located at a level equivalent to the upper surface of the second semiconductor patterns (SP2). Channel pillars (CHP), barrier insulating film (BI), second semiconductor pattern (SP2), gate insulating film (GI), barrier film (BA), and hard mask pattern (HMP) can constitute preliminary selection plugs (pSPL). The preliminary selection plugs (pSPL) can each be connected to cell plugs (CPL). While the gate insulating film (GI) is being formed, a liner film (LL) can be formed along the upper surface of the preliminary stack (pSTK).

[0093] Subsequently, barrier films (BA) may be deposited on the side of the gate insulating films (GI). The barrier films (BA) may surround the side of the gate insulating films (GI). The barrier films (BA) may be in contact with the side of the gate insulating films (GI). The barrier film (BA) may be located on the liner film (LL). The upper surface of the barrier film (BA) may be located at a level equivalent to the upper surface of the second semiconductor patterns (SP2) and the upper surface of the gate insulating films (GI). The barrier films (BA) may comprise titanium nitride.

[0094] Referring to FIG. 4g, a first upper insulating layer (UIL1) covering a pre-stack (pSTK) and pre-selection plugs (pSPL) may be formed. The first upper insulating layer (UIL1) may be formed to surround channel pillars (CHP), second semiconductor patterns (SP2), hard mask patterns (HMP), gate insulating layers (GI), and barrier layers (BA) included in the pre-selection plugs (pSPL). The first upper insulating layer (UIL1) may include an oxide material.

[0095] Subsequently, a slit opening (SOP) penetrating the first upper insulating layer (UIL1) and the pre-laminated layer (pSTK) may be formed. The sides of the sacrificial layers (SF) may be exposed by the slit opening (SOP). Subsequently, the sacrificial layers (SF) may be replaced with conductive layers (CD) through the slit opening (SOP). While the sacrificial layers (SF) are removed and the space between the interlayer insulating layers (IL) is empty, cell plugs (CPL) and support structures (SS) may support the interlayer insulating layers (IL). The conductive layers (CD) and the interlayer insulating layers (IL) may form a laminate (STK).

[0096] Referring to FIG. 4h, a slit (SI) that fills a slit opening (SOP) may be formed. The slit (SI) may include a slit insulating film. For example, an insulating material may be filled within the slit opening (SOP) to form a slit insulating film. The slit insulating film may include a material with a high etching selectivity ratio with the first upper insulating film (UIL1).

[0097] Subsequently, a portion of the first upper insulating film (UIL1) may be removed to form a first upper insulating pattern (UIP1) and a separation structure (IS). For example, after a first etching process is performed to reduce the height of the first upper insulating film (UIL1), a second etching process may be performed to remove the remaining regions of the first upper insulating film (UIL1), excluding a portion of the height-reduced first upper insulating film (UIL1). Thus, the first upper insulating pattern (UIP1) and the separation structure (IS) may contain the same material. Additionally, the first upper insulating pattern (UIP1) and the separation structure (IS) may have equivalent heights. The height of the separation structure (IS) may be lower than the height of the channel pillars (CHP). At this time, if a portion of the first upper insulating film (UIL1) remains unetched during the second etching process, a residual portion (RP) shown in FIG. 3c may be formed.

[0098] The separation structure (IS) can be in contact with the preliminary selection plugs (pSPL). The first upper insulation pattern (UIP1) can be superimposed on the steps of the laminate (STK).

[0099] Referring to FIG. 4i, selection lines (SL) may be formed on a laminate (STK). The selection lines (SL) may be separated from one another by a separation structure (IS) and a slit (SI). The selection lines (SL) may be in contact with preliminary selection plugs (pSPL). The selection lines (SL) may fill the space between the preliminary selection plugs (pSPL). For example, a conductive material covering the laminate (STK), preliminary selection plugs (pSPL), separation structure (IS), slit (SI), and first upper insulating pattern (UIP1) may be formed. Subsequently, a portion of the conductive film may be removed to be divided into a plurality of selection lines (SL). The height of the selection lines (SL) may be formed lower than the height of the separation structure (IS).

[0100] Next, a portion of the barrier film (BA) can be removed. Areas of the barrier film (BA) that are not covered by the selection line (SL) or the separation structure (IS) can be removed.

[0101] Referring to FIG. 4j, impurities may be injected into the channel pillars (CHP) to form doped regions (DP). The doped regions (DP) may be located below the barrier insulating films (BI). The doped regions (DP) may be located above the channel pillars (CHP). A junction may be formed by an implantation process injecting impurities into a region of the channel pillars (CHP).

[0102] Referring to FIG. 4k, preliminary selection plugs (pSPL), selection lines (SL), slits (SI), and a second upper insulation pattern (UIP2) covering the first upper insulation pattern (UIP1) may be formed. The upper surface of the second upper insulation pattern (UIP2) may be equivalent to the upper surface of the hard mask patterns (HMP). The second upper insulation pattern (UIP2) may expose the upper surface of the hard mask patterns (HMP).

[0103] Next, the hard mask patterns (HMP) can be removed. Also, the second semiconductor patterns (SP2) can be removed. As the hard mask patterns (HMP) and the second semiconductor patterns (SP2) are removed, the upper surface of the barrier insulating films (BI) may be exposed and some of the inner sides of the gate insulating films (GI) may be exposed. The space where the hard mask patterns (HMP) and the second semiconductor patterns (SP2) are removed may be referred to as the first contact openings (COP1).

[0104] Referring to FIG. 4l, the first contact openings (COP1) can be expanded. For example, parts of the barrier insulating films (BI), gate insulating films (GI), and the second upper insulating pattern (UIP2) exposed through the first contact openings (COP1) can be etched. The width and depth of the first contact openings (COP1) can be increased compared to FIG. 4k. Doping regions (DP) can be exposed through the expanded first contact openings (COP1). The channel pillar (CHP), gate insulating film (GI), and barrier film (BA) containing the doping region (DP) can form a select plug (SPL).

[0105] Additionally, a second contact opening (COP2) may be formed that penetrates the second upper insulation pattern (UIP2) and exposes the selection line (SL). Additionally, third contact openings (COP3) may be formed that penetrate the second upper insulation pattern (UIP2), the first upper insulation pattern (UIP1), the liner film (LL), the step insulation film (SIL), the second cover film (CV2), the first cover film (CV1), and the interlayer insulation film (IL), respectively, and expose the conductive films (CD), respectively.

[0106] Referring to FIG. 4m, a conductive material may be filled in the first contact openings (COP1), the second contact opening (COP2), and the third openings (COP3). Cell contacts (CCT) may be formed in each of the first contact openings (COP1). Select line contacts (SCT) may be formed in the second contact opening (COP2). Word line contacts (WCT) may be formed in the third contact openings (COP3).

[0107] Referring to FIG. 4n, a third upper insulating pattern (UIP3) may be formed covering a second upper insulating pattern (UIP2), cell contacts (CCT), select line contacts (SCT), and word line contacts (WCT). The third upper insulating pattern (UIP3) may include an oxide material. Subsequently, first contacts (CT1) may be formed penetrating the third upper insulating pattern (UIP3). The first contacts (CT1) may contact the cell contacts (CCT), select line contacts (SCT), and word line contacts (WCT), respectively. The first contacts (CT1) may include a conductive material.

[0108] Subsequently, a fourth upper insulating pattern (UIP4) may be formed on the third upper insulating pattern (UIP3). The fourth upper insulating pattern (UIP4) may include a nitride material. Subsequently, second contacts (CT2) penetrating the fourth upper insulating pattern (UIP4) may be formed. The second contacts (CT2) may each contact the first contacts (CT1). The second contacts (CT2) may include a conductive material.

[0109] Subsequently, bit lines (BL), a third contact (CT3), upper bonding pads (UPD), and a fifth upper insulation pattern (UIP5) may be formed on the fourth upper insulation pattern (UIP4). The bit lines (BL), the third contact (CT3), and the upper bonding pads (UPD) may each include a conductive material. The upper bonding pads (UPD) may be exposed to the outside through the upper surface of the fifth upper insulation pattern (UIP5).

[0110] Referring to FIG. 4o, a substructure (LSTR) may be formed including a lower substrate (LSUB), a lower insulating layer (LIL), a transistor (TR), peripheral circuit contacts (PCT), peripheral wiring (PLN), and lower bonding pads (LPD). The substructure (LSTR) may be understood to include the substrate (SST) and peripheral circuit structure (PC) of FIG. 2.

[0111] Next, the structure of FIG. 4n can be flipped upside down and bonded onto the lower structure (LSTR). The upper bonding pads (UPD) can each come into contact with the lower bonding pads (LPD).

[0112] Referring to FIG. 4p, the substrate (SUB) can be removed. Subsequently, a portion of the blocking film (BX), a portion of the charge trap film (CT), and a portion of the tunneling film (TX) included in the cell plugs (CPL) can be removed. Thus, the channel films (CH) can be exposed to the outside. While a portion of the blocking film (BX), a portion of the charge trap film (CT), and a portion of the tunneling film (TX) are etched, a portion of the support structures (SS) can be etched.

[0113] Referring to FIG. 4q, a source line (SC) in contact with the channel membrane (CH) of the cell plugs (CPL) can be formed. The source line (SC) may correspond to the source line (SC) of FIG. 1. The source line (SC) may include silicon.

[0115] FIG. 5 is a drawing for explaining a memory card system to which the memory device of the present invention is applied.

[0116] Referring to FIG. 5, the memory card system (3000) includes a controller (3100), a memory device (3200), and a connector (3300).

[0117] The controller (3100) may be connected to the memory device (3200). The controller (3100) may be configured to access the memory device (3200). For example, the controller (3100) may be configured to control program operations, read operations, or erase operations of the memory device (3200), or to control background operations. The controller (3100) may be configured to provide an interface between the memory device (3200) and a host. The controller (3100) may be configured to run firmware for controlling the memory device (3200). For example, the controller (3100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0118] The controller (3100) can communicate with an external device through a connector (3300). The controller (3100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller (3100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe. For example, the connector (3300) may be defined by at least one of the various communication standards described above.

[0119] The memory device (3200) may include a plurality of memory cells and may be configured in the same way as the memory device (100) shown in FIG. 1.

[0120] The controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card. For example, the controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC), or Universal Flash Storage (UFS).

[0122] FIG. 6 is a diagram illustrating a Solid State Drive (SSD) system to which the memory device of the present invention is applied.

[0123] Referring to FIG. 6, the SSD system (4000) may include a host (4100) and an SSD (4200). The SSD (4200) may exchange signals with the host (4100) through a signal connector (4001) and receive power through a power connector (4002). The SSD (4200) may include a controller (4210), a plurality of memory devices (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0124] The controller (4210) can control a plurality of memory devices (4221 to 422n) in response to a signal received from the host (4100). For example, the signal may be a signal based on the interface between the host (4100) and the SSD (4200). For example, the signal may be a signal defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, or NVMe.

[0125] A plurality of memory devices (4221 to 422n) may include a plurality of memory cells configured to store data. Each of the plurality of memory devices (4221 to 422n) may be configured identically to the memory device (100) shown in FIG. 1. The plurality of memory devices (4221 to 422n) may communicate with the controller (4210) through channels (CH1 to CHn).

[0126] The auxiliary power supply unit (4230) can be connected to the host (4100) via the power connector (4002). The auxiliary power supply unit (4230) can receive power voltage from the host (4100) and charge. The auxiliary power supply unit (4230) can provide power voltage to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power supply unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power supply unit (4230) may be located on the main board and can provide auxiliary power to the SSD (4200).

[0127] The buffer memory (4240) can operate as a buffer memory of the SSD (4200). For example, the buffer memory (4240) can temporarily store data received from the host (4100) or data received from a plurality of memory devices (4221 to 422n), or temporarily store metadata (e.g., mapping tables) of the memory devices (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0128] STK: Laminate CD: Challenge IL: Interlayer insulation film CPL: Cell plug SL: Selection line IS: Separation structure SPL: Select Plug CHP: Channel Pillar DP: Doping Zone GI: Gate insulating layer BA: Barrier

Claims

Claim 1 A memory device comprising: cell plugs penetrating a stack; selection plugs each connected to the cell plugs on the stack; selection lines surrounding the selection plugs on the stack; and a separation structure separating the selection lines from each other and contacting the selection plugs. Claim 2 A memory device according to claim 1, wherein each of the selection plugs comprises: a channel pillar; a gate insulating film in contact with the side of the channel pillar; and a barrier film in contact with the side of the gate insulating film. Claim 3 In paragraph 2, the memory device, wherein the gate insulating film surrounds at least a portion of the channel pillar. Claim 4 In paragraph 2, the memory device further comprises a liner film extending along the upper surface of the laminate, wherein the liner film extends from the gate insulating film. Claim 5 A memory device according to claim 2, wherein the barrier film comprises at least one of a first portion disposed between the gate insulating film and the selection lines; and a second portion disposed between the gate insulating film and the separation structure. Claim 6 In paragraph 5, the second portion of the barrier film is in contact with the side of the separation structure, a memory device. Claim 7 In paragraph 5, the memory device, wherein the first portion of the barrier film does not protrude upward relative to the selection line. Claim 8 In paragraph 5, the second portion of the barrier film does not protrude upward relative to the separation structure, in a memory device. Claim 9 In paragraph 5, a memory device wherein the height of the first portion of the barrier film is lower than the height of the second portion. Claim 10 A memory device according to paragraph 2, wherein the channel pillar includes a doping region and the gate insulating film surrounds at least a portion of the sides of the doping region. Claim 11 A memory device according to claim 10, further comprising a cell contact adjacent to the doping region. Claim 12 A memory device according to claim 1, wherein the height of the separation structure is lower than the height of the selection plugs. Claim 13 A memory device according to claim 1, wherein the height of the separation structure is higher than the height of the selection lines. Claim 14 In claim 1, the separation structure is a memory device that fills the space between adjacent selection plugs among the selection plugs with the separation structure in between. Claim 15 In claim 1, the memory device, wherein the selection lines fill the space between at least some of the selection plugs. Claim 16 A memory device according to claim 1, wherein the selection plugs protrude toward the cell plugs relative to the separation structure and the selection lines. Claim 17 In claim 1, a memory device wherein the upper width of each of the selection plugs is narrower than or equal to the lower width. Claim 18 A memory device according to claim 1, wherein the upper width of the separation structure is wider than or equal to the lower width. Claim 19 A memory device according to claim 1, further comprising selection line contacts connected to each of the selection lines. Claim 20 A memory device according to claim 1, wherein the laminate further comprises alternatingly stacked conductive films and interlayer insulating films, and further comprises word line contacts connected to each of the conductive films. Claim 21 A method for manufacturing a memory device comprising: forming cell plugs penetrating a stack; forming selection plugs on the stack that are each connected to the cell plugs; forming a first upper insulating film covering the stack and the selection plugs; removing a portion of the first upper insulating film to form a separation structure in contact with the selection plugs; and forming selection lines on the stack that are separated from each other by the separation structure and each contact with the selection plugs. Claim 22 A method for manufacturing a memory device according to claim 21, further comprising, after the step of forming the first upper insulating film, the step of forming a slit opening penetrating the first upper insulating film and the laminate; the step of replacing sacrificial films included in the laminate with conductive films using the slit opening; and the step of forming a slit insulating film by filling the slit opening with an insulating material. Claim 23 A method for manufacturing a memory device according to claim 21, wherein, in the step of forming the separation structure, the height of the separation structure is formed to be lower than the height of the selection plugs. Claim 24 A method for manufacturing a memory device according to claim 21, wherein the step of forming the selection lines comprises: forming a conductive film covering the laminate, the selection plugs, and the separation structure; and removing a portion of the conductive film to form selection lines that fill the space between the selection plugs. Claim 25 A method for manufacturing a memory device according to claim 21, wherein, in the step of forming the selection lines, the height of the selection lines is formed to be lower than the height of the separation structure. Claim 26 A method for manufacturing a memory device according to claim 21, wherein the step of forming the selection plugs comprises: forming a first semiconductor film on the laminate; removing a portion of the first semiconductor film to form first semiconductor patterns that each contact the cell plugs; oxidizing the surface of each of the first semiconductor patterns to form channel pillars and gate insulating films surrounding each of the channel pillars; and forming barrier films that contact the sides of the gate insulating films. Claim 27 A method for manufacturing a memory device according to claim 26, wherein the step of forming the selection plugs further comprises: forming a barrier insulating film on the first semiconductor film; forming a second semiconductor film on the barrier insulating film; and removing a portion of the second semiconductor film to form second semiconductor patterns on the first semiconductor patterns. Claim 28 A method for manufacturing a memory device according to claim 27, further comprising, after the step of forming the selection lines, a step of removing a portion of each of the barrier films that is not covered by the separation structure or the selection lines; a step of forming doping regions by injecting impurities into the channel pillars; a step of forming a second upper insulating film covering the selection plugs and the selection lines; a step of removing the second semiconductor patterns; a step of forming contact openings by etching a portion of each of the gate insulating films, the barrier insulating film, and a portion of the second upper insulating film; and a step of forming cell contacts within the contact openings. Claim 29 A method for manufacturing a memory device according to claim 21, further comprising: a step of forming a second upper insulating film covering the selection plugs and the selection lines after the step of forming the selection lines; a step of etching a portion of the second upper insulating film to form contact openings that expose the selection lines; and a step of forming selection line contacts within the contact openings. Claim 30 A method for manufacturing a memory device according to claim 21, further comprising, after the step of forming the cell plugs, the step of forming steps within the laminate, and after the step of forming the selection lines, the step of forming contact openings that expose each of the steps within the laminate; and further comprising the step of forming word line contacts within the contact openings.

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