Semiconductor package

Abstract

A semiconductor package according to an embodiment of the present disclosure comprises a substrate including a junction pad, a semiconductor chip disposed on the substrate and aligned with the junction pad in a first direction, and an underfill disposed on the substrate and surrounding the junction pad, wherein the substrate may include a dummy pad disposed spaced apart from the junction pad in a second direction intersecting the first direction along the surface of the substrate, dislocated from the semiconductor chip with respect to the first direction, and in contact with at least a portion of the underfill.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0002] Due to the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, methods can be utilized to mount multiple semiconductor chips by stacking them on a single package wiring structure, or to stack packages on top of each other. For example, package-in-package (PIP) or package-on-package (POP) semiconductor packages may be used.

[0003] Meanwhile, with the high integration of semiconductor packages, semiconductor chips are stacked vertically, and vertical wiring structures that electrically connect the chips are used. The problem to be solved

[0004] The technical problem that the present invention aims to solve may be to provide a semiconductor package in which underfill control is easy.

[0005] The technical problem that the present invention aims to solve may be to provide a substrate compatible with both SoC and SiP.

[0006] The technical problems of the present disclosure are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor package according to some embodiments of the present disclosure for achieving the above technical problem comprises a substrate including a junction pad, a semiconductor chip disposed on the substrate and aligned with the junction pad in a first direction, and an underfill disposed on the substrate and surrounding the junction pad, wherein the substrate may include a dummy pad disposed spaced apart from the junction pad in a second direction intersecting the first direction along the surface of the substrate, dislocated from the semiconductor chip with respect to the first direction, and in contact with at least a portion of the underfill.

[0008] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a substrate including a junction pad, a semiconductor chip including a junction bump disposed on the substrate and in contact with the junction pad, and an underfill disposed on the substrate and surrounding the junction pad and the junction bump, wherein the substrate may include a dummy pad spaced apart from the junction pad along the surface of the substrate and in contact with at least a portion of the underfill.

[0009] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a substrate including a junction pad, a semiconductor chip spaced apart from the substrate in a first direction, an interposer disposed between the substrate and the semiconductor chip and including a junction bump in contact with the junction pad, and an underfill surrounding the junction pad and the junction bump, wherein the substrate includes a dummy pad spaced apart from the junction pad along the surface of the substrate and in contact with at least a portion of the underfill, and the interposer may include a dummy bump in contact with the dummy pad.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0011] A semiconductor package according to an embodiment of the present disclosure may allow for easy control of the underfill.

[0012] A semiconductor package according to an embodiment of the present disclosure can provide a substrate compatible with both SoC and SiP. Brief explanation of the drawing

[0013] FIG. 1 is a drawing of a semiconductor package according to one embodiment of the present disclosure. FIG. 2 is a drawing of a semiconductor package according to another embodiment of the present disclosure. FIG. 3 is a drawing of a substrate according to one embodiment of the present disclosure. FIG. 4 is a drawing of a substrate according to another embodiment of the present disclosure. FIG. 5 is a drawing of a substrate according to another embodiment of the present disclosure. FIG. 6 is a drawing of a substrate according to another embodiment of the present disclosure. FIG. 7 is a drawing illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure. FIG. 8 is a drawing illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure. FIG. 9 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. FIG. 10 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. FIG. 11 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. FIG. 12 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. FIG. 13 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. FIG. 14 is a drawing illustrating a method for manufacturing a semiconductor package according to another embodiment of the present disclosure. Specific details for implementing the invention

[0014] Prior to the detailed description of the embodiments, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor may appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of this disclosure and do not represent all of the technical spirit of this disclosure; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0015] In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise. Terms such as "comprising" or "constituting" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0016] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms, and said terms may be used for the purpose of distinguishing one component from another. Within the scope of the technical spirit of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. Furthermore, in the drawings, the shapes and sizes of the components may be exaggerated to emphasize clear explanations.

[0017] Furthermore, it should be noted in advance that expressions such as upper side, top, lower side, bottom, side, front, and rear in the following description are based on the direction depicted in the drawings, and may be expressed differently if the direction of the object changes. The shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

[0018] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0020] FIG. 1 is a drawing of a semiconductor package (100) according to one embodiment of the present disclosure. The semiconductor package (100) described with reference to FIG. 1 may include a System on Chip (SoC). The semiconductor package (100) illustrated in FIG. 1 illustrates a part of the components constituting the System on Chip (SoC).

[0021] According to some embodiments, the semiconductor package (100) may include a substrate (10), a semiconductor chip (110), and an underfill (120).

[0022] According to some embodiments, the substrate (10) may be a wiring structure for a package. For example, the substrate (10) may be a printed circuit board (PCB) or a ceramic substrate. Alternatively, the substrate (10) may be a wiring structure for a wafer level package (WLP) manufactured at the wafer level.

[0023] According to some embodiments, the substrate (10) may function as a redistribution layer. For example, the substrate (10) may be a front redistribution layer (FRDL) of a fan-out package.

[0024] In some embodiments, the substrate (10) may be a glass substrate, a ceramic substrate, or a plastic substrate, but is not limited thereto. For example, the substrate (10) may include a resin impregnated in a core material such as glass fiber (glass fiber, glass cloth, glass fabric) together with an inorganic filler, such as prepreg, ABF (Ajinomoto Build-up Film), or FR-4, BT (Bismaleimide Triazine).

[0025] According to some embodiments, the substrate (10) may include a redistribution insulating film (11) and a redistribution structure (12).

[0026] According to some embodiments, when the substrate (10) is a printed circuit board, the redistribution insulating film (11) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. The substrate (10) may include at least one material selected from tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, and liquid crystal polymer.

[0027] In some embodiments, the redistribution insulating film (11) may include a photoimageable dielectric. For example, the redistribution insulating film (11) may include a photosensitive polymer. The photosensitive polymer may be formed from at least one of, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer. As another example, the redistribution insulating film (11) may be formed from a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0028] According to some embodiments, the redistribution insulating film (11) may include a plurality of stacked insulating films. Each of the plurality of insulating films may surround the wiring pattern and wiring via of the redistribution structure (12) to be described later.

[0029] Although not illustrated, the surface of the redistribution insulating film (11) may be covered by a solder resist. For example, a passivation film may be formed on the surface of the redistribution insulating film (11). The passivation film formed on the surface of the redistribution insulating film (11) can protect the redistribution structure (12) and other structures from external shock or moisture. The passivation film may include a solder resist. However, the technical concept of the present invention is not limited thereto.

[0030] According to some embodiments, the redistribution structure (12) may be disposed within the redistribution insulating film (11). The redistribution structure (12) may include a wiring pattern and wiring vias connecting each wiring pattern. For example, the redistribution structure (12) may be a multilayer structure in which two or more wiring patterns or two or more wiring vias are alternately stacked. A wiring pattern may be a portion for horizontal connection between conductive components, and a wiring via may be a portion for vertical connection between conductive components. For example, a wiring pattern may extend in a second direction (+X). A wiring via may connect wiring patterns spaced apart in a first direction (+Z). In this case, the first direction (+Z) may refer to a direction perpendicular to the surface of the substrate (10).

[0031] In some embodiments, the redistribution structure (12) may include a conductive material. For example, the redistribution structure (12) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, but is not limited thereto.

[0032] According to some embodiments, an external connection terminal (14) may be formed on the lower surface of the substrate (10). The external connection terminal (14) may be placed on an external connection pad (13). The external connection terminal (14) may come into contact with the external connection pad (13). For example, the external connection terminal (14) may include a solder ball or a solder bump. As another example, the external connection terminal (14) may include a microbump. The external connection terminal (14) may be spherical or elliptical, but is not limited thereto. The number, spacing, arrangement, shape, etc. of the external connection terminals (14) are not limited to those illustrated and may vary depending on the design. The external connection terminal (14) may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

[0033] According to some embodiments, the external connection terminal (14) can electrically connect the redistribution structure (12) to an external device. Accordingly, the external connection terminal (14) can provide an electrical signal to the redistribution structure (12) or provide an electrical signal provided from the redistribution structure (12) to an external device.

[0034] According to some embodiments, the substrate (10) may include bonding pads (15). A plurality of bonding pads (15) may be spaced apart from each other along the surface of the substrate (10). The bonding pads (15) may protrude in a first direction (+Z) from the surface of the substrate (10). The bonding pads (15) may be electrically connected to a semiconductor chip (110). The semiconductor chip (110) may be placed on the bonding pads (15).

[0035] According to some embodiments, the semiconductor package (100) may include a semiconductor chip (110). The semiconductor chip (110) may include a logic chip. The semiconductor chip (110) may be an application processor (AP), such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), FPGA (Field-Programmable Gate Array), digital signal processor, encryption processor, microprocessor, or microcontroller, but is not limited thereto.

[0036] According to some embodiments, a plurality of semiconductor chips (110) may be arranged. For example, the semiconductor chips (110) may include a first semiconductor chip (110a) and a second semiconductor chip (110b) arranged spaced apart from each other on a substrate (10). The first semiconductor chip (110a) and the second semiconductor chip (110b) may be spaced apart from each other in a second direction (+X) that intersects a first direction (+Z). The first semiconductor chip (110a) and the second semiconductor chip (110b) may be logic chips. For example, the first semiconductor chip (110a) and the second semiconductor chip (110b) may be CPUs (Central Processing Units) of the same type. However, the types of the first semiconductor chip (110a) and the second semiconductor chip (110b) are not limited to those described above.

[0037] According to some embodiments, the semiconductor chip (110) may include a substrate layer (111), a device layer (112), a circuit (113), a semiconductor device (114), a chip pad (115), and a junction bump (116). The description of the above-described components of the semiconductor chip (110) (e.g., substrate layer (111), device layer (112), circuit (113), semiconductor device (114), chip pad (115), junction bump (116)) may be applied to both the first semiconductor chip (110a) and the second semiconductor chip (110b).

[0038] According to some embodiments, the substrate layer (111) may be bulk silicon or silicon-on-insulator (SOI). In another example, the substrate layer (111) may be a silicon substrate. In yet another example, the substrate layer (111) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto. The substrate layer (111) may include conductive regions, for example, impurity-doped wells or impurity-doped structures. The substrate layer (111) may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0039] According to some embodiments, the device layer (112) may be disposed on one side of the substrate layer (111). The device layer (112) may include a plurality of semiconductor devices (114) of various types. The plurality of semiconductor devices (114) may include various microelectronic devices, for example, a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, an RRAM, an image sensor such as a CIS (CMOS imaging sensor), a micro-electro-mechanical system (MEMS), active devices, passive devices, etc.

[0040] According to some embodiments, the device layer (112) may include a circuit (113) that electrically connects a plurality of semiconductor devices (114) and a conductive region of the substrate layer (111). The circuit (113) may be a multilayer structure in which two or more metal wires or two or more via plugs are alternately stacked. The circuit (113) may include a conductive material. For example, the circuit (113) may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, but is not limited thereto.

[0041] According to some embodiments, the semiconductor chip (110) may be arranged such that the device layer (112) among the substrate layer (111) and the device layer (112) faces the substrate (10). The chip pad (115) and the bonding bump (116) of the semiconductor chip (110) may face the substrate (10). The bonding bump (116) may protrude toward the substrate (10). The bonding bump (116) may be connected to the bonding pad (15) of the substrate (10).

[0042] According to some embodiments, the semiconductor package (100) may include a space (110c) formed between a first semiconductor chip (110a) and a second semiconductor chip (110b). The first semiconductor chip (110a) and the second semiconductor chip (110b) may be spaced apart from each other to form the space (110c). The substrate (10) may include a first substrate portion (16) corresponding to the space (110c) formed between the first semiconductor chip (110a) and the second semiconductor chip (110b). The first substrate portion (16) may be a part of the substrate (10) that does not overlap with the semiconductor chip (110) in a first direction (+Z).

[0043] According to some embodiments, the first semiconductor chip (110a) and the second semiconductor chip (110b) may be spaced apart from each other. A gap (D1) may be formed between the first semiconductor chip (110a) and the second semiconductor chip (110b). The size of the gap (D1) between the first semiconductor chip (110a) and the second semiconductor chip (110b) may be smaller than 500 micrometers (500 µm). When the gap between the first semiconductor chip (110a) and the second semiconductor chip (110b) is within a predetermined range, the SI (Signal Integrity) and PI (Power Integrity) characteristics of the semiconductor package (100) may be improved. However, the size of the gap (D1) is not limited to that described above.

[0044] According to some embodiments, the semiconductor package (100) may include an underfill (120). The underfill (120) may be placed between the substrate (10) and the semiconductor chip (110). The underfill (120) may include an adhesive material that fills between the substrate (10) and the semiconductor chip (110). For example, the underfill (120) may include an epoxy resin, a filler, or a hardener. After the underfill (120) is filled between the substrate (10) and the semiconductor chip (110), the substrate (10) and the semiconductor chip (110) may be bonded through curing.

[0045] According to some embodiments, the underfill (120) may flow along the surface of the substrate (10) and then be hardened by curing. The underfill (120) may flow toward the outside of the semiconductor chip (110) before being cured, and a portion of the underfill (120) may be cured at a location that does not overlap with the semiconductor chip (110) in the first direction (+Z). For example, at least a portion of the underfill (120) may be placed on the first substrate portion (16).

[0046] According to some embodiments, the underfill (120) may surround the bonding pad (15) and the bonding bump (116). The underfill (120) may fill between a plurality of bonding pads (15) spaced apart from each other. The underfill (120) may fill between a plurality of bonding bumps (116) spaced apart from each other.

[0047] According to some embodiments, the substrate (10) may include a dummy pad (17). The dummy pad (17) may be spaced apart from the bonding pad (15) along the surface of the substrate (10). The dummy pad (17) may be spaced apart from the bonding pad (15) in a second direction (e.g., +X direction or -X direction). The dummy pad (17) may be positioned offset from the semiconductor chip (110) with respect to the first direction (+Z). The dummy pad (17) may be in contact with at least a portion of the underfill (120).

[0048] According to some embodiments, the dummy pad (17) may be positioned so as not to overlap with the semiconductor chip (110) in the first direction (+Z). The dummy pad (17) may be located outside the semiconductor chip (110) (e.g., in the second direction (+X or -X direction)). The dummy pad (17) may be located further away from the semiconductor chip (110) with respect to the first substrate portion (16).

[0049] According to some embodiments, the dummy pad (17) may include a first dummy pad (17a) positioned offset from the first semiconductor chip (110a) in a first direction (+Z) and a second dummy pad (17b) positioned offset from the second semiconductor chip (110b) in a first direction (+Z). The first dummy pad (17a) may be positioned outside the first semiconductor chip (110a) with respect to the first substrate portion (16). The second dummy pad (17b) may be positioned outside the second semiconductor chip (110b) with respect to the first substrate portion (16).

[0050] According to some embodiments, at least a portion of the underfill (120) may come into contact with the dummy pad (17). Before curing, the underfill (120) may flow outward from the semiconductor chip (110) and come into contact with the dummy pad (17). The underfill (120) may come into contact with the dummy pad (17). The dummy pad (17) may function as a fence for the underfill (120) before curing. For example, the dummy pad (17) may prevent the underfill (120) before curing from flowing excessively outward from the semiconductor chip (110) beyond the dummy pad (17). The dummy pad (17) may control the position of the underfill (120) and control the distribution of the underfill (120) so that the underfill (120) uniformly surrounds the semiconductor chip (110).

[0052] FIG. 2 is a drawing of a semiconductor package (200) according to one embodiment of the present disclosure. The semiconductor package (200) described with reference to FIG. 2 may include a System in Package (SiP). The semiconductor package (200) illustrated in FIG. 2 illustrates a part of the components constituting the System in Package (SiP).

[0053] According to some embodiments, the semiconductor package (200) may include a substrate (10), a semiconductor chip (210), an underfill (220), and an interposer (230).

[0054] According to some embodiments, the substrate (10) may be a wiring structure for a package. For example, the substrate (10) may be a printed circuit board (PCB) or a ceramic substrate. Alternatively, the substrate (10) may be a wiring structure for a wafer level package (WLP) manufactured at the wafer level. The description of the substrate (10) may be the same as the description of the substrate (10) described with reference to FIG. 1. For example, the substrate (10) may include a bonding pad (15) and a dummy pad (17) spaced apart from the bonding pad (15).

[0055] According to some embodiments, the semiconductor package (200) may include a semiconductor chip (210). The semiconductor chip (210) may include a logic chip. The semiconductor chip (210) may be an application processor (AP), such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), FPGA (Field-Programmable Gate Array), digital signal processor, encryption processor, microprocessor, or microcontroller, but is not limited thereto.

[0056] According to some embodiments, a plurality of semiconductor chips (210) may be arranged. For example, the semiconductor chips (210) may include a first semiconductor chip (210a) and a second semiconductor chip (210b) arranged spaced apart from each other on a substrate (10). The first semiconductor chip (210a) and the second semiconductor chip (210b) may be spaced apart from each other in a second direction (+X) that intersects a first direction (+Z). The first semiconductor chip (210a) and the second semiconductor chip (210b) may be logic chips. For example, the first semiconductor chip (210a) and the second semiconductor chip (210b) may be CPUs (Central Processing Units) of the same type. However, the types of the first semiconductor chip (210a) and the second semiconductor chip (210b) are not limited to those described above.

[0057] According to some embodiments, the semiconductor chip (210) may include a substrate layer (211), a device layer (212), a circuit (213), a semiconductor device (214), a chip pad (215), and a chip bump (216). The description of the above-described components of the semiconductor chip (210) (e.g., substrate layer (211), device layer (212), circuit (213), semiconductor device (214), chip pad (215), chip bump (216)) may be applied to both the first semiconductor chip (210a) and the second semiconductor chip (210b). The description of the components of the semiconductor chip (110) described with reference to FIG. 1 (e.g., substrate layer (111), device layer (112), circuit (113), semiconductor device (114), chip pad (115)) can be applied in the same way to the components of the semiconductor chip (210) described with reference to FIG. 2 (e.g., substrate layer (212), device layer (212), circuit (213), semiconductor device (214), chip pad (215)).

[0058] According to some embodiments, the semiconductor chip (210) may include a chip bump (216). Unlike the bonding bump (116) of the semiconductor chip (110) described with reference to FIG. 1, the chip bump (216) of the semiconductor chip (210) described with reference to FIG. 2 may be spaced apart from the substrate (10) and may not be in direct contact with the bonding pad (15) of the substrate (10). The chip bump (216) of the semiconductor chip (210) may be indirectly connected to the bonding pad (15) through an interposer (230).

[0059] According to some embodiments, the semiconductor chip (210) may be positioned such that the device layer (212) among the substrate layer (211) and the device layer (212) faces the substrate (10). The chip pad (215) and chip bump (216) of the semiconductor chip (210) may be positioned such that they face the substrate (10).

[0060] According to some embodiments, the semiconductor package (200) may include a space (210c) formed between a first semiconductor chip (210a) and a second semiconductor chip (210b). The first semiconductor chip (210a) and the second semiconductor chip (210b) may be spaced apart from each other to form the space (210c). The substrate (10) may include a first substrate portion (16) corresponding to the space (210c) formed between the first semiconductor chip (210a) and the second semiconductor chip (210b). The first substrate portion (16) may be a part of the substrate (10) that does not overlap with the semiconductor chip (210) in a first direction (+Z).

[0061] According to some embodiments, the first semiconductor chip (210a) and the second semiconductor chip (210b) may be spaced apart from each other. A gap (D2) may be formed between the first semiconductor chip (210a) and the second semiconductor chip (210b). The size of the gap (D2) between the first semiconductor chip (210a) and the second semiconductor chip (210b) may be smaller than 500 micrometers (500 µm). When the gap between the first semiconductor chip (210a) and the second semiconductor chip (210b) is within a predetermined range, the SI (Signal Integrity) and PI (Power Integrity) characteristics of the semiconductor package (200) may be improved. However, the size of the gap (D2) is not limited to that described above.

[0062] According to some embodiments, the semiconductor package (200) may include molding films (240a, 240b). The molding films (240a, 240b) may surround the semiconductor chip (210). The molding films (240a, 240b) may include an epoxy molding compound (EMC) material. The molding films (240a, 240b) may include a first molding film (240a) surrounding the first semiconductor chip (210a) and a second molding film (240b) surrounding the second semiconductor chip (210b).

[0063] According to some embodiments, the semiconductor package (200) may include an interposer (230). The semiconductor chip (210) may be spaced apart from the substrate (10) in a first direction (+Z). The interposer (230) may be placed between the substrate (10) and the semiconductor chip (210). In the semiconductor package (200) according to an embodiment of the present disclosure, the Power Integrity (PI) characteristics of the semiconductor chip (210) may be improved due to the interposer (230) being placed between the substrate (10) and the semiconductor chip (210).

[0064] According to some embodiments, a plurality of interposers (230) may be arranged. For example, the interposer (230) may include a first interposer (230a) and a second interposer (230b) arranged spaced apart from each other on a substrate (10). The first interposer (230a) and the second interposer (230b) may be spaced apart from each other in a second direction (+X) that intersects a first direction (+Z). The first interposer (230a) may be arranged between the substrate (10) and the first semiconductor chip (210a). The second interposer (230b) may be arranged between the substrate (10) and the second semiconductor chip (210b).

[0065] According to some embodiments, the interposer (230) may include a first layer (231), a second layer (232), an insulating layer (233), interposer wiring (234), a connecting via (235), a first interposer pad (236), a second interposer pad (237), a third interposer pad (238), and a bonding bump (239). The description of the above-described components (e.g., the first layer (231), the second layer (232), the insulating layer (233), the interposer wiring (234), the connecting via (235), the first interposer pad (236), the second interposer pad (237), the third interposer pad (238), and the bonding bump (239)) may apply to both the first interposer (230a) and the second interposer (230b).

[0066] According to some embodiments, the first layer (231) may face the semiconductor chip (210). The first layer (231) may be positioned between the semiconductor chip (210) and the second layer (232). The second layer (232) may be positioned to face the substrate (10). An insulating layer (233) may be positioned between the first layer (231) and the second layer (232) and may bond the first layer (231) and the second layer (232). The interposer wiring (234) may include a conductive material. The interposer wiring (234) may be positioned inside the first layer (231). A connecting via (235) may be electrically connected to the interposer wiring (234). The connecting via (235) may be positioned inside the second layer (232). A first interposer pad (236) may be placed between an interposer wire (234) and a connecting via (235), and may electrically connect the interposer wire (234) and the connecting via (235). The first interposer pad (236) may be placed inside an insulating layer (233). A second interposer pad (237) may protrude from the first layer (231) toward the semiconductor chip (210). The second interposer pad (237) may come into contact with a chip bump (216) of the semiconductor chip (210). A third interposer pad (238) may protrude from the second layer (232) toward the substrate (10). A bonding bump (239) may protrude from the third interposer pad (238) toward the substrate (10). The bonding bump (239) may come into contact with a bonding pad (15).

[0067] According to some embodiments, a signal generated from a semiconductor chip (210) can be transmitted to an interposer (230) through a chip bump (216) and a second interposer pad (237), and can be transmitted to a substrate (10) by passing through an interposer wiring (234), a first interposer pad (236), a connecting via (235), a third interposer pad (238), and a bonding bump (239) in sequence.

[0068] According to some embodiments, the interposer (230) may include dummy vias (2351), interposer dummy pads (2381), and dummy bumps (2391). The dummy vias (2351), interposer dummy pads (2381), and dummy bumps (2391) may be positioned offset from the semiconductor chip (210) in a first direction (+Z). The dummy vias (2351), interposer dummy pads (2381), and dummy bumps (2391) may not overlap with the semiconductor chip (210) in the first direction (+Z).

[0069] According to some embodiments, the dummy via (2351) may not be connected to the interposer wiring (234). The dummy via (2351) may increase the rigidity of the second layer (232). The interposer dummy pad (2381) may connect the dummy via (2351) and the dummy bump (2391). The dummy bump (2391) may come into contact with the dummy pad (17) of the substrate (10).

[0070] According to some embodiments, the semiconductor package (200) may include an underfill (220). The underfill (220) may be placed between the substrate (10) and the interposer (230). The underfill (220) may include an adhesive material that fills between the substrate (10) and the interposer (230). For example, the underfill (220) may include an epoxy resin, a filler, or a hardener. After the underfill (220) is filled between the substrate (10) and the interposer (230), the substrate (10) and the interposer (230) may be bonded through curing.

[0071] According to some embodiments, the underfill (220) may flow along the surface of the substrate (10) and then be hardened by curing. The underfill (220) may flow toward the outside of the interposer (230) before being cured, and a portion of the underfill (220) may be cured at a location that does not overlap with the semiconductor chip (210) in the first direction (+Z). For example, at least a portion of the underfill (220) may be placed on the first substrate portion (16).

[0072] According to some embodiments, the underfill (220) may surround the bonding pad (15) and the bonding bump (239). The underfill (220) may fill between a plurality of bonding pads (15) spaced apart from each other. The underfill (220) may fill between a plurality of bonding bumps (239) spaced apart from each other.

[0073] According to some embodiments, the substrate (10) may include a dummy pad (17). The dummy pad (17) may be spaced apart from the bonding pad (15) along the surface of the substrate (10). The dummy pad (17) may be spaced apart from the bonding pad (15) in a second direction (e.g., +X direction or -X direction). The dummy pad (17) may be positioned offset from the semiconductor chip (210) with respect to the first direction (+Z). The dummy pad (17) may be in contact with at least a portion of the underfill (220).

[0074] According to some embodiments, the dummy pad (17) may be positioned so as not to overlap with the semiconductor chip (210) in the first direction (+Z). The dummy pad (17) may be located outside the semiconductor chip (210) (e.g., in the second direction (+X or -X direction)). The dummy pad (17) may be located further away from the semiconductor chip (210) with respect to the first substrate portion (16).

[0075] According to some embodiments, the dummy pad (17) may include a first dummy pad (17a) positioned offset from the first semiconductor chip (210a) in a first direction (+Z) and a second dummy pad (17b) positioned offset from the second semiconductor chip (210b) in a first direction (+Z). The first dummy pad (17a) may be positioned outside the first semiconductor chip (210a) with respect to the first substrate portion (16). The second dummy pad (17b) may be positioned outside the second semiconductor chip (210b) with respect to the first substrate portion (16).

[0076] According to some embodiments, at least a portion of the underfill (220) may come into contact with the dummy pad (17). Before curing, the underfill (220) may flow outward of the interposer (230) and come into contact with the dummy pad (17). The underfill (220) may come into contact with the dummy pad (17) after coming into contact with it. The dummy pad (17) may function as a fence for the underfill (220) before it comes into contact with it. For example, the dummy pad (17) may prevent the underfill (220) before it comes into contact with it from flowing excessively outward of the interposer (230) beyond the dummy pad (17). The dummy pad (17) may control the position of the underfill (220) and control the distribution of the underfill (220) so that the underfill (220) evenly surrounds the interposer (230).

[0077] According to some embodiments, the underfill (220) may surround the dummy pad (17) and the dummy bump (2391). By surrounding the dummy pad (17) and the dummy bump (2391) that are in contact with each other, the underfill (220) may enhance the adhesion between the dummy pad (17) and the dummy bump (2391). At least a portion of the underfill (220) may be positioned on the outside of the dummy pad (17) and the dummy bump (2391) (e.g., in a second direction (-X or +X direction)).

[0079] FIGS. 3 to 6 are top views of substrates (10, 20, 30, 40) according to various embodiments of the present disclosure. The description of the substrate (10) described with reference to FIGS. 1 and FIG. 2 can be applied in the same way to the substrates (10, 20, 30, 40) described with reference to FIGS. 3 to 6.

[0080] According to some embodiments, the substrate (10, 20, 30, 40) may include a redistribution insulating film (11, 21, 31, 41), a bonding pad (15, 25, 35, 45), a first substrate portion (16, 26, 36, 46), and a dummy pad (17, 27, 37, 47). The description of the above-described components (e.g., redistribution insulating film, bonding pad, first substrate portion, dummy pad) may be applied in the same way as the description of the components (e.g., redistribution insulating film (11), bonding pad (15), first substrate portion (16), dummy pad (17)) described with reference to FIG. 1 and FIG. 2.

[0081] According to some embodiments, the substrate (10, 20, 30, 40) may include a first region (18a, 18b, 28a, 28b, 38a, 38b, 48a, 48b) and a second region (19a, 19b, 29a, 29b, 39a, 39b, 49a, 49b). The first region (18a, 18b, 28a, 28b, 38a, 38b, 48a, 48b) may be a part of the substrate (10) on which a plurality of bonding pads (15, 25, 35, 45) are disposed. The second region (19a, 19b, 29a, 29b, 39a, 39b, 49a, 49b) may be a part of the substrate (10) on which a plurality of dummy pads (17, 27, 37, 47) are placed. The second region (19a, 19b, 29a, 29b, 39a, 39b, 49a, 49b) may surround a part of the first region (18a, 18b, 28a, 28b, 38a, 38b, 48a, 48b).

[0082] Referring to FIG. 3, the substrate (10) may include a redistribution insulating film (11), a bonding pad (15), a first substrate portion (16), and a dummy pad (17). The substrate (10) may include a first region (18a, 18b) in which a plurality of bonding pads (15) are disposed. The substrate (10) may include a second region (19a, 19b) in which a plurality of dummy pads (17) are disposed. The second region (19a, 19b) may surround a portion of the first region (18a, 18b). The second region (19a, 19b) may surround only a portion of the perimeter defining the first region (18a, 18b) and not surround the remaining portion. For example, the perimeter of the first region (18a, 18b) facing the first substrate portion (16) may not be surrounded by the second region (19a, 19b). Dummy pads (17) may not be placed between the perimeter of the first-1 region (18a) facing the first substrate portion (16) and the perimeter of the first-2 region (18b). In the direction in which the first-1 region (18a) and the first-2 region (18b) are spaced apart, dummy pads (17) may not be placed between the first-1 region (18a) and the first-2 region (18b). For example, in the second direction (-X or +X direction), dummy pads (17) may not be placed between the first-1 region (18a) and the first-2 region (18b). A bonding pad (15) may be placed on both sides of the first substrate portion (16) with the first substrate portion (16) in between. The first region (18a, 18b) may include a first-1 region (18a) formed on one side of the first substrate portion (16) and a first-2 region (18b) formed at a position opposite to the first-1 region (18a) with respect to the first substrate portion (16). The second region (19a, 19b) may include a second-1 region (19a) surrounding a part of the first-1 region (18a) and a second-2 region (19b) surrounding a part of the first-2 region (18b).The first dummy pad (17a) may be located inside the second-1 region (19a). The second dummy pad (17b) may be located inside the second-2 region (19b). The first cross-sectional area of ​​the joining pad (15) perpendicular to the first direction (+Z) may be smaller than the second cross-sectional area of ​​the dummy pad (17) perpendicular to the first direction (+Z).

[0083] Referring to FIG. 4, the substrate (20) may include a redistribution insulating film (21), a bonding pad (25), a first substrate portion (26), and a dummy pad (27). The substrate (20) may include a first region (28a, 28b) in which a plurality of bonding pads (25) are disposed. The substrate (20) may include a second region (29a, 29b) in which a plurality of dummy pads (27) are disposed. The second region (29a, 29b) may surround a portion of the first region (28a, 28b). The second region (29a, 29b) may surround only a portion of the perimeter defining the first region (28a, 28b) and not surround the remaining portion. For example, the perimeter of the first region (28a, 28b) facing the first substrate portion (26) may not be surrounded by the second region (29a, 29b). Dummy pads (27) may not be placed between the perimeter of the first-1 region (28a) facing the first substrate portion (26) and the perimeter of the first-2 region (28b). In the direction in which the first-1 region (28a) and the first-2 region (28b) are spaced apart, dummy pads (27) may not be placed between the first-1 region (28a) and the first-2 region (28b). For example, in the second direction (-X or +X direction), dummy pads (27) may not be placed between the first-1 region (28a) and the first-2 region (28b). A bonding pad (25) may be placed on both sides of the first substrate portion (26) with the first substrate portion (26) in between. The first region (28a, 28b) may include a first-1 region (28a) formed on one side of the first substrate portion (26) and a first-2 region (28b) formed at a position opposite to the first-1 region (28a) with respect to the first substrate portion (26). The second region (29a, 29b) may include a second-1 region (29a) surrounding a part of the first-1 region (28a) and a second-2 region (29b) surrounding a part of the first-2 region (28b).The first dummy pad (27a) may be located inside the second-1 region (29a). The second dummy pad (27b) may be located inside the second-2 region (29b). The first cross-sectional area of ​​the joining pad (25) perpendicular to the first direction (+Z) may be smaller than the second cross-sectional area of ​​the dummy pad (27) perpendicular to the first direction (+Z). The first length (L1) of the dummy pad (27) in the direction away from the first region (28a, 28b) may be smaller than the second length (L2) of the dummy pad (27) in the direction perpendicular to the direction away.

[0084] Referring to FIG. 5, the substrate (30) may include a redistribution insulating film (31), a bonding pad (35), a first substrate portion (36), and a dummy pad (37). The substrate (30) may include a first region (38a, 38b) in which a plurality of bonding pads (35) are disposed. The substrate (30) may include a second region (39a, 39b) in which a plurality of dummy pads (37) are disposed. The second region (39a, 39b) may surround a portion of the first region (38a, 38b). The second region (39a, 39b) may surround only a portion of the perimeter defining the first region (38a, 38b) and not surround the remaining portion. For example, the perimeter of the first region (38a, 38b) facing the first substrate portion (36) may not be surrounded by the second region (39a, 39b). Dummy pads (37) may not be placed between the perimeter of the first-1 region (38a) facing the first substrate portion (36) and the perimeter of the first-2 region (38b). In the direction in which the first-1 region (38a) and the first-2 region (38b) are spaced apart, dummy pads (37) may not be placed between the first-1 region (38a) and the first-2 region (38b). For example, in the second direction (-X or +X direction), dummy pads (37) may not be placed between the first-1 region (38a) and the first-2 region (38b). A bonding pad (35) may be placed on both sides of the first substrate portion (36) with the first substrate portion (36) in between. The first region (38a, 38b) may include a first-1 region (38a) formed on one side of the first substrate portion (36) and a first-2 region (38b) formed at a position opposite to the first-1 region (38a) with respect to the first substrate portion (36). The second region (39a, 39b) may include a second-1 region (39a) surrounding a part of the first-1 region (38a) and a second-2 region (39b) surrounding a part of the first-2 region (38b).The first dummy pad (37a) may be located inside the second-1 region (39a). The second dummy pad (37b) may be located inside the second-2 region (39b). The second region (39a, 39b) may include a corner portion (39c) formed on one side of the first region (38a, 38b). The dummy pad (37) may include a first pad (37a, 37b) placed outside the corner portion (39c) and a second pad (37c) placed inside the corner portion (39c). The first cross-sectional area of ​​the first pad (37a, 37b) perpendicular to the first direction (+Z) may be smaller than the second cross-sectional area of ​​the second pad (37c) perpendicular to the first direction (+Z). The first length (L1) of the second pad (37c) in one direction (e.g., +Y direction) may be greater than the third length (L3) of the first pad (37a, 37b) in the same said one direction (e.g., +Y direction), and the second length (L2) of the second pad (37c) in another direction perpendicular to said one direction (e.g., +X direction) may be greater than the fourth length (L4) of the first pad (37a, 37b) in the same said other direction (e.g., +X direction). Due to the structure of the dummy pad (37) described above, the position and distribution of the underfill (e.g., the underfill (120, 220) of FIG. 1 and FIG. 2) in the corner portion (39c) can be easily controlled.

[0085] Referring to FIG. 6, the substrate (40) may include a redistribution insulating film (41), a bonding pad (45), a first substrate portion (46), and a dummy pad (47). The substrate (40) may include a first region (48a, 48b, 48c, 48d) in which a plurality of bonding pads (45) are disposed. The substrate (40) may include a second region (49a, 49b, 49c, 49d) in which a plurality of dummy pads (47) are disposed. The second region (49a, 49b, 49c, 49d) may surround a portion of the first region (48a, 48b, 48c, 48d). The second region (49a, 49b, 49c, 49d) may surround only a portion of the perimeter defining the first region (48a, 48b, 48c, 48d) and not surround the remaining portion. For example, the perimeter portion of the first region (48a, 48b, 48c, 48d) facing the first substrate portion (46) may not be surrounded by the second region (49a, 49b, 49c, 49d). Dummy pads (47) may not be placed between the first-1 region (48a) and the first-2 region (48b). Dummy pads (47) may not be placed between the first-1 region (48a) and the first-3 region (48c). Dummy pads (47) may not be placed between the first-1 region (48a) and the first-4 region (48d). Dummy pads (47) may not be placed between the first-2 region (48b) and the first-3 region (48c). Dummy pads (47) may not be placed between the first-2 region (48b) and the first-4 region (48d). Dummy pads (47) may not be placed between the first-3 region (48c) and the first-4 region (48d). Bonding pads (45) may be arranged in a cluster on one side of the first substrate portion (36) centered on the first substrate portion (46).A plurality of semiconductor chips (e.g., semiconductor chips (110, 210) of FIG. 1 and FIG. 2) may be arranged so as to correspond to each of the first regions (48a, 48b, 48c, 48d) in which a plurality of bonding pads (45) are arranged in a cluster. The first regions (48a, 48b, 48c, 48d)) may include a first-1 region (48a), a first-2 region (48b), a first-3 region (48c), and a first-4 region (48d) that are spaced apart from each other. The second region (49a, 49b, 49c, 49d) may include a second-1 region (49a) surrounding a part of the first-1 region (48a), a second-2 region (49b) surrounding a part of the first-2 region (48b), a second-3 region (49c) surrounding a part of the first-3 region (48c), and a second-4 region (49d) surrounding a part of the first-4 region (48d). The dummy pad (47) may include a first dummy pad (47a) located inside the second-1 region (49a), a second dummy pad (47b) located inside the second-2 region (49b), a third dummy pad (47c) located inside the second-3 region (49c), and a fourth dummy pad (47d) located inside the second-4 region (49d).

[0087] FIGS. 7 and FIGS. 8 are drawings illustrating a method for manufacturing a semiconductor package (100) described with reference to FIG. 1.

[0088] Referring to FIG. 7, semiconductor chips (110a, 110b) can be placed on a substrate (10). The semiconductor chips (110a, 110b) can be placed on the substrate (10) such that the bonding bump (116) is seated on the bonding pad (15).

[0089] Referring to FIG. 8, an underfill (120) may be filled to surround the bonding pad (15) and the bonding bump (116). The underfill (120) may be cured to surround at least a portion of the plurality of dummy pads (17a, 17b).

[0091] FIGS. 9 to 14 are drawings illustrating a method for manufacturing a semiconductor package (200) described with reference to FIG. 2.

[0092] Referring to FIG. 9, semiconductor chips (210a, 210b) can be placed on the interposer (230). The semiconductor chips (210a, 210b) can be placed on the interposer (230) such that the chip bump (216) is seated on the second interposer pad (237).

[0093] Referring to FIG. 10, a molding film (240) may be formed to surround semiconductor chips (210a, 210b). The molding film (240) may be placed on an interposer (230).

[0094] Referring to FIG. 11, a portion of the molding film (240) can be cut. For example, at least a portion of the molding film (240) can be removed through a chemical mechanical polishing (CMP) process. The surface (240s) of the molding film (240) and the surface (210s) of the semiconductor chip (210a, 210b) can be aligned along one direction.

[0095] Referring to FIG. 12, a portion of the interposer (230) and the molding film (240) may be cut. The structure illustrated in FIG. 11 may be cut for each of the first semiconductor chip (210a) and the second semiconductor chip (210b). After cutting, a first molding film (240a) surrounding the first semiconductor chip (210a) and a first interposer (230a) on which the first semiconductor chip (210a) is placed may be formed. After cutting, a second molding film (240b) surrounding the second semiconductor chip (210b) and a second interposer (230b) on which the second semiconductor chip (210b) is placed may be formed.

[0096] Referring to FIG. 13, an interposer (230) may be placed on a substrate (10). The interposer (230) may be placed on the substrate (10) so that a bonding bump (239) is seated on a bonding pad (15). The interposer (230) may be placed on the substrate (10) so that a dummy bump (2391) is seated on a dummy pad (17a, 17b).

[0097] Referring to FIG. 14, an underfill (220) may be filled to surround the bonding pad (15) and the bonding bump (239). The underfill (220) may be cured to surround at least a portion of the plurality of dummy pads (17a, 17b) and the plurality of dummy bumps (2391).

[0098] Although various embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and it will be obvious to those with average knowledge in the art that various modifications and variations are possible within the scope of the technical concept of the present invention as described in the claims. Furthermore, the above-described embodiments may be implemented by deleting some components, and each embodiment may be implemented in combination with one another. Explanation of the symbols

[0099] 10: Substrate 15: Bonding pad 17: Dummy Pad 100: Semiconductor package 110: Semiconductor chip 116: Joining bump 120: Underfill 200: Semiconductor package 210: Semiconductor chip 220: Underfill 230: Interposer 239: Joint bump 2391: Dummy Bump

Claims

Claim 1 A semiconductor package comprising: a substrate including a bonding pad; a semiconductor chip disposed on the substrate and aligned with the bonding pad in a first direction; and an underfill disposed on the substrate and surrounding the bonding pad, wherein the substrate is disposed spaced apart from the bonding pad in a second direction intersecting the first direction along the surface of the substrate, and a dummy pad dislocated from the semiconductor chip with respect to the first direction and in contact with at least a portion of the underfill. Claim 2 A semiconductor package according to claim 1, wherein each of the bonding pad and the dummy pad protrudes in the first direction from the surface of the substrate and is spaced apart from each other in the second direction. Claim 3 A semiconductor package according to claim 1, wherein the bonding pad comprises a plurality of bonding pads spaced apart from each other, and the dummy pad comprises a plurality of dummy pads spaced apart from each other, and the substrate comprises a first region in which the plurality of bonding pads are disposed; and a second region in which the plurality of dummy pads are disposed and which surrounds at least a portion of the first region. Claim 4 A semiconductor package according to claim 3, wherein the second region includes a corner portion formed on one side of the first region, and the plurality of dummy pads include: a first pad located outside the corner portion and having a first cross-sectional area perpendicular to the first direction; and a second pad located inside the corner portion and having a second cross-sectional area larger than the first cross-sectional area. Claim 5 A semiconductor package according to claim 1, wherein the first cross-sectional area of ​​the dummy pad perpendicular to the first direction is larger than the second cross-sectional area of ​​the junction pad. Claim 6 In claim 1, the semiconductor chip comprises a first semiconductor chip; and a second semiconductor chip spaced apart from the first semiconductor chip in a second direction intersecting the first direction, and the substrate comprises a first substrate portion corresponding to the space between the first semiconductor chip and the second semiconductor chip spaced apart from each other, and the dummy pad is a semiconductor package disposed on the outside of the semiconductor chip with respect to the first substrate portion in the second direction. Claim 7 In claim 1, the semiconductor chip comprises a junction bump that is in contact with the junction pad and surrounded by the underfill, and the dummy pad is positioned offset from the junction bump with respect to the first direction, in a semiconductor package. Claim 8 A semiconductor package according to claim 1, further comprising an interposer disposed between the substrate and the semiconductor chip and including a bonding bump in contact with the bonding pad and a dummy bump in contact with the dummy pad and positioned offset from the semiconductor chip in the first direction. Claim 9 A semiconductor package comprising: a substrate including a bonding pad; a bonding bump disposed on the substrate and in contact with the bonding pad; and an underfill disposed on the substrate and surrounding the bonding pad and the bonding bump, wherein the substrate includes a dummy pad spaced apart from the bonding pad along the surface of the substrate and in contact with at least a portion of the underfill. Claim 10 A semiconductor package comprising: a substrate including a junction pad; a semiconductor chip spaced apart from the substrate in a first direction; an interposer disposed between the substrate and the semiconductor chip and including a junction bump in contact with the junction pad; and an underfill surrounding the junction pad and the junction bump, wherein the substrate includes a dummy pad spaced apart from the junction pad along the surface of the substrate and in contact with at least a portion of the underfill, and the interposer includes a dummy bump in contact with the dummy pad.

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