Vertical chip stacking package and manufacturing method thereof
Patent Information
- Application Number
- KR1020250015369
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-06
- Publication Date
- 2026-08-14
Smart Images
Figure PAT00001_ABST
Abstract
Description
Technology Field
[0001] The present disclosure relates to a vertical chip stacking package and a method for manufacturing the same. Background Technology
[0002] In response to demands for high speed, integration, and miniaturization, semiconductor chips are evolving into structures that place multiple pins on small chips. System-in-package (SIP) technology refers to a package structure in which multiple semiconductor chips are placed within a single package. In semiconductor packages, signal transmission performance can generally degrade if the signal path is long. Furthermore, the complexity of the manufacturing process for signal transmission paths tends to increase due to the miniaturization of electrode patterns. This increased complexity in the manufacturing process of placing multiple semiconductor chips within a SIP is becoming a stumbling block to commercialization. Prior art literature
[0003] (Patent Document 0001) KR 10-2007-0105553 A The problem to be solved
[0004] According to one aspect of the present disclosure, a first semiconductor chip is arranged face down and a second semiconductor chip is arranged face up to vertically stack semiconductor chips, thereby providing a vertical chip stacking package and a method for manufacturing the same.
[0005] According to one aspect of the present disclosure, a vertical chip stacking package comprising a metal layer capable of shielding each of a plurality of semiconductor chips, dissipating heat from the semiconductor chips, and providing a ground, and a method for manufacturing the same are provided. means of solving the problem
[0006] According to one aspect of the present disclosure, a vertical chip stacking package comprises: a core having a receiving portion formed penetrating from an upper surface to a lower surface; a first semiconductor chip located within the receiving portion such that an active surface faces the lower surface of the core; a first conductive layer formed across the lower surface of the core and an inactive surface of the first semiconductor chip; a charging layer charged on the first conductive layer within the receiving portion; a second conductive layer formed across the charging layer and the upper surface of the core; a fixed layer formed on the second conductive layer within the receiving portion; a second semiconductor chip located on the fixed layer within the receiving portion such that an active surface faces the upper surface of the core; a first redistribution layer formed below the first conductive layer and having a plurality of electrode patterns connected to the first semiconductor chip or the first conductive layer to transmit an electrical signal; a second redistribution layer formed on the second conductive layer and having a plurality of electrode patterns connected to the second semiconductor chip or the second conductive layer to transmit an electrical signal; and a structure formed penetrating the core to transmit an electrical signal between the first redistribution layer and the second redistribution layer. It may include core-penetrating vias.
[0007] According to one embodiment, the core may include a substrate on which the second conductive layer is formed on an upper surface, and an adhesive layer connected to the lower surface of the substrate and bonded to the first conductive layer.
[0008] According to one embodiment, the first conductive layer and the second conductive layer may include an open portion with a portion removed so as to be spaced apart from the core through-via.
[0009] According to one embodiment, the first semiconductor chip and the second semiconductor chip can be connected to transmit and receive electrical signals through the first redistribution layer, the core through-via, and the second redistribution layer.
[0010] According to one embodiment, the first redistribution layer may include a heat dissipation electrode connected to the first conductive layer to discharge heat generated by the first semiconductor chip to the outside.
[0011] According to one embodiment, the second redistribution layer may include a heat dissipation electrode connected to the second conductive layer to discharge heat generated by the second semiconductor chip to the outside.
[0012] According to one embodiment, the first redistribution layer may include a ground electrode connected to the first conductive layer and connected to an external electrical ground.
[0013] According to one embodiment, the second redistribution layer may include a ground electrode connected to the second conductive layer and connected to an external electrical ground.
[0014] According to one embodiment, the first conductive layer can provide shielding that blocks electromagnetic waves by covering the lower surface and side of the first semiconductor chip.
[0015] According to one embodiment, the second conductive layer can provide shielding that blocks electromagnetic waves by surrounding the lower surface and side of the second semiconductor chip so as to be spaced apart from it.
[0016] According to one embodiment, the filling layer is formed of a material having higher thermal conductivity than the core and can transfer heat between the first conductive layer and the second conductive layer.
[0017] According to one embodiment, the charging layer is formed of a material having electrical conductivity and can electrically connect the first conductive layer and the second conductive layer.
[0018] According to one aspect of the present disclosure, a method for manufacturing a vertical chip stacking package may include the steps of: placing a first semiconductor chip on a carrier substrate such that an active surface faces the carrier substrate; forming a first conductive layer covering the carrier substrate and the first semiconductor chip; coupling a core on the first conductive layer so that a receiving portion accommodates the first semiconductor chip inside; forming a filling layer to cover the first conductive layer inside the receiving portion; forming a second conductive layer to cover the filling layer, the inner surface of the receiving portion, and the upper surface of the core; forming a fixing layer on the second conductive layer inside the receiving portion; placing a second semiconductor chip on the fixing layer such that an active surface faces the upper surface of the core; and forming one or more core-through-vias penetrating the upper and lower surfaces of the core and a redistribution layer on the upper and lower surfaces of the core, respectively.
[0019] According to one embodiment, a method for manufacturing a vertical chip stacking package may further include, before the step of bonding the core, the step of bonding an adhesive layer to the lower surface of a substrate to form the core, and the step of forming a receiving portion that penetrates both the substrate and the adhesive layer of the core.
[0020] According to one embodiment, the step of forming the core-through-via and the redistribution layer comprises: removing the carrier substrate; removing a portion of the first conductive layer and the second conductive layer corresponding to the portion where the core-through-via is to be formed to form an open portion; forming a first base insulating layer covering the first conductive layer and the first semiconductor chip and a second base insulating layer covering the second conductive layer and the second semiconductor chip; forming one or more first via holes penetrating the first base insulating layer, the core, and the second base insulating layer at the location where the core-through-via is to be formed; removing a portion of the first base insulating layer to form a plurality of second via holes exposing a portion of the first conductive layer or a pad of the first semiconductor chip; removing a portion of the second base insulating layer to form a plurality of second via holes exposing a portion of the second conductive layer or a pad of the second semiconductor chip; filling the first via hole with an electrically conductive material and filling the second via hole with an electrically conductive material; and the one or more core-through-vias and the plurality of conductive It may include the step of forming a plurality of electrode patterns connecting some of the vias.
[0021] According to one embodiment, the step of forming the electrode pattern may form one or more of a heat dissipation electrode connected to the first conductive layer to discharge heat generated by the first semiconductor chip to the outside, or a heat dissipation electrode connected to the second conductive layer to discharge heat generated by the second semiconductor chip to the outside.
[0022] According to one embodiment, the step of forming the electrode pattern may form one or more of a ground electrode connected to the first conductive layer and connected to an external electrical ground, or a ground electrode connected to the second conductive layer and connected to an external electrical ground.
[0023] The features and advantages of the present disclosure will become more apparent from the following detailed description based on the accompanying drawings.
[0024] Prior to this, terms and words used in this specification and claims should not be interpreted in their ordinary and dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor can appropriately define the concept of the terms to best describe his invention. Effects of the invention
[0025] According to one embodiment of the present disclosure, the size of the semiconductor package can be reduced.
[0026] According to one embodiment of the present disclosure, the manufacturing convenience of a semiconductor package can be high and the efficiency of the manufacturing process can be increased.
[0027] According to one embodiment of the present disclosure, the signal transmission path can be shortened. Brief explanation of the drawing
[0028] FIG. 1 is a drawing showing a vertical chip stacking package according to one embodiment. FIG. 2 is a flowchart showing each step of a method for manufacturing a vertical chip stacked package according to one embodiment. FIG. 3 is a drawing showing a state in which a first conductive layer is formed to cover a first semiconductor chip disposed on a carrier substrate according to one embodiment. FIG. 4 is a diagram illustrating the step of bonding a core on a first conductive layer according to one embodiment. FIG. 5 is a drawing showing the state in which a charging layer and a second conductive layer are formed according to one embodiment. FIG. 6 is a diagram showing the state in which a second semiconductor chip is arranged according to one embodiment. FIG. 7 is a flowchart showing each detailed step of forming a core-through-via and a redistribution layer according to one embodiment. FIG. 8 is a drawing showing a state in which a carrier substrate according to one embodiment is removed and an open portion is formed in the first conductive layer and the second conductive layer. FIG. 9 is a drawing showing a state in which an insulating layer is formed and a via hole is formed to form a via according to one embodiment. FIG. 10 is a drawing showing the state in which a core-through-via and a redistribution layer are formed according to one embodiment. Specific details for implementing the invention
[0029] Hereinafter, the present disclosure will be described in detail (with reference to the attached drawings). However, this is merely illustrative and the present disclosure is not limited to the specific embodiments described illustratively.
[0030] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the attached drawings.
[0031] FIG. 1 is a drawing showing a vertical chip stacking package (1) according to one embodiment.
[0032] A vertical chip stacking package (1) according to one embodiment comprises a core (10) having a receiving portion (13) formed that penetrates from the upper surface to the lower surface, a first semiconductor chip (21) located within the receiving portion (13) such that its active surface faces the lower surface of the core (10), a first conductive layer (31) formed across the lower surface of the core (10) and the inactive surface of the first semiconductor chip (21), a charging layer (40) charged on the first conductive layer (31) within the receiving portion (13), a second conductive layer (32) formed across the charging layer (40) and the upper surface of the core (10), a fixed layer (50) formed on the second conductive layer (32) within the receiving portion (13), a second semiconductor chip (22) located on the fixed layer (50) within the receiving portion (13) such that its active surface faces the upper surface of the core (10), and a plurality of components formed under the first conductive layer (31) and connected to the first semiconductor chip (21) or the first conductive layer (31) to transmit an electrical signal. It may include a first redistribution layer (71) having an electrode pattern (92), a second redistribution layer (72) having a plurality of electrode patterns (92) formed on a second conductive layer (32) and connected to a second semiconductor chip (22) or the second conductive layer (32) to transmit an electrical signal, and a core-through-via (60) formed through the core (10) to transmit an electrical signal between the first redistribution layer (71) and the second redistribution layer (72).
[0033] The core (10) may have an upper surface (10a) and a lower surface (10b) opposite to the upper surface (10a). The core (10) may have a receiving portion (13) formed inside for receiving a semiconductor chip. The receiving portion (13) may be a hole penetrating from the upper surface (10a) to the lower surface (10b) of the core (10). The shape and size of the receiving portion (13) may be determined according to the shape and size of the semiconductor chip. The height of the receiving portion (13) is equal to the height from the upper surface (10a) to the lower surface (10b) of the core (10). The height from the upper surface (10a) to the lower surface (10b) of the core (10) can be determined by considering the height obtained by adding the thickness of the first semiconductor chip (21), the thickness of the first conductive layer (31), the thickness of the charging layer (40), the thickness of the second conductive layer (32), the thickness of the fixed layer (50), the thickness of the second conductive layer (32), and the thickness of the second semiconductor chip (22). The receiving portion (13) can accommodate the first semiconductor chip (21), the second semiconductor chip (22), a part of the first conductive layer (31), a part of the second conductive layer (32), the charging layer (40), and the fixed layer (50). The receiving portion (13) can accommodate not only semiconductor chips but also passive components such as inductors, capacitors, and resistors.
[0034] The core (10) may include a substrate (11) having a second conductive layer (32) formed on its upper surface, and an adhesive layer (12) connected to the lower surface of the substrate (11) and bonded to the first conductive layer (31). The core (10) may include the substrate (11) and the adhesive layer (12) bonded to the substrate (11). The substrate (11) may have an upper surface (11a) and a lower surface (11b). The substrate (11) may be formed of silicon, ceramic, polymer, glass, PCB, etc. The substrate (11) may perform a heat dissipation function using a material with high thermal conductivity. The substrate (11) may maintain the rigidity of the vertical chip stacking package (1) using a material with high strength. The adhesive layer (12) may be connected to the lower surface (11b) of the substrate (11). The adhesive layer (12) may connect the first conductive layer (31) and the substrate (11). The lower surface (12b) of the adhesive layer (12) may be adhered to the first conductive layer (31), and the upper surface (12a) of the adhesive layer (12) may be adhered to the lower surface (11b) of the substrate (11). The adhesive layer (12) may be formed from an adhesive film, a liquid adhesive, or various other materials.
[0035] A semiconductor chip may be located inside a receiving portion (13) of a core (10). The receiving portion (13) may accommodate a plurality of semiconductor chips. The semiconductor chips may include communication semiconductor chips, power semiconductor chips, and chips for various other purposes. The semiconductor chips may include a first semiconductor chip (21) and a second semiconductor chip (22). The first semiconductor chip (21) and the second semiconductor chip (22) may be stacked vertically. Alternatively, the first semiconductor chip (21) and the second semiconductor chip (22) may be stacked vertically. The first semiconductor chip (21) may be accommodated in the receiving portion (13) in a face-down position such that the active surface (21a) faces the lower surface (10b) of the core (10). Face-down is a position in which the active surface (upper surface) of the semiconductor chip faces downward and the inactive surface (lower surface) of the semiconductor chip faces upward. The second semiconductor chip (22) can be received in the receiving portion (13) in a face-up position such that the active surface (22a) faces the upper surface (10a) of the core (10). Face-up is a position in which the active surface (upper surface) of the semiconductor chip faces upward and the inactive surface (lower surface) of the semiconductor chip faces downward. The active surface refers to the surface where the electrode pads (21p, 22p) of the semiconductor chip are formed. Since the first semiconductor chip (21) and the second semiconductor chip (22) are stacked vertically within the receiving portion (13), the area of the package can be minimized, and the electrical signal transmission path between the first semiconductor chip (21) and the second semiconductor chip (22) can be designed to be short. If the electrical signal transmission path is short, the signal characteristics of the package can be improved.
[0036] The first conductive layer (31) can cover the lower surface (10b) of the core (10) and the inactive surface (lower surface (21b)) of the first semiconductor chip (21). The first conductive layer (31) can also cover the side surface (21c) of the first semiconductor chip (21). The first conductive layer (31) is formed on the lower surface (10b) of the core (10) and can be continuously formed on the side surface (21c) and the lower surface (21b) of the first semiconductor chip (21). The first conductive layer (31) can be formed as a thin layer. The first conductive layer (31) can be formed from a material having electrical conductivity. For example, the first conductive layer (31) can be formed from a metal such as copper (Cu) or aluminum (Al), an alloy having electrical conductivity, a carbon-based material such as graphene, etc. The first conductive layer (31) has electrical conductivity and can be connected to the ground of an external circuit to provide an electrical ground to the vertical chip stacking package (1). The first conductive layer (31) can cover the bottom surface (21b) and side surface (21c) of the first semiconductor chip (21) to provide shielding that blocks electromagnetic waves. The first conductive layer (31) can be formed of a material with a higher thermal conductivity than the core (10). Heat generated from the first semiconductor chip (21) is transferred to the first conductive layer (31) and can be discharged to the outside through a heat dissipation electrode (93) connected to the first conductive layer (31).
[0037] A charging layer (40) may be formed on the first conductive layer (31) inside the receiving portion (13). The charging layer (40) is a layer that forms the necessary gap for stacking the second semiconductor chip (22) on the first semiconductor chip (21). The charging layer (40) may serve as a base for forming the second conductive layer (32) inside the receiving portion (13). The charging layer (40) may fill the space between the first conductive layer (31) and the inner surface (13a) of the receiving portion (13). The upper surface (40a) of the charging layer (40) may be formed flat. The charging layer (40) may be formed of a non-electrically conductive material. If the charging layer (40) is not electrically conductive, the first conductive layer (31) and the second conductive layer (32) may be electrically isolated.
[0038] The charging layer (40) is formed of an electrically conductive material and can electrically connect the first conductive layer (31) and the second conductive layer (32). The charging layer (40) can be formed of an electrically conductive material. If the charging layer (40) is electrically conductive, the first conductive layer (31) and the second conductive layer (32) can have the same potential and can perform a shielding function between the first semiconductor chip (21) and the second semiconductor chip (22).
[0039] The charging layer (40) is formed of a material with higher thermal conductivity than the core (10) and can transfer heat between the first conductive layer (31) and the second conductive layer (32). The charging layer (40) can be formed of a material with higher thermal conductivity than the core (10). When the charging layer (40) is formed of a material with higher thermal conductivity, heat generated from the first semiconductor chip (21) or the second semiconductor chip (22) can be transferred to the second conductive layer (32) or the first conductive layer (31). For example, heat generated from the first semiconductor chip (21) can be transferred to the second conductive layer (32) through the first conductive layer (31) and the charging layer (40), and can be discharged to the outside through a heat dissipation electrode (93) connected to the second conductive layer (32). Conversely, heat generated in the second semiconductor chip (22) can be transferred to the first conductive layer (31) through the second conductive layer (32) and the charging layer (40), and can be discharged to the outside through the heat dissipation electrode (93) connected to the first conductive layer (31). Thus, the heat dissipation performance of the vertical chip stacking package (1) can be improved.
[0040] The second conductive layer (32) can cover the upper surface (40a) of the charging layer (40), the inner surface (13a) of the receiving portion (13), and the upper surface (10a) of the core (10). The second conductive layer (32) can be in direct contact with the lower surface (22b) of the second semiconductor chip (22) or connected through a fixing layer (50). The second conductive layer (32) can be formed as a thin layer. The second conductive layer (32) can be formed from a material having electrical conductivity. For example, the second conductive layer (32) can be formed from a metal such as copper (Cu) or aluminum (Al), an alloy having electrical conductivity, a carbon-based material such as graphene, etc. The second conductive layer (32) has electrical conductivity and can be connected to the ground of an external circuit to provide an electrical ground to the vertical chip stacking package (1). The second conductive layer (32) has electrical conductivity and forms a concave space where the second semiconductor chip (22) can be seated, thereby providing shielding that blocks electromagnetic waves to the second semiconductor chip (22). The second conductive layer (32) may be formed of a material with a higher thermal conductivity than the core (10). Heat generated from the second semiconductor chip (22) is transferred to the second conductive layer (32) and can be discharged to the outside through a heat dissipation electrode (93) connected to the second conductive layer (32).
[0041] A fixing layer (50) can be formed on the second conductive layer (32) to fix the lower surface (22b) of the second semiconductor chip (22). The fixing layer (50) may include an adhesive film, an adhesive, etc. The fixing layer (50) may be formed on a part of the second conductive layer (32) formed inside the receiving portion (13). That is, the fixing layer (50) may be formed on the bottom portion (32c) of the second conductive layer (32) which is formed concavely to accommodate the second semiconductor chip (22). The fixing layer (50) may be formed from a material having electrical conductivity or a material having a higher thermal conductivity than the core (10). A fixing layer (50) formed from a material having electrical conductivity may provide a shielding function that blocks electromagnetic waves to the second semiconductor chip (22). A fixing layer (50) formed from a material having high thermal conductivity may effectively transfer heat generated from the second semiconductor chip (22) to the second conductive layer (32).
[0042] The second semiconductor chip (22) may be positioned such that its lower surface (22b) is connected to the fixed layer (50) and its upper surface (22a, active surface) faces the upper surface (10a) of the core (10). The upper surface (22a) of the second semiconductor chip (22) may be positioned in alignment with the second conductive layer (32). The side surface (22c) of the second semiconductor chip (22) may be spaced apart from the second conductive layer (32). However, to improve the heat dissipation performance of the second semiconductor chip (22), the gap between the second conductive layer (32) and the second semiconductor chip (22) may be minimized. The second conductive layer (32) may provide shielding that blocks electromagnetic waves by surrounding the lower surface (22b) and side surface (22c) of the second semiconductor chip (22) so as to be spaced apart. Since the second semiconductor chip (22) is located in a space where the second conductive layer (32) is formed concavely into the receiving portion (13), the lower surface (22b) and side surface (22c) of the second semiconductor chip (22) can be covered by the second conductive layer (32).
[0043] The first redistribution layer (71) may be formed on the lower surface (10b) of the core (10). The first redistribution layer (71) may be formed below the active surface (21a) of the first semiconductor chip (21) and the first conductive layer (31). The second redistribution layer (72) may be formed on the upper surface (10a) of the core (10). The second redistribution layer (72) may be formed on the active surface (22a) of the second semiconductor chip (22) and the second conductive layer (32). The first redistribution layer (71) and the second redistribution layer (72) may include one or more insulating layers, conductive vias (91) penetrating the insulating layers, and a plurality of electrode patterns (92). The insulating layer may include a first insulating layer (81) covering a first semiconductor chip (21) and a first conductive layer (31), and a second insulating layer (82) covering a second semiconductor chip (22) and a second conductive layer (32) and filling the space between the second semiconductor chip (22) and the receiving portion (13). A conductive via (91) may be formed by penetrating the insulating layer. A conductive via (91) formed in the first insulating layer (81) may connect the first semiconductor chip (21) and the electrode pattern (92), or the first conductive layer (31) and the electrode pattern (92). A conductive via (91) formed in the second insulating layer (82) may connect the second semiconductor chip (22) and the electrode pattern (92), or the second conductive layer (32) and the electrode pattern (92).
[0044] The first redistribution layer (71) and the second redistribution layer (72) can both be referred to as redistribution layers. The redistribution layer may include a plurality of layers in which an insulating layer (81, 82), a conductive via (91), and an electrode pattern (92) are formed. The redistribution layer may have a structure in which an electrode pad is formed in the upper layer and can be connected to the outside by being connected to the electrode pattern (92) of the lower layer, and the lower layer performs an electrical connection.
[0045] A plurality of conductive vias (91) and a plurality of electrode patterns (92) are partially connected to each other to form a path for providing power to a semiconductor chip, a path for transmitting and receiving electrical signals (data, etc.) to a semiconductor chip, a path for discharging heat, a path for transmitting an electrical ground, etc.
[0046] The electrode patterns (92) exposed on the outside of the redistribution layer can be used as electrode pads for connecting to an external circuit. The electrode patterns (92) used as electrode pads can be formed thickly.
[0047] The first redistribution layer (71) may include a heat dissipation electrode (93) connected to the first conductive layer (31) to discharge heat generated by the first semiconductor chip (21) to the outside. The second redistribution layer (72) may include a heat dissipation electrode (93) connected to the second conductive layer (32) to discharge heat generated by the second semiconductor chip (22) to the outside.
[0048] The heat dissipation electrode (93) is one of a plurality of electrode patterns (92). The heat dissipation electrode (93) may be formed in the first redistribution layer (71), formed in the second redistribution layer (72), or formed in both the first redistribution layer (71) and the second redistribution layer (72). The heat dissipation electrode (93) may be connected to the first conductive layer (31) or the second conductive layer (32) through a conductive via (91). The area of the conductive via (91) connecting the heat dissipation electrode (93) and the conductive layer may be larger than the area of the conductive via (91) for transmitting an electrical signal. Alternatively, the heat dissipation electrode (93) may be connected to the first conductive layer (31) or the second conductive layer (32) through a plurality of conductive vias (91). The heat dissipation electrode (93) can dissipate heat from the first conductive layer (31) through an external circuit connected to the first redistribution layer (71). The heat dissipation electrode (93) can dissipate heat from the second conductive layer (32) through an external circuit connected to the second redistribution layer (72).
[0049] The first redistribution layer (71) may include a ground electrode (94) connected to the first conductive layer (31) and connected to an external electrical ground. The second redistribution layer (72) may include a ground electrode (94) connected to the second conductive layer (32) and connected to an external electrical ground.
[0050] The ground electrode (94) is one of a plurality of electrode patterns (92). The ground electrode (94) may be formed in the first redistribution layer (71), in the second redistribution layer (72), or in both the first redistribution layer (71) and the second redistribution layer (72). The ground electrode (94) may be connected to the first conductive layer (31) or the second conductive layer (32) through a conductive via (91). A plurality of ground electrodes (94) may be formed in the first redistribution layer (71) or the second redistribution layer (72). The ground electrode (94) of the first redistribution layer (71) may be connected to the ground of an external circuit connected to the first redistribution layer (71). The ground electrode (94) of the second redistribution layer (72) may be connected to the ground of an external circuit connected to the second redistribution layer (72). The ground electrode (94) can be connected to an external circuit to receive a ground potential and can provide a ground potential to another external circuit. Since the first conductive layer (31) or the second conductive layer (32) has a ground potential through the ground electrode (94), the first conductive layer (31) or the second conductive layer (32) can be used as a ground in the vertical chip stacking package (1).
[0051] The core through-via (60) can connect the first redistribution layer (71) and the second redistribution layer (72) by penetrating the upper and lower surfaces of the core (10). The core through-via (60) can be formed by filling an electrically conductive material within a first via hole (60h) that penetrates the first insulating layer (81), the core (10), and the second insulating layer (82). The core through-via (60) can connect the electrode pattern (92) of the first redistribution layer (71) and the electrode pattern (92) of the second redistribution layer (72).
[0052] The first semiconductor chip (21) and the second semiconductor chip (22) can be connected to transmit and receive electrical signals through the first redistribution layer (71), the core through-via (60), and the second redistribution layer (72). Since the core through-via (60) provides an electrical signal transmission path that penetrates the core (10), the path through which the first semiconductor chip (21) and the second semiconductor chip (22) transmit electrical signals can be minimized. The core through-via (60) can provide the shortest path for transmitting electrical signals between an external circuit connected to the first redistribution layer (71) and an external circuit connected to the second redistribution layer (72).
[0053] The first conductive layer (31) and the second conductive layer (32) may include an open portion (33) with a portion removed to be spaced apart from the core through-via (60). Since the first conductive layer (31) covers the lower surface of the core (10), an open portion (33) may be formed in the first conductive layer (31) so that the core through-via (60) and the first conductive layer (31) do not come into contact. Since the second conductive layer (32) covers the upper surface (10a) of the core (10), an open portion (33) may be formed in the second conductive layer (32) so that the core through-via (60) and the second conductive layer (32) do not come into contact. The open portion (33) formed in the first conductive layer (31) may expose the upper surface (10a) of the core (10). The open portion (33) formed in the second conductive layer (32) may expose the lower surface (10b, lower surface (12b)) of the core (10) and the adhesive layer (12). The open portion (33) formed in the first conductive layer (31) may be a space formed by removing a portion of the first conductive layer (31) surrounding the portion where the core-penetrating via (60) is formed. The open portion (33) formed in the second conductive layer (32) may be a space formed by removing a portion of the second conductive layer (32) surrounding the portion where the core-penetrating via (60) is formed. The open portion (33) may be formed in a circular shape. The center of the open portion (33) and the center of the first via hole (60h) may coincide. The open portion (33) may be formed in a number corresponding to the number of core-penetrating vias (60).
[0054] FIG. 2 is a flowchart showing each step of a method for manufacturing a vertical chip stacking package (1) according to one embodiment.
[0055] A method for manufacturing a vertical chip stacking package (1) comprises the steps of: placing a first semiconductor chip (21) on a carrier substrate (100) such that the active surface (21a) faces the carrier substrate (100) (S11); forming a first conductive layer (31) that covers the carrier substrate (100) and the first semiconductor chip (21) (S12); coupling a core (10) on the first conductive layer (31) so that the receiving portion (13) accommodates the first semiconductor chip (21) inside (S13); forming a filling layer (40) that covers the first conductive layer (31) inside the receiving portion (13) (S14); forming a second conductive layer (32) that covers the filling layer (40), the inner surface (13a) of the receiving portion (13), and the upper surface (10a) of the core (10) (S15); and forming a fixing layer (50) on the second conductive layer (32) inside the receiving portion (13). The method may include a step (S16), a step (S17) of placing a second semiconductor chip (22) on a fixed layer (50) such that the active surface (22a) faces the upper surface of the core (10), and a step (S18) of forming one or more core-through-vias (60) penetrating the upper surface (10a) and lower surface (10b) of the core (10) and a redistribution layer on the upper surface (10a) and lower surface (10b) of the core (10), respectively.
[0056] FIG. 3 is a drawing showing a state in which a first conductive layer (31) is formed to cover a first semiconductor chip (21) disposed on a carrier substrate (100) according to one embodiment. Refer to FIG. 2 together.
[0057] The step (S11) of placing the first semiconductor chip (21) is to place the first semiconductor chip (21) on a carrier substrate (100) such that the active surface (21a) faces the carrier substrate (100). The carrier substrate (100) may be a carrier tape or other configuration. The carrier substrate (100) may support the first semiconductor chip (21) by contacting the active surface (21a) of the first semiconductor chip (21).
[0058] The step (S12) of forming the first conductive layer (31) is to form the first conductive layer (31) to cover the carrier substrate (100) and the first semiconductor chip (21). The first conductive layer (31) can be formed using sputtering, electroplating, electroless plating, or other methods. The first conductive layer (31) can be formed in the form of a thin layer overall. When the first conductive layer (31) is formed, as shown in FIG. 3, the first conductive layer (31) can be formed to cover the carrier substrate (100) and the first semiconductor chip (21) overall while the first semiconductor chip (21) is positioned face down on the carrier substrate (100). The first conductive layer (31) can be formed on the lower surface (21b) and the side surface (21c) of the carrier substrate (100) and the first semiconductor chip (21).
[0059] FIG. 4 is a drawing illustrating the step of bonding a core (10) on a first conductive layer (31) according to one embodiment. Refer to FIG. 2 together.
[0060] The step (S13) of combining the core (10) involves combining the core (10), in which the receiving portion (13) is formed, onto the first conductive layer (31). When the core (10), in which the receiving portion (13) is formed, is combined onto the first conductive layer (31), the first semiconductor chip (21) and a portion of the first conductive layer (31) can be accommodated within the receiving portion (13). The size of the receiving portion (13) may be slightly larger than the first conductive layer (31) covering the first semiconductor chip (21). Therefore, a space may exist between the inner surface (13a) of the receiving portion (13) and the first conductive layer (31). This space may be filled by a charging layer (40).
[0061] In order to combine the first conductive layer (31) and the core (10) with each other while the first conductive layer (31) is already formed, the core (10) may include an adhesive layer (12). The adhesive layer (12) can fix the first conductive layer (31) and the substrate (11). The manufacturing method of the vertical chip stacking package (1) is not to form the first conductive layer (31) on the core (10), but to fix the already formed first conductive layer (31) to the core (10) using the adhesive layer (12). Because this manufacturing sequence is performed, vertical stacking is possible in the order of the first semiconductor chip, the first conductive layer (31), the filling layer (40), the second conductive layer (32), the fixing layer (50), and the second semiconductor chip (22) within the receiving portion (13) of the core (10).
[0062] A method for manufacturing a vertical chip stacking package (1) may further include, prior to the step (S13) of combining the core (10), a step (S21) of forming the core (10) by combining an adhesive layer (12) on the lower surface (11b) of a substrate (11), and a step (S22) of forming a receiving portion (13) that penetrates both the substrate (11) and the adhesive layer (12) of the core (10).
[0063] The step (S21) of forming the core (10) is to bond an adhesive layer (12) to the lower surface (11b) of the substrate (11). The adhesive layer (12) may be formed from an adhesive sheet or an adhesive liquid, and the core (10) may be formed by forming the adhesive layer (12) on the lower surface (11b) of the substrate (11).
[0064] The step (S22) of forming the receiving portion (13) is to form a hole that penetrates the substrate (11) and the core (10) entirely. The receiving portion (13) may be formed to penetrate the upper surface (10a) and the lower surface (10b) of the core (10). The receiving portion (13) may be formed by removing a portion of the core (10) using ion milling, UV laser, excimer laser, wet etching, or various other methods. Alternatively, the receiving portion (13) may be formed on the substrate (11) first, and then an adhesive layer (12) may be formed on the lower surface of the substrate (11). In this case, a hole corresponding to the receiving portion (13) must already be formed in the adhesive layer (12). Alternatively, if the adhesive layer (12) is formed using an adhesive liquid, the adhesive layer (12) may be formed by applying the adhesive liquid to the lower surface of the substrate (11) on which the receiving portion (13) is formed.
[0065] FIG. 5 is a drawing showing the state in which a charging layer (40) and a second conductive layer (32) are formed according to one embodiment. Refer to FIG. 2 together.
[0066] The step (S14) of forming the charging layer (40) is to form a charging layer (40) that covers the first conductive layer (31) inside the receiving portion (13). The charging layer (40) may be formed to completely cover the first conductive layer (31) located inside the receiving portion (13). The lower part of the charging layer (40) is filled between the first conductive layer (31) and the receiving portion (13), and the upper surface of the charging layer (40) may be formed flat. The charging layer (40) may be filled with an electrically conductive material or a non-electrically conductive material. The upper thickness of the charging layer (40) may be formed thinly to minimize the overall height of the vertical chip stacking package (1).
[0067] The step (S15) of forming the second conductive layer (32) is to form a second conductive layer (32) that covers the inner surface (13a) of the filling layer (40) and the receiving portion (13) and the upper surface (10a) of the core (10). The second conductive layer (32) can be formed by sputtering, electroplating, electroless plating, or various other methods similar to the first conductive layer (31). The second conductive layer (32) can be formed as a continuous layer with a portion (32a) formed on the upper surface (10a) of the core (10), a portion (32b) formed on the inner surface (13a) of the receiving portion (13), and a portion (32c) formed on the upper surface (40a) of the filling portion. The second conductive layer (32) is formed concavely into the receiving portion (13), and the second semiconductor chip (22) can be placed in the portion (32c) formed on the upper surface (40) of the charging portion, which is the concave portion.
[0068] FIG. 6 is a drawing showing the state in which a second semiconductor chip (22) is arranged according to one embodiment. Refer to FIG. 2 together.
[0069] The step (S16) of forming the fixed layer (50) is to form the fixed layer (50) on the second conductive layer (32) inside the receiving portion (13). The fixed layer (50) is configured to fix the second semiconductor chip (22) to the second conductive layer (32). The fixed layer (50) may be formed of a material having a higher thermal conductivity than the core (10) or the insulating layer. The fixed layer (50) may be formed in the portion of the second conductive layer (32) that is concavely formed into the receiving portion (13).
[0070] The step of placing the second semiconductor chip (22) involves placing the second semiconductor chip (22) on the fixed layer (50) in a face-up position with the active surface (22a) facing upward. The second semiconductor chip (22) can be combined with the fixed layer (50) so that the lower surface (22b) of the second semiconductor chip (22) contacts the fixed layer (50). Since the size of the receiving portion (13) is larger than that of the second semiconductor chip (22) and the second conductive layer (32) is formed along the inner surface of the receiving portion (13), a space may exist between the side surface (22c) of the second semiconductor chip (22) and the second conductive layer (32). This space may be filled by the second insulating layer (82).
[0071] Refer again to FIG. 2. After placing the second semiconductor chip (22), the step (S18) of forming the core through-via (60) and the redistribution layer can be performed. The step (S18) of forming the core through-via (60) and the redistribution layer involves forming the core through-via (60) that penetrates the core (10), and forming the first redistribution layer (71) and the second redistribution layer (72) on the lower and upper surfaces of the core (10).
[0072] FIG. 7 is a flowchart showing each detailed step of the step (S18) of forming a core through-via (60) and a redistribution layer according to one embodiment.
[0073] The step (S18) of forming a core-through-via (60) and a redistribution layer comprises: a step (S31) of removing a carrier substrate (100); a step (S32) of removing a portion of a first conductive layer (31) and a second conductive layer (32) corresponding to the portion where the core-through-via (60) is to be formed to form an open portion (33); a step (S33) of forming a first insulating layer (81) covering the first conductive layer (31) and the first semiconductor chip (21) and a second insulating layer (82) covering the second conductive layer (32) and the second semiconductor chip (22); a step of forming one or more first via holes (60h) penetrating the first insulating layer (81), the core (10), and the second insulating layer (82) at the location where the core-through-via (60) is to be formed, and removing a portion of the first insulating layer (81) to expose a portion of the first conductive layer (31) or a pad of the first semiconductor chip (21) and a plurality of second The method may include the step (S34) of forming via holes (91h) and removing a portion of the second insulating layer (82) to expose a portion of the second conductive layer (32) or a pad of the second semiconductor chip (22); the step (S35) of filling an electrically conductive material into the first via hole (60h) and filling an electrically conductive material into the second via hole (91h); and the step (S36) of forming a plurality of electrode patterns (92) that connect a portion of one or more core-through vias (60) and a plurality of conductive vias (91).
[0074] FIG. 8 is a drawing showing a state in which a carrier substrate (100) according to one embodiment is removed and an open portion (33) is formed in the first conductive layer (31) and the second conductive layer (32).
[0075] The step (S31) of removing the carrier substrate (100) is to remove the carrier substrate (100) for temporarily fixing the first conductive layer (31) and the first semiconductor chip (21). Even after removing the carrier substrate (100), the first conductive layer (31) and the first semiconductor chip (21) can be fixed to the core (10) because the adhesive layer (12) of the core (10) fixes the first conductive layer (31).
[0076] The step (S32) of forming the open portion (33) involves removing a portion of the first conductive layer (31) and the second conductive layer (32) to expose the portion for forming the core through-via (60). The step (S32) of forming the open portion (33) can be performed using methods such as etching. The open portion (33) formed in the first conductive layer (31) and the open portion (33) formed in the second conductive layer (32) can be formed at a location for forming the core through-via (60). The area of the open portion (33) can be formed larger than the area where the core through-via (60) is formed.
[0077] FIG. 9 is a drawing showing a state in which an insulating layer is formed and a via hole is formed to form a via according to one embodiment.
[0078] The step (S33) of forming the first insulating layer (81) and the second insulating layer (82) is to form the first insulating layer (81) to cover the first conductive layer (31) and to form the second insulating layer (82) to form the second conductive layer (32). The first insulating layer (81) may be formed to cover the first conductive layer (31) and the active surface (21a) of the first semiconductor chip (21). The second insulating layer (82) may be formed to cover the second conductive layer (32) and the active surface (22a) of the second semiconductor chip (22), and to fill the space between the second conductive layer (32) and the second semiconductor chip (22).
[0079] The step (S34) of forming the first via hole (60h) and the second via hole (91h) is to form the first via hole (60h) for forming the core-penetrating via (60) and the second via hole (91h) for forming the conductive via (91).
[0080] The first via hole (60h) can be formed at the location where the core-penetrating via (60) is to be formed. The size of the first via hole (60h) can be formed smaller than the size of the open portion (33). The first via hole (60h) can be formed to penetrate the first insulating layer (81), the core (10) layer, and the second insulating layer (82). The first via hole (60h) can be formed as many times as the number of core-penetrating vias (60).
[0081] The second via hole (91h) is formed to penetrate the first insulating layer (81) or the second insulating layer (82) for electrical connection, thereby exposing the electrode pad (21p) of the first semiconductor chip (21), the electrode pad (22p) of the second semiconductor chip (22), a part of the first conductive layer (31), and a part of the second conductive layer (32). The second via hole (91h) exposing the first conductive layer (31) or the second conductive layer (32) may be formed at a location for forming a ground electrode (94) or a heat dissipation electrode (93). The second via hole (91h) exposing the electrode pad (21p) of the first semiconductor chip (21) or the electrode pad (22p) of the second semiconductor chip (22) may be formed to form an electrode pattern (92) that transmits an electrical signal.
[0082] FIG. 10 is a drawing showing the state in which a core through-via (60) and a redistribution layer are formed according to one embodiment.
[0083] The step (S35) of filling with an electrically conductive material is to fill the first via hole (60h) and the second via hole (91h) with an electrically conductive material. When the first via hole (60h) is filled with an electrically conductive material, the core-penetrating via (60) can be completed. When the second via hole (91h) is filled with an electrically conductive material, the conductive via (91) can be completed.
[0084] The step (S36) of forming the electrode pattern (92) is to form an electrode pattern (92) that is connected to the core through-via (60) and the conductive via (91) and is formed on the first insulating layer (81) or on the second insulating layer (82). The step (S36) of forming the electrode pattern (92) can be performed through a plating and patterning process. When the step (S36) of forming the electrode pattern (92) is performed, the first redistribution layer (71) and the second redistribution layer (72) can be formed.
[0085] The step of filling the electrically conductive material (S35) and the step of forming the electrode pattern (92) (S36) may be performed as a single step. A patterning process may be performed in which a metal layer is formed on the first insulating layer (81) and the second insulating layer (82) while filling the electrically conductive material into the first via hole (60h) and the second via hole (91h), and the metal layer is removed while leaving only the portion to be used as the electrode pattern (92). Some of the plurality of electrode patterns (92) may be heat dissipation electrodes (93) or ground electrodes (94).
[0086] The process of forming the first redistribution layer (71) and the second redistribution layer (72) can be performed using a semi-additive process or a damascene process.
[0087] The step (S36) of forming the electrode pattern (92) may form one or more of a heat dissipation electrode (93) connected to the first conductive layer (31) to discharge heat generated by the first semiconductor chip (21) to the outside, or a heat dissipation electrode (93) connected to the second conductive layer (32) to discharge heat generated by the second semiconductor chip (22) to the outside. In the step (S36) of forming the electrode pattern (92), a heat dissipation electrode (93) capable of performing a function of discharging heat connected to an external circuit may be formed. The location where the heat dissipation electrode (93) is formed is determined during the design stage, and the heat dissipation electrode (93) may be left during the patterning process.
[0088] The step (S36) of forming the electrode pattern (92) may form one or more of a ground electrode (94) connected to the first conductive layer (31) and connected to an external electrical ground, or a ground electrode (94) connected to the second conductive layer (32) and connected to an external electrical ground. In the step (S36) of forming the electrode pattern (92), a ground electrode (94) connected to an external circuit and providing a ground potential may be formed. The location where the ground electrode (94) is formed is determined during the design stage, and the ground electrode (94) may be left during the patterning process.
[0089] A multilayer redistribution layer may also be formed by repeating the process of forming an insulating layer, forming a second via hole in the insulating layer, forming a metal layer on the insulating layer, and patterning.
[0090] As described above, the manufacturing method of the vertical chip stacking package (1) allows the vertical chip stacking package (1) to be manufactured through a simple process. By performing the manufacturing method of the vertical chip stacking package (1), the first semiconductor chip (21) and the second semiconductor chip (22) can be stacked vertically within the core (10). By performing the manufacturing method of the vertical chip stacking package (1), the first semiconductor chip (21), the first conductive layer (31), the filling layer (40), the second conductive layer (32), the fixing layer (50), and the second semiconductor chip (22) can be stacked in order. This is possible because the process is performed by placing the first semiconductor chip (21) on the carrier substrate (100), forming the first conductive layer (31), and then bonding the core (10) with the receiving portion (13) formed thereon onto the first conductive layer (31). Therefore, a vertical chip stacking package (1) can be manufactured using one core (10) without combining two cores (10) or using a multilayer core (10).
[0091] The present disclosure has been described in detail through specific embodiments. The description above is merely an example of applying the principles of the present disclosure, and other configurations may be further included without departing from the scope of the present invention. Explanation of the symbols
[0092] 1: Vertical chip stacking package 10: Core 11: Substrate 12: Adhesive layer 13: Reception Department 21: The first semiconductor chip 22: The second semiconductor chip 31: 1st Challenge Floor 32: 2nd Challenge Floor 40: Filled layer 50: Fixed layer 60: Core Penetrating Via 71: 1st redistribution layer 72: Second redistribution layer 81: First base insulating layer 82: Second base insulation layer 91: Conductive via 92: Electrode pattern 93: Heat dissipation electrode 94: Ground electrode 100: Carrier substrate
Claims
Claim 1 A vertical chip stacking package comprising: a core having a receiving portion formed penetrating from the upper surface to the lower surface; a first semiconductor chip located within the receiving portion such that its active surface faces the lower surface of the core; a first conductive layer formed across the lower surface of the core and the inactive surface of the first semiconductor chip; a charging layer charged on the first conductive layer within the receiving portion; a second conductive layer formed across the charging layer and the upper surface of the core; a fixed layer formed on the second conductive layer within the receiving portion; a second semiconductor chip located on the fixed layer within the receiving portion such that its active surface faces the upper surface of the core; a first redistribution layer formed below the first conductive layer and having a plurality of electrode patterns connected to the first semiconductor chip or the first conductive layer to transmit an electrical signal; a second redistribution layer formed on the second conductive layer and having a plurality of electrode patterns connected to the second semiconductor chip or the second conductive layer to transmit an electrical signal; and a core-penetrating via formed penetrating the core to transmit an electrical signal between the first redistribution layer and the second redistribution layer. Claim 2 A vertical chip stacking package according to claim 1, wherein the core comprises a substrate having the second conductive layer formed on its upper surface; and an adhesive layer connected to the lower surface of the substrate and bonded to the first conductive layer. Claim 3 A vertical chip stacking package according to claim 1, wherein the first conductive layer and the second conductive layer include an open portion with a portion removed so as to be spaced apart from the core through-via. Claim 4 A vertical chip stacking package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are connected to transmit and receive electrical signals through the first redistribution layer, the core through-via, and the second redistribution layer. Claim 5 A vertical chip stacking package according to claim 1, wherein the first redistribution layer includes a heat dissipation electrode connected to the first conductive layer to discharge heat generated by the first semiconductor chip to the outside, and the second redistribution layer includes a heat dissipation electrode connected to the second conductive layer to discharge heat generated by the second semiconductor chip to the outside. Claim 6 A vertical chip stacked package according to claim 1, wherein the first redistribution layer includes a ground electrode connected to the first conductive layer and connected to an external electrical ground, and the second redistribution layer includes a ground electrode connected to the second conductive layer and connected to an external electrical ground. Claim 7 A vertical chip stacking package according to claim 1, wherein the first conductive layer covers the lower surface and side of the first semiconductor chip to provide shielding that blocks electromagnetic waves, and the second conductive layer surrounds the lower surface and side of the second semiconductor chip to provide shielding that blocks electromagnetic waves. Claim 8 A vertical chip stacking package according to claim 1, wherein the filling layer is formed of a material having higher thermal conductivity than the core and transfers heat between the first conductive layer and the second conductive layer. Claim 9 A vertical chip stacking package according to claim 1, wherein the charging layer is formed of an electrically conductive material and electrically connects the first conductive layer and the second conductive layer. Claim 10 A method for manufacturing a vertical chip stacking package, comprising: a step of placing a first semiconductor chip on a carrier substrate such that an active surface faces the carrier substrate; a step of forming a first conductive layer covering the carrier substrate and the first semiconductor chip; a step of coupling a core onto the first conductive layer so that a receiving portion accommodates the first semiconductor chip inside; a step of forming a filling layer to cover the first conductive layer inside the receiving portion; a step of forming a second conductive layer to cover the filling layer, the inner surface of the receiving portion, and the upper surface of the core; a step of forming a fixing layer on the second conductive layer inside the receiving portion; a step of placing a second semiconductor chip on the fixing layer such that an active surface faces the upper surface of the core; and a step of forming one or more core-through-vias penetrating the upper and lower surfaces of the core and a redistribution layer on the upper and lower surfaces of the core, respectively. Claim 11 A method for manufacturing a vertical chip stacking package according to claim 10, further comprising the steps of: forming the core by bonding an adhesive layer to the lower surface of a substrate before the step of bonding the core; and forming a receiving portion that penetrates both the substrate and the adhesive layer of the core. Claim 12 In claim 10, the step of forming the core-through-via and the redistribution layer comprises: removing the carrier substrate; removing a portion of the first conductive layer and the second conductive layer corresponding to the portion where the core-through-via is to be formed to form an open portion; forming a first base insulating layer covering the first conductive layer and the first semiconductor chip and a second base insulating layer covering the second conductive layer and the second semiconductor chip; forming one or more first via holes penetrating the first base insulating layer, the core, and the second base insulating layer at the location where the core-through-via is to be formed, removing a portion of the first base insulating layer to form a plurality of second via holes exposing a portion of the first conductive layer or a pad of the first semiconductor chip, and removing a portion of the second base insulating layer to form a plurality of second via holes exposing a portion of the second conductive layer or a pad of the second semiconductor chip; filling the first via hole with an electrically conductive material and filling the second via hole with an electrically conductive material. A method for manufacturing a vertical chip stacked package, comprising the step of forming a plurality of electrode patterns connecting some of the one or more core-through-vias and a plurality of conductive vias. Claim 13 A method for manufacturing a vertical chip stack package according to claim 12, wherein the step of forming the electrode pattern comprises forming one or more of a heat dissipation electrode connected to the first conductive layer to discharge heat generated by the first semiconductor chip to the outside, or a heat dissipation electrode connected to the second conductive layer to discharge heat generated by the second semiconductor chip to the outside. Claim 14 A method for manufacturing a vertical chip stacked package according to claim 12, wherein the step of forming the electrode pattern comprises forming one or more of a ground electrode connected to the first conductive layer and connected to an external electrical ground, or a ground electrode connected to the second conductive layer and connected to an external electrical ground.