A substrate processing method, and a semiconductor device manufacturing method using the same

Abstract

The present invention may provide a substrate processing method. The substrate processing method of the present invention comprises performing a first cleaning process in a substrate processing apparatus, and performing a second cleaning process in the substrate processing apparatus after performing the first cleaning process, wherein performing the first cleaning process includes removing a first indium compound in the substrate processing apparatus, and performing the second cleaning process includes removing a second indium compound in the substrate processing apparatus, wherein the first indium compound and the second indium compound are different from each other.

Description

Technology Field

[0001] The present invention relates to a substrate processing method and a method for manufacturing a semiconductor device using the same, and more specifically, to a substrate processing method including an efficient cleaning process and a method for manufacturing a semiconductor device using the same. Background Technology

[0002] Semiconductor devices can be manufactured through various processes. For example, semiconductor devices can be manufactured through photolithography, etching, deposition, etc., on wafers such as silicon. Various fluids may be used in these semiconductor processes. For example, plasma may be used in the etching and / or deposition processes. Electrodes may be used to form and / or control plasma during the semiconductor process. Additionally, a cleaning process may be performed to maintain a constant state of the substrate processing device performing the semiconductor process. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a substrate processing method for an efficient cleaning process and a method for manufacturing a semiconductor device using the same.

[0004] The problem that the present invention aims to solve is to provide a substrate treatment method for removing a metal oxide film and removing generated by-products, and a method for manufacturing a semiconductor device using the same.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0006] To achieve the above-mentioned problem, a substrate processing method according to an embodiment of the present invention comprises performing a first cleaning process in a substrate processing apparatus, and performing a second cleaning process in the substrate processing apparatus after performing the first cleaning process, wherein performing the first cleaning process includes removing a first indium compound in the substrate processing apparatus, and performing the second cleaning process includes removing a second indium compound in the substrate processing apparatus, and wherein the first indium compound and the second indium compound are different from each other.

[0007] To achieve the above-mentioned problem, a method for manufacturing a substrate processing semiconductor device according to an embodiment of the present invention comprises forming mold insulating patterns on a substrate, forming a channel film covering the mold insulating patterns, etching the channel film to form a channel pattern, and performing a cleaning process after forming the channel pattern, wherein the channel film comprises indium, forming the channel pattern comprises forming an indium compound, and performing the cleaning process comprises removing the indium compound. Effects of the invention

[0008] A substrate processing method according to embodiments of the present invention may include performing a cleaning process to remove by-products generated by an etching process. The etching process may generate indium compounds as by-products by etching a metal oxide film containing indium (In). The cleaning process can prevent contamination of the substrate processing device by indium compounds. As a result, the maintenance cycle of the substrate processing device may be extended. Therefore, the productivity of the semiconductor device may be improved. Brief explanation of the drawing

[0009] FIG. 1 is a flowchart illustrating a substrate processing method according to embodiments of the present invention. FIGS. 2 to 7 are drawings for explaining a substrate processing method according to embodiments of the present invention. FIGS. 8 to 21b are drawings for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. Throughout the entire specification, the same reference numerals may refer to the same components.

[0012] FIG. 1 is a flowchart illustrating a substrate processing method according to embodiments of the present invention.

[0013] Referring to FIG. 1, a substrate processing method (S) according to embodiments of the present invention may be provided. The substrate processing method (S) may be a method of processing a substrate using a substrate processing apparatus described below. In this specification, the term "substrate" may mean a semiconductor wafer. A semiconductor wafer may be a wafer containing silicon, but is not limited thereto.

[0014] A substrate processing method (S) may include performing an etching process (S1) and performing a cleaning process (S2). Performing the etching process (S1) may include preparing a substrate within a substrate processing device (S11), forming a plasma on the substrate (S13), and etching a metal oxide film on the substrate (S15). Performing the cleaning process (S2) may include performing a first cleaning process (S21) and performing a second cleaning process (S23).

[0015] Hereinafter, with reference to FIGS. 2 to 7, the substrate processing method (S) of FIG. 1 will be explained in more detail.

[0017] FIGS. 2 to 7 are drawings for explaining a substrate processing method according to embodiments of the present invention. FIGS. 2, FIGS. 4, FIGS. 6, and FIGS. 7 are cross-sectional views showing a substrate processing apparatus according to embodiments of the present invention. FIG. 3 is an enlarged view of the X region of FIG. 2, and FIG. 5 is an enlarged view of the X region of FIG. 4.

[0018] Referring to FIGS. 1, FIGS. 2, and FIGS. 3, preparing a substrate (S11) within a substrate processing device may include placing a substrate (100) on substrate lift pins (SLP), lowering the substrate lift pins (SLP) to place the substrate (100) on a stage (3), and fixing the substrate (100).

[0019] A substrate processing device (P) according to embodiments of the present invention can perform an etching process on a substrate (100). To do this, the substrate processing device (P) can use plasma. More specifically, the substrate processing device (P) can generate plasma using an inductive current. For example, the substrate processing device (P) may be an ICP (Inductively Coupled Plasma) device. However, the present invention is not limited thereto, and the substrate processing device (P) can perform a deposition process on the substrate (100).

[0020] The substrate processing device may include a process chamber (1), a plasma generation unit, a stage (3), substrate lift pins, a DC power generator (4), a first RF power generator (5), a second RF power generator (6), a gas supply unit (7), and a vacuum pump (VP).

[0021] The process chamber (1) may include a lower chamber (11) and an upper chamber (13) above the lower chamber (11). The lower chamber (11) may provide a process space (11h). An etching process for a substrate (100) may be performed in the process space (11h). While the etching process for the substrate (100) is being performed, the process space (11h) may be in a substantial vacuum state. The upper chamber (13) may provide an upper space (13h). A plasma generator may be located within the upper space (13h). Unlike the process space (11h), the upper space (13h) may be maintained at atmospheric pressure.

[0022] The plasma generation unit may include a plasma window (21), a gas distributor (23), and an antenna ring (25). The plasma window (21) is located between the lower chamber (11) and the upper chamber (13) and can separate the process space (11h) from the upper space (13h). The gas distributor (23) is located within the plasma window (21) and can be connected to a gas supply device (7). The gas distributor (23) can uniformly supply the reaction gas, etc. described later, within the process space (11h). The antenna ring (25) is located on the plasma window (21) and may have the shape of a plurality of concentric circles. The antenna ring (25) can be connected to a second RF power generator (6).

[0023] The stage (3) is disposed within the lower chamber (11) and may include a cooling plate (33) and a chuck (31) on the cooling plate (33). The chuck (31) may include a chuck body (311), a plasma electrode (313), a chuck electrode (315), and a heater (317). Additionally, substrate lift pins (SLP) may be provided within the stage (3).

[0024] The substrate lift pins (SLP) are connected to a driving unit, etc., and can move up and down. A substrate (100) can be loaded or unloaded onto a stage (3) by the substrate lift pins (SLP). For example, when the substrate lift pins (SLP) are raised, the upper surface of the substrate (100) can be positioned on the substrate lift pins (SLP) so as to be parallel to the first direction (D1) and the second direction (D2). Subsequently, the substrate (100) can be placed on the stage (3) by lowering the substrate lift pins (SLP).

[0025] In the present specification, the first direction (D1) and the second direction (D2) intersect each other and may be parallel to the upper surface of the substrate (100). The third direction (D3) intersects each of the first direction (D1) and the second direction (D2) and may be a direction perpendicular to the upper surface of the substrate (100). The first direction (D1) and the second direction (D2) may be referred to as horizontal directions, and the third direction (D3) may be referred to as vertical directions. For example, the first direction (D1), the second direction (D2), and the third direction (D3) may be orthogonal to each other.

[0026] The chuck body (311) may come into contact with the substrate (100). In a planar view, a focus ring (FR) and an edge ring (ER) may surround the chuck body (311). A plasma electrode (313) is located within the chuck body (311) and may be connected to a first RF power generator (5). A chuck electrode (315) may be located on the plasma electrode (313) within the chuck body (311). The chuck electrode (315) is connected to a DC power generator (4) and may receive DC power from the DC power generator (4). By the DC power applied to the chuck electrode (315), the substrate (100) may be fixed. For example, the substrate (100) may be fixed on the stage (3) by electrostatic force. The heater (317) is located between the chuck electrode (315) and the plasma electrode (313) within the chuck body (311) and can control the temperature of the substrate (100).

[0027] A cooling plate (33) may be located below the chuck (31). The cooling plate (33) may provide a cooling hole (33h). Cooling water may flow within the cooling hole (33h). The cooling water within the cooling hole (33h) may absorb heat from the substrate (100). As a result, the temperature of the substrate (100) on the stage (3) may be controlled.

[0028] The gas supply device (7) can supply fluids such as process gas and reaction gas to the process space (11h). For example, the gas supply device (7) may include a gas tank, a compressor, and a valve, etc. A portion of the fluid supplied to the process space (11h) by the gas supply device (7) may be formed into plasma.

[0029] A vacuum pump (VP) can be connected to a process space (11h). The vacuum pump (VP) can remove fluid present in the process space (11h). As a result, the process space (11h) can be maintained under vacuum pressure. For example, the vacuum pump (VP) may include a turbomolecular pump (TMP).

[0030] Referring to FIGS. 1, 4, and 5, forming plasma on a substrate (S13) may include supplying process gas into a substrate processing device (P) and applying RF power to an antenna ring (25).

[0031] Supplying process gas into the substrate processing device (P) can be performed by a gas supply device (7). The gas supply device (7) can provide process gas uniformly within the process space (11h) through a gas distributor (23). For example, the process gas may include reactive gases such as chlorine (Cl2), hydrofluoric acid (HF), silicon tetrachloride (SiCl4), but is not limited thereto.

[0032] Applying RF power to the antenna ring (25) can be performed by a second RF power generator (6). The second RF power generator (6) can provide RF power to the antenna ring (25). The antenna ring (25) can form an electric field and / or magnetic field in the process space (11h) using the provided RF power. A portion of the process gas provided in the process space (11h) can be formed into plasma (PL) on the stage (3) by the electric field and / or magnetic field.

[0033] Etching the metal oxide film (MOL) on the substrate (100) may include applying RF power to the stage (3) and generating a first indium compound and a second indium compound. The metal oxide film (MOL) on the substrate (100) may be formed by a deposition process or the like, but is not limited thereto. For example, the metal oxide film (MOL) may include indium (In). More specifically, the metal oxide film (MOL) may further include gallium (Ga), zinc (Zn), titanium (Ti), and aluminum (Al).

[0034] Applying RF power to the stage (3) can be performed by a first RF power generator (5). The first RF power generator (5) can provide RF power to the plasma electrode (313) of the stage (3). The plasma electrode (313) can use the provided RF power to pull plasma particles toward the substrate (100). As a result, at least a portion of the metal oxide film (MOL) on the substrate (100) can be etched.

[0035] A metal oxide film (MOL) may be etched to produce different first indium compounds and second indium compounds. For example, each of the first indium compound and the second indium compound may contain indium (In) and may also contain other elements. The first indium compound and the second indium compound may be byproducts of the metal oxide film (MOL) formed by etching. The first indium compound and the second indium compound may be in a solid state in the process space (11h). As a result, the first indium compound and the second indium compound may remain in the process space (11h) without being discharged to the outside by the vacuum pump (VP). Therefore, a problem of contamination of the interior of the substrate processing device (P) may occur. For example, the first indium compound may contain oxygen (O), and the second indium compound may contain chlorine (Cl).

[0036] Referring to FIGS. 1 and FIGS. 6, performing a first cleaning process (S21) may include supplying first reaction gases (RG1) into a substrate processing device (P), removing a first indium compound, and forming a plasma (PL) within the substrate processing device (P).

[0037] Supplying the first reaction gases (RG1) into the substrate processing device (P) can be performed by a gas supply device (7). The gas supply device (7) can uniformly supply the first reaction gases (RG1) to the process space (11h) of the lower chamber (11) through a gas distributor (23). The first reaction gases (RG1) can react with the first indium compound remaining in the process space (11h).

[0038] The first indium compound can be decomposed by reacting with the first reaction gases (RG1) provided in the process space (11h). For example, the first indium compound may contain oxygen (O), and the first reaction gases (RG1) may contain boron trichloride (BCl3) and chlorine (Cl2). In this case, the first indium compound can be decomposed according to the reaction scheme 1 below.

[0039] [Reaction Equation 1]

[0040]

[0041] A first indium compound containing oxygen (O) can react with first reaction gases (RG1) containing boron (B) and chlorine (Cl) to decompose into trichloroboroxin ((BOCl)3) and diboron trioxide (B2O3). Trichloroboroxin ((BOCl)3) and diboron trioxide (B2O3) may have higher volatility than the first indium compound. As a result, trichloroboroxin ((BOCl)3) and diboron trioxide (B2O3) may be in a gaseous state in the process space (11h). Therefore, trichloroboroxin ((BOCl)3) and diboron trioxide (B2O3) can be easily removed from the substrate processing device (P) by a vacuum pump (VP). That is, the first indium compound can be decomposed by the first reaction gases (RG1) and removed from the substrate processing device (P).

[0042] According to one embodiment, a first indium compound and first reaction gases (RG1) containing chlorine (Cl) may react to produce a second indium compound containing chlorine (Cl). That is, the second indium compound may be produced as the first indium compound decomposes. In other words, removing the first indium compound in the first cleaning process may include producing the second indium compound.

[0043] Forming plasma (PL) within the substrate processing device (P) may be substantially the same as forming plasma on the substrate (S13) described above. The second RF power generator (6) supplies RF power to the antenna ring (25), and the antenna ring (25) can form plasma (PL) on the substrate (100). That is, plasma (PL) can be formed on the substrate (100) by the second RF power generator (6). The first indium compound and the first reaction gases (RG1) can easily react with the plasma (PL). Thus, the first indium compound can be easily decomposed.

[0044] Referring to FIGS. 1 and FIGS. 7, performing a second cleaning process (S23) may include providing second reaction gases (RG2) within a substrate processing device (P), removing a second indium compound, and forming a plasma (PL) within the substrate processing device (P).

[0045] Supplying the second reaction gases (RG2) into the substrate processing device (P) can be performed by a gas supply device (7). The gas supply device (7) can uniformly supply the second reaction gases (RG2) to the process space (11h) of the lower chamber (11) through a gas distributor (23). The second reaction gases (RG2) can react with the second indium compound remaining in the process space (11h).

[0046] The second indium compound can be decomposed by reacting with the second reaction gases (RG2) provided in the process space (11h). For example, the second indium compound may contain chlorine (Cl), and the second reaction gases (RG2) may contain hydrogen bromide (HBr), methane (CH4), and hydrogen (H2). In this case, the second indium compound can be decomposed according to reaction scheme 2 below.

[0047] [Reaction Equation 2]

[0048]

[0049] A second indium compound containing chlorine (Cl) reacts with second reaction gases (RG2) containing bromine (Br), hydrogen (H), and carbon (C) to form indium bromide (InBr x It can decompose into indium bromide (In(CH3)3) and trimethylindium (InBr x ) and trimethylindium (In(CH3)3) can have lower boiling points than the second indium compound. Due to this, indium bromide (InBr x) and trimethylindium (In(CH3)3) may be in a gaseous state in the process space (11h). Therefore, indium bromide (InBr x ) and trimethylindium (In(CH3)3) can be easily removed from the substrate processing device (P) by a vacuum pump (VP). That is, the second indium compound can be decomposed by the second reaction gases (RG2) and removed from the substrate processing device (P).

[0050] According to one embodiment, providing the second reaction gases (RG2) within the substrate processing device (P) may include providing only some of the second reaction gases (RG2) within the substrate processing device (P). For example, only methane (CH4) and hydrogen (H2) among the second reaction gases (RG2) may be provided to the process space (11h). Alternatively, only hydrogen bromide (HBr) among the second reaction gases (RG2) may be provided to the process space (11h). In this case, the second indium compound reacts with the second reaction gases (RG2) to form indium bromide (InBr x Only one of ) and trimethylindium (In(CH3)3) can be produced.

[0051] According to one embodiment, performing the second cleaning process (S23) may be performed in a plurality of steps. Performing the second cleaning process (S23) may include providing some of the second reaction gases (RG2) into the substrate processing device (P), and providing the remainder of the second reaction gases (RG2) into the substrate processing device (P). For example, methane (CH4) and hydrogen (H2) among the second reaction gases (RG2) may be provided first into the process space (11h), and hydrogen bromide (HBr) among the second reaction gases (RG2) may be provided later. Alternatively, hydrogen bromide (HBr) among the second reaction gases (RG2) may be provided first into the process space (11h), and methane (CH4) and hydrogen (H2) may be provided later.

[0052] Forming plasma (PL) within the substrate processing device (P) may be substantially the same as forming plasma (PL) on the substrate (100) of the first cleaning process. Plasma (PL) may be formed on the substrate (100) by the second RF power generator (6). The second indium compound and the second reaction gases (RG2) can easily react with the plasma (PL). Thus, the second indium compound can be easily decomposed and removed within the substrate processing device (P).

[0053] Each of the first cleaning process and the second cleaning process according to embodiments of the present invention is performed within a substrate processing device (P) in which an etching process is performed, and may be a cleaning process using gases rather than liquids. For example, each of the first cleaning process and the second cleaning process may be an in-situ dry cleaning (ISD) process.

[0054] A substrate processing method (S) according to embodiments of the present invention may include performing a cleaning process to remove by-products generated by an etching process. The etching process may generate indium compounds as by-products by etching a metal oxide film containing indium (In). The cleaning process can prevent contamination of the substrate processing device (P) by indium compounds. As a result, the maintenance cycle of the substrate processing device (P) may be extended. Therefore, the productivity of the semiconductor device may be improved.

[0056] FIGS. 8 to 21b are drawings for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 8, 10, 12, 14, 16, 18, and 20 are plan views showing a semiconductor device according to embodiments of the present invention. FIGS. 9a, 9b, 11a, 11b, 13a, 13b, 15a, 15b, 17a, 17b, 19a, 19b, 21a, and 21b are each cross-sections cut along the lines A-A', B-B', C-C', and D-D' of FIGS. 8, 10, 12, 14, 16, 18, and 20, respectively.

[0057] Referring to FIGS. 8, FIGS. 9a, and FIGS. 9b, a peripheral circuit structure (PS) including core circuits (SA) can be formed on a substrate (100).

[0058] More specifically, core circuits (SA) and a lower insulating film (ILD) covering the core circuits (SA) may be formed on a substrate (100). For example, the lower insulating film (ILD) may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric material. The lower insulating film (ILD) may be composed of a single film or a multilayer film comprising different materials.

[0059] Circuit wirings (PCL) and lower contact plugs (LCP) connected to the circuit wirings (PCL) may be formed within the lower insulating layer (ILD). The circuit wirings (PCL) may be electrically connected to the core circuits (SA) through the lower contact plugs (LCP).

[0060] Bit lines (BL) may be formed on the lower insulating film (ILD). Forming the bit lines (BL) may include forming a first interlayer insulating film on the lower insulating film (ILD), forming lower contact plugs (LCP) penetrating the first interlayer insulating film, depositing a lower conductive film on the first interlayer insulating film, and patterning the lower conductive film and the first interlayer insulating film. As a result, bit lines (BL) and a first interlayer insulating pattern (111) may be formed from the lower conductive film and the first interlayer insulating film, respectively. Additionally, a portion of the lower insulating film (ILD) may be exposed.

[0061] Referring to FIGS. 10, FIGS. 11a, and FIGS. 11b, a second interlayer insulating film (113a) may be formed on a lower insulating film (ILD). The second interlayer insulating film (113a) may cover the upper surface of the lower insulating film (ILD) and the bit lines (BL) with a uniform thickness. The thickness of the second interlayer insulating film (113a) may be less than half the gap between adjacent bit lines (BL). As a result, the second interlayer insulating film (113a) may define gap regions located between adjacent bit lines (BL). Each of the gap regions may extend in a first direction (D1) parallel to the bit lines (BL).

[0062] Subsequently, shielding structures (SS) that fill the gap regions of the second interlayer insulating film (113a) may be formed. Each of the shielding structures (SS) may be located between adjacent bit lines (BL). Forming the shielding structures (SS) may include forming a shielding film that fills the gap regions on the second interlayer insulating film (113a) and recessing the upper surface of the shielding film. For example, the shielding structures (SS) may include metallic materials such as W, Ti, Ni, and Co, or conductive two-dimensional materials such as graphene.

[0063] For example, forming shielding structures (SS) may be omitted. In this case, the space between adjacent bit lines (BL) may be filled with a second interlayer insulating film (113a). However, the present invention is not limited thereto.

[0064] Referring to FIG. 12, FIG. 13a, and FIG. 13b, a second interlayer insulation pattern (113) may be formed on a lower insulating film (ILD). Forming the second interlayer insulation pattern (113) may include depositing an insulating material on the second interlayer insulating film (113a) and shielding structures (SS), and performing a planarization process on the insulating material and the second interlayer insulating film (113a). The upper surfaces of the bit lines (BL) may be exposed during the planarization process. Unlike the bit lines (BL), the upper surfaces of the shielding structures (SS) may not be exposed.

[0065] Subsequently, mold insulation patterns (115) may be formed on the second interlayer insulation pattern (113) and the bit lines (BL). Each of the mold insulation patterns (115) may extend in a second direction (D2) and be spaced apart from each other in a first direction (D1). The mold insulation patterns (115) may expose a portion of the bit lines (BL). For example, the mold insulation patterns (115) may comprise a material having etch selectivity with respect to the second interlayer insulation pattern (113), but is not limited thereto.

[0066] A channel film (CHL) covering the mold insulation patterns (115) can be formed. The channel film (CHL) can be formed with a uniform thickness. The channel film (CHL) can be formed by a deposition process such as physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD). The channel film (CHL) can extend onto the bit lines (BL) and the upper surfaces of the second interlayer insulation pattern (113) on the mold insulation patterns (115). That is, the channel film (CHL) can be easily formed by a deposition process on the patterned structure. Thus, the structure of the semiconductor device can be varied.

[0067] The channel film (CHL) comprises indium (In) and may further comprise at least one of gallium (Ga), zinc (Zn), titanium (Ti), and aluminum (Al). For example, the channel film (CHL) may comprise at least one of indium oxide (InO), IGZO, IATO, ITZO, and ITO. The channel film (CHL) may correspond to a metal oxide film on a substrate described with reference to FIGS. 1 to 7.

[0068] A sacrificial layer (117) covering the channel layer (CHL) may be formed. The sacrificial layer (117) may fill the spaces between the mold insulation patterns (115). Forming the sacrificial layer (117) may include performing a planarization process on the sacrificial layer (117). As a result, the sacrificial layer (117) may have a substantially flat top surface. The sacrificial layer (117) may comprise a material having etch selectivity with respect to the mold insulation patterns (115). For example, the sacrificial layer (117) may comprise either insulating materials formed using SOG (Spin On Glass) technology or silicon oxide.

[0069] Referring to FIGS. 14, 15a, and 15b, a mask pattern (MP) may be formed on a sacrificial film (117). The mask pattern (MP) may have openings (OP). The openings (OP) of the mask pattern (MP) may be spaced apart from each other in a first direction (D1) and a second direction (D2). After the mask pattern (MP) is formed, an etching process using the mask pattern (MP) may be performed. Through the etching process, a portion of the sacrificial film (117) and the channel film (CHL) may be removed. As a result, a portion of the second interlayer insulation pattern (113) and a portion of the mold insulation patterns (115) may be exposed. Additionally, a portion of the channel film (CHL) may be removed so that channel patterns (CHP) may be formed from the channel film (CHL).

[0070] Each of the channel patterns (CHP) may include a horizontal portion extending over the bit lines (BL) and a vertical portion extending over the side of the mold insulation patterns (115). At least a portion of each of the channel patterns (CHP) may extend in a direction perpendicular to the upper surface of the substrate (100) (e.g., a third direction (D3)). For example, the semiconductor device of the present invention may include a vertical channel transistor (VCT). However, the present invention is not limited thereto.

[0071] According to one embodiment, the channel film (CHL) can be partially removed after the sacrificial film (117) is partially removed. That is, the sacrificial film (117) and the channel film (CHL) can be etched in different processes. According to another embodiment, the sacrificial film (117) and the channel film (CHL) can be partially removed simultaneously. That is, the sacrificial film (117) and the channel film (CHL) can be etched simultaneously in a single process.

[0072] Since the channel film (CHL) contains indium (In), indium oxide may be generated during the etching process of etching the channel film (CHL). That is, forming channel patterns (CHP) may involve generating indium compounds. Therefore, after the channel patterns (CHP) are formed, a cleaning process to remove indium compounds may be performed.

[0073] According to embodiments of the present invention, channel patterns (CHP) may be formed by a substrate processing method (S) described with reference to FIGS. 1 to 7. Forming the channel patterns (CHP) may include generating a first indium compound and a second indium compound. Additionally, after the channel patterns (CHP) are formed, a first cleaning process for removing the first indium compound and a second cleaning process for removing the second indium compound may be performed. The second cleaning process may be performed after the first cleaning process.

[0074] Referring to FIGS. 16, FIGS. 17a, and FIGS. 17b, the mask pattern (MP) and the sacrificial layer (117) can be removed. The sacrificial layer (117) can be selectively removed using an etching process having etch selectivity for the mold insulation patterns (115) and channel patterns (CHP). As a result, the channel patterns (CHP) can be exposed.

[0075] A preliminary gate insulating film (GIa) and a gate conductive film (CL) may be formed sequentially on the mold insulating patterns (115) and channel patterns (CHP). The preliminary gate insulating film (GIa) may cover the channel patterns (CHP) and the mold insulating patterns (115) with a uniform thickness. The gate conductive film (CL) may cover the preliminary gate insulating film (GIa) with a uniform thickness. The thickness of the gate conductive film (CL) may be substantially greater than the thickness of the preliminary gate insulating film (GIa). For example, the preliminary gate insulating film (GIa) and the gate conductive film (CL) may each be formed by a deposition process.

[0076] Referring to FIGS. 18, 19a, and 19b, word lines (WL) including first and second word lines (WL1, WL2) can be formed. The first and second word lines (WL1, WL2) can be formed by performing an anisotropic etching process on a gate conductive film (CL). Through the anisotropic etching process, the upper surfaces of the first and second word lines (WL1, WL2) can be lower than the upper surfaces of the channel patterns (CP).

[0077] Subsequently, first insulation patterns (143) may be formed between a pair of first and second word lines (WL1, WL2). Each of the first insulation patterns (143) may fill the space between the pair of first and second word lines (WL1, WL2). The upper surfaces of the first insulation patterns (143) may co-plane with the upper surfaces of the first and second word lines (WL1, WL2).

[0078] Capping patterns (145) may be formed on the first insulation patterns (143). Forming the capping patterns (145) may include performing a flattening process so that the upper surface of the mold insulation patterns (115) is exposed. The upper surfaces of the capping patterns (145) may co-plane with the upper surfaces of the channel patterns (CP) and the upper surfaces of the mold insulation patterns (115).

[0079] Referring to FIGS. 20, FIGS. 21a, and FIGS. 21b, landing pads (LP) and second insulation patterns (150) may be formed on capping patterns (145) and mold insulation patterns (115). The landing pads (LP) may be spaced apart from each other in a first direction (D1) and a second direction (D2). Each landing pad (LP) may be connected to each channel pattern (CHP). The second insulation patterns (150) may fill the space between the landing pads (LP). The landing pads (LP) and the second insulation patterns (150) may have upper surfaces of a co-plane.

[0080] Data storage patterns (DSP) can be formed on each of the landing pads (LP). The data storage patterns (DSP) are connected to the landing pads (LP) and can be electrically connected to the channel patterns (CHP) through the landing pads (LP). As a result, a cell array structure (CS) including bit lines (BL), channel patterns (CHP), word lines (WL), and data storage patterns (DSP) can be formed on a peripheral circuit structure (PS).

[0081] According to one embodiment, each of the data storage patterns (DSP) may be a capacitor comprising a lower electrode, a dielectric film, and an upper electrode. In this case, the semiconductor device may be a dynamic random access memory (DRAM). According to another embodiment, the data storage patterns (DSP) may include a magnetic tunnel junction pattern. In this case, the semiconductor device may be a magnetic random access memory (MRAM). According to yet another embodiment, the data storage patterns (DSP) may include a phase change material or a variable resistance material. In this case, the semiconductor device may be a phase-change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is merely exemplary and the present invention is not limited thereto, and the data storage patterns (DSP) may include various structures and / or materials capable of storing data.

[0083] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A substrate processing method comprising: performing a first cleaning process in a substrate processing device; and, after performing the first cleaning process, performing a second cleaning process in the substrate processing device, wherein performing the first cleaning process includes removing a first indium compound in the substrate processing device, and performing the second cleaning process includes removing a second indium compound in the substrate processing device, wherein the first indium compound and the second indium compound are different substrate processing methods. Claim 2 A substrate processing method according to claim 1, further comprising performing an etching process in the substrate processing device before performing the first cleaning process. Claim 3 A substrate processing method according to claim 2, wherein performing the etching process comprises etching a metal oxide film containing indium on a substrate. Claim 4 A substrate processing method according to claim 3, wherein etching the metal oxide film comprises generating the first and second indium compounds. Claim 5 A substrate processing method according to claim 1, wherein each of performing the first cleaning process and performing the second cleaning process comprises forming plasma within the substrate processing apparatus. Claim 6 A substrate processing method according to claim 1, wherein performing the first cleaning process comprises providing a first reaction gas within the substrate processing device, and performing the second cleaning process comprises providing a second reaction gas within the substrate processing device. Claim 7 A substrate treatment method according to claim 6, wherein the first reaction gas comprises boron trichloride and chlorine, and the first indium compound comprises oxygen. Claim 8 A substrate treatment method according to claim 6, wherein the second reaction gas comprises at least one of hydrogen bromide, methane, and hydrogen, and the second indium compound comprises chlorine. Claim 9 A substrate processing method according to claim 1, wherein each of the first cleaning process and the second cleaning process is an in-situ dry cleaning process performed within the substrate processing apparatus. Claim 10 A substrate processing method according to claim 1, wherein performing the first cleaning process further comprises generating the second indium compound.

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