Etch-stop layer topography for advanced integrated circuit structure fabrication

Abstract

The embodiments of the present disclosure relate to the field of manufacturing advanced integrated circuit structures, particularly the field of manufacturing integrated circuit structures at 10 nanometer nodes and smaller, and the resulting structures. In one example, the integrated circuit structure comprises a plurality of conductive interconnect lines located within an interlayer dielectric (ILD) layer on a substrate and spaced apart by the interlayer dielectric (ILD) layer. Each of the plurality of conductive interconnect lines has an upper surface below the upper surface of the ILD layer. An etching stop layer is located on the ILD layer and the plurality of conductive interconnect lines and is conformal to them, and the etching stop layer has a non-planar upper surface, the uppermost portion of the non-planar upper surface is above the ILD layer, and the lowermost portion of the non-planar upper surface is above the plurality of conductive interconnect lines.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed on November 30, 2017, with the title of the invention “ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION”—the entire contents of which are incorporated herein by reference.

[0003] Technology field

[0004] The embodiments of the present disclosure relate to the field of manufacturing advanced integrated circuit structures, particularly the field of manufacturing 10 nanometer nodes and smaller integrated circuit structures and the resulting structures. Background Technology

[0005] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the continuously growing semiconductor industry. Scaling to increasingly smaller features enables an increased density of functional units on the limited real estate of semiconductor chips. For example, reducing transistor size makes it possible to integrate a larger number of memory or logic devices onto a chip, leading to the manufacture of products with increased capacity. However, the drive for greater capacity is not without its challenges. The need to optimize the performance of each individual device is becoming increasingly important.

[0006] Variability in conventional and currently known manufacturing processes may limit the possibility of further extending them to the 10-nanometer node or sub-10-nanometer node range. Consequently, the manufacturing of functional components required for future technology nodes may require the introduction of new methodologies or the integration of new technologies into or in place of current manufacturing processes. Brief explanation of the drawing

[0007] FIG. 1a illustrates a cross-sectional view of a starting structure after the deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning. FIG. 1b illustrates a cross-sectional view of the structure of FIG. 1a after patterning of the hard mask layer by pitch halving. FIG. 2a is a schematic diagram of a pitch quartering approach used to manufacture semiconductor fins according to one embodiment of the present disclosure. FIG. 2b illustrates a cross-sectional view of semiconductor pins manufactured using a pitch 4-division approach according to one embodiment of the present disclosure. FIG. 3a is a schematic diagram of a merged fin pitch quartering approach used to manufacture semiconductor fins according to one embodiment of the present disclosure. FIG. 3b illustrates a cross-sectional view of semiconductor pins manufactured using a merged pin pitch 4-part approach according to one embodiment of the present disclosure. FIGS. 4a to 4c illustrate cross-sectional views showing various operations in a method for manufacturing a plurality of semiconductor pins according to one embodiment of the present disclosure. FIG. 5a illustrates a cross-sectional view of a pair of semiconductor pins separated by a three-layer trench isolation structure according to one embodiment of the present disclosure. FIG. 5b illustrates a cross-sectional view of another pair of semiconductor pins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure. FIGS. 6a to 6d illustrate cross-sectional views of various operations in the manufacture of a three-layer trench isolation structure according to one embodiment of the present disclosure. FIGS. 7a through 7e illustrate angled three-dimensional cross-sectional views of various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure. FIGS. 8a through 8f illustrate slightly projected cross-sectional views cut along the aa' axis of FIG. 7e for various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure. FIG. 9a illustrates a slightly projected cross-sectional view cut along the aa' axis of FIG. 7e for an integrated circuit structure including permanent gate stacks and epitaxial source or drain regions according to one embodiment of the present disclosure. FIG. 9b illustrates a cross-sectional view taken along the bb' axis of FIG. 7e for an integrated circuit structure including epitaxial source or drain regions and a multilayer trench isolation structure according to one embodiment of the present disclosure. FIG. 10 illustrates a cross-sectional view of an integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure. FIG. 11 illustrates a cross-sectional view of another integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure. FIGS. 12a to 12d illustrate cross-sectional views taken at source or drain positions illustrating various operations in the manufacture of an integrated circuit structure according to one embodiment of the present disclosure. FIGS. 13a and FIGS. 13b illustrate plan views illustrating various operations in a method for patterning pins having multi-gate spacing to form a local isolation structure according to one embodiment of the present disclosure. FIGS. 14a through 14d illustrate plan views illustrating various operations in a method for patterning pins having a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. FIG. 15 illustrates a cross-sectional view of an integrated circuit structure having pins with multi-gate spacing for local isolation according to one embodiment of the present disclosure. FIG. 16a illustrates a cross-sectional view of an integrated circuit structure having pins with a single gate spacing for local isolation, according to another embodiment of the present disclosure. FIG. 16b illustrates a cross-sectional view showing locations where a pin isolation structure may be formed instead of a gate electrode, according to one embodiment of the present disclosure. FIGS. 17a through 17c illustrate various depth possibilities for a fin cut manufactured using a fin trim isolation approach according to one embodiment of the present disclosure. FIG. 18 illustrates a plan view and a corresponding cross-sectional view cut along the aa' axis showing possible options for the depth of local positions versus wider positions of pin cuts within a pin according to one embodiment of the present disclosure. FIGS. 19a and 19b illustrate cross-sectional views of various operations in a method for selecting fin end stressor positions at the ends of a fin having a wide cut, according to one embodiment of the present disclosure. FIGS. 20a and 20b illustrate cross-sectional views of various operations in a method for selecting pin end stressor positions at the ends of a pin having a local cut, according to one embodiment of the present disclosure. FIGS. 21a through 21m illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having differentiated pin end dielectric plugs according to one embodiment of the present disclosure. FIGS. 22a to 22d illustrate cross-sectional views of exemplary structures of PMOS pin end stressor dielectric plugs according to one embodiment of the present disclosure. FIG. 23a illustrates a cross-sectional view of another semiconductor structure having pin end stress-inducing features according to another embodiment of the present disclosure. FIG. 23b illustrates a cross-sectional view of another semiconductor structure having pin end stress-inducing features according to another embodiment of the present disclosure. FIG. 24a illustrates an angled view of a pin having tensile uniaxial stress according to one embodiment of the present disclosure. FIG. 24b illustrates an angled view of a pin having compressive uniaxial stress according to one embodiment of the present disclosure. FIGS. 25a and FIGS. 25b illustrate plan views illustrating various operations in a method for patterning pins having a single gate gap to form a local isolation structure at selected gate line cut positions according to one embodiment of the present disclosure. FIGS. 26a through 26c illustrate cross-sectional views of various possibilities for poly cut and pin trim isolation (FTI) local pin cut locations and dielectric plugs for poly cut only locations for various regions of the structure of FIG. 25b according to one embodiment of the present disclosure. FIG. 27a illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut into a dielectric plug extending into dielectric spacers of the gate line, according to one embodiment of the present disclosure. FIG. 27b illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut by a dielectric plug extending beyond the dielectric spacers of the gate line, according to another embodiment of the present disclosure. FIGS. 28a through 28f illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having a gate line cut into a dielectric plug, having an upper portion extending beyond the dielectric spacers of the gate line and a lower portion extending into the dielectric spacers of the gate line, according to another embodiment of the present disclosure. FIGS. 29a through 29c illustrate plan views and corresponding cross-sectional views of an integrated circuit structure having residual dummy gate material in the lower portions of a permanent gate stack according to one embodiment of the present disclosure. FIGS. 30a through 30d illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having residual dummy gate material in the lower portions of a permanent gate stack according to another embodiment of the present disclosure. FIG. 31a illustrates a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to one embodiment of the present disclosure. FIG. 31b illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure. FIG. 32a illustrates a plan view of a plurality of gate lines above a pair of semiconductor pins according to one embodiment of the present disclosure. FIG. 32b illustrates a cross-sectional view taken along the aa' axis of FIG. 32a according to one embodiment of the present disclosure. FIG. 33a illustrates cross-sectional views of a pair of NMOS devices having a differentiated voltage threshold based on modulated doping and a pair of PMOS devices having a differentiated voltage threshold based on modulated doping, according to one embodiment of the present disclosure. FIG. 33b illustrates cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures, according to another embodiment of the present disclosure. FIG. 34a illustrates cross-sectional views of a triplet NMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, and a triplet PMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, according to one embodiment of the present disclosure. FIG. 34b illustrates cross-sectional views of a triplet NMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, and a triplet PMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, according to another embodiment of the present disclosure. FIGS. 35a through 35d illustrate cross-sectional views of various operations in a method for manufacturing NMOS devices having differentiated voltage threshold values ​​based on differentiated gate electrode structures according to another embodiment of the present disclosure. FIGS. 36a through 36d illustrate cross-sectional views of various operations in a method for manufacturing PMOS devices having differentiated voltage threshold values ​​based on differentiated gate electrode structures according to another embodiment of the present disclosure. FIG. 37 illustrates a cross-sectional view of an integrated circuit structure having a P / N junction according to one embodiment of the present disclosure. FIGS. 38a through 38h illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure using a dual metal gate alternative gate process flow according to one embodiment of the present disclosure. FIGS. 39a through 39h illustrate cross-sectional views illustrating various operations in a method for manufacturing a dual silicide-based integrated circuit according to one embodiment of the present disclosure. FIG. 40a illustrates a cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to one embodiment of the present disclosure. FIG. 40b illustrates a cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure. FIG. 41a illustrates a cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to one embodiment of the present disclosure. FIG. 41b illustrates a cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to one embodiment of the present disclosure. FIG. 42 illustrates a plan view of a plurality of gate lines above a pair of semiconductor pins according to one embodiment of the present disclosure. FIGS. 43a to 43c illustrate cross-sectional views taken along the aa' axis of FIG. 42 for various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure. FIG. 44 illustrates a cross-sectional view taken along the bb' axis of FIG. 42 of an integrated circuit structure according to one embodiment of the present disclosure. FIGS. 45a and FIGS. 45b respectively illustrate a plan view and a corresponding cross-sectional view of an integrated circuit structure comprising trench contact plugs—having a hard mask material thereon—according to one embodiment of the present disclosure. FIGS. 46a through 46d illustrate cross-sectional views illustrating various operations in a method for manufacturing an integrated circuit structure comprising trench contact plugs—having a hard mask material thereon—according to one embodiment of the present disclosure. FIG. 47a illustrates a plan view of a semiconductor device having a gate contact positioned above an inactive portion of a gate electrode. FIG. 47b illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact positioned above an inactive portion of a gate electrode. FIG. 48a illustrates a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to one embodiment of the present disclosure. FIG. 48b illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to one embodiment of the present disclosure. FIGS. 49a to 49d illustrate cross-sectional views illustrating various operations in a method for manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of a gate, according to one embodiment of the present disclosure. FIG. 50 illustrates a plan view and corresponding cross-sectional views of an integrated circuit structure having trench contacts including an overlying insulating cap layer according to one embodiment of the present disclosure. FIGS. 51a through 51f illustrate cross-sectional views of various integrated circuit structures according to one embodiment of the present disclosure, each having trench contacts having an insulating cap layer above and gate stacks having an insulating cap layer above. FIG. 52a illustrates a plan view of another semiconductor device having a gate contact via positioned above an active portion of a gate, according to another embodiment of the present disclosure. FIG. 52b illustrates a plan view of another semiconductor device having a trench contact via coupling a pair of trench contacts according to another embodiment of the present disclosure. FIGS. 53a through 53e illustrate cross-sectional views illustrating various operations in a method for manufacturing an integrated circuit structure having a gate stack having an insulating cap layer above, according to one embodiment of the present disclosure. FIG. 54 is a schematic diagram of a pitch 4-part approach used to manufacture trenches for interconnect structures according to one embodiment of the present disclosure. FIG. 55a illustrates a cross-sectional view of a metallized layer manufactured using a pitch 4-part scheme according to one embodiment of the present disclosure. FIG. 55b illustrates a cross-sectional view of a metallization layer manufactured using a pitch 2-part scheme on a metallization layer manufactured using a pitch 4-part scheme according to one embodiment of the present disclosure. FIG. 56a illustrates a cross-sectional view of an integrated circuit structure having a metallization layer having one metallization layer having a different metallization layer having one metallization layer having a different metallization layer having a metallization layer having a metallization layer having a metallization layer having a metallization layer having a metallization layer FIG. 56b illustrates a cross-sectional view of an integrated circuit structure having a metallized layer having one metallized line composition coupled to a metallized layer having a different metallized line composition, according to one embodiment of the present disclosure. FIGS. 57a through 57c illustrate cross-sectional views of individual interconnect lines having various liner and conductive capping structural arrangements according to one embodiment of the present disclosure. FIG. 58 illustrates a cross-sectional view of an integrated circuit structure having four metallized layers having one metal line composition and pitch on top of two metallized layers having different metal line compositions and smaller pitches, according to one embodiment of the present disclosure. FIGS. 59a through 59d illustrate cross-sectional views of various interconnect lines and via arrays having a bottom conductive layer according to one embodiment of the present disclosure. FIGS. 60a through 60d illustrate cross-sectional views of structural arrangements for a reset line topography of a BEOL metallized layer according to one embodiment of the present disclosure. FIGS. 61a through 61d illustrate cross-sectional views of structural arrangements for a stepped line topography of a BEOL metallized layer according to one embodiment of the present disclosure. FIG. 62a illustrates a plan view of a metallized layer and a corresponding cross-sectional view cut along the aa' axis of the plan view according to one embodiment of the present disclosure. FIG. 62b illustrates a cross-sectional view of a line end or plug according to one embodiment of the present disclosure. FIG. 62c illustrates another cross-sectional view of a line end or plug according to one embodiment of the present disclosure. FIGS. 63a through 63f illustrate plan views and corresponding cross-sectional views illustrating various operations in a plug last processing scheme according to one embodiment of the present disclosure. FIG. 64a illustrates a cross-sectional view of a conductive line plug—having a seam therein—according to one embodiment of the present disclosure. FIG. 64b illustrates a cross-sectional view of a stack of metallized layers including a conductive line plug at a lower metal line position according to one embodiment of the present disclosure. FIG. 65 illustrates a first view of a cell layout for a memory cell. FIG. 66 illustrates a first view of a cell layout for a memory cell having an internal node jumper according to one embodiment of the present disclosure. FIG. 67 illustrates a second view of the cell layout for a memory cell. FIG. 68 illustrates a second view of a cell layout for a memory cell having an internal node jumper according to one embodiment of the present disclosure. FIG. 69 illustrates a third view of the cell layout for a memory cell. FIG. 70 illustrates a third view of a cell layout for a memory cell having an internal node jumper according to one embodiment of the present disclosure. FIGS. 71a and FIGS. 71b respectively illustrate a bit cell layout and a schematic diagram for a 6-transistor (6T) static random access memory (SRAM) according to one embodiment of the present disclosure. FIG. 72 illustrates cross-sectional views of two different layouts for the same standard cell according to one embodiment of the present disclosure. FIG. 73 illustrates plan views of four different cell arrays indicating even (E) or odd (O) designations according to one embodiment of the present disclosure. FIG. 74 illustrates a plan view of a block-level polygrid according to one embodiment of the present disclosure. FIG. 75 illustrates an exemplary acceptable (pass) layout based on standard cells having different versions according to one embodiment of the present disclosure. FIG. 76 illustrates an exemplary unacceptable (fail) layout based on standard cells having different versions according to one embodiment of the present disclosure. FIG. 77 illustrates another exemplary acceptable layout based on standard cells having different versions according to one embodiment of the present disclosure. FIG. 78 illustrates a partial cut plan view and a corresponding cross-sectional view of a pin-based thin-film resistor structure according to one embodiment of the present disclosure, wherein the cross-sectional view is cut along the aa' axis of the partial cut plan view. FIGS. 79 to 83 illustrate plan views and corresponding cross-sectional views illustrating various operations in a method for manufacturing a pin-based thin-film resistor structure according to one embodiment of the present disclosure. FIG. 84 illustrates a plan view of a pin-based thin-film resistor structure having various exemplary positions for anode or cathode electrode contacts according to one embodiment of the present disclosure. FIGS. 85a through 85d illustrate plan views of various pin geometries for manufacturing a pin-based precision resistor according to one embodiment of the present disclosure. FIG. 86 illustrates a cross-sectional view of a lithography mask structure according to one embodiment of the present disclosure. FIG. 87 illustrates a computing device according to one embodiment of the present disclosure. FIG. 88 illustrates an interposer comprising one or more embodiments of the present disclosure. FIG. 89 is an isometric view of a mobile computing platform using an IC manufactured according to one or more processes described herein or including one or more features described herein, according to one embodiment of the present disclosure. FIG. 90 illustrates a cross-sectional view of a flip-chip mounted die according to one embodiment of the present disclosure. Specific details for implementing the invention

[0008] The manufacture of an advanced integrated circuit structure is described. In the following detailed description, numerous specific details, such as specific integration and material regimes, are described to provide a complete understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other cases, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be recognized that the various embodiments depicted in the drawings are exemplary representations and are not necessarily drawn to a specific scale.

[0009] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the essence of the invention or the applications and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, an example, or an illustration.” Any embodiment described as exemplary herein is not to be interpreted as being better or more advantageous than other embodiments. Furthermore, there is no intention to be bound by any expressed or implied theories presented in the foregoing art, background art, brief summary, or the following detailed description.

[0010] This specification includes references to "one embodiment" or "an embodiment." Appearances of the phrases "in one embodiment" or "in one embodiment" do not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0011] Terms. The following paragraphs provide definitions or context for terms found in the present disclosure (including the appended claims).

[0012] "Comprising." This term is open-ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0013] "Configured To." Various units or components may be described or claimed as being "configured to" perform a task or tasks. In these contexts, "configured to" is used to imply structure by indicating that the units or components include a structure that performs the task or tasks during operation. Accordingly, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not on or not active). A reference that a unit or circuit or component is "configured to" perform one or more tasks is clearly intended not to invoke the sixth paragraph of 35 USC §112 with respect to that unit or component.

[0014] "First," "Second," etc. As used herein, these terms are used as labels for the nouns that follow and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0015] "Coupled"—The following description refers to elements, nodes, or features that are "coupled" to one another. As used herein, unless explicitly stated otherwise, "coupled" means that one element, node, or feature is joined (or communicates directly or indirectly with) another element, node, or feature, not necessarily mechanically.

[0016] In addition, specific terms may also be used in the following description for reference purposes only and are therefore not intended to be restrictive. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the referenced drawings. Terms such as "front," "back," "rear," "side," "outboard," and "inboard" describe the orientation or position, or both, of parts of the component within a consistent but arbitrary reference frame that becomes apparent by referring to the text describing the component under discussion and the associated drawings. These terms may include words specifically mentioned above, their derivatives, and words of similar meaning.

[0017] "Inhibit" – As used herein, "inhibit" is used to describe reducing or minimizing an effect. When a component or feature is described as inhibiting an action, movement, or condition, it may completely prevent a result, outcome, or future state. In addition, "inhibit" may also indicate a reduction or diminishment of a result, performance, or effect that might otherwise have occurred. Accordingly, when a component, element, or feature is referred to as inhibiting a result or state, it is not necessary to completely prevent or eliminate the result or state.

[0018] The embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned onto a semiconductor substrate or layer. FEOL generally covers everything up to the deposition of metal interconnect layers (but does not include deposition). After the final FEOL operation, the result is typically a wafer having isolated transistors (e.g., having no wires).

[0019] The embodiments described herein may relate to back-end of line (BEOL) semiconductor processing and structures. BEOL is the latter part of IC manufacturing in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer, such as metallization layers or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0020] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, this approach may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, this approach may also be applicable to FEOL processing.

[0021] Pitch splitting processing and patterning schemes may be implemented to enable the embodiments described herein, or may be included as part of the embodiments described herein. Pitch splitting patterning typically refers to pitch 2-segmentation, pitch 4-segmentation, and others. Pitch splitting schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., strictly unidirectional or primarily unidirectional) at a predefined pitch. Pitch splitting processing is subsequently implemented as a technique to increase line density.

[0022] In one embodiment, the term “grating structure” for pins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not directly achievable through selected lithography. For example, a pattern based on selected lithography may be formed first, but as is known in the art, the pitch may be divided into two by the use of spacer mask patterning. Furthermore, the original pitch may be divided into four by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have metal lines, ILD lines, or hard mask lines that are spaced at substantially constant pitch and have substantially constant width. For example, in some embodiments, the pitch variation will be within 10% and the width variation will be within 10%, and in some embodiments, the pitch variation will be within 5% and the width variation will be within 5%. The pattern may be manufactured by a pitch 2-part or pitch 4-part approach, or other pitch 2-part approach. In one embodiment, the grating does not necessarily have to be a single pitch.

[0023] In the first example, pitch splitting can be implemented to double the line density of the manufactured grating structure. FIG. 1a illustrates a cross-sectional view of a starting structure after the deposition of a hard mask material layer formed on an interlayer dielectric (ILD) layer, but before its patterning. FIG. 1b illustrates a cross-sectional view of the structure of FIG. 1a after the patterning of the hard mask layer by pitch splitting.

[0024] Referring to FIG. 1a, the starting structure (100) has a hard mask material layer (104) formed on an interlayer dielectric (ILD) layer (102). A patterned mask (106) is placed on the hard mask material layer (104). The patterned mask (106) has spacers (108) formed along the sidewalls of its features (lines) on the hard mask material layer (104).

[0025] Referring to FIG. 1b, a hard mask material layer (104) is patterned using a pitch-divided approach. Specifically, the patterned mask (106) is removed first. The resulting pattern of spacers (108) has twice the density of the features of the mask (106) or half the pitch. As illustrated in FIG. 1b, the pattern of spacers (108) is transferred to the hard mask material layer (104), for example, by an etching process, so as to form a patterned hard mask (110). In one such embodiment, the patterned hard mask (110) is formed as a grating pattern having unidirectional lines. The grating pattern of the patterned hard mask (110) may be a dense pitch grating structure. For example, a dense pitch may not be directly achievable through selected lithography techniques. In addition, although not illustrated, the original pitch can be divided into four by the second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hard mask (110) of FIG. 1b may have hard mask lines that are spaced apart from each other at a constant pitch and have a constant width. The dimensions achieved may be much smaller than the critical dimensions of the lithography technique used.

[0026] Accordingly, for either or both of the FEOL (front-end of line) or BEOL (back-end of line) integration schemes, the blanket film may be patterned using lithography and etching processes that may involve, for example, SBDP (spacer-based-double-patterning) or pitch splitting, or SBQP (spacer-based-quadruple-patterning) or pitch splitting. It should be recognized that other pitch splitting approaches may also be implemented. In any case, in one embodiment, the gridded layout may be fabricated by a selected lithography approach, such as 193 nm immersion lithography (193i). Pitch splitting may be implemented to increase the density of lines in the gridded layout by a factor of n. The formation of a grid layout using 193i lithography and 'n'-fold pitch splitting can be denoted as 193i + P / n pitch splitting. In one such embodiment, 193nm immersion scaling can be extended over many generations with cost-effective pitch splitting.

[0027] In the manufacturing of integrated circuit devices, as device dimensions continue to scale down, multi-gate transistors, such as tri-gate transistors, have become more common. Tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructures.

[0028] However, scaling multi-gate transistors yielded no results. As the dimensions of these basic building blocks of microelectronic circuits decreased and the net number of basic building blocks manufactured in a given area increased, the constraints on the semiconductor processes used to manufacture these building blocks became overwhelming.

[0029] According to one or more embodiments of the present disclosure, a pitch 4-division approach is implemented to pattern a semiconductor layer to form semiconductor fins. In one or more embodiments, a merged fin pitch 4-division approach is implemented.

[0030] FIG. 2a is a schematic diagram of a pitch 4-division approach (200) used to manufacture semiconductor pins according to one embodiment of the present disclosure. FIG. 2b illustrates a cross-sectional view of semiconductor pins manufactured using the pitch 4-division approach according to one embodiment of the present disclosure.

[0031] Referring to FIG. 2a, in operation (a), a photoresist layer (PR) is patterned to form photoresist features (202). The photoresist features (202) can be patterned using standard lithography processing techniques, such as 193 immersion lithography. In operation (b), the photoresist features (202) are used to pattern a material layer, such as an insulating or dielectric hardmask layer, to form first backbone (BB1) features (204). First spacer (SP1) features (206) are then formed adjacent to the sidewalls of the first backbone features (204). In operation (c), the first backbone features (204) are removed so as to leave only the first spacer features (206). Before or during the removal of the first backbone features (204), as illustrated in FIG. 2a, the first spacer features (206) may be thinned to form the first spacer features (206'). This thinning may be performed before (as illustrated) or after the removal of BB1 (feature (204)), depending on the required spacing and size required for the BB2 features (208, described below). In operation (d), the first spacer features (206) or the thinned first spacer features (206') are used to pattern a material layer, such as an insulating or dielectric hardmask layer, to form the second backbone (BB2) features (208). Second spacer (SP2) features (210) are subsequently formed adjacent to the sidewalls of the second backbone features (208). In operation (e), the second backbone features (208) are removed so as to leave only the second spacer features (210). The remaining second spacer features (210) can then be used to pattern a semiconductor layer to provide a plurality of semiconductor pins having dimensions that are pitch-four times smaller than the initially patterned photoresist features (202).For example, referring to FIG. 2b, a plurality of semiconductor pins (250), such as silicon pins formed from a bulk silicon layer, are formed using the second spacer features (210) as a mask for patterning, e.g., dry or plasma etching patterning. In the example of FIG. 2b, the plurality of semiconductor pins (250) have essentially the same pitch and spacing throughout.

[0032] It should be recognized that the spacing between initially patterned photoresist features can be modified to change the structural result of the pitch 4-part process. In one example, FIG. 3a is a schematic diagram of a merged pin pitch 4-part approach (300) used to manufacture semiconductor pins according to one embodiment of the present disclosure. FIG. 3b illustrates a cross-sectional view of semiconductor pins manufactured using the merged pin pitch 4-part approach according to one embodiment of the present disclosure.

[0033] Referring to FIG. 3a, in operation (a), a photoresist layer (PR) is patterned to form photoresist features (302). The photoresist features (302) can be patterned using standard lithography processing techniques, such as 193 immersion lithography, but with spacing (e.g., referred to as sub design rule space) that can ultimately interfere with the design rules required to create a uniform pitch multiplied pattern. In operation (b), the photoresist features (302) are used to pattern a material layer, such as an insulating or dielectric hardmask layer, to form first backbone (BB1) features (304). First spacer (SP1) features (306) are subsequently formed adjacent to the sidewalls of the first backbone features (304). However, unlike the scheme illustrated in FIG. 2a, some of the adjacent first spacer features (306) are merged spacer features as a result of the denser photoresist features (302). In operation (c), the first backbone features (304) are removed so as to leave only the first spacer features (306). Before or after the removal of the first backbone features (304), some of the first spacer features (306) may be thinned to form the thinned first spacer features (306'), as illustrated in FIG. 3a. In operation (d), the first spacer features (306) and the thinned first spacer features (306') are used to pattern a material layer, such as an insulating or dielectric hardmask layer, to form the second backbone (BB2) features (308). Second spacer (SP2) features (310) are subsequently formed adjacent to the sidewalls of the second backbone features (308). However, as in the central BB2 features (308) of FIG. 3A, second spacers are not formed at locations where the BB2 features (308) are merged features.In operation (e), the second backbone features (308) are removed so as to leave only the second spacer features (310). The remaining second spacer features (310) can then be used to pattern a semiconductor layer to provide a plurality of semiconductor pins having a pitch four-part dimension compared to the initially patterned photoresist features (302).

[0034] For example, referring to FIG. 3b, a plurality of semiconductor pins (350), such as silicon pins formed from a bulk silicon layer, are formed using the second spacer features (310) as a mask for patterning, e.g., dry or plasma etching patterning. However, in the example of FIG. 3b, the plurality of semiconductor pins (350) have various pitches and spacings. This merged pin spacer patterning approach can be implemented to fundamentally eliminate the presence of pins at specific locations in the pattern of the plurality of pins. Accordingly, merging the first spacer features (306) at specific locations makes it possible to manufacture six or four pins based on two first backbone features (304) that typically generate eight pins, as described in relation to FIG. 2a and FIG. 2b. In one example, the in-board fins have a denser pitch than would normally be possible by creating the fins at a uniform pitch and then cutting off the unnecessary fins, but the latter approach can still be implemented according to the embodiments described herein.

[0035] In an exemplary embodiment, referring to FIG. 3b, in an integrated circuit structure, a first plurality of semiconductor pins (352) have the longest dimension along a first direction (y, the direction into the ground). Adjacent individual semiconductor pins (353) of the first plurality of semiconductor pins (352) are spaced apart from each other by a first amount (S1) in a second direction (x) that is orthogonal to the first direction (y). A second plurality of semiconductor pins (354) have the longest dimension along the first direction (y). Adjacent individual semiconductor pins (355) of the second plurality of semiconductor pins (354) are spaced apart from each other by a first amount (S1) in the second direction. The closest semiconductor pins (356 and 357, respectively) of the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354) are spaced apart from each other by a second amount (S2) in the second direction (x). In one embodiment, the second amount (S2) is greater than the first amount (S1) but less than twice the first amount (S1). In another embodiment, the second amount (S2) is more than twice the first amount (S1).

[0036] In one embodiment, the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354) comprise silicon. In one embodiment, the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354) are continuous with an underlying monocrystalline silicon substrate. In one embodiment, individual parts of the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354) have sidewalls that tape outwardly along a second direction (x) from the top to the bottom of individual parts of the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354). In one embodiment, the first plurality of semiconductor pins (352) have exactly five semiconductor pins, and the second plurality of semiconductor pins (354) have exactly five semiconductor pins.

[0037] In another exemplary embodiment, referring to FIGS. 3a and 3b, a method for manufacturing an integrated circuit structure comprises the step of forming a first primary backbone structure (304) (left BB1) and a second primary backbone structure (304) (right BB1). Primary spacer structures (306) are formed adjacent to the sidewalls of the first primary backbone structure (304) (left BB1) and the second primary backbone structure (304) (right BB1). The primary spacer structures (306) between the first primary backbone structure (304) (left BB1) and the second primary backbone structure (304) (right BB1) are merged. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and first, second, third, and fourth secondary backbone structures (308) are provided. The second and third secondary backbone structures (e.g., a central pair of secondary backbone structures (308)) are merged. Secondary spacer structures (310) are formed adjacent to the sidewalls of the first, second, third, and fourth secondary backbone structures (308). The first, second, third, and fourth secondary backbone structures (308) are subsequently removed. A semiconductor material is subsequently patterned using the secondary spacer structures (310) to form semiconductor pins (350) within the semiconductor material.

[0038] In one embodiment, the first primary backbone structure (304) (left BB1) and the second primary backbone structure (304) (right BB1) are patterned to have a sub-design rule spacing between the first primary backbone structure and the second primary backbone structure. In one embodiment, the semiconductor material comprises silicon. In one embodiment, individual semiconductor pins (350) have sidewalls that tapere outward along a second direction (x) from the top to the bottom of individual semiconductor pins (350). In one embodiment, the semiconductor pins (350) are continuous with the single-crystal silicon substrate underneath. In one embodiment, the step of patterning a semiconductor material using secondary spacer structures (310) includes forming a first plurality of semiconductor pins (352) having the longest dimension along a first direction (y), wherein adjacent individual semiconductor pins of the first plurality of semiconductor pins (352) are spaced apart from each other by a first amount (S1) in a second direction (x) orthogonal to the first direction (y). A second plurality of semiconductor pins (354) having the longest dimension along the first direction (y) are formed, wherein adjacent individual semiconductor pins of the second plurality of semiconductor pins (354) are spaced apart from each other by a first amount (S1) in a second direction (x). The closest semiconductor pins (356 and 357, respectively) of the first plurality of semiconductor pins (352) and the second plurality of semiconductor pins (354) are spaced apart from each other by a second amount (S2) in a second direction (x). In one embodiment, the second amount (S2) is greater than the first amount (S1). In one such embodiment, the second amount (S2) is less than twice the first amount (S1). In another such embodiment, the second amount (S2) is greater than twice and less than three times the first amount (S1). In one embodiment, as shown in FIG. 3b, the first plurality of semiconductor pins (352) has exactly five semiconductor pins, and the second plurality of semiconductor pins (254) has exactly five semiconductor pins.

[0039] In another aspect, in a pin trimming process in which pin removal is performed as an alternative to the merged pin approach, it should be recognized that the pins may be trimmed (removed) during hard mask patterning or by physically removing the pins. As an example of the latter approach, FIGS. 4a through 4c illustrate cross-sectional views illustrating various operations in a method for manufacturing a plurality of semiconductor pins according to an embodiment of the present disclosure.

[0040] Referring to FIG. 4a, a patterned hard mask layer (402) is formed on a semiconductor layer (404), such as a bulk single crystalline silicon layer. Referring to FIG. 4b, fins (406) are subsequently formed within the semiconductor layer (404), for example, by a dry or plasma etching process. Referring to FIG. 4c, selected fins (406) are removed, for example, using a masking and etching process. In the illustrated example, as shown in FIG. 4c, one of the fins (406) may be removed, leaving a remnant fin stub (408). In this "fin trim last" approach, the hard mask (402) is patterned as a whole to provide a grating structure without removing or modifying individual features. The fin population is modified only after the fins have been manufactured.

[0041] In another embodiment, a multilayer trench isolation region, which may be referred to as a shallow trench isolation (STI) structure, can be implemented between semiconductor fins. In one embodiment, a multilayer STI structure is formed between silicon fins formed within a bulk silicon substrate to define sub-fin regions of the silicon fins.

[0042] It may be desirable to use bulk silicon for pins or tri-gate based transistors. However, there is a concern that regions beneath the active silicon pin portion of the device (sub-pins) (e.g., gate control regions, or HSi) may be under reduced gate control or not under gate control at all. Consequently, if source or drain regions are located at or beneath the HSi, leakage paths may exist through the sub-pin regions. For proper device operation, leakage paths within the sub-pin regions may need to be controlled.

[0043] One approach to resolving the above issues is to heavily dope the sub-fin region (e.g., 2E18 / cm²). 3 Much larger than) - this shuts off sub-fin leakage but also results in significant doping at the fins - involved the use of well implant operations. The addition of halo implants caused end-of-line fins to be doped to high levels (e.g., approximately 1E18 / cm²). 3 (Greater than) further increases pin doping.

[0044] Another approach involves doping provided through sub-fin doping, rather than necessarily delivering the same level of doping to the HSi portions of the fins. Processes may involve a step of selectively doping the sub-fin regions of tri-gate or FinFET transistors fabricated on bulk silicon wafers, for example, through tri-gate doped glass sub-fin out-diffusion. For example, selectively doping the sub-fin regions of tri-gate or FinFET transistors can mitigate sub-fin leakage while maintaining low fin doping. Including solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) in the transistor process flow after resetting from the fin sidewalls delivers well doping into the sub-fin regions while keeping the fin bodies relatively undoped.

[0045] Accordingly, process schemes may involve the use of a solid source doping layer (e.g., boron-doped oxide) deposited on the fins after fin etching. Later, after trench filling and polishing, the doping layer is reset with the trench fill material to define the fin height (HSi) of the device. This operation removes the doping layer from the fin sidewalls on the HSi. Thus, the doping layer exists only along the fin sidewalls in the sub-fin region, which ensures precise control of the doping placement. After drive-in annealing, the high doping is confined to the sub-fin region and rapidly transitions to low doping in the adjacent region of the fins on the HSi (forming the channel region of the transistor). Generally, borosilicate glass (BSG) is implemented for NMOS fin doping, whereas phosphosilicate glass (PSG) or arsenic-silicate glass (AsSG) layers are implemented for PMOS fin doping. In one example, these P-type solid-state dopant source layers are BSG layers having a boron concentration in the range of approximately 0.1 to 10 wt%. In another example, these N-type solid-state dopant source layers are PSG layers or AsSG layers having a phosphorus concentration or arsenic concentration in the range of approximately 0.1 to 10 wt%, respectively. A silicon nitride capping layer may be included on the doping layer, and a silicon dioxide or silicon oxide filler material may subsequently be included on the silicon nitride capping layer.

[0046] According to another embodiment of the present disclosure, for relatively thinner fins (e.g., fins having a width of approximately 20 nanometers or less), sub-fin leakage is sufficiently low, wherein an undoped or lightly doped silicon oxide or silicon dioxide film is formed immediately adjacent to the fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is included on the silicon nitride capping layer. It should be recognized that for such structures, doping, such as halo doping of the sub-fin regions, can also be implemented.

[0047] FIG. 5a illustrates a cross-sectional view of a pair of semiconductor pins separated by a three-layer trench isolation structure according to one embodiment of the present disclosure.

[0048] Referring to FIG. 5a, the integrated circuit structure includes a pin (502), such as a silicon pin. The pin (502) has a lower pin portion (sub-pin) (502A) and an upper pin portion (502B) (H Si It has a first insulating layer (504) located directly above the side walls of the lower pin portion (502A) of the pin (502). A second insulating layer (506) located directly above the first insulating layer (504) located directly above the side walls of the lower pin portion (502A) of the pin (502). A dielectric filling material (508) is located laterally adjacent to the second insulating layer (506) located directly above the first insulating layer (504) located directly above the side walls of the lower pin portion (502A) of the pin (502).

[0049] In one embodiment, the first insulating layer (504) is a non-doped insulating layer comprising silicon and oxygen, such as, for example, a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer (504) comprises silicon and oxygen and 1E15 atoms / cm² 3It does not have other atomic species with a greater atomic concentration. In one embodiment, the first insulating layer (504) has a thickness in the range of 0.5 to 2 nanometers.

[0050] In one embodiment, the second insulating layer (506) comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the second insulating layer (506) has a thickness in the range of 2 to 5 nanometers.

[0051] In one embodiment, the dielectric filling material (508) comprises silicon and oxygen, such as silicon oxide and silicon dioxide insulating layers. In one embodiment, the gate electrode is ultimately formed on the upper upper portion (502B) of the pin (502) and laterally adjacent to the sidewalls of the upper portion (502B) of the pin (502).

[0052] It should be recognized that during processing, the upper portions of the semiconductor pins may be eroded or consumed. Additionally, the trench isolation structures between the pins may also be eroded to have a non-planar topography or may be formed with a non-planar topography during manufacturing. As an example, FIG. 5b illustrates a cross-sectional view of another pair of semiconductor pins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure.

[0053] Referring to FIG. 5b, the integrated circuit structure includes a first pin (552), such as a silicon pin. The first pin (552) has a lower pin portion (552A) and an upper pin portion (552B), and a shoulder feature (554) in the area between the lower pin portion (552A) and the upper pin portion (552B). The second pin (562), such as a second silicon pin, has a lower pin portion (562A) and an upper pin portion (562B), and a shoulder feature (564) in the area between the lower pin portion (562A) and the upper pin portion (562B). A first insulating layer (574) is located directly above the sidewalls of the lower pin portion (552A) of the first pin (552) and directly above the sidewalls of the lower pin portion (562A) of the second pin (562). The first insulating layer (574) has a first end portion (574A) that is substantially co-planar with the shoulder feature (554) of the first pin (552), and the first insulating layer (574) further has a second end portion (574B) that is substantially co-planar with the shoulder feature (564) of the second pin (562). The second insulating layer (576) is located directly above the first insulating layer (574) and directly above the sidewalls of the lower pin portion (552A) of the first pin (552) and the sidewalls of the lower pin portion (562A) of the second pin (562).

[0054] The dielectric filling material (578) is laterally adjacent to the second insulating layer (576) which is immediately above the first insulating layer (574) which is immediately above the sidewalls of the lower pin portion (552A) of the first pin (552) and immediately above the sidewalls of the lower pin portion (562A) of the second pin (562). In one embodiment, as shown in FIG. 5b, the dielectric filling material (578) has an upper surface (578A), wherein a portion of the upper surface (578A) of the dielectric filling material (578) is below at least one of the shoulder features (554) of the first pin (552) and below at least one of the shoulder features (564) of the second pin (562).

[0055] In one embodiment, the first insulating layer (574) is a non-doped insulating layer comprising silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer (574) comprises silicon and oxygen and has 1E15 atoms / cm² 3 It does not have other atomic species having a greater atomic concentration. In one embodiment, the first insulating layer (574) has a thickness in the range of 0.5 to 2 nanometers.

[0056] In one embodiment, the second insulating layer (576) comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-deficient silicon nitride insulating layer. In one embodiment, the second insulating layer (576) has a thickness in the range of 2 to 5 nanometers.

[0057] In one embodiment, the dielectric filling material (578) comprises silicon and oxygen, such as silicon oxide and silicon dioxide insulating layers. In one embodiment, the gate electrode is ultimately formed above the top of the upper pin portion (552B) of the first pin (552) and laterally adjacent to the sidewalls of the upper pin portion (552B) of the first pin (552), and above the top of the upper pin portion (562B) of the second pin (562) and laterally adjacent to the sidewalls of the upper pin portion (562B) of the second pin (562). The gate electrode is additionally located above the dielectric filling material (578) between the first pin (552) and the second pin (562).

[0058] FIGS. 6a to 6d illustrate cross-sectional views of various operations in the manufacture of a three-layer trench isolation structure according to one embodiment of the present disclosure.

[0059] Referring to FIG. 6a, a method for manufacturing an integrated circuit structure includes the step of forming a pin (602), such as a silicon pin. As shown in FIG. 6b, a first insulating layer (604) is formed directly over the pin (602) and conformally to the pin (602). In one embodiment, the first insulating layer (604) comprises silicon and oxygen and 1E15 atoms / cm³ 3 It does not have other atomic species with a greater atomic concentration.

[0060] Referring to FIG. 6c, a second insulating layer (606) is formed directly above the first insulating layer (604) and conformally with the first insulating layer (604). In one embodiment, the second insulating layer (606) comprises silicon and nitrogen. As shown in FIG. 6d, a dielectric filler material (608) is formed directly above the second insulating layer (606).

[0061] In one embodiment, the method further comprises the step of resetting the dielectric filler material (608), the first insulating layer (604), and the second insulating layer (606) to provide a pin (602) having an exposed upper pin portion (602A) (e.g., upper pin portions (502B, 552B, or 562B) of FIG. 5a and 5b). The resulting structure may be as described in relation to FIG. 5a or FIG. 5b. In one embodiment, the step of resetting the dielectric filler material (608), the first insulating layer (604), and the second insulating layer (606) involves the step of using a wet etching process. In another embodiment, the step of resetting the dielectric filler material (608), the first insulating layer (604), and the second insulating layer (606) involves the step of using a plasma etching or dry etching process.

[0062] In one embodiment, the first insulating layer (604) is formed using a chemical vapor deposition process. In one embodiment, the second insulating layer (606) is formed using a chemical vapor deposition process. In one embodiment, the dielectric filler material (608) is formed using a spin-on process. In one such embodiment, the dielectric filler material (608) is a spin-on material and is exposed to steam treatment, for example, before or after a recess etching process, to provide a cured material containing silicon and oxygen. In one embodiment, the gate electrode is ultimately formed on the upper top of the upper pin portion of the pin (602) and laterally adjacent to the sidewalls of the upper pin portion of the pin (602).

[0063] In another embodiment, a gate sidewall spacer material may be maintained over the trench isolation regions as a protective layer against erosion of the specific trench isolation regions during subsequent processing operations. For example, FIGS. 7a through 7e illustrate angled three-dimensional cross-sectional views of various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure.

[0064] Referring to FIG. 7a, a method for manufacturing an integrated circuit structure includes the step of forming a pin (702), such as a silicon pin. The pin (702) has a lower pin portion (702A) and an upper pin portion (702B). An insulating structure (704) is formed immediately adjacent to the sidewalls of the lower pin portion (702A) of the pin (702). A gate structure (706) is formed above the upper pin portion (702B) and above the insulating structure (704). In one embodiment, the gate structure is a placeholder or dummy gate structure comprising a sacrificial gate dielectric layer (706A), a sacrificial gate (706B), and a hard mask (706C). The dielectric material (708) is formed conformally with the upper pin portion (702B) of the pin (702), conformally with the gate structure (706), and conformally with the insulating structure (704).

[0065] Referring to FIG. 7b, a hard mask material (710) is formed on top of a dielectric material (708). In one embodiment, the hard mask material (710) is a carbon-based hard mask material formed using a spin-on process.

[0066] Referring to FIG. 7c, the hard mask material (710) is reset to form a reset hard mask material (712) and to expose a portion of the dielectric material (708) that is conformal to the upper pin portion (702B) of the pin (702) and conformal to the gate structure (706). The reset hard mask material (712) covers a portion of the dielectric material (708) that is conformal to the insulating structure (704). In one embodiment, the hard mask material (710) is reset using a wet etching process. In another embodiment, the hard mask material (710) is reset using an ash, dry etching, or plasma etching process.

[0067] Referring to FIG. 7d, the dielectric material (708) is anisotropically etched to form the patterned dielectric material (714) along the sidewalls of the gate structure (706) (as dielectric spacers (714A)), along the sidewalls of the upper pin portion (702B) of the pin (702), and on top of the insulating structure (704).

[0068] Referring to FIG. 7e, the reset hardmask material (712) is removed from the structure of FIG. 7d. In one embodiment, the gate structure (706) is a dummy gate structure, and subsequent processing includes replacing the gate structure (706) with a permanent gate dielectric and gate electrode stack. In one embodiment, additional processing includes forming embedded source or drain structures on opposite sides of the gate structure (706), as described in more detail below.

[0069] Referring again to FIG. 7e, in one embodiment, an integrated circuit structure (700) includes a first pin (left 702), such as a first silicon pin, and the first pin has a lower pin portion (702A) and an upper pin portion (702B). The integrated circuit structure further includes a second pin (right 702), such as a second silicon pin, and the second pin has a lower pin portion (702A) and an upper pin portion (702B). An insulating structure (704) is immediately adjacent to the sidewalls of the lower pin portion (702A) of the first pin and immediately adjacent to the sidewalls of the lower pin portion (702A) of the second pin. The gate electrode (706) is located above the upper pin portion (702B) of the first pin (left 702), above the upper pin portion (702B) of the second pin (right 702), and above the first portion of the insulating structure (704). The first dielectric spacer (714B) is located along the sidewall of the upper pin portion (702B) of the first pin (left 702), and the second dielectric spacer (714C) is located along the sidewall of the upper pin portion (702B) of the second pin (right 702). The second dielectric spacer (714C) is continuous with the first dielectric spacer (714B) above the second portion (704B) of the insulating structure (704) between the first pin (left 702) and the second pin (right 702).

[0070] In one embodiment, the first and second dielectric spacers (714B and 714C) comprise silicon and nitrogen, such as stoichiometric Si3N4 silicon nitride material, silicon-rich silicon nitride material, or silicon-deficient silicon nitride material.

[0071] In one embodiment, as described below in relation to FIG. 9b, the integrated circuit structure (700) further comprises embedded source or drain structures on opposite sides of the gate electrode (706), the embedded source or drain structures have a bottom surface below the top surface of the first and second dielectric spacers (714B and 714C) along the sidewalls of the upper pin portions (702B) of the first and second pins (702), and the source or drain structures have a top surface above the top surface of the first and second dielectric spacers (714B and 714C) along the sidewalls of the upper pin portions (702B) of the first and second pins (702). In one embodiment, as also described below in relation to FIG. 9b, the insulating structure (704) comprises a first insulating layer, a second insulating layer immediately above the first insulating layer, and a dielectric filling material immediately above the second insulating layer.

[0072] FIGS. 8a through 8f illustrate slightly projected cross-sectional views cut along the aa' axis of FIG. 7e for various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure.

[0073] Referring to FIG. 8a, a method for manufacturing an integrated circuit structure includes the step of forming a pin (702), such as a silicon pin. The pin (702) has a lower pin portion (not shown in FIG. 8a) and an upper pin portion (702B). An insulating structure (704) is formed immediately adjacent to the side walls of the lower pin portion (702A) of the pin (702). A pair of gate structures (706) are formed above the upper pin portion (702B) and above the insulating structure (704). It should be recognized that the view shown in FIG. 8a through 8f is slightly projected to show portions of the insulating structure and gate structures (706) in front of the upper pin portion (702B) (out of the ground) so that the upper pin portion is slightly recessed into the ground. In one embodiment, the gate structures (706) are placeholder or dummy gate structures comprising a sacrifice gate dielectric layer (706A), a sacrifice gate (706B), and a hard mask (706C).

[0074] Referring to FIG. 8b, which corresponds to the process operation described in relation to FIG. 7a, the dielectric material (708) is formed conformally with the upper pin portion (702B) of the pin (702), conformally with the gate structures (706), and conformally with the exposed portions of the insulating structure (704).

[0075] Referring to FIG. 8c, which corresponds to the process operation described in relation to FIG. 7b, a hard mask material (710) is formed on top of a dielectric material (708). In one embodiment, the hard mask material (710) is a carbon-based hard mask material formed using a spin-on process.

[0076] Referring to FIG. 8d, which corresponds to the process operation described in relation to FIG. 7c, the hard mask material (710) is reset to form a reset hard mask material (712) and to expose a portion of the dielectric material (708) that is conformal to the upper pin portion (702B) of the pin (702) and conformal to the gate structures (706). The reset hard mask material (712) covers a portion of the dielectric material (708) that is conformal to the insulating structure (704). In one embodiment, the hard mask material (710) is reset using a wet etching process. In another embodiment, the hard mask material (710) is reset using an ashing, dry etching, or plasma etching process.

[0077] Referring to FIG. 8e, which corresponds to the process operation described in relation to FIG. 7d, the dielectric material (708) is anisotropically etched to form the patterned dielectric material (714) along the sidewalls of the gate structure (706) (as portions (714A)), along portions of the sidewalls of the upper pin portion (702B) of the pin (702), and on top of the insulating structure (704).

[0078] Referring to FIG. 8f, which corresponds to the process operation described in relation to FIG. 7e, the reset hardmask material (712) is removed from the structure of FIG. 8e. In one embodiment, the gate structures (706) are dummy gate structures, and subsequent processing includes replacing the gate structures (706) with permanent gate dielectric and gate electrode stacks. In one embodiment, additional processing includes forming embedded source or drain structures on opposite sides of the gate structures (706), as described in more detail below.

[0079] Referring again to FIG. 8f, in one embodiment, an integrated circuit structure (700) includes a pin (702), such as a silicon pin, and the pin (702) has a lower pin portion (not shown in FIG. 8f) and an upper pin portion (702B). An insulating structure (704) is immediately adjacent to the sidewalls of the lower pin portion of the pin (702). A first gate electrode (left 706) is located above the upper pin portion (702B) and above the first portion (704A) of the insulating structure (704). A second gate electrode (right 706) is located above the upper pin portion (702B) and above the second portion (704A') of the insulating structure (704). The first dielectric spacer (714A to the right of the left 706) is along the sidewall of the first gate electrode (706 to the left), and the second dielectric spacer (714A to the left of the right 706) is along the sidewall of the second gate electrode (706 to the right), and the second dielectric spacer is continuous with the first dielectric spacer above the third part (704A) of the insulating structure (704) between the first gate electrode (706 to the left) and the second gate electrode (706 to the right).

[0080] FIG. 9a illustrates a slightly projected cross-sectional view cut along the aa' axis of FIG. 7e for an integrated circuit structure including permanent gate stacks and epitaxial source or drain regions according to one embodiment of the present disclosure. FIG. 9b illustrates a cross-sectional view cut along the bb' axis of FIG. 7e for an integrated circuit structure including epitaxial source or drain regions and a multilayer trench isolation structure according to one embodiment of the present disclosure.

[0081] Referring to FIGS. 9a and 9b, in one embodiment, the integrated circuit structure includes embedded source or drain structures (910) on opposite sides of gate electrodes (706). The embedded source or drain structures (910) have a bottom surface (910A) below the top surface (990) of first and second dielectric spacers (714B and 714C) along the sidewalls of the upper pin portions (702B) of the first and second pins (702). The embedded source or drain structures (910) have a top surface (910B) above the top surface of the first and second dielectric spacers (714B and 714C) along the sidewalls of the upper pin portions (702B) of the first and second pins (702).

[0082] In one embodiment, the gate stacks (706) are permanent gate stacks (920). In one such embodiment, as illustrated in FIG. 9a, the permanent gate stacks (920) include a gate dielectric layer (922), a first gate layer (924) such as a work function gate layer, and a gate filling material (926). In one embodiment where the permanent gate structures (920) are above the insulating structure (704), the permanent gate structures (920) are formed on residual polycrystalline silicon portions (930) which may be residues of an alternative gate process involving sacrificial polycrystalline silicon gate electrodes.

[0083] In one embodiment, the insulating structure (704) comprises a first insulating layer (902), a second insulating layer (904) immediately above the first insulating layer (902), and a dielectric filling material (906) immediately above the second insulating layer (904). In one embodiment, the first insulating layer (902) is an un-doped insulating layer comprising silicon and oxygen. In one embodiment, the second insulating layer (904) comprises silicon and nitrogen. In one embodiment, the dielectric filling material (906) comprises silicon and oxygen.

[0084] In another embodiment, epitaxial embedded source or drain regions are implemented as source or drain structures for semiconductor pins. As an example, FIG. 10 illustrates a cross-sectional view of an integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure.

[0085] Referring to FIG. 10, the integrated circuit structure (1000) includes a P-type device, such as a P-type metal oxide semiconductor (PMOS) device. The integrated circuit structure (1000) also includes an N-type device, such as an N-type metal oxide semiconductor (NMOS) device.

[0086] The PMOS device of FIG. 10 includes a first plurality of semiconductor pins (1002), such as silicon pins formed from a bulk silicon substrate (1001). At the source or drain location, the upper portions of the pins (1002) are removed, and the same or different semiconductor material is grown to form source or drain structures (1004). It should be recognized that the source or drain structures (1004) will appear identical on both sides of the gate electrode in a cut section view, for example, that they will appear essentially the same on the source side as on the drain side. In one embodiment, as illustrated, the source or drain structures (1004) have a portion below the upper surface and a portion above the upper surface of the insulating structure (1006). In one embodiment, as illustrated, the source or drain structures (1004) are strongly faceted. In one embodiment, a conductive contact (1008) is formed on the source or drain structures (1004). However, in one such embodiment, strong faceting and relatively wide growth of source or drain structures (1004) prevent good coverage by the conductive contact (1008) for at least some time.

[0087] The NMOS device of FIG. 10 includes a second plurality of semiconductor pins (1052), such as silicon pins formed from a bulk silicon substrate (1001). At the source or drain location, the upper portions of the pins (1052) are removed, and the same or different semiconductor material is grown to form source or drain structures (1054). It should be recognized that the source or drain structures (1054) will appear identical on both sides of the gate electrode in a cut section view, for example, that they will appear essentially the same on the source side as on the drain side. In one embodiment, as illustrated, the source or drain structures (1054) have a portion below the upper surface and a portion above the upper surface of the insulating structure (1006). In one embodiment, as illustrated, the source or drain structures (1054) are weakly faceted with respect to the source or drain structures (1004). In one embodiment, a conductive contact (1058) is formed on top of the source or drain structures (1054). In one such embodiment, the relatively weak faceting of the source or drain structures (1054) (compared to the source or drain structures (1004)) and the resulting relatively narrower growth improve good coverage by the conductive contact (1058).

[0088] The shape of the source or drain structures of the PMOS device may be changed to improve the contact area with the overlying contact. For example, FIG. 11 illustrates a cross-sectional view of another integrated circuit structure cut at a source or drain location according to one embodiment of the present disclosure.

[0089] Referring to FIG. 11, the integrated circuit structure (1100) includes a P-type semiconductor (e.g., PMOS) device. The PMOS device includes a first pin (1102), such as a silicon pin. A first epitaxial source or drain structure (1104) is embedded in the first pin (1102). In one embodiment, although not illustrated, the first epitaxial source or drain structure (1104) is on a first side of a first gate electrode (which may be formed above an upper pin portion, such as a channel portion of the pin (1102)), and a second epitaxial source or drain structure is embedded in the first pin (1102) on a second side of the first gate electrode opposite to the first side. In one embodiment, the first (1104) and second epitaxial source or drain structures comprise silicon and germanium and have a profile (1105). In one embodiment, as shown in FIG. 11, the profile is a matchstick profile. A first conductive electrode (1108) is located above the first epitaxial source or drain structure (1104).

[0090] Referring again to FIG. 11, in one embodiment, the integrated circuit structure (1100) also includes an N-type semiconductor (e.g., NMOS) device. The NMOS device includes a second pin (1152), such as a silicon pin. A third epitaxial source or drain structure (1154) is embedded in the second pin (1152). In one embodiment, although not illustrated, the third epitaxial source or drain structure (1154) is on a first side of a second gate electrode (which may be formed above an upper pin portion, such as a channel portion of the pin (1152)), and a fourth epitaxial source or drain structure is embedded in the second pin (1152) on a second side of this second gate electrode opposite to the first side. In one embodiment, the third (1154) and fourth epitaxial source or drain structures comprise silicon and have a profile substantially identical to the profile (1105) of the first (1104) and second epitaxial source or drain structures. A second conductive electrode (1158) is located above the third epitaxial source or drain structure (1154).

[0091] In one embodiment, the first epitaxial source or drain structure (1104) is weakly faceted. In one embodiment, the first epitaxial source or drain structure (1104) has a height of approximately 50 nanometers and a width in the range of 30 to 35 nanometers. In one such embodiment, the third epitaxial source or drain structure (1154) has a height of approximately 50 nanometers and a width in the range of 30 to 35 nanometers.

[0092] In one embodiment, the first epitaxial source or drain structure (1104) is graded from a germanium concentration of approximately 20% at the bottom (1104A) of the first epitaxial source or drain structure (1104) to a germanium concentration of approximately 45% at the top (1104B) of the first epitaxial source or drain structure (1104). In one embodiment, the first epitaxial source or drain structure (1104) is doped with boron atoms. In one such embodiment, the third epitaxial source or drain structure (1154) is doped with phosphorus atoms or arsenic atoms.

[0093] FIGS. 12a to 12d illustrate cross-sectional views taken at source or drain positions illustrating various operations in the manufacture of an integrated circuit structure according to one embodiment of the present disclosure.

[0094] Referring to FIG. 12a, a method for manufacturing an integrated circuit structure comprises the step of forming a pin, such as a silicon pin formed from a silicon substrate (1201). The pin (1202) has a lower pin portion (1202A) and an upper pin portion (1202B). In one embodiment, although not illustrated, a gate electrode is formed above a portion of the upper pin portion (1202B) of the pin (1202) at a location where it enters the ground. This gate electrode has a first side opposite to the second side and defines source or drain locations on the first and second sides. For example, for illustration purposes, cross-sectional locations for the drawings in FIG. 12a through 12d are cut at one of the source or drain locations on one of the sides of the gate electrode.

[0095] Referring to FIG. 12b, the source or drain location of the pin (1202) is resized to form a resized pin portion (1206). The resized source or drain location of the pin (1202) may be on one side of the gate electrode and on a second side of the gate electrode. Referring to both FIG. 12a and FIG. 12b, in one embodiment, dielectric spacers (1204) are formed along the sidewalls of a portion of the pin (1202), for example, on one side of the gate structure. In one such embodiment, resized the pin (1202) involves resized the pin (1202) down below the top surface (1204A) of the dielectric spacers (1204).

[0096] Referring to FIG. 12c, an epitaxial source or drain structure (1208) may be formed, for example, on a recessed pin (1206) and thus on one side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed pin (1206) on a second side of the gate electrode. In one embodiment, as shown in FIG. 12c, the epitaxial source or drain structure (1208) comprises silicon and germanium and has a matchstick profile. In one embodiment, as shown, dielectric spacers (1204) are included and are located along the lower portion (1208A) of the sidewalls of the epitaxial source or drain structure (1208).

[0097] Referring to FIG. 12d, a conductive electrode (1210) is formed on an epitaxial source or drain structure (1208). In one embodiment, the conductive electrode (1210) comprises a conductive barrier layer (1210A) and a conductive filler material (1210B). In one embodiment, as illustrated, the conductive electrode (1210) follows the profile of the epitaxial source or drain structure (1208). In other embodiments, upper portions of the epitaxial source or drain structure (1208) are eroded during the manufacture of the conductive electrode (1210).

[0098] In another embodiment, pin trim isolation (FTI) and single gate spacing for isolated pins are described. Non-planar transistors utilizing pins of semiconductor material protruding from the substrate surface utilize gate electrodes that wrap around two, three, or even all sides of the pins (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are typically subsequently formed on both sides of the gate electrode, either within the pins or as regrowthed portions of the pins. To isolate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor, a gap or space may be formed between the two adjacent pins. Such an isolation gap generally requires some kind of masked etching. Once isolated, the gate stack is subsequently patterned over the individual pins, again, typically using some kind of masked etching (e.g., line etch or opening etch depending on the specific implementation).

[0099] One potential issue with the previously described fin isolation technologies is that the gates are not self-aligned with the ends of the fins, and the alignment of the gate stack pattern and the semiconductor fin pattern depends on the overlay of these two patterns. Consequently, lithography overlay tolerances are added to the dimensioning of the semiconductor fins and isolation gaps, requiring fins to have greater lengths and isolation gaps to be larger for a given level of transistor function than would otherwise be the case. Device architectures and manufacturing technologies that reduce this over-dimensioning thus provide highly advantageous improvements in transistor density.

[0100] Another potential issue with the fin isolation techniques described above is that excessive stress on semiconductor fins, which is desirable for improving carrier mobility, is lost from the channel region of the transistor where too many fin surfaces remain free during manufacturing, thereby allowing fin strain to be relieved. Device architectures and manufacturing techniques that maintain higher levels of desirable fin stress thus provide advantageous improvements in non-planar transistor performance.

[0101] According to one embodiment of the present disclosure, through-gate pin isolation architectures and techniques are described herein. In the exemplary embodiments illustrated, non-planar transistors within a microelectronic device, such as an integrated circuit (IC), are isolated from one another in such a manner that the gate electrodes of the transistors are self-aligned. Although the embodiments of the present disclosure are applicable to almost any IC utilizing non-planar transistors, exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0102] In the embodiments, two ends of adjacent semiconductor pins are electrically isolated from each other by isolation regions positioned relative to the gate electrodes using only a single patterning mask level. In one embodiment, a single mask is used to form a plurality of fixed-pitch sacrificial placeholder stripes, where a first subset of placeholder stripes defines the location or dimensions of the isolation regions, while a second subset of placeholder stripes defines the location or dimensions of the gate electrodes. In certain embodiments, the first subset of placeholder stripes is removed and isolation cuts are made within the semiconductor pins within the openings resulting from the removal of the first subset, while the second subset of placeholder stripes is ultimately replaced by non-sacrificial gate electrode stacks. Because the subset of placeholders used for gate electrode replacement is used to form the isolation regions, the method and the resulting architecture are referred to herein as "through-gate" isolation. One or more through-gate isolation embodiments described in this specification can enable, for example, higher transistor densities and higher levels of advantageous transistor channel stress.

[0103] When isolation is defined after the placement or definition of the gate electrode, a greater transistor density can be achieved because the fin isolation dimensioning and placement can be perfectly on-pitch with the gate electrodes, such that both the gate electrodes and the isolation regions are integer multiples of the minimum feature pitch of a single masking level. In additional embodiments where the semiconductor fin has a lattice mismatch with the substrate on which the fin is placed, a greater degree of strain is maintained by defining isolation after the placement or definition of the gate electrode. In these embodiments, other features of the transistor (such as the gate electrode and added source or drain material) formed before the ends of the fin are defined help to mechanically maintain the fin strain after the isolation cut is made within the fin.

[0104] To provide additional context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are separated from their neighbors by two or more dummy gates having embedded pins. Cells are isolated by etching the pins beneath these two or more dummy gates, which connect one cell to another. Scaling can be significantly improved if the number of dummy gates separating neighboring cells can be reduced from two or more to one. As previously described, one solution requires two or more dummy gates. The pins beneath the two or more dummy gates are etched during pin patterning. A potential issue with this approach is that the dummy gates consume space on the chip that could be used for the cells. In one embodiment, the approaches described herein make it possible to use only one dummy gate to separate neighboring cells.

[0105] In one embodiment, the pin trim isolation approach is implemented as a self-aligned patterning scheme. Here, the pins under a single gate are etched out. Thus, neighboring cells can be separated by a single dummy gate. Advantages of this approach may include reducing space on the chip and enabling more computational power for a given area. This approach may also enable pin trimming to be performed at sub-pin pitch distances.

[0106] FIGS. 13a and FIGS. 13b illustrate plan views showing various operations in a method for patterning pins having multi-gate spacing to form a local isolation structure according to one embodiment of the present disclosure.

[0107] Referring to FIG. 13a, a plurality of pins (1302) are shown having a length along a first direction (1304). A grid (1306) defining positions for ultimately forming a plurality of gate lines—having gaps (1307) between them—is shown along a second direction (1308) orthogonal to the first direction (1304).

[0108] Referring to FIG. 13b, a portion of a plurality of pins (1302) is cut (e.g., removed by an etching process) to leave pins (1310)—which have a cut (1312) within them. Thus, the isolation structure ultimately formed in the cut (1312) has dimensions larger than a single gate line, e.g., the dimensions of three gate lines (1306). Accordingly, gate structures ultimately formed along the locations of the gate lines (1306) will be formed at least partially over the isolation structure formed in the cut (1312). Thus, the cut (1312) is a relatively wide pin cut.

[0109] FIGS. 14a through 14d illustrate plan views illustrating various operations in a method for patterning pins having a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure.

[0110] Referring to FIG. 14a, a method for manufacturing an integrated circuit structure comprises the step of forming a plurality of pins (1402)—each of the plurality of pins (1402) having the longest dimension along a first direction (1404). A plurality of gate structures (1406) are positioned above the plurality of pins (1402), and each of the gate structures (1406) has the longest dimension along a second direction (1408) which is orthogonal to the first direction (1404). In one embodiment, the gate structures (1406) are sacrificial or dummy gate lines, for example, made of polycrystalline silicon. In one embodiment, the plurality of pins (1402) are silicon pins and are continuous with a portion of the silicon substrate underneath.

[0111] Referring to FIG. 14b, a dielectric material structure (1410) is formed between adjacent gate structures of a plurality of gate structures (1406).

[0112] Referring to FIG. 14c, a portion (1412) of one of the gate structures (1406) is removed to expose a portion (1414) of each of the pins (1402). In one embodiment, removing a portion (1412) of one of the gate structures (1406) involves using a lithographic window (1416) that is wider than the width (1418) of the portion (1412) of one of the gate structures (1406).

[0113] Referring to FIG. 14d, the exposed portion (1414) of each of the plurality of pins (1402) is removed to form a cut area (1420). In one embodiment, the exposed portion (1414) of each of the plurality of pins (1402) is removed using a dry or plasma etching process. In one embodiment, removing the exposed portion (1414) of each of the plurality of pins (1402) involves etching to a depth smaller than the height of the plurality of pins (1402). In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of pins (1402). In one embodiment, the depth is deeper than the depth of the active portion of the plurality of pins (1402) to provide an isolation margin. In one embodiment, the exposed portion (1414) of each of the plurality of pins (1402) is removed without or substantially without etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of pins (1402). In one such embodiment, the exposed portion (1414) of each of the plurality of pins (1402) is removed without or substantially laterally etching the source or drain regions (such as epitaxial source or drain regions) of the plurality of pins (1402).

[0114] In one embodiment, the cut area (1420) is ultimately filled with an insulating layer, for example, at the locations of the removed portions (1414) of each of the plurality of pins (1402). Exemplary insulating layers or "poly cut" or "plug" structures are described below. However, in other embodiments, the cut area (1420) is only partially filled with an insulating layer, and a conductive structure is formed following this insulating layer. The conductive structure can be used as a local interconnect. In one embodiment, before filling the cut area (1420) with an insulating layer or an insulating layer housing a local interconnect structure, dopants may be injected or delivered through the cut area (1420) into the pin or the locally cut portion of the pins by a solid source dopant layer.

[0115] FIG. 15 illustrates a cross-sectional view of an integrated circuit structure having pins with multi-gate spacing for local isolation according to one embodiment of the present disclosure.

[0116] Referring to FIG. 15, the silicon pin (1502) has a first pin portion (1504) that is laterally adjacent to a second pin portion (1506). The first pin portion (1504) is separated from the second pin portion (1506) by a relatively wide cut (1508), as described in relation to FIG. 13a and FIG. 13b, and the relatively wide cut (1508) has a width X. A dielectric filling material (1510) is formed in the relatively wide cut (1508) and electrically isolates the first pin portion (1504) from the second pin portion (1506). A plurality of gate lines (1512) are above the silicon pin (1502), wherein each of the gate lines may include a gate dielectric and gate electrode stack (1514), a dielectric cap layer (1516), and sidewall spacers (1518). Two gate lines (two left gate lines (1512)) occupy a relatively wide cut (1508), and accordingly, the first pin portion (1504) is effectively separated from the second pin portion (1506) by two dummy or inactive gates.

[0117] In contrast, the pin portions may be separated by a single gate distance. As an example, FIG. 16a illustrates a cross-sectional view of an integrated circuit structure having pins with a single gate spacing for local isolation according to another embodiment of the present disclosure.

[0118] Referring to FIG. 16a, the silicon pin (1602) has a first pin portion (1604) that is laterally adjacent to a second pin portion (1606). The first pin portion (1604) is separated from the second pin portion (1606) by a relatively narrow cut (1608), as described in relation to FIG. 14a through 14d, and the relatively narrow cut (1608) has a width Y, where Y is smaller than X in FIG. 15. A dielectric filling material (1610) is formed in the relatively narrow cut (1608) and electrically isolates the first pin portion (1604) from the second pin portion (1606). Multiple gate lines (1612) are positioned above the silicon pin (1602), each of which may include a gate dielectric and gate electrode stack (1614), a dielectric cap layer (1616), and sidewall spacers (1618). A dielectric filling material (1610) occupies the position where a single gate line was previously located, and accordingly, the first pin portion (1604) is separated from the second pin portion (1606) by a single "plugged" gate line. In one embodiment, as illustrated, residual spacer material (1620) remains on the sidewalls at the location of the removed gate line portion. As described below, it should be recognized that other regions of the pin (1602) may be isolated from one another by two or more inactive gate lines (region (1622) having three inactive gate lines) manufactured by an earlier, wider pin cut process.

[0119] Referring again to FIG. 16a, the integrated circuit structure (1600) includes a pin (1602), such as a silicon pin. The pin (1602) has the longest dimension along the first direction (1650). An isolation structure (1610) separates the first upper portion (1604) of the pin (1602) from the second upper portion (1606) of the pin (1602) along the first direction (1650). The isolation structure (1610) has a center (1611) along the first direction (1650).

[0120] A first gate structure (1612A) is positioned above the first upper portion (1604) of the pin (1602), and the first gate structure (1612A) has the longest dimension along a second direction (1652) that is orthogonal to the first direction (1650) (e.g., into the ground). The center (1613A) of the first gate structure (1612A) is spaced apart from the center (1611) of the isolation structure (1610) by a pitch along the first direction (1650). A second gate structure (1612B) is positioned above the first upper portion (1604) of the pin, and the second gate structure (1612B) has the longest dimension along the second direction (1652). The center (1613B) of the second gate structure (1612B) is spaced apart from the center (1613A) of the first gate structure (1612A) by a pitch along the first direction (1650). The third gate structure (1612C) is located above the second upper portion (1606) of the pin (1602), and the third gate structure (1612C) has the longest dimension along the second direction (1652). The center (1613C) of the third gate structure (1612C) is spaced apart from the center (1611) of the isolation structure (1610) by a pitch along the first direction (1650). In one embodiment, as illustrated, the isolation structure (1610) has a top that is substantially flat with the top of the first gate structure (1612A), the top of the second gate structure (1612B), and the top of the third gate structure (1612C).

[0121] In one embodiment, each of the first gate structure (1612A), the second gate structure (1612B), and the third gate structure (1612C) includes a gate electrode (1660) on and between the sidewalls of the high-k gate dielectric layer (1662), as illustrated for the exemplary third gate structure (1612C). In one such embodiment, each of the first gate structure (1612A), the second gate structure (1612B), and the third gate structure (1612C) further includes an insulating cap (1616) on the gate electrode (1660) and on the sidewalls of the high-k gate dielectric layer (1662).

[0122] In one embodiment, the integrated circuit structure (1600) further includes a first epitaxial semiconductor region (1664A) on a first upper portion (1604) of a pin (1602) between a first gate structure (1612A) and an isolation structure (1610). A second epitaxial semiconductor region (1664B) is on a first upper portion (1604) of a pin (1602) between a first gate structure (1612A) and a second gate structure (1612B). A third epitaxial semiconductor region (1664C) is on a second upper portion (1606) of a pin (1602) between a third gate structure (1612C) and an isolation structure (1610). In one embodiment, the first, second, and third epitaxial semiconductor regions (1664A, 1664B, and 1664C) comprise silicon and germanium. In another embodiment, the first, second, and third epitaxial semiconductor regions (1664A, 1664B, and 1664C) comprise silicon.

[0123] In one embodiment, the isolation structure (1610) induces stress on the first upper portion (1604) of the pin (1602) and on the second upper portion (1606) of the pin (1602). In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure (1610) is a partially filled insulating layer, and a conductive structure is subsequently formed on this insulating layer. The conductive structure can be used as a local interconnect. In one embodiment, before forming the isolation structure (1610) having an insulating layer or an insulating layer housing a local interconnect structure, dopants are injected or delivered into the pin or a locally cut portion of the pins by a solid source dopant layer.

[0124] In another aspect, it should be recognized that isolation structures such as the isolation structure (1610) described above may be formed in place of the active gate electrode at local locations of the pin cut or at wider locations of the pin cut. In addition, the depths of these local or wider locations of the pin cut may be formed within the pin at various depths relative to each other. In the first example, FIG. 16b illustrates a cross-sectional view showing locations where the pin isolation structure may be formed in place of the gate electrode according to one embodiment of the present disclosure.

[0125] Referring to FIG. 16b, a pin (1680), such as a silicon pin, is formed on a substrate (1682) and may be continuous with the substrate (1682). The pin (1680) has pin ends or wide pin cuts (1684), which may be formed during pin patterning, for example, in the pin trim last approach described above. The pin (1680) also has a local cut (1686), where a portion of the pin (1680) is removed using a pin trim isolation approach, for example, where dummy gates are replaced with dielectric plugs, as described above. Active gate electrodes (1688) are formed on the pin and are shown slightly in front of the pin (1680) so that the pin (1680) is in the background for illustrative purposes, where dashed lines indicate areas covered so as not to be seen from the front. In the pin ends or wide pin cuts (1684), dielectric plugs (1690) may be formed instead of using active gates at these locations. In addition to, or alternatively, in the local cuts (1686), dielectric plugs (1692) may be formed instead of using active gates at these locations. It should be recognized that epitaxial source or drain regions (1694) are also shown at locations of the pins (1680) between the active gate electrodes (1688) and the plugs (1690 or 1692). In addition, in one embodiment, as shown in FIG. 16b, the surface roughness of the pin ends at the local cuts (1686) is rougher than that of the pin ends at the locations of the wider cuts.

[0126] FIGS. 17a through 17c illustrate various depth possibilities for a pin cut manufactured using a pin trim isolation approach according to one embodiment of the present disclosure.

[0127] Referring to FIG. 17a, a semiconductor pin (1700), such as a silicon pin, is formed on a substrate (1702) below and may be continuous with the substrate (1702) below. The pin (1700) has a lower pin portion (1700A) and an upper pin portion (1700B), as defined by the height of an insulating structure (1704) relative to the pin (1700). A local pin isolation cut (1706A) separates the pin (1700) into a first pin portion (1710) and a second pin portion (1712). In the example of FIG. 17a, as illustrated along the aa' axis, the depth of the local pin isolation cut (1706A) is the total depth of the pin (1700) to the substrate (1702).

[0128] Referring to FIG. 17b, in the second example, as illustrated along the aa' axis, the depth of the local pin isolation cut (1706B) is deeper than the total depth of the pin (1700) to the substrate (1702). That is, the cut (1706B) extends into the substrate (1702) below.

[0129] Referring to FIG. 17c, in the third example, as illustrated along the aa' axis, the depth of the local pin isolation cut (1706C) is smaller than the total depth of the pin (1700) but deeper than the upper surface of the isolation structure (1704). Referring again to FIG. 17c, in the fourth example, as illustrated along the aa' axis, the depth of the local pin isolation cut (1706D) is smaller than the total depth of the pin (1700) but is at a level that is approximately coplanar with the upper surface of the isolation structure (1704).

[0130] FIG. 18 illustrates a plan view and a corresponding cross-sectional view cut along the aa' axis showing possible options for the depth of local positions versus wider positions of pin cuts within a pin according to one embodiment of the present disclosure.

[0131] Referring to FIG. 18, first and second semiconductor pins (1800 and 1802), such as silicon pins, have upper pin portions (1800B and 1802B) extending over an insulating structure (1804). Both pins (1800 and 1802) have pin ends or wide pin cuts (1806) that can be formed during pin patterning, for example, in the pin trim last approach described above. Both pins (1800 and 1802) also have a local cut (1808) where a portion of the pin (1800 or 1802) is removed, for example, using a pin trim isolation approach where dummy gates are replaced with dielectric plugs, as described above. In one embodiment, as shown in FIG. 18, the surface roughness of the ends of the pins (1800 and 1802) in the local cut (1808) is rougher than that of the ends of the pins in position 1806.

[0132] Referring to the cross-sectional view of FIG. 18, the lower pin portions (1800A and 1802A) may be seen below the height of the insulating structure (1804). Additionally, as previously described, the residual portion (1810) of the pin removed in the pin trim last process prior to the formation of the insulating structure (1804) is seen in the cross-sectional view. Although shown as protruding above the substrate, the residual portion (1810) may also be at the level of the substrate or within the substrate, as illustrated by additional exemplary wide cut depths (1820). It should be recognized that the wide cuts (1806) for the pins (1800 and 1802) may also be at the levels described for the cut depth (1820)—examples of which are illustrated. As illustrated, the local cuts (1808) may have exemplary depths corresponding to the depths described for FIG. 17a through FIG. 17c.

[0133] Referring collectively to FIGS. 16a, 16b, FIGS. 17a through 17c and FIG. 18, according to one embodiment of the present disclosure, an integrated circuit structure comprises a fin comprising silicon, wherein the fin has a top and side walls, wherein the top has the longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has surface roughness. A gate structure comprises a gate electrode located above the top of the region of the first portion of the fin and laterally adjacent to the side walls of the region of the first portion of the fin. The gate structure has a width along the first direction, and the center of the gate structure is spaced from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is located above the second end of the first portion of the fin, and the second end is on the opposite side of the first end. The second isolation structure has a width along the first direction, and the second end of the first part of the pin has a surface roughness smaller than the surface roughness of the first end of the first part of the pin. The center of the second isolation structure is spaced from the center of the gate structure by a pitch along the first direction.

[0134] In one embodiment, as illustrated in FIG. 16b, the first end of the first portion of the fin has a scalloped topography. In one embodiment, a first epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is located on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width of the first portion of the fin along the second direction below the gate structure, such as the epitaxial features described in relation to FIG. 11 and FIG. 12d, which have a wider width than the fin portions where they are grown, for example, from the perspective illustrated in FIG. 11 and FIG. 12d. In one embodiment, the gate structure further comprises a high-k dielectric layer between the gate electrode and the first portion of the fin and along the sidewalls of the gate electrode.

[0135] Referring collectively to FIGS. 16a, 16b, FIGS. 17a through 17c and FIG. 18, according to another embodiment of the present disclosure, an integrated circuit structure comprises a fin comprising silicon, wherein the fin has a top and side walls, wherein the top has the longest dimension along one direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along that direction. The first end of the first portion of the fin has a depth. A gate structure comprises a gate electrode located above the top of the region of the first portion of the fin and laterally adjacent to the side walls of the region of the first portion of the fin. A second isolation structure is located above the second end of the first portion of the fin, and the second end is on the opposite side of the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0136] In one embodiment, the depth of the second end of the first part of the pin is smaller than the depth of the first end of the first part of the pin. In one embodiment, the depth of the second end of the first part of the pin is larger than the depth of the first end of the first part of the pin. In one embodiment, the first isolation structure has a width along its direction, and the gate structure has a width along its direction. The second isolation structure has a width along its direction. In one embodiment, the center of the gate structure is spaced from the center of the first isolation structure by a pitch along its direction, and the center of the second isolation structure is spaced from the center of the gate structure by a pitch along its direction.

[0137] Referring collectively to FIGS. 16a, 16b, FIGS. 17a through 17c and FIG. 18, according to another embodiment of the present disclosure, an integrated circuit structure comprises a first pin comprising silicon, wherein the first pin has a top and side walls, wherein the top has the longest dimension along one direction, and a discontinuity separates a first end of a first portion of the first pin from a first end of a second portion of the pin along that direction. The first portion of the first pin has a second end opposite to the first end, and the first end of the first portion of the pin has depth. The integrated circuit structures also comprise a second pin comprising silicon, wherein the second pin has a top and side walls, wherein the top has the longest dimension along that direction. The integrated circuit structure also comprises a residual or residual pin portion between the first pin and the second pin. The remaining pin portion has a top and side walls, where the top has the longest dimension along its direction and the top is not coplanar with the depth of the first end of the first portion of the pin.

[0138] In one embodiment, the depth of the first end of the first part of the pin is below the top of the remaining or residual pin part. In one embodiment, the second end of the first part of the pin has a depth that is coplanar with the depth of the first end of the first part of the pin. In one embodiment, the second end of the first part of the pin has a depth that is below the depth of the first end of the first part of the pin. In one embodiment, the second end of the first part of the pin has a depth that is above the depth of the first end of the first part of the pin. In one embodiment, the depth of the first end of the first part of the pin is above the top of the remaining or residual pin part. In one embodiment, the second end of the first part of the pin has a depth that is coplanar with the depth of the first end of the first part of the pin. In one embodiment, the second end of the first part of the pin has a depth that is below the depth of the first end of the first part of the pin. In one embodiment, the second end of the first part of the pin has a depth that is above the depth of the first end of the first part of the pin. In one embodiment, the second end of the first portion of the pin has a depth that is flush with the top of the remaining pin portion. In one embodiment, the second end of the first portion of the pin has a depth that is lower than the top of the remaining pin portion. In one embodiment, the second end of the first portion of the pin has a depth that is higher than the top of the remaining pin portion.

[0139] In another embodiment, dielectric plugs formed at locations of local or wide pin cuts may be tailored to provide specific stress to the pin or pin portion. In these embodiments, the dielectric plugs may be referred to as pin end stressors.

[0140] One or more embodiments relate to the manufacture of pin-based semiconductor devices. Performance improvements for these devices may be achieved through channel stress induced from a poly plug charging process. The embodiments may include utilizing material properties in a poly plug charging process to induce mechanical stress in the channel of a metal oxide semiconductor field-effect transistor (MOSFET). As a result, the induced stress can boost the mobility and drive current of the transistor. In addition, the plug charging method described herein may enable the elimination of any seam or void formation during deposition.

[0141] To provide context, manipulating the intrinsic material properties of the plug fill in contact with the pins can induce stress within the channel. According to one or more embodiments, by tuning the composition, deposition, and post-treatment conditions of the plug filler material, the stress in the channel is modulated to be beneficial to both NMOS and PMOS transistors. In addition, these plugs may exist deeper within the pin substrate compared to other conventional stressor techniques, such as epitaxial sources or drains. The properties of the plug filler to achieve this effect also eliminate seams or voids during deposition and mitigate specific defect modes during the process.

[0142] To provide additional context, there is currently no intentional stress engineering for gate (poly) plugs. Unfortunately, stress enhancement from traditional stressors, such as epitaxial sources or drains, dummy poly gate removal, and stress liners, tends to decrease as device pitches are reduced. By addressing one or more of the above issues, according to one or more embodiments of the present disclosure, additional stress sources are incorporated within the transistor structure. Another possible advantage of this process may be the removal of seams or voids within the plug, which may be conventional in other chemical vapor deposition methods.

[0143] FIGS. 19a and 19b illustrate cross-sectional views of various operations in a method for selecting pin end stressor positions at the ends of a pin having a wide cut, as part of a pin trim last process as described above, according to one embodiment of the present disclosure.

[0144] Referring to FIG. 19a, a pin (1900), such as a silicon pin, is formed on a substrate (1902) and may be continuous with the substrate (1902). The pin (1900) has pin ends or wide pin cuts (1904) that may be formed during pin patterning, for example, as in the pin trim last approach described above. Active gate electrode locations (1906) and dummy gate electrode locations (1908) are formed on the pin (1900) and, for illustrative purposes, are shown slightly in front of the pin (1900) so that the pin (1900) is in the background, where dashed lines indicate areas covered so as not to be seen from the front. It should be noted that epitaxial source or drain regions (1910) are also shown at locations of the pin (1900) between the gate locations (1906 and 1908). In addition, an interlayer dielectric material (1912) is included in the locations of the pin (1900) between the gate locations (1906 and 1908).

[0145] Referring to FIG. 19b, gate placeholder structures or dummy gate locations (1908) are removed to expose pin ends or wide pin cuts (1904). The removal creates openings (1920) in which dielectric plugs, such as pin end stressor dielectric plugs, can ultimately be formed.

[0146] FIGS. 20a and 20b illustrate cross-sectional views of various operations in a method for selecting pin end stressor locations at the ends of a pin having a local cut, as part of a pin trim isolation process as described above, according to one embodiment of the present disclosure.

[0147] Referring to FIG. 20a, a pin (2000), such as a silicon pin, is formed on a substrate (2002) and may be continuous with the substrate (2002). The pin (2000) has a local cut (2004), where a portion of the pin (2000) is removed using a pin trim isolation approach, such as the dummy gate being removed and the pin being etched at a local location, as previously described. Active gate electrode locations (2006) and dummy gate electrode locations (2008) are formed on the pin (2000) and, for illustrative purposes, are shown slightly in front of the pin (2000) so that the pin (2000) is in the background, where dashed lines indicate areas covered so as not to be seen from the front. It should be noted that epitaxial source or drain regions (2010) are also shown at locations of the pin (2000) between the gate locations (2006 and 2008). In addition, an interlayer dielectric material (2012) is included in the locations of the pin (2000) between the gate locations (2006 and 2008).

[0148] Referring to FIG. 20b, the gate placeholder structure or dummy gate electrode location (2008) is removed to expose pin ends having a local cut (2004). The removal creates an opening (2020) in which a dielectric plug, such as a pin end stressor dielectric plug, can ultimately be formed.

[0149] FIGS. 21a through 21m illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having differentiated pin end dielectric plugs according to one embodiment of the present disclosure.

[0150] Referring to FIG. 21a, the start structure (2100) includes an NMOS region and a PMOS region. The NMOS region of the start structure (2100) includes a first pin (2102), such as a first silicon pin, which is formed on a substrate (2104) and may be continuous with the substrate (2104). The first pin (2102) has pin ends (2106) that may be formed from local or wide pin cuts. A first active gate electrode location (2108) and first dummy gate electrode locations (2110) are formed above the first pin (2102) and, for illustrative purposes, are shown slightly in front of the first pin (2102) so that the first pin (2102) is in the background, where dashed lines indicate areas covered so as not to be seen from the front. Epitaxial N-type source or drain regions (2112), such as epitaxial silicon sources of drain structures, are also shown at the locations of the first pin (2102) between the gate locations (2108 and 2110). In addition, an interlayer dielectric material (2114) is included at the locations of the first pin (2102) between the gate locations (2108 and 2110).

[0151] The PMOS region of the starting structure (2100) includes a second pin (2122), such as a second silicon pin, which is formed on the substrate (2104) and may be continuous with the substrate (2104). The second pin (2122) has pin ends (2126) that may be formed from local or wide pin cuts. A second active gate electrode location (2128) and second dummy gate electrode locations (2130) are formed above the second pin (2122) and, for illustrative purposes, are shown slightly in front of the second pin (2122) so that the second pin (2122) is in the background, where dashed lines indicate areas covered so as not to be seen from the front. Epitaxial P-type source or drain regions (2132), such as an epitaxial silicon germanium source of drain structures, are also shown at the locations of the second pin (2122) between the gate locations (2128 and 2130). In addition, an interlayer dielectric material (2134) is included at the locations of the second pin (2122) between the gate locations (2128 and 2130).

[0152] Referring to FIG. 21b, the first and second dummy gate electrodes at the respective locations (2110 and 2130) are removed. Upon removal, the pin ends (2106) of the first pin (2102) and the pin ends (2126) of the second pin (2122) are exposed. The removal also creates, respectively, openings (2116 and 2136) in which dielectric plugs, such as pin end stressor dielectric plugs, can ultimately be formed.

[0153] Referring to FIG. 21c, a material liner (2140) is formed conformally with the structure of FIG. 21b. In one embodiment, the material liner comprises silicon and nitrogen, such as a silicon nitride material liner.

[0154] Referring to FIG. 21d, a protective crown layer (2142), such as a metal nitride layer, is formed on the structure of FIG. 21c.

[0155] Referring to FIG. 21e, a hard mask material (2144), such as a carbon-based hard mask material, is formed on top of the structure of FIG. 21d. A lithography mask or mask stack (2146) is formed on top of the hard mask material (2144).

[0156] Referring to FIG. 21f, portions of the hard mask material (2144) and portions of the protective crown layer (2142) within the PMOS region are removed from the structure of FIG. 21e. The lithography mask or mask stack (2146) is also removed.

[0157] Referring to FIG. 21g, a second material liner (2148) is formed conformally with the structure of FIG. 21f. In one embodiment, the second material liner comprises silicon and nitrogen, such as the second silicon nitride material liner. In one embodiment, the second material liner (2148) has different stress states to control stress in the exposed plugs.

[0158] Referring to FIG. 21h, a second hard mask material (2150), such as a second carbon-based hard mask material, is formed on the upper side of the structure of FIG. 21g and then reset within the openings (2136) of the PMOS region of the structure.

[0159] Referring to FIG. 21i, the second material liner (2148) is etched from the structure of FIG. 21h to remove the second material liner (2148) from the NMOS region and to reset the second material liner (2148) from the PMOS region of the structure.

[0160] Referring to FIG. 21j, the hard mask material (2144), the protective crown layer (2142), and the second hard mask material (2150) are removed from the structure of FIG. 21i. The removal leaves two different filling structures for each opening (2116) compared to the openings (2136).

[0161] Referring to FIG. 21k, an insulating filler material (2152) is formed and flattened in the openings (2116 and 2136) of the structure of FIG. 21j. In one embodiment, the insulating filler material (2152) is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

[0162] Referring to FIG. 21, the insulating filler material (2152) is recessed within the openings (2116 and 2136) of the structure of FIG. 21k to form the recessed insulating filler material (2154). In one embodiment, a steam oxidation process is performed as part of or after the recess process to cure the recessed insulating filler material (2154). In one such embodiment, the recessed insulating filler material (2154) shrinks to induce tensile stress on the pins (2102 and 2122). However, there is relatively less tensile stress-inducing material in the PMOS region than in the NMOS region.

[0163] Referring to FIG. 21m, a third material liner (2156) is located on top of the structure of FIG. 21l. In one embodiment, the third material liner (2156) comprises silicon and nitrogen, such as the third silicon nitride material liner. In one embodiment, the third material liner (2156) prevents the reset insulating filler material (2154) from being etched out during subsequent source or drain contact etching.

[0164] FIGS. 22a to 22d illustrate cross-sectional views of exemplary structures of PMOS pin end stressor dielectric plugs according to one embodiment of the present disclosure.

[0165] Referring to FIG. 22a, an opening (2136) on the PMOS region of the structure (2100) includes a material liner (2140) along the sidewalls of the opening (2136). A second material liner (2148) is conformal to the lower portion of the material liner (2140) but is recessed relative to the upper portion of the material liner (2140). The recessed insulating filler material (2154) is within the second material liner (2148) and has an upper surface that is coplanar with the upper surface of the second material liner (2148). A third material liner (2156) is within the upper portion of the material liner (2140) and is on the upper surface of the insulating filler material (2154) and on the upper surface of the second material liner (2148). The third material liner (2156) has a core (2157) as an artifact of the deposition process used to form the third material liner (2156), for example.

[0166] Referring to FIG. 22b, an opening (2136) on the PMOS region of the structure (2100) includes a material liner (2140) along the sidewalls of the opening (2136). A second material liner (2148) is conformal to the lower portion of the material liner (2140) but is recessed relative to the upper portion of the material liner (2140). The recessed insulating filler material (2154) is within the second material liner (2148) and has an upper surface that is coplanar with the upper surface of the second material liner (2148). A third material liner (2156) is within the upper portion of the material liner (2140) and is on the upper surface of the insulating filler material (2154) and on the upper surface of the second material liner (2148). The third material liner (2156) does not have a seam.

[0167] Referring to FIG. 22c, an opening (2136) on the PMOS region of the structure (2100) includes a material liner (2140) along the sidewalls of the opening (2136). A second material liner (2148) is conformal to the lower portion of the material liner (2140) but is recessed relative to the upper portion of the material liner (2140). The recessed insulating filler material (2154) is within the second material liner (2148) and above the second material liner (2148), and has an upper surface above the upper surface of the second material liner (2148). A third material liner (2156) is within the upper portion of the material liner (2140) and on the upper surface of the insulating filler material (2154). Although the third material liner (2156) is depicted as not having a core, in other embodiments, the third material liner (2156) has a core.

[0168] Referring to FIG. 22d, an opening (2136) on the PMOS region of the structure (2100) includes a material liner (2140) along the sidewalls of the opening (2136). A second material liner (2148) is conformal to the lower portion of the material liner (2140) but is recessed relative to the upper portion of the material liner (2140). The recessed insulating filler material (2154) is within the second material liner (2148) and has an upper surface that is recessed below the upper surface of the second material liner (2148). A third material liner (2156) is within the upper portion of the material liner (2140) and is on the upper surface of the insulating filler material (2154) and on the upper surface of the second material liner (2148). Although the third material liner (2156) is depicted as not having a core, in other embodiments, the third material liner (2156) has a core.

[0169] Referring collectively to FIGS. 19a, 19b, FIGS. 20a, 20b, FIGS. 21a through 21m, and FIGS. 22a through 22d, according to one embodiment of the present disclosure, an integrated circuit structure comprises a pin, such as silicon, and the pin has a top and side walls. The top has the longest dimension along one direction. A first isolation structure is located above a first end of the pin. A gate structure comprises a gate electrode located above the top of the pin's region and laterally adjacent to the side walls of the pin's region. The gate structure is spaced apart from the first isolation structure along that direction. A second isolation structure is located above a second end of the pin, and the second end is on the opposite side of the first end. The second isolation structure is spaced apart from the gate structure along that direction. Both the first isolation structure and the second isolation structure include a first dielectric material (e.g., material liner (2140)) that laterally surrounds a recessed second dielectric material (e.g., second material liner (2148)) that is distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least one portion of a third dielectric material (e.g., recessed insulating filler material (2154)) that is different from the first and second dielectric materials.

[0170] In one embodiment, both the first isolation structure and the second isolation structure further comprise a fourth dielectric material (e.g., a third material liner (2156)) laterally surrounded by an upper portion of the first dielectric material, and the fourth dielectric material is on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a roughly vertical central core. In another such embodiment, the fourth dielectric material does not have a core.

[0171] In one embodiment, the third dielectric material has an upper surface that is coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface below the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface above the upper surface of the second dielectric material, and the third dielectric material is additionally located above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the pin. In one such embodiment, the gate electrode is a P-type gate electrode.

[0172] In one embodiment, the first isolation structure has a width along its direction, the gate structure has a width along its direction, and the second isolation structure has a width along its direction. In one such embodiment, the center of the gate structure is spaced from the center of the first isolation structure by a pitch along its direction, and the center of the second isolation structure is spaced from the center of the gate structure by a pitch along its direction. In one embodiment, both the first and second isolation structures are located within corresponding trenches within the interlayer dielectric layer.

[0173] In one such embodiment, a first source or drain region is located between a gate structure and a first isolation structure. A second source or drain region is located between a gate structure and a second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further comprises a high-k dielectric layer between the gate electrode and the pin and along the sidewalls of the gate electrode.

[0174] In another embodiment, the depth of individual dielectric plugs may be varied within a semiconductor structure or within an architecture formed on a common substrate. As an example, FIG. 23a illustrates a cross-sectional view of another semiconductor structure having pin end stress-inducing features according to another embodiment of the present disclosure. Referring to FIG. 23a, a shallow dielectric plug (2308A) is included together with a pair of deep dielectric plugs (2308B and 2308C). In one such embodiment, as illustrated, the shallow dielectric plug (2308A) is at a depth approximately equal to the depth of the semiconductor pin (2302) within the substrate (2304), whereas the pair of deep dielectric plugs (2308B and 2308C) are at a depth lower than the depth of the semiconductor pin (2302) within the substrate (2304).

[0175] Referring again to FIG. 23a, this arrangement can enable stress amplification for pin trim isolation (FTI) devices in trenches etched deeper into the substrate (2304) to provide isolation between adjacent pins (2302). This approach can be implemented to increase the density of transistors on the chip. In one embodiment, the stress effect induced on the transistors due to plug charging is amplified in FTI transistors because stress transfer occurs at the pins, at the substrate, or quite below the transistors.

[0176] In another embodiment, the width or amount of the tensile stress-induced oxide layer included in the dielectric plug may vary within the semiconductor structure or within an architecture formed on a common substrate, for example, depending on whether the device is a PMOS device or an NMOS device. As an example, FIG. 23b illustrates a cross-sectional view of another semiconductor structure having pin end stress-induced features according to another embodiment of the present disclosure. Referring to FIG. 23b, in a particular embodiment, NMOS devices include a relatively larger amount of the tensile stress-induced oxide layer (2350) than the corresponding PMOS devices.

[0177] Referring again to FIG. 23b, in one embodiment, the plug filler is differentiated to induce appropriate stress in the NMOS and PMOS devices. For example, the NMOS plugs (2308D and 2308E) have a larger volume and a wider tensile stress-inducing oxide layer (2350) than the PMOS plugs (2308F and 2308G). The plug filler can be patterned to induce different stresses in the NMOS and PMOS devices. For example, lithographic patterning can be used to open up the PMOS devices (e.g., to widen dielectric plug trenches for the PMOS devices), at which point different filler options can be performed to differentiate the plug filler in the NMOS devices and PMOS devices. In an exemplary embodiment, reducing the volume of the fluid oxide within the plug on the PMOS devices can reduce the induced tensile stress. In one such embodiment, compressive stress may be dominant, for example, by applying compressive stress to the source and drain regions. In other embodiments, the use of different plug liners or different filler materials provides tunable stress control.

[0178] As previously described, it should be recognized that polyplug stress effects can be beneficial to both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to one embodiment of the present disclosure, a semiconductor pin is a uniaxially stressed semiconductor pin. A uniaxially stressed semiconductor pin may be uniaxially stressed as tensile stress or as compressive stress. For example, according to one or more embodiments of the present disclosure, FIG. 24a illustrates an angled view of a pin having tensile uniaxial stress, whereas FIG. 24b illustrates an angled view of a pin having compressive uniaxial stress.

[0179] Referring to FIG. 24a, the semiconductor pin (2400) has a discrete channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed on both sides of the channel region (C) in the semiconductor pin (2400). The discrete channel region of the semiconductor pin (2400) has a direction of current flow from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing away from each other toward the ends (2402 and 2404)).

[0180] Referring to FIG. 24b, the semiconductor pin (2450) has a separate channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed on both sides of the channel region (C) in the semiconductor pin (2450). The separate channel regions of the semiconductor pin (2450) have a direction of current flow from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing toward each other from the ends (2452 and 2454). Accordingly, the embodiments described herein can be implemented to improve transistor mobility and drive current, thereby enabling circuits and chips with faster performance.

[0181] In another embodiment, there may be a relationship between the locations where gate line cuts (poly cuts) are made and the locations where pin trim isolation (FTI) local pin cuts are made. In one embodiment, FTI local pin cuts are made only at the locations where poly cuts are made. However, in one such embodiment, an FTI cut is not necessarily made at every location where a poly cut is made.

[0182] FIGS. 25a and FIGS. 25b illustrate plan views illustrating various operations in a method for patterning pins having a single gate gap to form a local isolation structure at selected gate line cut positions according to one embodiment of the present disclosure.

[0183] Referring to FIG. 25a, a method for manufacturing an integrated circuit structure comprises the step of forming a plurality of pins (2502)—each of the plurality of pins (2502) having the longest dimension along a first direction (2504). A plurality of gate structures (2506) are positioned above the plurality of pins (2502), and each of the gate structures (2506) has the longest dimension along a second direction (2508) which is orthogonal to the first direction (2504). In one embodiment, the gate structures (2506) are sacrificial or dummy gate lines, for example, made of polycrystalline silicon. In one embodiment, the plurality of pins (2502) are silicon pins and are continuous with a portion of the silicon substrate underneath.

[0184] Referring again to FIG. 25a, a dielectric material structure (2510) is formed between adjacent gate structures of a plurality of gate structures (2506). Parts (2512 and 2513) of two of the plurality of gate structures (2506) are removed to expose parts of each of the plurality of pins (2502). In one embodiment, removing parts (2512 and 2513) of two of the gate structures (2506) involves using a lithography window wider than the width of each of the parts (2512 and 2513) of the gate structures (2506). The exposed part of each of the plurality of pins (2502) at location (2512) is removed to form a cut area (2520). In one embodiment, the exposed part of each of the plurality of pins (2502) is removed using a dry or plasma etching process. However, the exposed portion of each of the multiple pins (2502) at location (2513) is masked so as not to be removed. In one embodiment, the area (2512 / 2520) represents both a poly cut and an FTI local pin cut. However, location (2513) represents only a poly cut.

[0185] Referring to FIG. 25b, the locations of the poly cut and FTI local pin cut (2512 / 2520) and the location of the poly cut (2513) are filled with insulating structures (2530), such as dielectric plugs. Exemplary insulating structures or "poly cut" or "plug" structures are described below.

[0186] FIGS. 26a through 26c illustrate cross-sectional views of various possibilities for dielectric plugs for poly-cut and FTI local pin-cut locations and poly-cut-only locations for various regions of the structure of FIG. 25b according to one embodiment of the present disclosure.

[0187] Referring to FIG. 26a, a cross-sectional view of a portion (2600A) of a dielectric plug (2530) at a position (2513) along the aa' axis of the structure of FIG. 25b is shown. The portion (2600A) of the dielectric plug (2530) is shown on an uncut pin (2502) and between dielectric material structures (2510).

[0188] Referring to FIG. 26b, a cross-sectional view of a portion (2600B) of a dielectric plug (2530) at a position (2512) along the bb' axis of the structure of FIG. 25b is shown. The portion (2600B) of the dielectric plug (2530) is shown on a cut pin position (2520) and between dielectric material structures (2510).

[0189] Referring to FIG. 26c, a cross-sectional view of a portion (2600C) of a dielectric plug (2530) at a position (2512) along the cc' axis of the structure of FIG. 25b is shown. The portion (2600C) of the dielectric plug (2530) is shown between the pins (2502) and between the dielectric material structures (2510) on the trench isolation structure (2602). In one embodiment—the examples thereof are described above—the trench isolation structure (2602) comprises a first insulating layer (2602A), a second insulating layer (2602B), and an insulating filler material (2602C) on the second insulating layer (2602B).

[0190] Referring collectively to FIGS. 25a, 25b and FIGS. 26a through 26c, according to one embodiment of the present disclosure, a method for manufacturing an integrated circuit structure comprises the step of forming a plurality of pins—individuals of the plurality of pins along a first direction. A plurality of gate structures are formed above the plurality of pins, and individuals of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent gate structures of the plurality of gate structures. A portion of a first gate structure among the plurality of gate structures is removed to expose a first portion of each of the plurality of pins. A portion of a second gate structure among the plurality of gate structures is removed to expose a second portion of each of the plurality of pins. The exposed first portion of each of the plurality of pins is removed, but the exposed second portion of each of the plurality of pins is not removed. A first insulating structure is formed at the location of the removed first portion of the plurality of pins. A second insulating structure is formed at the location of the removed portion of the second gate structure among the plurality of gate structures.

[0191] In one embodiment, removing portions of the first and second gate structures among the plurality of gate structures involves using a lithography window wider than the width of each portion of the first and second gate structures among the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of pins involves etching to a depth smaller than the height of the plurality of pins. In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of pins. In one embodiment, the plurality of pins comprises silicon and is continuous with a portion of the silicon substrate.

[0192] Referring collectively to FIGS. 16a, 25a, 25b and FIGS. 26a through 26c, according to another embodiment of the present disclosure, an integrated circuit structure comprises a fin comprising silicon, and the fin has the longest dimension along a first direction. An isolation structure is located above the upper portion of the fin, and the isolation structure has a center along the first direction. A first gate structure is located above the upper portion of the fin, and the first gate structure has the longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced from the center of the isolation structure by a pitch along the first direction. A second gate structure is located above the upper portion of the fin, and the second gate structure has the longest dimension along the second direction. The center of the second gate structure is spaced from the center of the first gate structure by a pitch along the first direction. A third gate structure is located above the upper portion of the fin on the side opposite to the isolation structure from the first and second gate structures, and the third gate structure has the longest dimension along the second direction. The center of the third gate structure is spaced from the center of the isolation structure by a pitch along the first direction.

[0193] In one embodiment, the first gate structure, the second gate structure, and the third gate structure each include a gate electrode on the sidewalls of the high-k gate dielectric layer and between the sidewalls. In one such embodiment, the first gate structure, the second gate structure, and the third gate structure each further include an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer.

[0194] In one embodiment, a first epitaxial semiconductor region is located on the upper portion of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is located on the upper portion of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is located on the upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0195] Referring collectively to FIGS. 16a, FIGS. 25a, FIGS. 25b, and FIGS. 26a through 26c, according to another embodiment of the present disclosure, an integrated circuit structure comprises a shallow trench isolation (STI) structure between a pair of semiconductor pins, wherein the STI structure has the longest dimension along a first direction. The isolation structure is on the STI structure, and the isolation structure has a center along the first direction. A first gate structure is on the STI structure, and the first gate structure has the longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced from the center of the isolation structure by a pitch along the first direction. A second gate structure is on the STI structure, and the second gate structure has the longest dimension along the second direction. The center of the second gate structure is spaced from the center of the first gate structure by a pitch along the first direction. The third gate structure is on the STI structure opposite to the side of the isolation structure from the first and second gate structures, and the third gate structure has the longest dimension along the second direction. The center of the third gate structure is spaced from the center of the isolation structure by a pitch along the first direction.

[0196] In one embodiment, the first gate structure, the second gate structure, and the third gate structure each include a gate electrode on the sidewalls of the high-k gate dielectric layer and between the sidewalls. In one such embodiment, the first gate structure, the second gate structure, and the third gate structure each further include an insulating cap on the gate electrode and on the sidewalls of the high-k gate dielectric layer. In one embodiment, a pair of semiconductor pins are a pair of silicon pins.

[0197] In another embodiment, insulating structures or dielectric plugs used to fill the cut locations, whether they are both poly cuts and FTI local pin cuts or only poly cuts, may extend laterally into or even beyond the dielectric spacers of the corresponding cut gate lines.

[0198] In a first example in which the trench contact shape is not affected by the poly-cut dielectric plug, FIG. 27a illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut by a dielectric plug extending into the dielectric spacers of the gate line, according to one embodiment of the present disclosure.

[0199] Referring to FIG. 27a, the integrated circuit structure (2700A) includes a first silicon pin (2702) having the longest dimension along the first direction (2703). A second silicon pin (2704) has the longest dimension along the first direction (2703). An insulating material (2706) is present between the first silicon pin (2702) and the second silicon pin (2704). A gate line (2708) is located above the first silicon pin (2702) and above the second silicon pin (2704) along the second direction (2709), and the second direction (2709) is orthogonal to the first direction (2703). The gate line (2708) has a first side (2708A) and a second side (2708B), and has a first end (2708C) and a second end (2708D). The gate line (2708) has a discontinuity (2710) between the first end (2708C) and the second end (2708D) of the gate line (2708) above the insulating material (2706). The discontinuity (2710) is filled by a dielectric plug (2712).

[0200] The trench contact (2714) is located above the first silicon pin (2702) and above the second silicon pin (2704) along the second direction (2709) on the first side (2708A) of the gate line (2708). The trench contact (2714) is continuous across the insulating material (2706) at a location (2715) laterally adjacent to the dielectric plug (2712). The dielectric spacer (2716) is located laterally between the trench contact (2714) and the first side (2708A) of the gate line (2708). The dielectric spacer (2716) is continuous along the first side (2708A) of the gate line (2708) and the dielectric plug (2712). The dielectric spacer (2716) has a width (W2) laterally adjacent to the dielectric plug (2712) that is thinner than the width (W1) laterally adjacent to the first side (2708A) of the gate line (2708).

[0201] In one embodiment, the second trench contact (2718) is located above the first silicon pin (2702) and above the second silicon pin (2704) along the second direction (2709) on the second side (2708B) of the gate line (2708). The second trench contact (2718) is continuous across the insulating material (2706) at a location (2719) laterally adjacent to the dielectric plug (2712). In one such embodiment, the second dielectric spacer (2720) is located laterally between the second trench contact (2718) and the second side (2708B) of the gate line (2708). The second dielectric spacer (2720) is continuous along the second side (2708B) of the gate line (2708) and the dielectric plug (2712). The second dielectric spacer has a width laterally adjacent to the dielectric plug (2712) that is thinner than the width laterally adjacent to the second side (2708B) of the gate line (2708).

[0202] In one embodiment, the gate line (2708) includes a high-k gate dielectric layer (2722), a gate electrode (2724), and a dielectric cap layer (2726). In one embodiment, the dielectric plug (2712) includes the same material as the dielectric spacer (2714) but is distinct from the dielectric spacer (2714). In one embodiment, the dielectric plug (2712) includes a different material from the dielectric spacer (2714).

[0203] In a second example where the trench contact shape is affected by a poly-cut dielectric plug, FIG. 27b illustrates a plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut by a dielectric plug that extends beyond the dielectric spacers of the gate line, according to another embodiment of the present disclosure.

[0204] Referring to FIG. 27b, the integrated circuit structure (2700B) includes a first silicon pin (2752) having the longest dimension along the first direction (2753). A second silicon pin (2754) has the longest dimension along the first direction (2753). An insulating material (2756) is located between the first silicon pin (2752) and the second silicon pin (2754). A gate line (2758) is located above the first silicon pin (2752) and above the second silicon pin (2754) along the second direction (2759), and the second direction (2759) is orthogonal to the first direction (2753). The gate line (2758) has a first side (2758A) and a second side (2758B), and has a first end (2758C) and a second end (2758D). The gate line (2758) has a discontinuity (2760) between the first end (2758C) and the second end (2758D) of the gate line (2758) above the insulating material (2756). The discontinuity (2760) is filled by a dielectric plug (2762).

[0205] The trench contact (2764) is located along the second direction (2759) from the first side (2758A) of the gate line (2758) above the first silicon pin (2752) and above the second silicon pin (2754). The trench contact (2764) is continuous across the insulating material (2756) at a location (2765) laterally adjacent to the dielectric plug (2762). The dielectric spacer (2766) is located laterally between the trench contact (2764) and the first side (2758A) of the gate line (2758). Since the dielectric spacer (2766) is along the first side (2758A) of the gate line (2758) but not along the dielectric plug (2762), it results in a discontinuous dielectric spacer (2766). The trench contact (2764) has a width (W1) laterally adjacent to the dielectric plug (2762) that is thinner than the width (W2) laterally adjacent to the dielectric spacer (2766).

[0206] In one embodiment, the second trench contact (2768) is located above the first silicon pin (2752) and above the second silicon pin (2754) along the second direction (2759) on the second side (2758B) of the gate line (2758). The second trench contact (2768) is continuous across the insulating material (2756) at a location (2769) laterally adjacent to the dielectric plug (2762). In one such embodiment, the second dielectric spacer (2770) is located laterally between the second trench contact (2768) and the second side (2758B) of the gate line (2758). The second dielectric spacer (2770) follows the second side (2508B) of the gate line (2758) but does not follow the dielectric plug (2762), resulting in a discontinuous dielectric spacer (2770). The second trench contact (2768) is thinner in width laterally adjacent to the dielectric plug (2762) than in width laterally adjacent to the second dielectric spacer (2770).

[0207] In one embodiment, the gate line (2758) includes a high-k gate dielectric layer (2772), a gate electrode (2774), and a dielectric cap layer (2776). In one embodiment, the dielectric plug (2762) includes the same material as the dielectric spacer (2764) but is distinct from the dielectric spacer (2764). In one embodiment, the dielectric plug (2762) includes a different material from the dielectric spacer (2764).

[0208] In a third example in which the dielectric plug for the poly cut position is tapered from the top of the plug to the bottom of the plug, FIGS. 28a through 28f illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having a gate line cut by a dielectric plug having an upper portion extending beyond the dielectric spacers of the gate line and a lower portion extending into the dielectric spacers of the gate line, according to another embodiment of the present disclosure.

[0209] Referring to FIG. 28a, a plurality of gate lines (2802) are formed on a structure (2804), such as on a trench isolation structure between semiconductor pins. In one embodiment, each of the gate lines (2802) is a sacrificial or dummy gate line having, for example, a dummy gate electrode (2806) and a dielectric cap (2808). Parts of these sacrificial or dummy gate lines may be replaced later in a replacement gate process, for example, after the formation of the dielectric plug described below. Dielectric spacers (2810) are located along the sidewalls of the gate lines (2802). A dielectric material (2812), such as an interlayer dielectric layer, is located between the gate lines (2802). A mask (2814) is formed and lithographically patterned to expose a portion of one of the gate lines (2802).

[0210] Referring to FIG. 28b, with the mask (2814) in place, the central gate line (2802) is removed using an etching process. The mask (2814) is subsequently removed. In one embodiment, the etching process erodes portions of the dielectric spacers (2810) of the removed gate line (2802) to form reduced dielectric spacers (2816). In addition, the upper portions of the dielectric material (2812) exposed by the mask (2814) are eroded in the etching process to form eroded dielectric material portions (2818). In a specific embodiment, residual dummy gate material (2820), such as residual polycrystalline silicon, remains in the structure as an artifact of an incomplete etching process.

[0211] Referring to FIG. 28c, a hard mask (2822) is formed on the upper part of the structure of FIG. 28b. The hard mask (2822) can be conformal to the upper part of the structure of FIG. 28b and, in particular, to the eroded dielectric material parts (2818).

[0212] Referring to FIG. 28d, the residual dummy gate material (2820) is removed using an etching process that may have a chemistry similar to, for example, the etching process used to remove the central gate line among the gate lines (2802). In one embodiment, a hard mask (2822) protects the eroded dielectric material portions (2818) from further erosion during the removal of the residual dummy gate material (2820).

[0213] Referring to FIG. 28e, the hard mask (2822) is removed. In one embodiment, the hard mask (2822) is removed without further erosion of the eroded dielectric material portions (2818) or essentially without further erosion.

[0214] Referring to FIG. 28f, a dielectric plug (2830) is formed within the opening of the structure of FIG. 28e. The upper portion of the dielectric plug (2830) extends over the eroded dielectric material portions (2818), for example, effectively over the original spacers (2810). The lower portion of the dielectric plug (2830) is adjacent to the reduced dielectric spacers (2816), for example, within the effectively original spacers (2810) but not over them. As a result, the dielectric plug (2830) has a tapered profile as shown in FIG. 28f. It should be recognized that the dielectric plug (2830) can be manufactured from the materials and processes previously described for other poly cut or FTI plugs or pin end stressors.

[0215] In another embodiment, portions of a placeholder gate structure or a dummy gate structure may be maintained above trench isolation regions below a permanent gate structure as protection against erosion of the trench isolation regions during the replacement gate process. For example, FIGS. 29a through 29c illustrate plan views and corresponding cross-sectional views of an integrated circuit structure having residual dummy gate material in portions at the bottom of a permanent gate stack according to one embodiment of the present disclosure.

[0216] Referring to FIGS. 29a through 29c, the integrated circuit structure includes a pin (2902), such as a silicon pin, protruding from a semiconductor substrate (2904). The pin (2902) has a lower pin portion (2902B) and an upper pin portion (2902A). The upper pin portion (2902A) has a top (2902C) and side walls (2902D). An isolation structure (2906) surrounds the lower pin portion (2902B). The isolation structure (2906) includes an insulating material (2906C) having a top surface (2907). A semiconductor material (2908) is on a portion of the top surface (2907) of the insulating material (2906C). The semiconductor material (2908) is separated from the pin (2902).

[0217] The gate dielectric layer (2910) is located above the top (2902C) of the upper pin portion (2902A) and laterally adjacent to the sidewalls (2902D) of the upper pin portion (2902A). The gate dielectric layer (2910) is additionally located on the semiconductor material (2908) on the portion of the upper surface (2907) of the insulating material (2906C). An additional gate dielectric layer (2911), such as the oxidized portion of the pin (2902), may be located between the gate dielectric layer (2910) and above the top (2902C) of the upper pin portion (2902A) and laterally adjacent to the sidewalls (2902D) of the upper pin portion (2902A). The gate electrode (2912) is located above the top (2902C) of the upper pin portion (2902A) and above the gate dielectric layer (2910) which is laterally adjacent to the sidewalls (2902D) of the upper pin portion (2902A). The gate electrode (2912) is additionally located above the gate dielectric layer (2910) on the semiconductor material (2908) on a portion of the upper surface (2907) of the insulating material (2906C). A first source or drain region (2916) is adjacent to the first side of the gate electrode (2912), and a second source or drain region (2918) is adjacent to the second side of the gate electrode (2912), with the second side being opposite the first side. In one embodiment—the examples thereof described above—the insulating structure (2906) comprises a first insulating layer (2906A), a second insulating layer (2906B), and an insulating material (2906C).

[0218] In one embodiment, the semiconductor material (2908) on a portion of the top surface (2907) of the insulating material (2906C) is polycrystalline silicon or comprises polycrystalline silicon. In one embodiment, the top surface (2907) of the insulating material (2906C) has a concave depression, as illustrated, and the semiconductor material (2908) is in the concave depression. In one embodiment, the insulating structure (2906) comprises a second insulating material (2906A or 2906B or both 2906A / 2906B) along the bottom and side walls of the insulating material (2906C). In one such embodiment, as illustrated, the portion of the second insulating material (2906A or 2906B or both 2906A / 2906B) along the side walls of the insulating material (2906C) has a top surface above the top surface of the insulating material (2906C). In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A / 2906B) is above or coplanar with the top surface of the semiconductor material (2908).

[0219] In one embodiment, the semiconductor material (2908) on the upper surface (2907) portion of the insulating material (2906C) does not extend beyond the gate dielectric layer (2910). That is, in terms of a plan view, the location of the semiconductor material (2908) is limited to the area covered by the gate stack (2912 / 2910). In one embodiment, the first dielectric spacer (2920) is along the first side of the gate electrode (2912). The second dielectric spacer (2922) is along the second side of the gate electrode (2912). In one such embodiment, as shown in FIG. 29b, the gate dielectric layer (2910) is further extended along the sidewalls of the first dielectric spacer (2920) and the second dielectric spacer (2922).

[0220] In one embodiment, the gate electrode (2912) comprises a conformal conductive layer (2912A) (e.g., a work function layer). In one such embodiment, the work function layer (2912A) comprises titanium and nitrogen. In another embodiment, the work function layer (2912A) comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode (2912) further comprises a conductive fill metal layer (2912B) above the work function layer (2912A). In one such embodiment, the conductive fill metal layer (2912B) comprises tungsten. In a specific embodiment, the conductive fill metal layer (2912B) comprises 95 atomic percent or more of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, as shown in FIG. 29b, an insulating cap (2924) may be on the gate electrode (2912) and extend over the gate dielectric layer (2910).

[0221] FIGS. 30a through 30d illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having residual dummy gate material in portions of the bottom of a permanent gate stack, according to another embodiment of the present disclosure. A view along a portion of the aa' axis of the structure of FIG. 29c is shown.

[0222] Referring to FIG. 30a, a method for manufacturing an integrated circuit structure includes the step of forming a pin (3000) from a semiconductor substrate (3002). The pin (3000) has a lower pin portion (3000A) and an upper pin portion (3000B). The upper pin portion (3000B) has a top (3000C) and side walls (3000D). An isolation structure (3004) surrounds the lower pin portion (3000A). The isolation structure (3004) comprises an insulating material (3004C) having a top surface (3005). A placeholder gate electrode (3006) is positioned above the top (3000C) of the upper pin portion (3000B) and laterally adjacent to the side walls (3000D) of the upper pin portion (3000B). The placeholder gate electrode (3006) comprises a semiconductor material.

[0223] Although not illustrated in view of FIG. 30a (however, locations thereof are illustrated in FIG. 29c), a first source or drain region may be formed adjacent to a first side of the placeholder gate electrode (3006), and a second source or drain region may be formed adjacent to a second side of the placeholder gate electrode (3006), with the second side being opposite to the first side. In addition, gate dielectric spacers may be formed along the sidewalls of the placeholder gate electrode (3006), and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode (3006).

[0224] In one embodiment, the placeholder gate electrode (3006) is polycrystalline silicon or comprises polycrystalline silicon. In one embodiment, as illustrated, the top surface (3005) of the insulating material (3004C) of the isolation structure (3004) has a concave depression. A portion of the placeholder gate electrode (3006) is in the concave depression. In one embodiment, as illustrated, the isolation structure (3004) comprises a second insulating material (3004A or 3004B or both 3004A and 3004B) along the bottom and sidewalls of the insulating material (3004C). In one such embodiment, a portion of the second insulating material (3004A or 3004B or both 3004A and 3004B) along the sidewalls of the insulating material (3004C) has a top surface above at least one portion of the top surface (3005) of the insulating material (3004C). In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A and 3004B) is on the bottom surface of one part of the placeholder gate electrode (3006).

[0225] Referring to FIG. 30b, the placeholder gate electrode (3006) is etched from the top (3000C) and sidewalls (3000D) of the upper pin portion (3000B), for example, along the direction (3008) of FIG. 30a. The etching process may be referred to as a replacement gate process. In one embodiment, the etching or replacement gate process is incomplete and leaves a portion (3012) of the placeholder gate electrode (3006) on at least one portion of the top surface (3005) of the insulating material (3004C) of the isolation structure (3004).

[0226] Referring to both FIG. 30a and FIG. 30b, in one embodiment, as illustrated, the oxidized portion (3010) of the upper pin portion (3000B) formed prior to forming the placeholder gate electrode (3006) is retained during the etching process. However, in another embodiment, the placeholder gate dielectric layer is formed prior to forming the placeholder gate electrode (3006), and the placeholder gate dielectric layer is removed after etching the placeholder gate electrode.

[0227] Referring to FIG. 30c, the gate dielectric layer (3014) is formed above the top (3000C) of the upper pin portion (3000B) and laterally adjacent to the sidewalls (3000D) of the upper pin portion (3000B). In one embodiment, as illustrated, the gate dielectric layer (3014) is formed on the oxidized portion (3010) of the upper pin portion (3000B) above the top (3000C) of the upper pin portion (3000B) and laterally adjacent to the sidewalls (3000D) of the upper pin portion (3000B). In another embodiment, when the oxidized portion (3010) of the upper pin portion (3000B) is removed following the etching of the placeholder gate electrode, the gate dielectric layer (3014) is formed directly above the upper pin portion (3000B) above the top (3000C) of the upper pin portion (3000B) and laterally adjacent to the sidewalls (3000D) of the upper pin portion (3000B). In either case, in one embodiment, the gate dielectric layer (3014) is additionally formed on the portion (3012) of the placeholder gate electrode (3006) on the portion of the top surface (3005) of the insulating material (3004C) of the isolation structure (3004).

[0228] Referring to FIG. 30d, a permanent gate electrode (3016) is formed above the top (3000C) of the upper pin portion (3000B) and above the gate dielectric layer (3014) which is laterally adjacent to the sidewalls (3000D) of the upper pin portion (3000B). The permanent gate electrode (3016) is additionally located above the gate dielectric layer (3014) on the portion (3012) of the placeholder gate electrode (3006) on the portion of the upper surface (3005) of the insulating material (3004C).

[0229] In one embodiment, the step of forming a permanent gate electrode (3016) includes the step of forming a work function layer (3016A). In one such embodiment, the work function layer (3016A) comprises titanium and nitrogen. In another such embodiment, the work function layer (3016A) comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the step of forming a permanent gate electrode (3016) further includes the step of forming a conductive filling metal layer (3016B) on top of the work function layer (3016A). In one such embodiment, the step of forming the conductive filling metal layer (3016B) includes the step of forming a tungsten-containing film with a tungsten hexafluoride (WF6) precursor using atomic layer deposition (ALD). In one embodiment, an insulating gate cap layer (3018) is formed on the permanent gate electrode (3016).

[0230] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer in a gate dielectric structure for a gate electrode. In other embodiments, a partially or wholly crystalline high-k layer is included in a gate dielectric structure for a gate electrode. In one embodiment in which a partially or wholly crystalline high-k layer is included, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment in which a partially or wholly crystalline high-k layer is included, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0231] In one embodiment, approaches to increase the charge within the device channel and improve sub-threshold behavior by adopting ferroelectric or antiferroelectric gate oxides are described herein. Ferroelectric and antiferroelectric gate oxides can increase the channel charge for higher currents and also enable more rapid turn-on behavior.

[0232] To provide context, hafnium or zirconium (Hf or Zr)-based ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT), and thus can be compatible with highly scaled logic technologies. There are two characteristics of FE or AFE materials that can improve the performance of logic transistors: (1) higher charge within the channel achieved by FE or AFE polarization and (2) more rapid turn-on behavior due to rapid FE or AFE transition. These characteristics can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0233] FIG. 31a illustrates a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to one embodiment of the present disclosure.

[0234] Referring to FIG. 31a, an integrated circuit structure (3100) includes a gate structure (3102) on a substrate (3104). In one embodiment, the gate structure (3102) is on or above a semiconductor channel structure (3106) comprising a single-crystal material, such as single-crystal silicon. The gate structure (3102) includes a gate dielectric on the semiconductor channel structure (3106) and a gate electrode on the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer (3102A). The gate electrode has a conductive layer (3102B) on the ferroelectric or antiferroelectric polycrystalline material layer (3102A). The conductive layer (3102B) may include a metal and may be a templating layer that enhances the crystallization of a barrier layer, a work function layer, or FE or AFE layers. The gate charge layer or layer(s) (3102C) is on or above the conductive layer (3102B). The source region (3108) and the drain region (3110) are on opposite sides of the gate structure (3102). Source or drain contacts (3112) are electrically connected to the source region (3108) and the drain region (3110) at locations (3149) and are spaced apart from the gate structure (3102) by one or both of the interlayer dielectric layer (3114) or the gate dielectric spacers (3116). In the example of FIG. 31a, the source region (3108) and the drain region (3110) are regions of the substrate (3104). In one embodiment, the source or drain contacts (3112) comprise a barrier layer (3112A) and a conductive trench filling material (3112B). In one embodiment, as shown in FIG. 31a, a ferroelectric or antiferroelectric polycrystalline material layer (3102A) extends along dielectric spacers (3116).

[0235] In one embodiment, and as applicable throughout this disclosure, the ferroelectric or antiferroelectric polycrystalline material layer (3102A) is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide containing Zr and Hf in a Zr:Hf ratio where Zr is 50:50 or greater. The ferroelectric effect may increase as the orthorhombic crystallinity increases. In one embodiment, the ferroelectric polycrystalline material layer has an orthorhombic crystallinity of at least 80%.

[0236] In one embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer (3102A) is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide containing Zr and Hf in a Zr:Hf ratio such that Zr is 80:20 or greater and even up to 100% (ZrO2). In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0237] In one embodiment, and as applicable throughout the disclosure, the gate dielectric of the gate stack (3102) further comprises an amorphous dielectric layer (3103), such as a native silicon oxide layer, a high-K dielectric (HfOx, Al2O3, etc.), or a combination of oxide and high-K, between the ferroelectric or antiferroelectric polycrystalline material layer (3102A) and the semiconductor channel structure (3106). In one embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer (3102A) has a thickness in the range of 1 nanometer to 8 nanometers. In one embodiment, and as applicable throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer (3102A) has a crystal grain size in the range of approximately 20 nanometers or more.

[0238] In one embodiment, after the deposition of a ferroelectric or antiferroelectric polycrystalline material layer (3102A) by, for example, atomic layer deposition (ALD), a layer containing a metal (e.g., a layer (3102B) such as 5 to 10 nanometer titanium nitride or tantalum nitride or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer (3102A). Annealing is then performed. In one embodiment, annealing is performed for a duration ranging from 1 millisecond to 30 minutes. In one embodiment, annealing is performed at a temperature ranging from 500 to 1100 °C.

[0239] FIG. 31b illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure.

[0240] Referring to FIG. 31b, the integrated circuit structure (3150) includes a gate structure (3152) on a substrate (3154). In one embodiment, the gate structure (3152) is on or above a semiconductor channel structure (3156) comprising a single-crystal material, such as single-crystal silicon. The gate structure (3152) includes a gate dielectric on the semiconductor channel structure (3156) and a gate electrode on the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer (3152A) and may further include an amorphous oxide layer (3153). The gate electrode has a conductive layer (3152B) on the ferroelectric or antiferroelectric polycrystalline material layer (3152A). The conductive layer (3152B) may include a metal and be a barrier layer or a work function layer. A gate charge layer or layer(s) (3152C) is on or above a conductive layer (3152B). Raised source regions (3158) and raised drain regions (3160), such as regions of semiconductor material different from the semiconductor channel structure (3156), are on both sides of the gate structure (3152). Source or drain contacts (3162) are electrically connected to the source region (3158) and drain region (3160) at locations (3199) and are spaced apart from the gate structure (3152) by one or both of an interlayer dielectric layer (3164) or gate dielectric spacers (3166). In one embodiment, the source or drain contacts (3162) comprise a barrier layer (3162A) and a conductive trench fill material (3162B). In one embodiment, as shown in FIG. 31b, a ferroelectric or antiferroelectric polycrystalline material layer (3152A) extends along dielectric spacers (3166).

[0241] FIG. 32a illustrates a plan view of a plurality of gate lines above a pair of semiconductor pins according to another embodiment of the present disclosure.

[0242] Referring to FIG. 32a, a plurality of active gate lines (3204) are formed above a plurality of semiconductor pins (3200). Dummy gate lines (3206) are located at the ends of the plurality of semiconductor pins (3200). The gaps (3208) between the gate lines (3204 / 3206) are locations where trench contacts can be positioned to provide conductive contacts to source or drain regions, such as source or drain regions (3251, 3252, 3253, and 3254). In one embodiment, a pattern of a plurality of gate lines (3204 / 3206) or a pattern of a plurality of semiconductor pins (3200) is described as a grating structure. In one embodiment, a grating-like pattern includes a plurality of gate lines (3204 / 3206) or a pattern of a plurality of semiconductor pins (3200) spaced apart at a constant pitch and having a constant width, or both.

[0243] FIG. 32b illustrates a cross-sectional view taken along the aa' axis of FIG. 32a according to one embodiment of the present disclosure.

[0244] Referring to FIG. 32b, a plurality of active gate lines (3264) are formed on the semiconductor pin (3262) formed on the substrate (3260). Dummy gate lines (3266) are located at the ends of the semiconductor pin (3262). A dielectric layer (3270) is located outside the dummy gate lines (3266). A trench contact material (3297) is located between the active gate lines (3264) and between the dummy gate lines (3266) and the active gate lines (3264). Embedded source or drain structures (3268) are located within the semiconductor pin (3262) between the active gate lines (3264) and between the dummy gate lines (3266) and the active gate lines (3264).

[0245] Active gate lines (3264) include a gate dielectric structure (3272), a work function gate electrode portion (3274) and a charge gate electrode portion (3276), and a dielectric capping layer (3278). Dielectric spacers (3280) line the sidewalls of the active gate lines (3264) and dummy gate lines (3266). In one embodiment, the gate dielectric structure (3272) includes a ferroelectric or antiferroelectric polycrystalline material layer (3298). In one embodiment, the gate dielectric structure (3272) further includes an amorphous oxide layer (3299).

[0246] In another embodiment, devices of the same conductivity type, e.g., N-type or P-type, may have gate electrode stacks that are differentiated for the same conductivity type. However, for comparison, devices of the same conductivity type may have differentiated voltage threshold values ​​(VT) based on modulated doping.

[0247] FIG. 33a illustrates cross-sectional views of a pair of NMOS devices having a differentiated voltage threshold value based on modulated doping and a pair of PMOS devices having a differentiated voltage threshold value based on modulated doping, according to one embodiment of the present disclosure.

[0248] Referring to FIG. 33a, the first NMOS device (3302) is adjacent to the second NMOS device (3304) above a semiconductor active region (3300), such as above a silicon fin or substrate. Both the first NMOS device (3302) and the second NMOS device (3304) include a gate dielectric layer (3306), a first gate electrode conductive layer (3308), such as a work function layer, and a gate electrode conductive filler (3310). In one embodiment, the first gate electrode conductive layer (3308) of the first NMOS device (3302) and the second NMOS device (3304) have the same material and the same thickness, and accordingly, have the same work function. However, the first NMOS device (3302) has a lower VT than the second NMOS device (3304). In one such embodiment, the first NMOS device (3302) is referred to as a "standard VT" device, and the second NMOS device (3304) is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using modulated or differentiated injection doping in regions (3312) of the first NMOS device (3302) and the second NMOS device (3304).

[0249] Referring again to FIG. 33a, the first PMOS device (3322) is adjacent to the second PMOS device (3324) above a semiconductor active region (3320), such as above a silicon fin or substrate. Both the first PMOS device (3322) and the second PMOS device (3324) include a gate dielectric layer (3326), a first gate electrode conductive layer (3328), such as a work function layer, and a gate electrode conductive filler (3330). In one embodiment, the first gate electrode conductive layer (3328) of the first PMOS device (3322) and the second PMOS device (3324) has the same material and the same thickness, and accordingly, has the same work function. However, the first PMOS device (3322) has a higher VT than the second PMOS device (3324). In one such embodiment, the first PMOS device (3322) is referred to as a "standard VT" device, and the second PMOS device (3324) is referred to as a "low VT" device. In one embodiment, a differentiated VT is achieved by using modulated or differentiated injection doping in regions (3332) of the first PMOS device (3322) and the second PMOS device (3324).

[0250] Unlike FIG. 33a, FIG. 33b illustrates cross-sectional views of a pair of NMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures and a pair of PMOS devices having differentiated voltage thresholds based on differentiated gate electrode structures, according to another embodiment of the present disclosure.

[0251] Referring to FIG. 33b, the first NMOS device (3352) is adjacent to the second NMOS device (3354) above a semiconductor active region (3350), such as above a silicon fin or substrate. Both the first NMOS device (3352) and the second NMOS device (3354) include a gate dielectric layer (3356). However, the first NMOS device (3352) and the second NMOS device (3354) have structurally different gate electrode stacks. In particular, the first NMOS device (3352) includes a first gate electrode conductive layer (3358), such as a first work function layer, and a gate electrode conductive filler (3360). The second NMOS device (3354) includes a second gate electrode conductive layer (3359), a first gate electrode conductive layer (3358), and a gate electrode conductive filler (3360), such as a second work function layer. The first NMOS device (3352) has a lower VT than the second NMOS device (3354). In one such embodiment, the first NMOS device (3352) is referred to as a "standard VT" device, and the second NMOS device (3354) is referred to as a "high VT" device. In one embodiment, a differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0252] Referring again to FIG. 33b, the first PMOS device (3372) is adjacent to the second PMOS device (3374) above a semiconductor active region (3370), such as above a silicon fin or substrate. Both the first PMOS device (3372) and the second PMOS device (3374) include a gate dielectric layer (3376). However, the first PMOS device (3372) and the second PMOS device (3374) have structurally different gate electrode stacks. In particular, the first PMOS device (3372) includes a gate electrode conductive layer (3378A) having a first thickness, such as a work function layer, and a gate electrode conductive filler (3380). The second PMOS device (3374) includes a gate electrode conductive layer (3378B) having a second thickness and a gate electrode conductive filler (3380). In one embodiment, the gate electrode conductive layer (3378A) and the gate electrode conductive layer (3378B) have the same composition, but the thickness of the gate electrode conductive layer (3378B) (second thickness) is greater than the thickness of the gate electrode conductive layer (3378A) (first thickness). The first PMOS device (3372) has a higher VT than the second PMOS device (3374). In one such embodiment, the first PMOS device (3372) is referred to as a "standard VT" device, and the second PMOS device (3374) is referred to as a "low VT" device. In one embodiment, a differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

[0253] Referring again to FIG. 33b, according to one embodiment of the present disclosure, an integrated circuit structure comprises a pin (e.g., a silicon pin such as 3350). It should be recognized that the pin has a top (as illustrated) and sidewalls (entering into and exiting the ground). A gate dielectric layer (3356) is located above the top of the pin and laterally adjacent to the sidewalls of the pin. An N-type gate electrode of the device (3354) is located above the gate dielectric layer (3356) which is located above the top of the pin and laterally adjacent to the sidewalls of the pin. The N-type gate electrode comprises a P-type metal layer (3359) on the gate dielectric layer (3356) and an N-type metal layer (3358) on the P-type metal layer (3359). As will be recognized, the first N-type source or drain region may be adjacent to the first side of the gate electrode (e.g., extending into the ground), and the second N-type source or drain region may be adjacent to the second side of the gate electrode (e.g., extending out of the ground), and the second side is on the opposite side of the first side.

[0254] In one embodiment, the P-type metal layer (3359) comprises titanium and nitrogen, and the N-type metal layer (3358) comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer (3359) has a thickness in the range of 2 to 12 Angstroms, and in a specific embodiment, the P-type metal layer (3359) has a thickness in the range of 2 to 4 Angstroms. In one embodiment, the N-type gate electrode further comprises a conductive filler metal layer (3360) on the N-type metal layer (3358). In one such embodiment, the conductive filler metal layer (3360) comprises tungsten. In a specific embodiment, the conductive filler metal layer (3360) comprises 95 atomic percent or more of tungsten and 0.1 to 2 atomic percent of fluorine.

[0255] Referring again to FIG. 33b, according to another embodiment of the present disclosure, an integrated circuit structure comprises a first N-type device (3352) having a voltage threshold value (VT), and the first N-type device (3352) has a first gate dielectric layer (3356) and a first N-type metal layer (3358) on the first gate dielectric layer (3356). Additionally, a second N-type device (3354) having a voltage threshold value (VT) is included, and the second N-type device (3354) has a second gate dielectric layer (3356), a P-type metal layer (3359) on the second gate dielectric layer (3356), and a second N-type metal layer (3358) on the P-type metal layer (3359).

[0256] In one embodiment, the VT of the second N-type device (3354) is higher than the VT of the first N-type device (3352). In one embodiment, the first N-type metal layer (3358) and the second N-type metal layer (3358) have the same composition. In one embodiment, the first N-type metal layer (3358) and the second N-type metal layer (3358) have the same thickness. In one embodiment, the N-type metal layer (3358) comprises titanium, aluminum, carbon, and nitrogen, and the P-type metal layer (3359) comprises titanium and nitrogen.

[0257] Referring again to FIG. 33b, according to another embodiment of the present disclosure, an integrated circuit structure comprises a first P-type device (3372) having a voltage threshold value (VT), and the first P-type device (3372) has a first gate dielectric layer (3376) and a first P-type metal layer (3378A) on the first gate dielectric layer (3376). The first P-type metal layer (3378A) has a thickness. A second P-type device (3374) is also included and has a voltage threshold value (VT). The second P-type device (3374) has a second gate dielectric layer (3376) and a second P-type metal layer (3378B) on the second gate dielectric layer (3376). The second P-type metal layer (3378B) has a thickness greater than the thickness of the first P-type metal layer (3378A).

[0258] In one embodiment, the VT of the second P-type device (3374) is lower than the VT of the first P-type device (3372). In one embodiment, the first P-type metal layer (3378A) and the second P-type metal layer (3378B) have the same composition. In one embodiment, both the first P-type metal layer (3378A) and the second P-type metal layer (3378B) contain titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer (3378A) is smaller than the work-function saturation thickness of the material of the first P-type metal layer (3378A). In one embodiment, although not illustrated, the second P-type metal layer (3378B) comprises a first metal film (e.g., from the second deposition) on a second metal film (e.g., from the first deposition), and there is a core between the first metal film and the second metal film.

[0259] Referring again to FIG. 33b, according to another embodiment of the present disclosure, an integrated circuit structure comprises a first N-type device (3352) having a first gate dielectric layer (3356) and a first N-type metal layer (3358) on the first gate dielectric layer (3356). A second N-type device (3354) has a second gate dielectric layer (3356), a first P-type metal layer (3359) on the second gate dielectric layer (3356), and a second N-type metal layer (3358) on the first P-type metal layer (3359). A first P-type device (3372) has a third gate dielectric layer (3376) and a second P-type metal layer (3378A) on the third gate dielectric layer (3376). The second P-type metal layer (3378A) has a thickness. The second P-type device (3374) has a fourth gate dielectric layer (3376) and a third P-type metal layer (3378B) on the fourth gate dielectric layer (3376). The third P-type metal layer (3378B) has a greater thickness than the thickness of the second P-type metal layer (3378A).

[0260] In one embodiment, the first N-type device (3352) has a voltage threshold value (VT), and the second N-type device (3354) has a voltage threshold value (VT), and the VT of the second N-type device (3354) is lower than the VT of the first N-type device (3352). In one embodiment, the first P-type device (3372) has a voltage threshold value (VT), and the second P-type device (3374) has a voltage threshold value (VT), and the VT of the second P-type device (3374) is lower than the VT of the first P-type device (3372). In one embodiment, the third P-type metal layer (3378B) includes the first metal film on the second metal film, and there is a seam between the first metal film and the second metal film.

[0261] It should be recognized that more than two types of VT devices for the same type of conductivity may be included within the same structure, such as on the same die. In the first example, FIG. 34a illustrates cross-sectional views of a triplet NMOS device having a differentiated gate electrode structure and a differentiated voltage threshold based on modulated doping and a triplet PMOS device having a differentiated gate electrode structure and a differentiated voltage threshold based on modulated doping, according to one embodiment of the present disclosure.

[0262] Referring to FIG. 34a, the first NMOS device (3402) is adjacent to the second NMOS device (3404) and the third NMOS device (3403) above a semiconductor active region (3400), such as above a silicon fin or substrate. The first NMOS device (3402), the second NMOS device (3404), and the third NMOS device (3403) include a gate dielectric layer (3406). The first NMOS device (3402) and the third NMOS device (3403) have structurally identical or similar gate electrode stacks. However, the second NMOS device (3404) has a gate electrode stack that is structurally different from the first NMOS device (3402) and the third NMOS device (3403). In particular, the first NMOS device (3402) and the third NMOS device (3403) include a first gate electrode conductive layer (3408), such as a first work function layer, and a gate electrode conductive filler (3410). The second NMOS device (3404) includes a second gate electrode conductive layer (3409), such as a second work function layer, a first gate electrode conductive layer (3408), and a gate electrode conductive filler (3410). The first NMOS device (3402) has a lower VT than the second NMOS device (3404). In one such embodiment, the first NMOS device (3402) is referred to as a "standard VT" device, and the second NMOS device (3404) is referred to as a "high VT" device. In one embodiment, a differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, even though the gate electrode structure of the third NMOS device (3403) is the same as the gate electrode structure of the first NMOS device (3402), the third NMOS device (3403) has a VT different from the VT of the first NMOS device (3402) and the second NMOS device (3404).In one embodiment, the VT of the third NMOS device (3403) is between the VT of the first NMOS device (3402) and the VT of the second NMOS device (3404). In one embodiment, a differentiated VT between the third NMOS device (3403) and the first NMOS device (3402) is achieved by using modulated or differentiated injection doping in the region (3412) of the third NMOS device (3403). In one such embodiment, the third N-type device (3403) has a channel region having a dopant concentration different from the dopant concentration of the channel region of the first N-type device (3402).

[0263] Referring again to FIG. 34a, the second PMOS device (3424) is adjacent to the first PMOS device (3422) and the third PMOS device (3423) above the semiconductor active region (3420), such as above the silicon pin or substrate. The first PMOS device (3422), the second PMOS device (3424), and the third PMOS device (3423) include a gate dielectric layer (3426). The first PMOS device (3422) and the third PMOS device (3423) have structurally identical or similar gate electrode stacks. However, the second PMOS device (3424) has a gate electrode stack that is structurally different from the first PMOS device (3422) and the third PMOS device (3423). In particular, the first PMOS device (3422) and the third PMOS device (3423) include a gate electrode conductive layer (3428A) having a first thickness, such as a work function layer, and a gate electrode conductive filler (3430). The second PMOS device (3424) includes a gate electrode conductive layer (3428B) having a second thickness and a gate electrode conductive filler (3430). In one embodiment, the gate electrode conductive layer (3428A) and the gate electrode conductive layer (3428B) have the same composition, but the thickness of the gate electrode conductive layer (3428B) (second thickness) is greater than the thickness of the gate electrode conductive layer (3428A) (first thickness). In one embodiment, the first PMOS device (3422) has a higher VT than the second PMOS device (3424). In one such embodiment, the first PMOS device (3422) is referred to as a "standard VT" device, and the second PMOS device (3424) is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.In one embodiment, even though the gate electrode structure of the third PMOS device (3423) is identical to the gate electrode structure of the first PMOS device (3422), the third PMOS device (3423) has a VT different from the VT of the first PMOS device (3422) and the second PMOS device (3424). In one embodiment, the VT of the third PMOS device (3423) is between the VT of the first PMOS device (3422) and the VT of the second PMOS device (3424). In one embodiment, the differentiated VT between the third PMOS device (3423) and the first PMOS device (3422) is achieved by using modulated or differentiated injection doping in the region (3432) of the third PMOS device (3423). In one such embodiment, the third P-type device (3423) has a channel region having a dopant concentration different from the dopant concentration of the channel region of the first P-type device (3422).

[0264] In the second example, FIG. 34b illustrates cross-sectional views of a triplet NMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, and a triplet PMOS device having a differentiated gate electrode structure and a differentiated voltage threshold value based on modulated doping, according to another embodiment of the present disclosure.

[0265] Referring to FIG. 34b, the first NMOS device (3452) is adjacent to the second NMOS device (3454) and the third NMOS device (3453) above a semiconductor active region (3450), such as above a silicon fin or substrate. The first NMOS device (3452), the second NMOS device (3454), and the third NMOS device (3453) include a gate dielectric layer (3456). The second NMOS device (3454) and the third NMOS device (3453) have structurally identical or similar gate electrode stacks. However, the first NMOS device (3452) has a gate electrode stack that is structurally different from that of the second NMOS device (3454) and the third NMOS device (3453). In particular, the first NMOS device (3452) includes a first gate electrode conductive layer (3458), such as a first work function layer, and a gate electrode conductive filler (3460). The second NMOS device (3454) and the third NMOS device (3453) include a second gate electrode conductive layer (3459), such as a second work function layer, a first gate electrode conductive layer (3458), and a gate electrode conductive filler (3460). The first NMOS device (3452) has a lower VT than the second NMOS device (3454). In one such embodiment, the first NMOS device (3452) is referred to as a "standard VT" device, and the second NMOS device (3454) is referred to as a "high VT" device. In one embodiment, a differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, even though the gate electrode structure of the third NMOS device (3453) is the same as the gate electrode structure of the second NMOS device (3454), the third NMOS device (3453) has a VT different from the VT of the first NMOS device (3452) and the second NMOS device (3454).In one embodiment, the VT of the third NMOS device (3453) is between the VT of the first NMOS device (3452) and the VT of the second NMOS device (3454). In one embodiment, a differentiated VT between the third NMOS device (3453) and the second NMOS device (3454) is achieved by using modulated or differentiated injection doping in the region (3462) of the third NMOS device (3453). In one such embodiment, the third N-type device (3453) has a channel region having a dopant concentration different from the dopant concentration of the channel region of the second N-type device (3454).

[0266] Referring again to FIG. 34b, the second PMOS device (3474) is adjacent to the first PMOS device (3472) and the third PMOS device (3473) above the semiconductor active region (3470), such as above the silicon pin or substrate. The first PMOS device (3472), the second PMOS device (3474), and the third PMOS device (3473) include a gate dielectric layer (3476). The second PMOS device (3474) and the third PMOS device (3473) have structurally identical or similar gate electrode stacks. However, the first PMOS device (3472) has a gate electrode stack that is structurally different from the second PMOS device (3474) and the third PMOS device (3473). In particular, the first PMOS device (3472) includes a gate electrode conductive layer (3478A) having a first thickness, such as a work function layer, and a gate electrode conductive filler (3480). The second PMOS device (3474) and the third PMOS device (3473) include a gate electrode conductive layer (3478B) having a second thickness and a gate electrode conductive filler (3480). In one embodiment, the gate electrode conductive layer (3478A) and the gate electrode conductive layer (3478B) have the same composition, but the thickness of the gate electrode conductive layer (3478B) (second thickness) is greater than the thickness of the gate electrode conductive layer (3478A) (first thickness). In one embodiment, the first PMOS device (3472) has a higher VT than the second PMOS device (3474). In one such embodiment, the first PMOS device (3472) is referred to as a "standard VT" device, and the second PMOS device (3474) is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.In one embodiment, even though the gate electrode structure of the third PMOS device (3473) is identical to the gate electrode structure of the second PMOS device (3474), the third PMOS device (3473) has a VT different from the VT of the first PMOS device (3472) and the second PMOS device (3474). In one embodiment, the VT of the third PMOS device (3473) is between the VT of the first PMOS device (3472) and the VT of the second PMOS device (3474). In one embodiment, the differentiated VT between the third PMOS device (3473) and the first PMOS device (3472) is achieved by using modulated or differentiated injection doping in the region (3482) of the third PMOS device (3473). In one such embodiment, the third P-type device (3473) has a channel region having a dopant concentration different from the dopant concentration of the channel region of the second P-type device (3474).

[0267] FIGS. 35a through 35d illustrate cross-sectional views of various operations in a method for manufacturing NMOS devices having differentiated voltage threshold values ​​based on differentiated gate electrode structures according to other embodiments of the present disclosure.

[0268] Referring to FIG. 35a, which is illustrated as having a “Standard VT NMOS” region (STD VT NMOS) and a “High VT NMOS” region (HIGH VT NMOS) bifurcate on a common substrate, a method for manufacturing an integrated circuit structure includes the step of forming a gate dielectric layer (3506) on a first semiconductor pin (3502) and on a second semiconductor pin (3504), such as on the first and second silicon pins. A P-type metal layer (3508) is formed on the gate dielectric layer (3506) on the first semiconductor pin (3502) and on the second semiconductor pin (3504).

[0269] Referring to FIG. 35b, a portion of the P-type metal layer (3508) is removed from the gate dielectric layer (3506) above the first semiconductor pin (3502), but a portion (3509) of the P-type metal layer (3508) is retained on the gate dielectric layer (3506) above the second semiconductor pin (3504).

[0270] Referring to FIG. 35c, an N-type metal layer (3510) is formed on a gate dielectric layer (3506) above a first semiconductor pin (3502) and on a portion (3509) of a P-type metal layer above a gate dielectric layer (3506) above a second semiconductor pin (3504). In one embodiment, subsequent processing includes the steps of forming a first N-type device having a voltage threshold value (VT) above the first semiconductor pin (3502), and forming a second N-type device having a voltage threshold value (VT) above the second semiconductor pin (3504), wherein the VT of the second N-type device is higher than the VT of the first N-type device.

[0271] Referring to FIG. 35d, in one embodiment, a conductive filler metal layer (3512) is formed on an N-type metal layer (3510). In one such embodiment, the step of forming the conductive filler metal layer (3512) includes the step of forming a tungsten-containing film with a tungsten hexafluoride (WF6) precursor using atomic layer deposition (ALD).

[0272] FIGS. 36a through 36d illustrate cross-sectional views of various operations in a method for manufacturing PMOS devices having differentiated voltage threshold values ​​based on differentiated gate electrode structures according to other embodiments of the present disclosure.

[0273] Referring to FIG. 36a, which is illustrated as having a “Standard VT PMOS” region (STD VT PMOS) and a “Low VT PMOS” region (LOW VT PMOS) divided on a common substrate, a method for manufacturing an integrated circuit structure includes the step of forming a gate dielectric layer (3606) on a first semiconductor pin (3602) and on a second semiconductor pin (3604), such as on the first and second silicon pins. A first P-type metal layer (3608) is formed on the gate dielectric layer (3606) on the first semiconductor pin (3602) and on the second semiconductor pin (3604).

[0274] Referring to FIG. 36b, a portion of the first P-type metal layer (3608) is removed from the gate dielectric layer (3606) above the first semiconductor pin (3602), but a portion (3609) of the first P-type metal layer (3608) is retained on the gate dielectric layer (3606) above the second semiconductor pin (3604).

[0275] Referring to FIG. 36c, a second P-type metal layer (3610) is formed on the gate dielectric layer (3606) above the first semiconductor pin (3602) and on a portion (3609) of the first P-type metal layer on the gate dielectric layer (3606) above the second semiconductor pin (3604). In one embodiment, subsequent processing includes the steps of forming a first P-type device having a voltage threshold value (VT) above the first semiconductor pin (3602), and forming a second P-type device having a voltage threshold value (VT) above the second semiconductor pin (3604), wherein the VT of the second P-type device is lower than the VT of the first P-type device.

[0276] In one embodiment, the first P-type metal layer (3608) and the second P-type metal layer (3610) have the same composition. In one embodiment, the first P-type metal layer (3608) and the second P-type metal layer (3610) have the same thickness. In one embodiment, the first P-type metal layer (3608) and the second P-type metal layer (3610) have the same thickness and the same composition. In one embodiment, as illustrated, there is a seam (3611) between the first P-type metal layer (3608) and the second P-type metal layer (3610).

[0277] Referring to FIG. 36d, in one embodiment, a conductive filler metal layer (3612) is formed on top of a P-type metal layer (3610). In one such embodiment, the step of forming the conductive filler metal layer (3612) includes the step of forming a tungsten-containing film with a tungsten hexafluoride (WF6) precursor using atomic layer deposition (ALD). In one embodiment, as illustrated, an N-type metal layer (3614) is formed on the P-type metal layer (3610) prior to forming the conductive filler metal layer (3612). In one such embodiment, the N-type metal layer (3614) is an artifact of a dual metal gate alternative processing scheme.

[0278] In another aspect, metal gate structures for CMOS (complementary metal oxide semiconductor) semiconductor devices are described. In one example, FIG. 37 illustrates a cross-sectional view of an integrated circuit structure having a P / N junction according to one embodiment of the present disclosure.

[0279] Referring to FIG. 37, the integrated circuit structure (3700) comprises a semiconductor substrate (3702) having an N-well region (3704) - having a first semiconductor pin (3706) protruding therefrom - and a P-well region (3708) - having a second semiconductor pin (3710) protruding therefrom. The first semiconductor pin (3706) is spaced apart from the second semiconductor pin (3710). The N-well region (3704) is immediately adjacent to the P-well region (3708) on the semiconductor substrate (3702). A trench isolation structure (3712) is located on the semiconductor substrate (3702) outside of and between the first semiconductor pin (3706) and the second semiconductor pin (3710). The first semiconductor pin (3706) and the second semiconductor pin (3210) extend above the trench isolation structure (3712).

[0280] A gate dielectric layer (3714) is on the first semiconductor pin (3706) and the second semiconductor pin (3710) and on the trench isolation structure (3712). The gate dielectric layer (3714) is continuous between the first semiconductor pin (3706) and the second semiconductor pin (3710). A conductive layer (3716) is above the gate dielectric layer (3714) above the first semiconductor pin (3706) but not above the second semiconductor pin (3710). In one embodiment, the conductive layer (3716) comprises titanium, nitrogen, and oxygen. A p-type metal gate layer (3718) is above the conductive layer (3716) above the first semiconductor pin (3706) but not above the second semiconductor pin (3710). A p-type metal gate layer (3718) is additionally located on a portion, not the entirety, of the trench isolation structure (3712) between the first semiconductor pin (3706) and the second semiconductor pin (3710). An n-type metal gate layer (3720) is located above the second semiconductor pin (3710), above the trench isolation structure (3712) between the first semiconductor pin (3706) and the second semiconductor pin (3710), and above the p-type metal gate layer (3718).

[0281] In one embodiment, an interlayer dielectric (ILD) layer (3722) is positioned on a trench isolation structure (3712) outside the first semiconductor pin (3706) and the second semiconductor pin (3710). The ILD layer (3722) has an opening (3724), which exposes the first and second semiconductor pins (3706 and 3710). In one such embodiment, as illustrated, a conductive layer (3716), a p-type metal gate layer (3718), and an n-type metal gate layer (3720) are additionally formed along the sidewall (3726) of the opening (3724). In a specific embodiment, as illustrated, the conductive layer (3716) has a top surface (3717) along the side wall (3726) of the opening (3724) below the top surface (3721) of the n-type metal gate layer (3720) and the top surface (3719) of the p-type metal gate layer (3718) along the side wall (3726) of the opening (3724).

[0282] In one embodiment, the p-type metal gate layer (3718) comprises titanium and nitrogen. In one embodiment, the n-type metal gate layer (3720) comprises titanium and aluminum. In one embodiment, as illustrated, a conductive filler metal layer (3730) is located above the n-type metal gate layer (3720). In one such embodiment, the conductive filler metal layer (3730) comprises tungsten. In a specific embodiment, the conductive filler metal layer (3730) comprises 95 atomic percent or more of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer (3714) has a layer comprising hafnium and oxygen. In one embodiment, as illustrated, a thermal or chemical oxide layer (3732) is located between the upper portions of the first semiconductor pin (3706) and the second semiconductor pin (3710). In one embodiment, the semiconductor substrate (3702) is a bulk silicon semiconductor substrate.

[0283] Now, referring only to the right side of FIG. 37, according to one embodiment of the present disclosure, an integrated circuit structure comprises a semiconductor substrate (3702) comprising an N-well region (3704)—having a semiconductor pin (3706) protruding therefrom. A trench isolation structure (3712) is present on the semiconductor substrate (3702) around the semiconductor pin (3706). The semiconductor pin (3706) extends above the trench isolation structure (3712). A gate dielectric layer (3714) is present above the semiconductor pin (3706). A conductive layer (3716) is present above the gate dielectric layer (3714) above the semiconductor pin (3706). In one embodiment, the conductive layer (3716) comprises titanium, nitrogen, and oxygen. A P-type metal gate layer (3718) is present above the conductive layer (3716) above the semiconductor pin (3706).

[0284] In one embodiment, an interlayer dielectric (ILD) layer (3722) is placed on a trench isolation structure (3712). The ILD layer has an opening, which exposes a semiconductor pin (3706). A conductive layer (3716) and a P-type metal gate layer (3718) are additionally formed along the sidewall of the opening. In one such embodiment, the conductive layer (3716) has a top surface along the sidewall of the opening below the top surface of the P-type metal gate layer (3718) along the sidewall of the opening. In one embodiment, the P-type metal gate layer (3718) is placed on the conductive layer (3716). In one embodiment, the P-type metal gate layer (3718) comprises titanium and nitrogen. In one embodiment, a conductive fill metal layer (3730) is placed on top of the P-type metal gate layer (3718). In one such embodiment, the conductive fill metal layer (3730) comprises tungsten. In a specific embodiment, the conductive filler metal layer (3730) is composed of 95 atomic percent or more of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer (3714) comprises a layer having hafnium and oxygen.

[0285] FIGS. 38a through 38h illustrate cross-sectional views of various operations in a method for manufacturing an integrated circuit structure using a dual metal gate alternative gate process flow according to one embodiment of the present disclosure.

[0286] Referring to FIG. 38a, which shows an NMOS (N-type) region and a PMOS (P-type) region, a method for manufacturing an integrated circuit structure includes the step of forming an interlayer dielectric (ILD) layer (3802) on first and second semiconductor pins (3804 and 3806) on a substrate (3800). An opening (3808) is formed in the ILD layer (3802), and the opening (3808) exposes the first and second semiconductor pins (3804 and 3806). In one embodiment, the opening (3808) is formed by removing a gate placeholder or dummy gate structure that was originally located on the first and second semiconductor pins (3804 and 3806).

[0287] A gate dielectric layer (3810) is formed within the opening (3808) and above the first and second semiconductor pins (3804 and 3806) and on a portion of the trench isolation structure (3812) between the first semiconductor pin (3804) and the second semiconductor pin (3806). In one embodiment, as illustrated, the gate dielectric layer (3810) is formed on a thermal or chemical oxide layer (3811), such as a silicon oxide or silicon dioxide layer, formed on the first and second semiconductor pins (3804 and 3806). In another embodiment, the gate dielectric layer (3810) is formed directly above the first semiconductor pin (3804) and the second semiconductor pin (3806).

[0288] A conductive layer (3814) is formed on top of a gate dielectric layer (3810) formed on top of a first semiconductor pin (3804) and a second semiconductor pin (3806). In one embodiment, the conductive layer (3814) comprises titanium, nitrogen, and oxygen. A p-type metal gate layer (3816) is formed on top of the first semiconductor pin (3804) and on top of the conductive layer (3814) formed on top of the second semiconductor pin (3806).

[0289] Referring to FIG. 38b, a dielectric etch stop layer (3818) is formed on a p-type metal gate layer (3816). In one embodiment, the dielectric etch stop layer (3818) comprises a first layer of silicon oxide (e.g., SiO2), a layer of aluminum oxide (Al2O3) on the first layer of silicon oxide, and a second layer of silicon oxide (e.g., SiO2) on the layer of aluminum oxide.

[0290] Referring to FIG. 38c, a mask (3820) is formed on the upper part of the structure of FIG. 38b. The mask (3820) covers the PMOS region and exposes the NMOS region.

[0291] Referring to FIG. 38d, the dielectric etching stop layer (3818), p-type metal gate layer (3816), and conductive layer (3814) are patterned to provide a patterned p-type metal gate layer (3817) and a patterned dielectric etching stop layer (3819) on top of the conductive layer (3815) patterned on top of the first semiconductor pin (3804) rather than on top of the second semiconductor pin (3806). In one embodiment, the conductive layer (3814) protects the second semiconductor pin (3806) during patterning.

[0292] Referring to FIG. 38e, the mask (3820) is removed from the structure of FIG. 38d. Referring to FIG. 38f, the patterned dielectric etching stop layer (3819) is removed from the structure of FIG. 38e.

[0293] Referring to FIG. 38g, an n-type metal gate layer (3822) is formed above the second semiconductor pin (3806), above a portion of the trench isolation structure (3812) between the first semiconductor pin (3804) and the second semiconductor pin (3806), and above the patterned p-type metal gate layer (3817). In one embodiment, a patterned conductive layer (3815), a patterned p-type metal gate layer (3817), and an n-type metal gate layer (3822) are additionally formed along the sidewall (3824) of the opening (3808). In one such embodiment, the patterned conductive layer (3815) has a top surface along the sidewall (3824) of the opening (3808) below the top surface of the patterned p-type metal gate layer (3817) and the top surface of the n-type metal gate layer (3822).

[0294] Referring to FIG. 38h, a conductive filling metal layer (3826) is formed on top of an n-type metal gate layer (3822). In one embodiment, the conductive filling metal layer (3826) is formed by depositing a tungsten-containing film with a tungsten hexafluoride (WF6) precursor using atomic layer deposition (ALD).

[0295] In another aspect, dual silicide structures for CMOS (complementary metal oxide semiconductor) semiconductor devices are described. As an exemplary process flow, FIGS. 39a through 39h illustrate cross-sectional views illustrating various operations in a method for manufacturing a dual silicide-based integrated circuit according to one embodiment of the present disclosure.

[0296] Referring to FIG. 39a, which is illustrated as having NMOS and PMOS regions divided on a common substrate, a method for manufacturing an integrated circuit structure comprises the step of forming a first gate structure (3902) which may include dielectric sidewall spacers (3903) above a first pin (3904), such as a first silicon pin. A second gate structure (3952) which may include dielectric sidewall spacers (3953) is formed above a second pin (3954), such as a second silicon pin. An insulating material (3906) is formed adjacent to the first gate structure (3902) above the first pin (3904) and adjacent to the second gate structure (3952) above the second pin (3954). In one embodiment, the insulating material (3906) is a sacrificial material and is used as a mask in a dual silicide process.

[0297] Referring to FIG. 39b, a first portion of the insulating material (3906) is removed from above the first pin (3904) but not from above the second pin (3954) to expose the first and second source or drain regions (3908 and 3910) of the first pin (3904) adjacent to the first gate structure (3902). In one embodiment, as illustrated, the first and second source or drain regions (3908 and 3910) are epitaxial regions formed within the recessed portions of the first pin (3904). In one such embodiment, the first and second source or drain regions (3908 and 3910) comprise silicon and germanium.

[0298] Referring to FIG. 39c, a first metal silicide layer (3912) is formed on the first and second source or drain regions (3908 and 3910) of the first pin (3904). In one embodiment, the first metal silicide layer (3912) is formed by depositing a layer containing nickel and platinum on the structure of FIG. 39b, annealing the layer containing nickel and platinum, and removing unreacted portions of the layer containing nickel and platinum.

[0299] Referring to FIG. 39d, after forming the first metal silicide layer (3912), a second portion of the insulating material (3906) is removed from above the second pin (3954) to expose the third and fourth source or drain regions (3958 and 3960) of the second pin (3954) adjacent to the second gate structure (3952). In one embodiment, as illustrated, the third and fourth source or drain regions (3958 and 3960) are formed within the second pin (3954), such as within the second silicon pin. However, in another embodiment, the third and fourth source or drain regions (3958 and 3960) are epitaxial regions formed within the recessed portions of the second pin (3954). In one such embodiment, the third and fourth source or drain regions (3958 and 3960) include silicon.

[0300] Referring to FIG. 39e, a first metal layer (3914) is formed on the structure of FIG. 39d, namely on the first source or drain region (3908), the second source or drain region (3910), the third source or drain region (3958), and the fourth source or drain region (3960). A second metal silicide layer (3962) is subsequently formed on the third source or drain region (3958) and the fourth source or drain region (3960) of the second pin (3954). The second metal silicide layer (3962) is formed from the first metal layer (3914), for example, using an annealing process. In one embodiment, the second metal silicide layer (3962) has a different composition from the first metal silicide layer (3912). In one embodiment, the first metal layer (3914) is a titanium layer or comprises a titanium layer. In one embodiment, as illustrated, the first metal layer (3914) is a conformal metal layer, formed conformally to, for example, the open trenches of FIG. 39d.

[0301] Referring to FIG. 39f, in one embodiment, the first metal layer (3914) is resized to form a U-shaped metal layer (3916) over each of the first source or drain region (3908), the second source or drain region (3910), the third source or drain region (3958), and the fourth source or drain region (3960).

[0302] Referring to FIG. 39g, in one embodiment, a second metal layer (3918) is formed on a U-shaped metal layer (3916) of the structure of FIG. 39f. In one embodiment, the second metal layer (3918) has a different composition from the U-shaped metal layer (3916).

[0303] Referring to FIG. 39h, in one embodiment, a third metal layer (3920) is formed on the second metal layer (3918) of the structure of FIG. 39g. In one embodiment, the third metal layer (3920) has the same composition as the U-shaped metal layer (3916).

[0304] Referring again to FIG. 39h, according to one embodiment of the present disclosure, an integrated circuit structure (3900) comprises a P-type semiconductor device (PMOS) on a substrate. The P-type semiconductor device comprises a first pin (3904), such as a first silicon pin. It should be recognized that the first pin has a top (as illustrated as 3904A) and sidewalls (e.g., going into and coming out of the ground). A first gate electrode (3902) comprises a first gate dielectric layer above the top (3904A) of the first pin (3904) and laterally adjacent to the sidewalls of the first pin (3904), and the first gate electrode comprises a first gate dielectric layer above the top (3904A) of the first pin (3904) and laterally adjacent to the sidewalls of the first pin (3904). The first gate electrode (3902) has a first side (3902A) and a second side (3902B) opposite the first side (3902A).

[0305] The first and second semiconductor source or drain regions (3908 and 3910) are each adjacent to the first and second sides (3902A and 3902B) of the first gate electrode (3902). The first and second trench contact structures (3930 and 3932) are each located above the first and second semiconductor source or drain regions (3908 and 3910) adjacent to the first and second sides (3902A and 3902B) of the first gate electrode (3902). A first metal silicide layer (3912) is each located directly between the first and second trench contact structures (3930 and 3932) and the first and second semiconductor source or drain regions (3908 and 3910).

[0306] An integrated circuit structure (3900) comprises an N-type semiconductor device (NMOS) on a substrate. The N-type semiconductor device comprises a second pin (3954), such as a second silicon pin. It should be recognized that the second pin has a top (as illustrated as 3954A) and sidewalls (e.g., going into and coming out of the ground). A second gate electrode (3952) comprises a second gate dielectric layer above the top (3954A) of the second pin (3954) and laterally adjacent to the sidewalls of the second pin (3954), and the second gate electrode comprises a second gate dielectric layer above the top (3954A) of the second pin (3954) and laterally adjacent to the sidewalls of the second pin (3954). The second gate electrode (3952) has a first side (3952A) and a second side (3952B) opposite to the first side (3952A).

[0307] Third and fourth semiconductor source or drain regions (3958 and 3960) are respectively adjacent to the first and second sides (3952A and 3952B) of the second gate electrode (3952). Third and fourth trench contact structures (3970 and 3972) are respectively located above the third and fourth semiconductor source or drain regions (3958 and 3960) adjacent to the first and second sides (3952A and 3952B) of the second gate electrode (3952). A second metal silicide layer (3962) is respectively located directly between the third and fourth trench contact structures (3970 and 3972) and the third and fourth semiconductor source or drain regions (3958 and 3960). In one embodiment, the first metal silicide layer (3912) includes at least one metal species not included in the second metal silicide layer (3962).

[0308] In one embodiment, the second metal silicide layer (3962) comprises titanium and silicon. The first metal silicide layer (3912) comprises nickel, platinum, and silicon. In one embodiment, the first metal silicide layer (3912) further comprises germanium. In one embodiment, the first metal silicide layer (3912) further comprises titanium, such as being incorporated into the first metal silicide layer (3912) during the subsequent formation of the second metal silicide layer (3962) using the first metal layer (3914). In one such embodiment, a silicide layer already formed on a PMOS source or drain region is further modified by an annealing process used to form a silicide region on an NMOS source or drain region. This may result in a silicide layer on the PMOS source or drain region having a fractional percentage of all the siliciding metals. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region is not changed or substantially changed by the annealing process used to form the silicide region on the NMOS source or drain region.

[0309] In one embodiment, the first and second semiconductor source or drain regions (3908 and 3910) are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third and fourth semiconductor source or drain regions (3958 and 3960) are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third and fourth semiconductor source or drain regions (3958 and 3960) are formed on the pin (3954) and are not embedded epitaxial regions.

[0310] In one embodiment, all of the first, second, third, and fourth trench contact structures (3930, 3932, 3970, and 3972) comprise a U-shaped metal layer (3916) and a T-shaped metal layer (3918) over and above the entire U-shaped metal layer (3916). In one embodiment, the U-shaped metal layer (3916) comprises titanium, and the T-shaped metal layer (3918) comprises cobalt. In one embodiment, all of the first, second, third, and fourth trench contact structures (3930, 3932, 3970, and 3972) further comprise a third metal layer (3920) on the T-shaped metal layer (3918). In one embodiment, the third metal layer (3920) and the U-shaped metal layer (3916) have the same composition. In a specific embodiment, the third metal layer (3920) and the U-shaped metal layer comprise titanium, and the T-shaped metal layer (3918) comprises cobalt.

[0311] In other embodiments, trench contact structures are described, for example, for source or drain regions. In one example, FIG. 40a illustrates a cross-sectional view of an integrated circuit structure having trench contacts for an NMOS device according to one embodiment of the present disclosure. FIG. 40b illustrates a cross-sectional view of an integrated circuit structure having trench contacts for a PMOS device according to another embodiment of the present disclosure.

[0312] Referring to FIG. 40a, an integrated circuit structure (4000) includes a pin (4002), such as a silicon pin. A gate dielectric layer (4004) is located above the pin (4002). A gate electrode (4006) is located above the gate dielectric layer (4004). In one embodiment, the gate electrode (4006) includes a conformal conductive layer (4008) and a conductive filler (4010). In one embodiment, a dielectric cap (4012) is located above the gate electrode (4006) and above the gate dielectric layer (4004). The gate electrode has a first side (4006A) and a second side (4006B) opposite the first side (4006A). Dielectric spacers (4013) are located along the sidewalls of the gate electrode (4006). In one embodiment, as illustrated, a gate dielectric layer (4004) is additionally provided between the first dielectric spacer among the dielectric spacers (4013) and the first side (4006A) of the gate electrode (4006), and between the second dielectric spacer among the dielectric spacers (4013) and the second side (4006B) of the gate electrode (4006). In one embodiment, although not illustrated, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is provided between the pin (4002) and the gate dielectric layer (4004).

[0313] The first and second semiconductor source or drain regions (4014 and 4016) are each adjacent to the first and second sides (4006A and 4006B) of the gate electrode (4006). In one embodiment, as illustrated, the first semiconductor source or drain region (4014) and the second semiconductor source or drain region (4016) are located in the pin (4002). However, in another embodiment, the first and second semiconductor source or drain regions (4014 and 4016) are embedded epitaxial regions formed within the recesses of the pin (4002).

[0314] The first and second trench contact structures (4018 and 4020) are each located above the first and second semiconductor source or drain regions (4014 and 4016) adjacent to the first and second sides (4006A and 4006B) of the gate electrode (4006). Both the first and second trench contact structures (4018 and 4020) comprise a U-shaped metal layer (4022) and a T-shaped metal layer (4024) over and above the entire U-shaped metal layer (4022). In one embodiment, the U-shaped metal layer (4022) and the T-shaped metal layer (4024) have different compositions. In one such embodiment, the U-shaped metal layer (4022) comprises titanium, and the T-shaped metal layer (4024) comprises cobalt. In one embodiment, both the first and second trench contact structures (4018 and 4020) further comprise a third metal layer (4026) on a T-shaped metal layer (4024). In one such embodiment, the third metal layer (4026) and the U-shaped metal layer (4022) have the same composition. In a specific embodiment, the third metal layer (4026) and the U-shaped metal layer (4022) comprise titanium, and the T-shaped metal layer (4024) comprises cobalt.

[0315] A first trench contact via (4028) is electrically connected to the first trench contact (4018). In a specific embodiment, the first trench contact via (4028) is on and coupled to the third metal layer (4026) of the first trench contact (4018). The first trench contact via (4028) is additionally on and in contact with a portion of one of the dielectric spacers (4013) and on and in contact with a portion of the dielectric cap (4012). A second trench contact via (4030) is electrically connected to the second trench contact (4020). In a specific embodiment, the second trench contact via (4030) is on and coupled to the third metal layer (4026) of the second trench contact (4020). A second trench contact via (4030) is additionally located on and in contact with one part of another dielectric spacer among the dielectric spacers (4013) and on and in contact with another part of the dielectric cap (4012).

[0316] In one embodiment, a metal silicide layer (4032) is located between the first and second trench contact structures (4018 and 4020) and the first and second semiconductor source or drain regions (4014 and 4016), respectively. In one embodiment, the metal silicide layer (4032) comprises titanium and silicon. In a specific such embodiment, the first and second semiconductor source or drain regions (4014 and 4016) are first and second N-type semiconductor source or drain regions.

[0317] Referring to FIG. 40b, an integrated circuit structure (4050) includes a pin (4052), such as a silicon pin. A gate dielectric layer (4054) is located above the pin (4052). A gate electrode (4056) is located above the gate dielectric layer (4054). In one embodiment, the gate electrode (4056) includes a conformal conductive layer (4058) and a conductive filler (4060). In one embodiment, a dielectric cap (4062) is located above the gate electrode (4056) and above the gate dielectric layer (4054). The gate electrode has a first side (4056A) and a second side (4056B) opposite the first side (4056A). Dielectric spacers (4063) are located along the sidewalls of the gate electrode (4056). In one embodiment, as illustrated, a gate dielectric layer (4054) is additionally located between the first dielectric spacer of the dielectric spacers (4063) and the first side (4056A) of the gate electrode (4056), and between the second dielectric spacer of the dielectric spacers (4063) and the second side (4056B) of the gate electrode (4056). In one embodiment, although not illustrated, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is located between the pin (4052) and the gate dielectric layer (4054).

[0318] The first and second semiconductor source or drain regions (4064 and 4066) are each adjacent to the first and second sides (4056A and 4056B) of the gate electrode (4056). In one embodiment, as illustrated, the first and second semiconductor source or drain regions (4064 and 4066) are each embedded epitaxial regions formed within the recesses (4065 and 4067) of the pin (4052). However, in another embodiment, the first semiconductor source or drain region (4064) and the second semiconductor source or drain region (4066) are located in the pin (4052).

[0319] The first and second trench contact structures (4068 and 4070) are each located above the first and second semiconductor source or drain regions (4064 and 4066) adjacent to the first and second sides (4056A and 4056B) of the gate electrode (4056). Both the first trench contact structure (4068) and the second trench contact structure (4070) comprise a U-shaped metal layer (4072) and a T-shaped metal layer (4074) over and above the entire U-shaped metal layer (4072). In one embodiment, the U-shaped metal layer (4072) and the T-shaped metal layer (4074) have different compositions. In one such embodiment, the U-shaped metal layer (4072) comprises titanium, and the T-shaped metal layer (4074) comprises cobalt. In one embodiment, both the first trench contact structure (4068) and the second trench contact structure (4070) further comprise a third metal layer (4076) on the T-shaped metal layer (4074). In one such embodiment, the third metal layer (4076) and the U-shaped metal layer (4072) have the same composition. In a specific embodiment, the third metal layer (4076) and the U-shaped metal layer (4072) comprise titanium, and the T-shaped metal layer (4074) comprises cobalt.

[0320] A first trench contact via (4078) is electrically connected to the first trench contact (4068). In a specific embodiment, the first trench contact via (4078) is on and coupled to the third metal layer (4076) of the first trench contact (4068). The first trench contact via (4078) is additionally on and in contact with a portion of one of the dielectric spacers (4063) and on and in contact with a portion of the dielectric cap (4062). A second trench contact via (4080) is electrically connected to the second trench contact (4070). In a specific embodiment, the second trench contact via (4080) is on and coupled to the third metal layer (4076) of the second trench contact (4070). A second trench contact via (4080) is additionally located on and in contact with one part of another dielectric spacer among the dielectric spacers (4063) and on and in contact with another part of the dielectric cap (4062).

[0321] In one embodiment, a metal silicide layer (4082) is located between the first and second trench contact structures (4068 and 4070) and the first and second semiconductor source or drain regions (4064 and 4066), respectively. In one embodiment, the metal silicide layer (4082) comprises nickel, platinum, and silicon. In a specific such embodiment, the first and second semiconductor source or drain regions (4064 and 4066) are the first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer (4082) further comprises germanium. In one embodiment, the metal silicide layer (4082) further comprises titanium.

[0322] One or more embodiments described herein relate to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. The embodiments may be applicable to or include one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0323] Certain embodiments may include preparing a titanium or similar metal layer using low-temperature (e.g., less than 500°C, or in the range of 400 to 500°C) chemical vapor deposition of a contact metal to provide a conformal source or drain contact. Implementation of such a conformal source or drain contact can improve three-dimensional (3D) transistor CMOS (complementary metal oxide semiconductor) performance.

[0324] To provide context, metal-semiconductor contact layers can be deposited using sputtering. Sputtering is a line-of-sight process and may not be very suitable for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on device contact surfaces depending on the deposition angle of incidence.

[0325] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented for the fabrication of a contact metal to provide conformality in three dimensions and to maximize the metal-semiconductor junction contact area. The resulting larger contact area can reduce the resistance of the junction. The embodiments may include deposition on semiconductor surfaces having a non-flat topography, wherein a topography of one region refers to the surface shapes and features themselves, and the non-flat topography includes non-flat surface shapes and features, i.e., surface shapes and features that are not completely flat, and parts of surface shapes and features.

[0326] The embodiments described herein may include the fabrication of wrap-around contact structures. In one such embodiment, the use of a pure metal is described for conformal deposition on transistor source-drain contacts by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition. Such conformal deposition can be used to improve the performance of transistor devices by increasing the available metal-semiconductor contact area and reducing resistance. In one embodiment, a relatively low deposition temperature results in minimized resistance of the junction per unit area.

[0327] It should be recognized that various integrated circuit structures can be manufactured using an integration scheme involving a metal layer deposition process as described in this specification. According to one embodiment of the present disclosure, a method for manufacturing an integrated circuit structure comprises the step of providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, wherein the substrate has features thereon. The method also comprises the step of reacting titanium tetrachloride (TiCl4) with hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0328] In one embodiment, the titanium layer has a total atomic composition comprising more than 98% titanium and 0.5 to 2% chlorine. In alternative embodiments, a similar process is used to produce high-purity metal layers of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In one embodiment, film thickness variation is relatively small; for example, in one embodiment, the total coverage is greater than 50% and the nominal coverage is greater than 70% (i.e., thickness variation of 30% or less). In one embodiment, the thickness on silicon (Si) or silicon germanium (SiGe) is measurably thicker than on other surfaces because Si or SiGe reacts during deposition and accelerates the uptake of Ti. In one embodiment, the film composition contains approximately 0.5% Cl (or less than 1%) as an impurity, and other observed impurities are essentially absent. In one embodiment, the deposition process enables metal coverage on non-visible surfaces, such as surfaces obscured by the sputter deposition line of sight. The embodiments described herein may be implemented to improve transistor device operation by reducing the external resistance of the current driven through the source and drain contacts.

[0329] According to one embodiment of the present disclosure, a feature of the substrate is a source or drain contact trench that exposes a semiconductor source or drain structure. A titanium layer (or other high-purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. Exemplary embodiments of such an implementation are described below in connection with FIGS. 41a, 41b, 42, 43a through 43c and 44.

[0330] FIG. 41a illustrates a cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to one embodiment of the present disclosure.

[0331] Referring to FIG. 41a, a semiconductor structure (4100) includes a gate structure (4102) on a substrate (4104). The gate structure (4102) includes a gate dielectric layer (4102A), a work function layer (4102B), and a gate filler (4102C). A source region (4108) and a drain region (4110) are located on both sides of the gate structure (4102). Source or drain contacts (4112) are electrically connected to the source region (4108) and the drain region (4110) and are spaced apart from the gate structure (4102) by one or both of an interlayer dielectric layer (4114) or gate dielectric spacers (4116). The source region (4108) and the drain region (4110) are regions of the substrate (4104).

[0332] In one embodiment, the source or drain contacts (4112) comprise a high-purity metal layer (4112A) and a conductive trench filling material (4112B) as described above. In one embodiment, the high-purity metal layer (4112A) has an overall atomic composition comprising 98% or more titanium. In one such embodiment, the overall atomic composition of the high-purity metal layer (4112A) further comprises 0.5 to 2% chlorine. In one embodiment, the high-purity metal layer (4112A) has a thickness variation of 30% or less. In one embodiment, the conductive trench filling material (4112B) is made of a conductive material such as Cu, Al, W, or an alloy thereof—not limited to these.

[0333] FIG. 41b illustrates a cross-sectional view of another semiconductor device having a conductive contact on a raised source or drain region according to one embodiment of the present disclosure.

[0334] Referring to FIG. 41b, a semiconductor structure (4150) includes a gate structure (4152) on a substrate (4154). The gate structure (4152) includes a gate dielectric layer (4152A), a work function layer (4152B), and a gate filler (4152C). A source region (4158) and a drain region (4160) are located on both sides of the gate structure (4152). Source or drain contacts (4162) are electrically connected to the source region (4158) and the drain region (4160) and are spaced apart from the gate structure (4152) by one or both of an interlayer dielectric layer (4164) or gate dielectric spacers (4166). The source region (4158) and drain region (4160) are epitaxial or embedded material regions formed in the etched-out regions of the substrate (4154). As illustrated, in one embodiment, the source region (4158) and drain region (4160) are raised source and drain regions. In this particular embodiment, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

[0335] In one embodiment, the source or drain contacts (4162) comprise a high-purity metal layer (4162A) and a conductive trench filler material (4162B) as described above. In one embodiment, the high-purity metal layer (4162A) has an overall atomic composition comprising 98% or more titanium. In one such embodiment, the overall atomic composition of the high-purity metal layer (4162A) further comprises 0.5 to 2% chlorine. In one embodiment, the high-purity metal layer (4162A) has a thickness variation of 30% or less. In one embodiment, the conductive trench filler material (4162B) is made of a conductive material such as Cu, Al, W, or an alloy thereof—not limited to these.

[0336] Accordingly, in one embodiment, referring collectively to FIG. 41a and FIG. 41b, the integrated circuit structure comprises a feature having a surface (a source or drain contact trench exposing a semiconductor source or drain structure). A high-purity metal layer (4112A or 4162A) is on the surface of the source or drain contact trench. It should be recognized that contact formation processes may involve the consumption of exposed silicon or germanium or silicon germanium material in the source or drain regions. Such consumption may degrade device performance. In contrast, according to one embodiment of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not eroded or consumed, or is substantially not eroded or consumed beneath the source or drain contact trench. In one of these embodiments, the absence of consumption or erosion is due to the low-temperature deposition of the high-purity metal contact layer.

[0337] FIG. 42 illustrates a plan view of a plurality of gate lines above a pair of semiconductor pins according to one embodiment of the present disclosure.

[0338] Referring to FIG. 42, a plurality of active gate lines (4204) are formed above a plurality of semiconductor pins (4200). Dummy gate lines (4206) are at the ends of the plurality of semiconductor pins (4200). The gaps (4208) between the gate lines (4204 / 4206) are locations where trench contacts can be formed as conductive contacts for source or drain regions, such as source or drain regions (4251, 4252, 4253, and 4254).

[0339] FIGS. 43a to 43c illustrate slightly projected cross-sectional views cut along the aa' axis of FIG. 42 for various operations in a method for manufacturing an integrated circuit structure according to one embodiment of the present disclosure.

[0340] Referring to FIG. 43a, a plurality of active gate lines (4304) are formed on a semiconductor pin (4302) formed on a substrate (4300). Dummy gate lines (4306) are located at the ends of the semiconductor pin (4302). A dielectric layer (4310) is located between the active gate lines (4304), between the dummy gate lines (4306) and the active gate lines (4304), and on the outside of the dummy gate lines (4306). Embedded source or drain structures (4308) are located within the semiconductor pin (4302) between the active gate lines (4304) and between the dummy gate lines (4306) and the active gate lines (4304). The active gate lines (4304) include a gate dielectric layer (4312), a work function gate electrode portion (4314) and a charge gate electrode portion (4316), and a dielectric capping layer (4318). Dielectric spacers (4320) line the sidewalls of the active gate lines (4304) and dummy gate lines (4306).

[0341] Referring to FIG. 43b, a portion of the dielectric layer (4310) between the active gate lines (4304) and between the dummy gate lines (4306) and the active gate lines (4304) is removed to provide openings (4330) at locations where trench contacts are to be formed. As illustrated in FIG. 43b, the removal of the portion of the dielectric layer (4310) between the active gate lines (4304) and between the dummy gate lines (4306) and the active gate lines (4304) may result in the erosion of the embedded source or drain structures (4308) to provide eroded embedded source or drain structures (4332) that may have an upper saddle-shaped topography.

[0342] Referring to FIG. 43c, trench contacts (4334) are formed in the openings (4330) between the active gate lines (4304) and between the dummy gate lines (4306) and the active gate lines (4304). Each of the trench contacts (4334) may include a metal contact layer (4336) and a conductive filler material (4338).

[0343] FIG. 44 illustrates a cross-sectional view taken along the bb' axis of FIG. 42 of an integrated circuit structure according to one embodiment of the present disclosure.

[0344] Referring to FIG. 44, pins (4402) are shown on a substrate (4400). The lower portions of the pins (4402) are surrounded by a trench isolation material (4404). The upper portions of the pins (4402) are removed to enable the growth of embedded source and drain structures (4406). A trench contact (4408) is formed within an opening of the dielectric layer (4410), and the opening exposes the embedded source and drain structures (4406). The trench contact may include a metal contact layer (4412) and a conductive filler material (4414). According to one embodiment, as shown in FIG. 44, it should be noted that the metal contact layer (4412) extends to the top of the trench contact (4408). However, in another embodiment, the metal contact layer (4412) is not extended to the top of the trench contact (4408) but is reset to some extent within the trench contact (4408), similar to the illustration of the metal contact layer (4336) in FIG. 43c.

[0345] Accordingly, referring collectively to FIG. 42, FIG. 43a through 43c and FIG. 44, according to one embodiment of the present disclosure, an integrated circuit structure comprises semiconductor pins (4200, 4302, 4402) on a substrate (4300, 4400). The semiconductor pins (4200, 4302, 4402) have tops and sidewalls. A gate electrode (4204, 4304) is located above the top of a portion of the semiconductor pins (4200, 4302, 4402) and adjacent to its sidewalls. The gate electrode (4204, 4304) defines a channel region within the semiconductor pins (4200, 4302, 4402). The first semiconductor source or drain structure (4251, 4332, 4406) is located at the first end of the channel region on the first side of the gate electrode (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non-flat topography. The second semiconductor source or drain structure (4252, 4332, 4406) is located at the second end of the channel region on the second side of the gate electrode (4204, 4304), the second end is on the opposite side of the first end, and the second side is on the opposite side of the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-flat topography. The metal contact material (4336, 4412) is located directly above the first semiconductor source or drain structure (4251, 4332, 4406) and directly above the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) is conformal to the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conformal to the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0346] In one embodiment, the metal contact material (4336, 4412) has an overall atomic composition comprising 95% or more of a single metal species. In one such embodiment, the metal contact material (4336, 4412) has an overall atomic composition comprising 98% or more of titanium. In this particular embodiment, the overall atomic composition of the metal contact material (4336, 4412) further comprises 0.5 to 2% of chlorine. In one embodiment, the metal contact material (4336, 4412) has a thickness variation of 30% or less along the uneven topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the uneven topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0347] In one embodiment, for example as illustrated in FIG. 44, both the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) include raised central portions and lower side portions. In one embodiment, for example as illustrated in FIG. 43c, both the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) include saddle-shaped portions.

[0348] In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) comprise silicon. In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) further comprise germanium, for example, in the form of silicon germanium.

[0349] In one embodiment, a metal contact material (4336, 4412) immediately above the first semiconductor source or drain structure (4251, 4332, 4406) is additionally located along the sidewalls of a trench within a dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), and the trench exposes a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In one such embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trench is thinned from 4336A in the first semiconductor source or drain structure (4332) to a location (4336B) above the first semiconductor source or drain structure (4332), an example thereof is illustrated in FIG. 43c. In one embodiment, as shown in FIG. 43c and FIG. 44, a conductive filler material (4338, 4414) is on a metal contact material (4336, 4412) in a trench.

[0350] In one embodiment, the integrated circuit structure further comprises a second semiconductor pin (e.g., the top pin (4200), 4302, 4402) having a top and side walls. A gate electrode (4204, 4304) is additionally located above the top of a portion of the second semiconductor pin and adjacent to its side walls, and the gate electrode defines a channel region within the second semiconductor pin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at the first end of the channel region of the second semiconductor pin on the first side of the gate electrode (4204, 4304), and the third semiconductor source or drain structure has a non-flat topography. The fourth semiconductor source or drain structure (4254, 4332, 4406) is located at the second end of the channel region of the second semiconductor pin on the second side of the gate electrode (4204, 4304), the second end is on the opposite side of the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) has a non-flat topography. The metal contact material (4336, 4412) is located directly above the third semiconductor source or drain structure (4253, 4332, 4406) and directly above the fourth semiconductor source or drain structure (4254, 4332, 4406), and the metal contact material (4336, 4412) is conformal to the non-flat topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conformal to the non-flat topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In one embodiment, the metal contact material (4336, 4412) is continuous between the first semiconductor source or drain structure (4251, 4332, left 4406) and the third semiconductor source or drain structure (4253, 4332, right 4406) and is continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0351] In another embodiment, a hard mask material may be used to preserve (prevent erosion) and may be maintained above a dielectric material at trench line locations where conductive trench contacts are interrupted, e.g., at contact plug locations. For example, FIG. 45a and FIG. 45b respectively illustrate a plan view and a corresponding cross-sectional view of an integrated circuit structure comprising trench contact plugs—having a hard mask material thereon—according to one embodiment of the present disclosure.

[0352] Referring to FIG. 45a and FIG. 45b, in one embodiment, an integrated circuit structure (4500) includes a pin (4502A), such as a silicon pin. A plurality of gate structures (4506) are located above the pin (4502A). Each of the gate structures (4506) is located along a direction (4508) orthogonal to the pin (4502A) and has a pair of dielectric sidewall spacers (4510). A trench contact structure (4512) is located above the pin (4502A) and immediately between the dielectric sidewall spacers (4510) of the first pair of gate structures (4506A / 4506B) of the gate structures (4506). The contact plug (4514B) is located above the pin (4502A) and directly between the dielectric sidewall spacers (4510) of the second pair of gate structures (4506B / 4506C) of the gate structures (4506). The contact plug (4514B) comprises a lower dielectric material (4516) and an upper hardmask material (4518).

[0353] In one embodiment, the lower dielectric material (4516) of the contact plug (4514B) comprises silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material (4518) of the contact plug (4514B) comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-deficient nitride material.

[0354] In one embodiment, the trench contact structure (4512) comprises a lower conductive structure (4520) and a dielectric cap (4522) on the lower conductive structure (4520). In one embodiment, as illustrated, the dielectric cap (4522) of the trench contact structure (4512) has an upper surface that is coplanar with the upper surface of the upper hard mask material (4518) of the contact plug (4514B).

[0355] In one embodiment, each of the plurality of gate structures (4506) includes a gate electrode (4524) on the gate dielectric layer (4526). A dielectric cap (4528) is on the gate electrode (4524). In one embodiment, as illustrated, the dielectric cap (4528) of each of the plurality of gate structures (4506) has an upper surface that is coplanar with the upper surface of the upper hard mask material (4518) of the contact plug (4514B). In one embodiment, although not illustrated, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the pin (4502A) and the gate dielectric layer (4526).

[0356] Referring again to FIG. 45a and FIG. 45b, in one embodiment, an integrated circuit structure (4500) comprises a plurality of pins (4502), such as a plurality of silicon pins. Individuals of the plurality of pins (4502) are located along a first direction (4504). A plurality of gate structures (4506) are located above the plurality of pins (4502). Individuals of the plurality of gate structures (4506) are located along a second direction (4508) orthogonal to the first direction (4504). Individuals of the plurality of gate structures (4506) have a pair of dielectric sidewall spacers (4510). A trench contact structure (4512) is located above the first pin (4502A) of the plurality of pins (4502) and immediately between the dielectric sidewall spacers (4510) of the pair of gate structures (4506). The contact plug (4514A) is located above the second pin (4502B) of the plurality of pins (4502) and directly between the dielectric sidewall spacers (4510) of a pair of gate structures (4506). Similar to the cross-sectional view of the contact plug (4514B), the contact plug (4514A) comprises a lower dielectric material (4516) and an upper hardmask material (4518).

[0357] In one embodiment, the lower dielectric material (4516) of the contact plug (4516A) comprises silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material (4518) of the contact plug (4516A) comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-deficient nitride material.

[0358] In one embodiment, the trench contact structure (4512) comprises a lower conductive structure (4520) and a dielectric cap (4522) on the lower conductive structure (4520). In one embodiment, as illustrated, the dielectric cap (4522) of the trench contact structure (4512) has an upper surface that is coplanar with the upper surface of the upper hard mask material (4518) of the contact plug (4514A or 4514B).

[0359] In one embodiment, each of the plurality of gate structures (4506) includes a gate electrode (4524) on the gate dielectric layer (4526). A dielectric cap (4528) is on the gate electrode (4524). In one embodiment, as illustrated, the dielectric cap (4528) of each of the plurality of gate structures (4506) has an upper surface that is coplanar with the upper surface of the upper hard mask material (4518) of the contact plug (4514A or 4514B). In one embodiment, although not illustrated, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the pin (4502A) and the gate dielectric layer (4526).

[0360] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process may be implemented to form contact structures for manufacturing semiconductor structures, e.g., for manufacturing integrated circuits. In one embodiment, a contact pattern is formed aligned with an existing gate pattern. Alternatively, other approaches typically involve an additional lithography process having tight registration of the lithographic contact pattern with respect to the existing gate pattern, along with selective contact etchings. For example, other processes may include patterning a poly (gate) grid by separately patterning the contacts and contact plugs.

[0361] According to one or more embodiments described herein, a contact formation method involves forming a contact pattern that is essentially perfectly aligned with an existing gate pattern while eliminating the use of lithography operations with a very strict alignment budget. In one such embodiment, this approach enables the use of wet etching, which is essentially highly selective (compared to dry or plasma etching, for example), to create contact openings. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for lithography operations that would otherwise be significant to create the contact pattern, as is used in other approaches. In one embodiment, a trench contact grid is not patterned separately but is rather formed between the poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed following the gate grating patterning but preceding the gate grating cuts.

[0362] FIGS. 46a through 46d illustrate cross-sectional views illustrating various operations in a method for manufacturing an integrated circuit structure comprising trench contact plugs—having a hard mask material thereon—according to one embodiment of the present disclosure.

[0363] Referring to FIG. 46a, a method for manufacturing an integrated circuit structure comprises the step of forming a plurality of pins—individuals (4602) of the plurality of pins along a first direction (4604). Individuals (4602) of the plurality of pins may include diffusion regions (4606). A plurality of gate structures (4608) are formed above the plurality of pins. Individuals of the plurality of gate structures (4508) are along a second direction (4610) orthogonal to the first direction (4604) (e.g., the direction (4610) goes into and out of the ground). A sacrificial material structure (4612) is formed between a first pair of gate structures of the gate structures (4608). A contact plug (4614) is formed between a second pair of gate structures of the gate structures (4608). The contact plug includes a lower dielectric material (4616). The hard mask material (4618) is on the lower dielectric material (4616).

[0364] In one embodiment, the gate structures (4608) include sacrificial or dummy gate stacks and dielectric spacers (4609). The sacrificial or dummy gate stacks may be made of polycrystalline silicon or silicon nitride pillars or any other sacrificial material, which may be referred to as gate dummy material.

[0365] Referring to FIG. 46b, a sacrificial material structure (4612) is removed from the structure of FIG. 46a to form an opening (4620) between the first pair of gate structures (4608).

[0366] Referring to FIG. 46c, a trench contact structure (4622) is formed within the opening (4620) between the first pair of gate structures (4608). In addition, in one embodiment, as part of the step of forming the trench contact structure (4622), the hard mask (4618) of FIG. 46a and FIG. 46b is flattened. The ultimately finished contact plugs (4614') comprise an upper hard mask material (4624) formed from the lower dielectric material (4616) and the hard mask material (4618).

[0367] In one embodiment, the lower dielectric material (4616) of each contact plug (4614') comprises silicon and oxygen, and the upper hard mask material (4624) of each contact plug (4614') comprises silicon and nitrogen. In one embodiment, each trench contact structure (4622) comprises a lower conductive structure (4626) and a dielectric cap (4628) on the lower conductive structure (4626). In one embodiment, the dielectric cap (4628) of the trench contact structure (4622) has an upper surface that is coplanar with the upper surface of the upper hard mask material (4624) of the contact plug (4614').

[0368] Referring to FIG. 46d, in an alternative gate process scheme, the sacrificial or dummy gate stacks of the gate structures (4608) are replaced. In this scheme, the dummy gate material, such as polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, unlike in a more prior processing.

[0369] Accordingly, the permanent gate structures (4630) include a permanent gate dielectric layer (4632) and a permanent gate electrode layer or stack (4634). In addition, in one embodiment, the top portion of the permanent gate structures (4630) is removed, for example, by an etching process and replaced with a dielectric cap (4636). In one embodiment, the dielectric cap (4636) of each of the permanent gate structures (4630) has an upper surface that is coplanar with the upper surface of the upper hardmask material (4624) of the contact plugs (4614').

[0370] Referring again to FIGS. 46a through 46d, in one embodiment, as illustrated, an alternative gate process is performed following the formation of trench contact structures (4622). However, according to other embodiments, the alternative gate process is performed prior to the formation of trench contact structures (4622).

[0371] In other embodiments, COAG (contact over active gate) structures and processes are described. One or more embodiments of the present disclosure relate to semiconductor structures or devices having one or more gate contact structures disposed over the active portions of the gate electrodes of the semiconductor structures or devices (e.g., as gate contact vias). One or more embodiments of the present disclosure relate to methods for manufacturing semiconductor structures or devices having one or more gate contact structures formed over the active portions of the gate electrodes of the semiconductor structures or devices. The approaches described herein can be used to reduce standard cell area by enabling the formation of gate contacts over active gate regions. In one or more embodiments, the gate contact structures manufactured to contact the gate electrodes are self-aligned via structures.

[0372] In technologies where spatial and layout constraints are somewhat relaxed compared to those of the current generation, a contact to a gate structure can be made by contacting a portion of a gate electrode placed above an isolation region. As an example, FIG. 47a illustrates a plan view of a semiconductor device having a gate contact placed above an inactive portion of a gate electrode.

[0373] Referring to FIG. 47a, a semiconductor structure or device (4700A) comprises a diffusion or active region (4704) disposed on a substrate (4702) and within an isolation region (4706). One or more gate lines (also known as poly lines), such as gate lines (4708A, 4708B, and 4708C), are disposed above the diffusion or active region (4704) as well as above a portion of the isolation region (4706). Source or drain contacts (also known as trench contacts), such as contacts (4710A and 4710B), are disposed above the source and drain regions of the semiconductor structure or device (4700A). Trench contact vias (4712A and 4712B) each provide contact to the trench contacts (4710A and 4710B). A separate gate contact (4714) and a gate contact via (4716) above it provide contact to the gate line (4708B). Unlike the source or drain trench contacts (4710A or 4710B), the gate contact (4714) is positioned above the isolation region (4706) in a plan view, but not above the diffusion or active region (4704). Furthermore, neither the gate contact (4714) nor the gate contact via (4716) is positioned between the source or drain trench contacts (4710A and 4710B).

[0374] FIG. 47b illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact positioned above an inactive portion of a gate electrode. Referring to FIG. 47b, a semiconductor structure or device (4700B), such as a non-planar version of the device (4700A) of FIG. 47a, comprises a non-planar diffusion or active region (4704C) (e.g., a pin structure) formed from a substrate (4702) and within an isolation region (4706). A gate line (4708B) is positioned above a portion of the isolation region (4706) as well as the non-planar diffusion or active region (4704B). As illustrated, the gate line (4708B) comprises a gate electrode (4750) and a gate dielectric layer (4752), together with a dielectric cap layer (4754). The gate contact (4714) and the gate contact via (4716) above it are also seen in this view, together with the metal interconnect (4760) above it, all of which are placed within the interlayer dielectric stacks or layers (4770). Also, as seen in view of FIG. 47b, the gate contact (4714) is placed above the isolation region (4706) but not above the non-planar diffusion or active region (4704B).

[0375] Referring again to FIGS. 47a and 47b, the arrangement of the semiconductor structure or device (4700A and 4700B) places the gate contact above the isolation regions, respectively. This arrangement wastes layout space. However, placing the gate contact above the active regions would require an extremely tight alignment budget, or the gate dimensions would need to be increased to provide sufficient space to land the gate contact. Furthermore, in the past, contact with the gate above the diffusion regions was avoided due to the risk of contacting the underlying active region by drilling through a different gate material (e.g., polysilicon). One or more embodiments described herein address the above issues by providing feasible approaches and resulting structures for manufacturing contact structures that contact portions of the gate electrode formed above the diffusion or active regions.

[0376] As an example, FIG. 48a illustrates a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to one embodiment of the present disclosure. Referring to FIG. 48a, a semiconductor structure or device (4800A) includes a diffusion or active region (4804) disposed on a substrate (4802) and within an isolation region (4806). One or more gate lines, such as gate lines (4808A, 4808B, and 4808C), are disposed above the diffusion or active region (4804) as well as above a portion of the isolation region (4806). Source or drain contacts, such as trench contacts (4810A and 4810B), are disposed above the source and drain regions of the semiconductor structure or device (4800A). Trench contact vias (4812A and 4812B) each provide contact to trench contacts (4810A and 4810B). A gate contact via (4816), which does not have a separate interposed gate contact layer, provides contact to the gate line (4808B). Unlike FIG. 47a, the gate contact (4816) is positioned above the diffusion or active region (4804) and between the source or drain contacts (4810A and 4810B) in view of the plan.

[0377] FIG. 48b illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed above an active portion of a gate electrode according to one embodiment of the present disclosure. Referring to FIG. 48b, a semiconductor structure or device (4800B), such as a non-planar version of the device (4800A) of FIG. 48a, comprises a non-planar diffusion or active region (4804B) (e.g., a pin structure) formed from a substrate (4802) and within an isolation region (4806). A gate line (4808B) is disposed above a portion of the isolation region (4806) as well as the non-planar diffusion or active region (4804B). As illustrated, the gate line (4808B) comprises a gate electrode (4850) and a gate dielectric layer (4852), together with a dielectric cap layer (4854). A gate contact via (4816) is also seen in this view, together with the metal interconnect (4860) above, all of which are placed within the interlayer dielectric stacks or layers (4870). Also, as seen in view of FIG. 48b, the gate contact via (4816) is placed above the non-planar diffusion or active region (4804B).

[0378] Accordingly, referring again to FIGS. 48a and 48b, in one embodiment, trench contact vias (4812A, 4812B) and a gate contact via (4816) are formed within the same layer and are essentially coplanar. Compared to FIGS. 47a and 47b, the contact for the gate line would otherwise include an additional gate contact layer that could extend perpendicularly to the corresponding gate line, for example. However, in the structure(s) described in relation to FIGS. 48a and 48b, the fabrication of the structures (4800A and 4800B) respectively makes it possible to land the contact directly from the metal interconnect layer on the active gate portion without shorting adjacent source-drain regions. In one embodiment, this arrangement provides a significant reduction in area in the circuit layout by eliminating the need to extend transistor gates over isolation to form reliable contacts. As used throughout, in one embodiment, the reference to the active portion of the gate refers to that portion of the gate line or structure positioned above the active or diffusion region of the substrate below (in view of the plan). In one embodiment, the reference to the inactive portion of the gate refers to that portion of the gate line or structure positioned above the isolation region of the substrate below (in view of the plan).

[0379] In one embodiment, the semiconductor structure or device (4800) is a non-planar device such as a fin-FET or a tri-gate device—not limited to these. In this embodiment, the corresponding semiconducting channel region is made of or formed within a three-dimensional body. In one such embodiment, the gate electrode stacks of the gate lines (4808A to 4808C) surround at least the top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made of a separate three-dimensional body, as in a gate-all-around device. In one such embodiment, each of the gate electrode stacks of the gate lines (4808A to 4808C) completely surrounds the channel region.

[0380] More generally, one or more embodiments relate to approaches for landing gate contact vias directly above the active transistor gate and structures formed therefrom. These approaches may eliminate the need for extending the gate line on the isolation portion for contact purposes. These approaches may also eliminate the need for a separate gate contact (GCN) layer for conducting signals from the gate line or structure. In one embodiment, eliminating the above features is achieved by resetting the contact metals within the trench contact (TCN) in the process flow and introducing an additional dielectric material (e.g., TILA). The additional dielectric material is included as a trench contact dielectric cap layer having different etching characteristics from the gate dielectric material cap layer already used for trench contact alignment in the gate alignment contact process (GAP) processing scheme (e.g., GILA).

[0381] As an exemplary manufacturing scheme, FIGS. 49a through 49d illustrate cross-sectional views illustrating various operations in a method for manufacturing a semiconductor structure having a gate contact structure disposed above an active portion of a gate, according to one embodiment of the present disclosure.

[0382] Referring to FIG. 49a, a semiconductor structure (4900) is provided after the formation of trench contacts (TCN). It should be recognized that a specific arrangement of the structure (4900) is used for illustrative purposes only and that various possible layouts may benefit from the embodiments of the disclosure described herein. The semiconductor structure (4900) includes one or more gate stack structures, such as gate stack structures (4908A to 4908E) disposed on a substrate (4902). The gate stack structures may include a gate dielectric layer and a gate electrode. Trench contacts, such as trench contacts (4910A to 4910C), for example, contacts to diffusion regions of the substrate (4902), are also included in the structure (4900) and are spaced apart from the gate stack structures (4908A to 4908E) by dielectric spacers (4920). As also illustrated in FIG. 49a, an insulating cap layer (4922) may be disposed on gate stack structures (4908A to 4908E) (e.g., GILA). As also illustrated in FIG. 49a, contact blocking regions or "contact plugs," such as a region (4923) made of an interlayer dielectric material, may be included in the regions where contact formation is to be blocked.

[0383] In one embodiment, providing the structure (4900) involves forming a contact pattern that is essentially perfectly aligned with the existing gate pattern while eliminating the use of lithography operations with a very strict alignment budget. In one such embodiment, this approach enables the use of wet etching, which is essentially highly selective (compared to dry or plasma etching, for example), to create contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for lithography operations that would otherwise be significant to create the contact pattern, as is used in other approaches. In one embodiment, the trench contact grid is not patterned separately but is rather formed between the poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed following the gate grating patterning but preceding the gate grating cuts.

[0384] Additionally, the gate stack structures (4908A to 4908E) may be manufactured by an alternative gate process. In this scheme, a dummy gate material, such as a polysilicon or silicon nitride pillar material, is removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, unlike in a more earlier processing. In one embodiment, the dummy gates are removed by a dry etching or wet etching process. In one embodiment, the dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a dry etching process involving SF6. In another embodiment, the dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a wet etching process involving aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are made of silicon nitride and are removed using a wet etching process involving aqueous phosphoric acid.

[0385] In one embodiment, one or more approaches described herein are considered to essentially combine a dummy and alternate gate process with a dummy and alternate contact process to reach a structure (4900). In one such embodiment, the alternate contact process is performed after the alternate gate process to enable high-temperature annealing of at least one portion of the permanent gate stack. For example, in this particular embodiment, annealing of at least one portion of the permanent gate structures is performed at a temperature of approximately 600°C or higher, for example, after the gate dielectric layer is formed. The annealing is performed prior to the formation of the permanent contacts.

[0386] Referring to FIG. 49b, trench contacts (4910A to 4910C) of a structure (4900) are recessed within the spacers (4920) to provide recessed trench contacts (4911A to 4911C) having a height below the top surface of the spacers (4920) and the insulating cap layer (4922). An insulating cap layer (4924) is subsequently formed on the recessed trench contacts (4911A to 4911C) (e.g., TILA). According to one embodiment of the present disclosure, the insulating cap layer (4924) on the recessed trench contacts (4911A to 4911C) is made of a material having different etching properties than the insulating cap layer (4922) on the gate stack structures (4908A to 4908E). As will be seen in subsequent processing operations, this difference can be used to selectively etch one of the 4922 / 4924 against the other of the 4922 / 4924.

[0387] The trench contacts (4910A to 4910C) may be reset by an optional process on the materials of the spacers (4920) and the insulating cap layer (4922). For example, in one embodiment, the trench contacts (4910A to 4910C) are reset by an etching process such as a wet etching process or a dry etching process. The insulating cap layer (4924) may be formed by a process suitable for providing a conformal sealing layer over the exposed portions of the trench contacts (4910A to 4910C). For example, in one embodiment, the insulating cap layer (4924) is formed as a conformal layer over the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is subsequently flattened, for example by chemical mechanical polishing (CMP), to provide insulating cap layer (4924) material only over the trench contacts (4910A to 4910C) and to re-expose the spacers (4920) and the insulating cap layer (4922).

[0388] Regarding suitable material combinations for the insulating cap layers (4922 / 4924), in one embodiment, one of the pair of 4922 / 4924 is made of silicon oxide while the other is made of silicon nitride. In another embodiment, one of the pair of 4922 / 4924 is made of silicon oxide while the other is made of carbon-doped silicon nitride. In another embodiment, one of the pair of 4922 / 4924 is made of silicon oxide while the other is made of silicon carbide. In another embodiment, one of the pair of 4922 / 4924 is made of silicon nitride while the other is made of carbon-doped silicon nitride. In another embodiment, one of the pair of 4922 / 4924 is made of silicon nitride while the other is made of silicon carbide. In another embodiment, one of the pair of 4922 / 4924 is made of carbon-doped silicon nitride while the other is made of silicon carbide.

[0389] Referring to FIG. 49c, an interlayer dielectric (ILD) (4930) and a hard mask (4932) stack are formed and patterned to provide a metal (0) trench (4934) patterned on, for example, the structure of FIG. 49b.

[0390] The interlayer dielectric (ILD) (4930) may be made of a material suitable for electrically isolating metal features ultimately formed therein while maintaining a robust structure between front-end processing and back-end processing. Furthermore, in one embodiment, as described in more detail below in relation to FIG. 49d, the composition of the ILD (4930) is selected to match via etching selectivity for trench contact dielectric cap layer patterning. In one embodiment, the ILD (4930) is made of a single or several layers of silicon oxide or a single or several layers of carbon-doped oxide (CDO) material. However, in other embodiments, the ILD (4930) has a bi-layer composition having an underlying bottom portion and an upper portion made of a different material. The hard mask layer (4932) may be made of a material suitable for functioning as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer (4932) is substantially made of carbon, for example, as a layer of a cross-linked organic polymer. In other embodiments, a silicon nitride or carbon-doped silicon nitride layer is used as the hard mask (4932). The stack of the interlayer dielectric (ILD) (4930) and the hard mask (4932) can be patterned by a lithography and etching process.

[0391] Referring to FIG. 49d, via openings (4936) (e.g., VCT) extending from one or more of the recessed trench contacts (4911A to 4911C) from the metal (0) trench (4934) are formed within the interlayer dielectric (ILD) (4930). For example, in FIG. 49d, the via openings are formed to expose the recessed trench contacts (4911A and 4911C). The formation of the via openings (4936) involves etching both portions of the interlayer dielectric (ILD) (4930) and the corresponding insulating cap layer (4924). In one such embodiment, a portion of the insulating cap layer (4922) is exposed during patterning of the interlayer dielectric (ILD) (4930) (e.g., a portion of the insulating cap layer (4922) above the gate stack structures (4908B and 4908E) is exposed). In that embodiment, the insulating cap layer (4924) is etched to form via openings (4936) optionally with respect to the insulating cap layer (4922) (i.e., without significantly etching or affecting the insulating cap layer (4922)).

[0392] In one embodiment, without etching the insulating cap layer (4922) (i.e., gate insulating cap layers), the via opening pattern is ultimately transferred to the insulating cap layer (4924) (i.e., trench contact insulating cap layers) by an etching process. The insulating cap layer (4924) (TILA) may be made of any or a combination thereof, including silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitrides, carbon-doped silicon oxides, amorphous silicon, various metal oxides, and silicates—including zirconium oxide, hafnium oxide, lanthanum oxide, or combinations thereof. The layer may be deposited using any of the techniques including CVD, ALD, PECVD, PVD, HDP-assisted CVD, and low-temperature CVD. A corresponding plasma dry etching is developed as a combination of chemical and physical sputtering mechanisms. Coincident polymer deposition may be used to control the material removal rate, etching profiles, and film selectivity. Dry etching is typically performed using a mixture of gases including NF3, CHF3, C4F8, HBr, and O2, typically having pressures in the range of 30 to 100 mTorr and a plasma bias of 50 to 1000 watts. Dry etching may be engineered to achieve significant etching selectivity between the cap layer (4924)(TILA) and the cap layer (4922)(GILA) to minimize loss of the 4922(GILA) during the dry etching of the 4924(TILA) to form contacts for the source-drain regions of the transistor.

[0393] Referring again to FIG. 49d, it should be recognized that a similar approach can be implemented to manufacture a via opening pattern that is ultimately transferred to an insulating cap layer (4922) (i.e., trench contact insulating cap layers) by an etching process without etching the insulating cap layer (4924) (i.e., gate insulating cap layers).

[0394] To further illustrate concepts of COAG (contact over active gate) technology, FIG. 50 illustrates a plan view and corresponding cross-sectional views of an integrated circuit structure having trench contacts including an insulating cap layer above, according to one embodiment of the present disclosure.

[0395] Referring to FIG. 50, an integrated circuit structure (5000) includes a gate line (5004) on a semiconductor substrate or pin (5002), such as a silicon pin. The gate line (5004) includes a gate stack (5005) (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating cap layer (5006) on the gate stack (5005). As illustrated, dielectric spacers (5008) are along the sidewalls of the gate stack (5005) and, in one embodiment, along the sidewalls of the gate insulating cap layer (5006).

[0396] Trench contacts (5010) are adjacent to the sidewalls of the gate line (5004), and dielectric spacers (5008) are located between the gate line (5004) and the trench contacts (5010). Each of the trench contacts (5010) comprises a conductive contact structure (5011) and a trench contact insulating cap layer (5012) on the conductive contact structure (5011).

[0397] Referring again to FIG. 50, a gate contact via (5014) is formed within an opening of the gate insulating cap layer (5006) and electrically contacts the gate stack (5005). In one embodiment, as illustrated, the gate contact via (5014) electrically contacts the gate stack (5005), which is located above the semiconductor substrate or pin (5002) and laterally between the trench contacts (5010). In one such embodiment, the trench contact insulating cap layer (5012) on the conductive contact structure (5011) prevents gate-to-source shorting or gate-to-drain shorting caused by the gate contact via (5014).

[0398] Referring again to FIG. 50, trench contact vias (5016) are formed within the openings of the trench contact insulating cap layer (5012) and electrically contact their respective conductive contact structures (5011). In one embodiment, as illustrated, the trench contact vias (5016) electrically contact their respective conductive contact structures (5011) located on the semiconductor substrate or pin (5002) and laterally adjacent to the gate stack (5005) of the gate line (5004). In one such embodiment, the gate insulating cap layer (5006) on the gate stack (5005) prevents source-to-gate shorting or drain-to-gate shorting caused by the trench contact vias (5016).

[0399] It should be recognized that different structural relationships between an insulating gate cap layer and an insulating trench contact cap layer can be manufactured. As examples, FIGS. 51a through 51f illustrate cross-sectional views of various integrated circuit structures according to one embodiment of the present disclosure, each having trench contacts having an insulating cap layer above and gate stacks having an insulating cap layer above.

[0400] Referring to FIGS. 51a, 51b, and 51c, integrated circuit structures (5100A, 5100B, and 5100C) each include a pin (5102), such as a silicon pin. Although illustrated as a cross-sectional view, it should be recognized that the pin (5102) has a top (5102A) and sidewalls (entering and exiting the ground at the illustrated viewpoint). A first gate dielectric layer (5104) and a second gate dielectric layer (5106) are located above the top (5102A) of the pin (5102) and laterally adjacent to the sidewalls of the pin (5102). The first and second gate electrodes (5108 and 5110) are each located above the top (5102A) of the pin (5102) and above the first and second gate dielectric layers (5104 and 5106) which are laterally adjacent to the sidewalls of the pin (5102). Each of the first gate electrode (5108) and the second gate electrode (5110) comprises a conformal conductive layer (5109A), such as a workfunction-setting layer, and a conductive filler material (5109B) on the conformal conductive layer (5109A). Both the first gate electrode (5108) and the second gate electrode (5110) have a first side (5112) and a second side (5114) opposite to the first side (5112). Both the first gate electrode (5108) and the second gate electrode (5110) also have an insulating cap (5116) having a top surface (5118).

[0401] The first dielectric spacer (5120) is adjacent to the first side (5112) of the first gate electrode (5108). The second dielectric spacer (5122) is adjacent to the second side (5114) of the second gate electrode (5110). The semiconductor source or drain region (5124) is adjacent to the first dielectric spacer (5120) and the second dielectric spacer (5122). A trench contact structure (5126) is located above the semiconductor source or drain region (5124), adjacent to the first dielectric spacer (5120) and the second dielectric spacer (5122).

[0402] The trench contact structure (5126) includes an insulating cap (5128) on a conductive structure (5130). The insulating cap (5128) of the trench contact structure (5126) has a top surface (5129) that is substantially flat with the top surfaces (5118) of the insulating caps (5116) of the first gate electrode (5108) and the second gate electrode (5110). In one embodiment, the insulating cap (5128) of the trench contact structure (5126) extends laterally into the recesses (5132) within the first dielectric spacer (5120) and the second dielectric spacer (5122). In this embodiment, the insulating cap (5128) of the trench contact structure (5126) overhangs the conductive structure (5130) of the trench contact structure (5126). However, in other embodiments, the insulating cap (5128) of the trench contact structure (5126) does not extend laterally into the recesses (5132) of the first dielectric spacer (5120) and the second dielectric spacer (5122), and thus does not ove...

Claims

Claim 1 An integrated circuit structure comprising: a plurality of conductive interconnect lines located within an interlayer dielectric (ILD) layer on a substrate and spaced apart by said interlayer dielectric (ILD) layer; wherein each of said conductive interconnect lines has an upper surface below the upper surface of said ILD layer, and each of said conductive interconnect lines comprises a barrier layer along the sidewalls and bottom of a conductive filler material, and both said barrier layer and said conductive filler material have an uppermost surface below the upper surface of said ILD layer; and an etching stop layer located on said ILD layer and said conductive interconnect lines and conformal thereto with them; wherein said etching stop layer has a non-planar upper surface, the uppermost portion of said non-planar upper surface is above said ILD layer and the lowermost portion of said non-planar upper surface is above said conductive interconnect lines. An integrated circuit structure comprising a conductive via that is on each of the plurality of conductive interconnect lines and is electrically coupled thereto, wherein the conductive via is within an opening of the etching stop layer, and the opening is above each of the plurality of conductive interconnect lines but does not overlap with the upper surface of the ILD layer. Claim 2 An integrated circuit structure according to claim 1, wherein the center of the conductive via is aligned with the center of each of the plurality of conductive interconnect lines. Claim 3 An integrated circuit structure according to claim 1, wherein the center of the conductive via is offset from the center of each of the plurality of conductive interconnect lines. Claim 4 An integrated circuit structure according to claim 1, wherein the uppermost surface of the barrier layer is above the uppermost surface of the conductive filler material. Claim 5 An integrated circuit structure according to claim 1, wherein the conductive via is in a second ILD layer, and the second ILD layer is on the etching stop layer and conformal to the etching stop layer. Claim 6 An integrated circuit structure according to claim 1, wherein the ILD layer comprises silicon, carbon, and oxygen, and the etching stop layer comprises silicon and nitrogen. Claim 7 An integrated circuit structure according to claim 1, wherein the upper surface of each of the plurality of conductive interconnect lines is below the upper surface of the ILD layer by an amount ranging from 0.5 to 1.5 nanometers. Claim 8 An integrated circuit structure comprising: a plurality of conductive interconnect lines located within an interlayer dielectric (ILD) layer on a substrate and spaced apart by said interlayer dielectric (ILD) layer; wherein each of said conductive interconnect lines has an upper surface above the upper surface of said ILD layer, and each of said conductive interconnect lines comprises a barrier layer along the sidewalls and bottom of a conductive filler material, and both said barrier layer and said conductive filler material have an uppermost surface above the upper surface of said ILD layer; and an etching stop layer located on said ILD layer and said conductive interconnect lines and conformal thereto with them; wherein said etching stop layer has a non-planar upper surface, the lowermost portion of said non-planar upper surface is above said ILD layer and the uppermost portion of said non-planar upper surface is above said conductive interconnect lines. An integrated circuit structure comprising a conductive via that is on each of the plurality of conductive interconnect lines and is electrically coupled thereto, wherein the conductive via is within an opening of the etching stop layer, and the opening is above each of the plurality of conductive interconnect lines but does not overlap with the upper surface of the ILD layer. Claim 9 An integrated circuit structure according to claim 8, wherein the center of the conductive via is aligned with the center of each of the plurality of conductive interconnect lines. Claim 10 An integrated circuit structure according to claim 8, wherein the center of the conductive via is offset from the center of each of the plurality of conductive interconnect lines. Claim 11 An integrated circuit structure, wherein the uppermost surface of the barrier layer is below the uppermost surface of the conductive filler material. Claim 12 An integrated circuit structure according to claim 8, wherein the conductive via is in a second ILD layer, and the second ILD layer is on the etching stop layer and conformal to the etching stop layer. Claim 13 An integrated circuit structure according to claim 8, wherein the ILD layer comprises silicon, carbon, and oxygen, and the etching stop layer comprises silicon and nitrogen. Claim 14 An integrated circuit structure according to claim 8, wherein the upper surface of each of the plurality of conductive interconnect lines is above the upper surface of the ILD layer by an amount ranging from 0.5 to 1.5 nanometers. Claim 15 A method for manufacturing an integrated circuit structure, comprising: forming a plurality of conductive interconnect lines within a first interlayer dielectric (ILD) layer on a substrate and spaced apart by the first interlayer dielectric (ILD) layer—each of the plurality of conductive interconnect lines comprises a barrier layer along the sidewalls and bottom of a conductive filler material—; resetting the plurality of conductive interconnect lines relative to the first ILD layer to provide each of the plurality of conductive interconnect lines having an upper surface below the upper surface of the first ILD layer—the step of resetting the plurality of conductive interconnect lines comprises resetting both the barrier layer and the conductive filler material below the upper surface of the first ILD layer—; and, following the step of resetting the plurality of conductive interconnect lines, forming an etching stop layer on the first ILD layer and the plurality of conductive interconnect lines and conformally with them—the etching stop layer being a non-planar top A surface having a non-planar upper surface, wherein the uppermost portion of the non-planar upper surface is above the first ILD layer and the lowermost portion of the non-planar upper surface is above the plurality of conductive interconnect lines; a step of forming a second ILD layer on the etching stop layer; a step of etching via trenches within the second ILD layer, wherein the etching stop layer directs the position of the via trenches within the second ILD layer during etching; a step of etching the etching stop layer through the via trenches to form openings within the etching stop layer, wherein the openings are above each individual of the plurality of conductive interconnect lines but do not overlap with the upper surface of the first ILD layer;A method comprising the step of forming a conductive via within the via trench and within the opening in the etching stop layer—the conductive via being on and electrically coupled to each of the plurality of conductive interconnect lines.; Claim 16 In claim 15, the method wherein the etching stop layer re-directs a lithographically misaligned via trench pattern. Claim 17 In claim 15, the step of resetting the plurality of conductive interconnect lines comprises resetting by an amount in the range of 0.5 to 1.5 nanometers relative to the first ILD layer.

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