Merge memory commands for improved bus utilization in volatile memory

Abstract

The present disclosure provides systems, methods, and devices for memory systems that support merge memory commands for improved bus utilization in volatile memory. In a first embodiment, a method for performing operations on a memory module comprises: receiving a merge command from a host device to perform at least a precharge operation, a refresh operation, and an enable operation on one or more rows of a memory module by means of a memory controller coupled to the memory module through a first channel and configured to access data stored in the memory module through the first channel; and performing the precharge operation, the refresh operation, and the enable operation upon receiving the merge command. Other embodiments and features are also claimed and described.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 398,396, filed on December 28, 2023, with the title of the invention "MERGED MEMORY COMMANDS FOR IMPROVED BUS UTILIZATION IN VOLATILE MEMORY," the entirety of which is expressly incorporated by reference into this specification.

[0003] Technology field

[0004] Aspects of the present disclosure generally relate to computer information systems, and more specifically to memory systems for storing data. Some features may enable and provide improved bus utilization, reduced power consumption, and improved memory capabilities for merged memory commands for enhanced performance. Background Technology

[0005] Computing devices (e.g., laptops, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephone, wireless data access, and camera / video functions. A memory system is an important component of a computing device. Processors may be coupled to a memory system to perform the aforementioned computing functions. For example, processors may fetch instructions from a memory system to perform computing functions and / or store temporary data associated with performing these computing functions within the memory system.

[0006] Memory systems can utilize memory cells that are inherently volatile. Volatile memory cells retain information for short periods, such as fractions of a second. One example of an operation that can be performed on memory cells is a refresh operation. Refresh operations can be performed with volatile memory cells to retain information for longer periods. In an exemplary volatile memory cell that stores information as an electric charge, the electric charge decays over fractions of a second. Before the charge decays beyond the point of information loss, the memory cell can be refreshed to extend the time period during which the memory cell retains information. In some cases, refresh can be performed repeatedly to extend the information storage period indefinitely, or as long as power is supplied to the circuit. This refresh operation consumes power, which affects the operation of devices running on limited power sources, such as battery-powered mobile devices. Other examples of operations that can be performed on memory cells are activation operations to prepare memory cells for reading or writing, and precharge operations to deactivate memory cells after the operation has been performed on the memory cells.

[0007] The following summarizes some aspects of the present disclosure to provide a basic understanding of the technology discussed. This summary is not a comprehensive overview of all the features considered of the present disclosure, nor is it intended to identify the essential or important elements of all aspects of the present disclosure or to describe the scope of any or all aspects of the present disclosure. The sole purpose of this summary is to present some concepts of one or more aspects of the present disclosure in a summary form as an introduction to the more detailed description to be provided later.

[0008] In some embodiments, a single command may be used to instruct a memory device, such as a memory controller connected to a memory module, to perform a precharge operation, a refresh operation, and an enable operation on one or more rows of one or more banks of the memory module. For example, a host device may generate and transmit a command to perform a precharge operation, a refresh operation, and an enable operation, and a memory controller may receive it. Subsequently, the memory controller may perform a precharge operation, a refresh operation, and an enable operation on one or more rows of one or more memory banks of a memory module connected to the memory controller. The command may be transmitted, for example, via a command bus between the host device and the memory controller. As an example, a command may be (1) a merge precharge command including commands for performing refresh and activate operations, (2) a merge refresh command including commands for performing precharge and activate operations, (3) a read command including commands for performing precharge, refresh, and activate operations, or (4) a write command including commands for performing precharge, refresh, and activate operations. As described herein, the use of merge commands can reduce congestion on the command bus in a dynamic random access memory (DRAM) system, thereby enabling more efficient use of command bus bandwidth. As used herein, merge commands may refer to merge memory commands. For example, merging precharge, refresh, and enable commands into a single command transmitted over the command bus can reduce the number of commands transmitted over the command bus to perform such operations, thereby freeing up command bus bandwidth for other uses.

[0009] These embodiments may be implemented as one or more commands transmitted from a host to a memory system. The commands transmitted by the host may include commands for reading capabilities from the memory system, setting configurations in the memory system, reading data from one or more specified addresses from the memory system, and / or writing data to the memory system at one or more specified addresses.

[0010] An apparatus according to at least one embodiment includes a memory system configured to communicate with a host. The memory system includes a memory array configured to store data. The memory system may include a memory controller configured to provide data stored in the memory array to the host for further processing by the host's processor or other components. The memory controller may also be configured to receive data from the host for storage in the memory array. In some embodiments, the memory array may be a plurality of volatile memory cells organized into rows and columns, as in dynamic random access memory (DRAM) or static random access memory (SRAM).

[0011] An apparatus according to at least one other embodiment includes a host device having a memory controller configured to communicate with a memory system to receive data stored in a memory array and / or to store data in a memory array. The host device may be a user equipment (UE) device, such as, for example, a mobile phone, a tablet computing device, a personal computer, a server, a smart watch, or an Internet of Things (IoT) device.

[0012] In one aspect of the disclosure, the method comprises receiving a merge command from a host device by a memory controller—the memory controller is coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel—for performing at least a precharge operation, a refresh operation, and an activation operation for one or more rows of a memory module, and performing the precharge operation, the refresh operation, and the activation operation upon receiving the merge command.

[0013] In a further aspect of the present disclosure, the device comprises at least one processor and a memory coupled to at least one processor. The at least one processor is configured to perform operations including receiving a merge command from a host device to perform at least a precharge operation, a refresh operation, and an enable operation on one or more rows of a memory module, and performing the precharge operation, the refresh operation, and the enable operation upon receiving the merge command. The processor may be a processor, a controller, or other logic circuit within the host. Alternatively, the processor may be a controller embedded in the memory device. For example, the processor may be a memory controller coupled to the memory module through a first channel and configured to access data stored in the memory module through the first channel.

[0014] In a further aspect of the present disclosure, the method comprises generating a merge command for performing at least a precharge operation, a refresh operation, and an activation operation on one or more rows of a memory module by a host device configured to communicate with a memory module through a channel, and transmitting the merge command to the memory module.

[0015] In a further aspect of the present disclosure, the device comprises at least one processor and a memory coupled to at least one processor. The at least one processor is configured to perform operations including generating a merge command to perform at least a precharge operation, a refresh operation, and an enable operation for one or more rows of a memory module, and transmitting the merge command to the memory module. The processor may be a processor, a controller, or other logic circuit within a host. For example, the device may include a host device configured to communicate with the memory module through a channel. The host device may include a memory controller coupled to the channel and configured to perform the operations described herein. Alternatively, the processor may be a controller embedded in the memory device. For example, the processor may be a memory controller coupled to the memory module through a first channel and configured to access data stored in the memory module through the first channel.

[0016] In a further aspect of the present disclosure, a device such as a wireless device comprises at least one processor and a memory coupled to at least one processor. The at least one processor is configured to communicate with a memory system through a memory controller coupled to a channel that couples the processor to the memory system. The processor may be a processor, a controller, or other logic circuit within a host.

[0017] In a further embodiment of the present disclosure, a non-transient computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein in relation to the embodiments of the present disclosure.

[0018] The memory systems in the present disclosure may be embedded within a processor on a semiconductor die or may be part of a different semiconductor die. The memory systems may be of various types. For example, the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash.

[0019] Methods and devices are presented in this disclosure by non-limiting examples of Low-Power Double Data Rate (LPDDR) Synchronous Dynamic Random Access Memory (SDRAM). For example, LPDDR operates according to LPDDR specifications published by the Joint Electronic Device Engineering Council (JEDEC). One such LPDDR specification may be LPDDR5. Another such LPDDR specification may be LPDDR6.

[0020] Other embodiments, features, and implementations will become apparent to those skilled in the art upon reviewing the description below of specific exemplary embodiments in conjunction with the accompanying drawings. While features may be discussed below with respect to specific embodiments and drawings, various embodiments may include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having specific advantageous features, one or more of such features may also be utilized according to various embodiments. In a similar manner, exemplary embodiments may be discussed below as device, system, or method embodiments, but exemplary embodiments may be implemented in various devices, systems, and methods.

[0021] The methods may be embedded in a computer-readable medium as computer program code comprising instructions that cause a processor to perform the steps of the methods. In some embodiments, the processor may be part of a mobile device comprising a first network adapter configured to transmit data, such as images or videos, as recording or streaming data through a first network connection among a plurality of network connections. The processor may be coupled to the first network adapter and to memory for storing data to support processing and communication operations performed by the processor. The network adapter may support communication over a wireless communication network, such as a 5G NR communication network. The processor may cause the transmission of data stored in memory over the wireless communication network.

[0022] The foregoing has broadly outlined the features and technical advantages of the examples according to the present disclosure so that the following detailed description may be better understood. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as a basis for modifying or designing other structures to perform the same purposes of the present disclosure. Such equivalent structures do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, namely their organization and method of operation, will be better understood from the following description when considered in conjunction with the accompanying drawings, along with the associated advantages. Each drawing is provided for the purposes of illustration and description and is not provided as a definition of the limitations of the claims.

[0023] While aspects and implementations are described in this application by way of example for some examples, those skilled in the art will understand that additional implementations and use cases may occur in many different arrangements and scenarios. The innovations described herein may be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and / or uses may occur through integrated chip implementations and other non-module-component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI (artificial intelligence)-enabled devices, etc.). Various applicability of the described innovations may occur, although some examples may or may not be specifically related to use cases or applications. Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations, and to aggregate, distributed, or OEM (original equipment manufacturer) devices or systems comprising one or more aspects of the further described innovations. In some practical settings, devices comprising the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals must include a number of components for analog and digital purposes (hardware components including, e.g., antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processor(s), interleavers, adders / summers, etc.).It is intended that the innovations described herein may be implemented in a wide variety of devices, chip-level components, systems, distributed arrays, end-user devices, etc., of various sizes, shapes, and configurations. Brief explanation of the drawing

[0024] Further understanding of the attributes and advantages of the present disclosure may be realized by referring to the following drawings. In the attached drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by a dash symbol following the reference label and a second label distinguishing between similar components. Where only the first reference label is used in this specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label. FIG. 1 illustrates a block diagram of an exemplary computing system integrating a host, a memory system, and channels coupling the host and the memory system, according to one or more aspects of the present disclosure. FIG. 2 illustrates a block diagram of an exemplary computing system that integrates channels coupling the host and the memory system using a host, a memory system, and other implementations of channels according to one or more aspects of the present disclosure. FIGS. 3a and 3b illustrate waveforms for the transmission of data through an exemplary channel in a writing operation according to specific embodiments of the present disclosure. FIGS. 4a and 4b illustrate waveforms for the transmission of data through an exemplary channel in a reading operation according to certain embodiments of the present disclosure. FIG. 5a is an exemplary flowchart of exemplary memory commands according to specific embodiments of the present disclosure. FIG. 5b is an exemplary flowchart of exemplary merge memory commands according to specific embodiments of the present disclosure. FIG. 5c is an exemplary flowchart of exemplary merge memory commands according to specific embodiments of the present disclosure. FIG. 5d is an exemplary flowchart of exemplary merge memory commands according to specific embodiments of the present disclosure. FIG. 6a is a chart of bits of an exemplary read command according to specific embodiments of the present disclosure. FIG. 6b is a chart of bit values ​​of a read command and corresponding operations to be performed in response to a read command according to specific embodiments of the present disclosure. FIG. 7a is a chart of bits of an exemplary precharge command according to specific embodiments of the present disclosure. FIG. 7b is a chart of bit values ​​of precharge commands and corresponding precharge command formats according to specific embodiments of the present disclosure. FIG. 8a is a chart of bits of an exemplary refresh command according to specific embodiments of the present disclosure. FIG. 8b is a chart of bit values ​​of refresh commands and corresponding refresh command formats according to specific embodiments of the present disclosure. FIG. 8c is a chart of bit values ​​of refresh commands and corresponding refresh command formats according to specific embodiments of the present disclosure. FIG. 9 is a flowchart illustrating a method for receiving and executing a merged memory command according to specific embodiments of the present disclosure. FIG. 10 is a flowchart illustrating a method for generating and transmitting a merged memory command according to specific embodiments of the present disclosure. Similar reference numbers and designations in various drawings indicate similar elements. Specific details for implementing the invention

[0025] The detailed description provided below in connection with the attached drawings is intended to describe various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a complete understanding of the gist of the invention. Such specific details are not required in all cases, and it will be apparent to those skilled in the art that in some cases, well-known structures and components are depicted in block diagram form for clarity of presentation.

[0026] The present disclosure provides systems, devices, methods, and computer-readable media that support data processing, including techniques for merged memory commands for improved bus utilization in volatile memory. For example, precharge, refresh, and / or enable commands for one or more rows of one or more memory banks of a device may be merged into a single command to form a merged memory command transmitted from a host device to a memory system via a command bus. The merged memory command may be a single command for performing a plurality of operations by a memory module and / or controller. As one particular example, the single command may be a command having a precharge command format or a refresh command format and may include an indication that the memory system should perform a precharge operation, an enable operation, and / or a refresh operation on one or more rows of one or more banks of the memory system. As another example, a single command may be a command having a write format and may include an indication that the memory system should perform a write operation, a precharge operation, an enable operation, and / or a refresh operation on one or more rows of one or more banks of the memory system. As another example, a single command may be a command having a read format and may include an indication that the memory system should perform a read operation, a precharge operation, an enable operation, and / or a refresh operation on one or more rows of one or more banks of the memory system. In some embodiments, the command may further specify one or more rows of one or more banks to which the operations are to be applied.

[0027] Specific implementations of the gist described in this disclosure may be implemented to realize one or more of the following potential advantages or benefits. In some embodiments, this disclosure provides merged precharge, refresh, and / or enable commands for transmission over a command bus between a host device and a memory system, e.g., between a memory controller and a memory system. Such merging can reduce congestion on the command bus, particularly in the context of dynamic random access memory (DRAM). For example, in DRAM, to precharge open pages or rows of a memory module, a precharge command may be transmitted before a refresh command, and a subsequent enable command may be transmitted after the refresh command to re-enable the same row when there are multiple pending page hits for the row. The merging of precharge, refresh, and enable commands, and, in some embodiments, the merging of read or write commands, can reduce the number of commands transmitted over the command bus, thereby reducing command bus congestion and freeing up bus bandwidth for the transmission of other commands. Merged precharge, refresh, and enable commands can be particularly useful for reducing command bus congestion in the context of precharge, refresh, and enable operations performed on frequently accessed pages or rows of a memory module. Such reductions in congestion can lead to improved memory performance and reduced power consumption by memory systems.

[0028] An exemplary memory device that may include aspects of the present disclosure, including merge memory commands for improved bus utilization in volatile memory, is illustrated in FIG. 1. FIG. 1 illustrates a device (100) comprising a host (110), memories (150), and channels (190) coupling the host (110) and the memories (150). The device (100) may be a device among, for example, computing systems (e.g., servers, data centers, desktop computers), mobile computing devices (e.g., laptops, mobile phones, vehicles, etc.), Internet of Things devices, virtual reality (VR) systems, augmented reality (AR) systems, automotive systems (e.g., driver assistance systems, autonomous driving systems), image capture devices (e.g., standalone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets such as mobile phones, cellular or satellite radio phones, personal digital assistants (PDAs), panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices having digital imaging or video capabilities), and / or multimedia systems (e.g., televisions, disc players, streaming devices).

[0029] The host (110) may include at least one processor such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), a multimedia engine, and / or a neural processing unit (NPU). The host (110) may be configured to be coupled to and communicate with memories (150) (e.g., memories (150-1 to 150-4)) through channels (190) (e.g., channels (190-1 to 190-4)) when performing computing functions such as data processing, data communication, graphic display, camera, AR or VR rendering, image processing, neural processing, etc. For example, the memories (150-1 to 150-4) may store instructions or data for the host to perform computing functions.

[0030] The host (110) may include a memory controller (130) that may include controller PHY modules (134-1 to 134-4). Each of the controller PHY modules (134-1 to 134-4) may be coupled to each of the memories (150-1 to 150-4) through their respective channels (190-1 to 190-4). For convenience of reference, read and write are referred to in terms of the host (110). For example, in a read operation, the host (110) may receive stored data from one or more of the memories (150-1 to 150-4) through one or more of the channels (190-1 to 190-4). In a write operation, the host (110) may provide data to be written to one or more of the memories (150-1 to 150-4) for storage through one or more of the channels (190-1 to 190-4). The memory controller (130) may be configured to control various aspects, such as logical layers of communications to and from the memories (150-1 to 150-4). The controller PHY modules (134-1 to 134-4) may each be configured to control the electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) of the signals provided or received on the channels (190-1 to 190-4).

[0031] In some examples, the memories (150-1 to 150-4) may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, the memories (150-1 to 150-4) may each be different types of memory, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM. The host (110), the memories (150-1 to 150-4), and / or the channels (190-1 to 190-4) may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of the channels (190-1 to 190-4) may contain 16 bits of data (e.g., 16 DQs). In some examples, each of the channels (190-1 to 190-4) can operate on 32 bits of data (e.g., 32 DQs). In FIG. 1, four channels are shown, but the device (100) may include more or fewer channels, such as eight or sixteen channels.

[0032] Further details of an embodiment of an apparatus (100) for providing access to a memory system (such as one of the memories (150-1 to 150-4) including logic and control circuits) are illustrated in FIG. 2. FIG. 2 illustrates the configuration of the host (110), memory system (250), and channel (190) of FIG. 1. The channel (190) between the host (110) and the memory system (250) may include a plurality of connections, some of which carry data (e.g., user data or application data), and some of which carry non-data (e.g., addresses and other signaling information). For example, non-data connections within the channel (190) may include, in byte units, a data clock (e.g., WCK) used to provide data to each memory system (250) and a read data strobe (e.g., RDQS) used to receive data from each memory system (250). The channel (190) may further include data mask signaling (e.g., DM, sometimes referred to as data mask inversion (DMI) to indicate a number of functions performed by signal connections) used to mask a certain portion of data in a write operation. The channel (190) may further include a command and an address (e.g., CA[0:n]) and an associated CA clock to provide commands (e.g., read or write commands) to the memory system (250). The CA[0:n] and / or CA clock of channel (190) may be a command bus for transmitting commands from the memory controller (130) to the memory system (250) as described in this specification.

[0033] The host (110) may include at least one processor (120) that may include a CPU (122), a GPU (123), and / or an NPU (124). The host (110) may further include a memory controller (130) having a controller memory PHY module (134). The memory controller (130) may be coupled to at least one processor (120) via a bus system (115) to perform various computing functions. The term "bus system" may provide that elements coupled to the "bus system" can exchange information directly or indirectly among themselves. In different embodiments, the "bus system" may encompass multiple physical connections as well as intervening stages such as buffers, latches, registers, etc. The module may be implemented in hardware, software, or a combination of hardware and software.

[0034] The memory controller (130) can transmit and / or receive blocks of data, commands, and addresses to at least one processor (120) and / or other modules such as a memory system (250). The memory system (250) may include a memory controller (180) having a memory PHY (160) (e.g., a memory I / O module or PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on connections of the channel (190). For example, the memory PHY (160) may be configured to capture (e.g., sample) data, commands, and addresses from the host (110) through the channel (190) and output data to the host (110) through the channel (190). Exemplary techniques for communicating on a channel (190) between a memory PHY (160) and a memory controller (130) are illustrated in the examples of FIGS. 3a, 3b, 4a, and 4b. The memory controller (180) may also include data registers (182A-K) configured to store data being transmitted between the host (110) and the memory array (175) and / or to store configuration settings or other data.

[0035] The memory system (250) may further include a memory array (175) that may include a plurality of memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) for storing values. The host (110) may read data stored in the memory array (175) and write data to the memory array (175) through the channel (190) and the memory PHY (160). The memory array (175) may be divided into a plurality of banks, each bank being structured as a plurality of pages.

[0036] Application or user data may be processed by the processor (120) and the memory controller (130) in response to instructions / commands for storing and / or retrieving such data from the memory system (250). For example, data may be generated during the execution of an application, such as a spreadsheet program that calculates values ​​based on other data. As another example, data may be generated during the execution of an application, for example, by receiving user input to a spreadsheet program. As an additional example, data may be generated during the execution of a gaming application, which generates information regarding the representation of a scene rendered by a three-dimensional (3D) application.

[0037] A host (110) is coupled to a memory system (250) via a channel (190) exemplified for the byte DQ[0:7] of data. The channel (190) and signaling between the host (110) and the memory system (250) can be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As exemplified, the channel (190) includes signal connections of DQs, a read data strobe (RDQS), a data mask (DM), a data clock (WCK), a command and address (CA[0:n]), and a command and address clock (CK). The host (110) may use the read data strobe (RDQS) to strobe (e.g., clock) the data in a read operation to receive data on the DQs. The memory system (250) may use a data mask (DM) to mask certain parts of the data being written during a write operation. The memory system (250) may use a data clock (WCK) to sample data on the DQs for a write operation. The memory system (250) may use a command and address clock (CK) to clock the CAs (e.g., to receive them). A signal connection for each of the signalings may include a pin in the host (110), a pin in the memory system (250), and a conductive trace or traces electrically connecting the pins. The conductive traces or traces may be part of a single integrated circuit (IC) on a silicon chip including a processor (120) and a memory system (250), part of a package on package (PoP) including a processor (120) and a memory system (250), or part of a printed circuit board (PCB) coupled to both the processor (120) and the memory system (250).

[0038] The memory system (250) may include a memory PHY (160) (e.g., a memory I / O module or a PHY layer) configured to control electrical characteristics (e.g., voltage levels, phases, delays, frequencies, etc.) to provide or receive signals on the channel (190). For example, the memory PHY (160) may be configured to capture (e.g., sample) data, commands, and addresses from the host (110) through the channel (190) and to output data to the host (110) through the channel (190). Information transmitted across the channel (190) may be stored in registers within the memory PHY (160) of the memory system (250) as a temporary or short-term storage location prior to longer-term storage in the memory array (175).

[0039] The memory system (250) may further include a memory array (175) that may include a plurality of memory cells (e.g., DRAM memory cells) for storing information. The host (110) may read data stored in the memory array (175) and write data into the memory array (175) through the channel (190). Furthermore, the memory array (175) may be configured to store metadata such as ECCs associated with the stored data (e.g., system or array ECCs).

[0040] Operations according to some embodiments of the present disclosure for storing and retrieving information from a memory array (175) can be performed by controlling signals on individual lines of a channel (190). Exemplary embodiments of signaling for a write operation are illustrated and described with reference to FIGS. 3a and 3b. Exemplary embodiments of signaling for a read operation are illustrated and described with reference to FIGS. 4a and 4b.

[0041] FIGS. 3a and 3b illustrate waveforms of data transmission through an exemplary channel in a write operation according to certain embodiments of the present disclosure. The command and address clock (CK) may be a differential signal having CK_t and CK_c signal connections. The data clock (WCK) may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe (RDQS) may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled as DM0 to indicate that DM0 corresponds to the lower byte of the DQs (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command may be provided by the host (110) for a write operation to the memory system (250). In T1, a write command can be provided to the memory system (250) by the host (110).

[0042] After a write latency (WL) of a certain period, the host (110) may toggle the data clock (WCK0_t, WCK0_c) to provide the memory system (250) with clocking for receiving data to be written over the DQ signal connections. At Tc0 to Tc2, the memory system (250) may receive 16 bytes of data serially over each of the DQ[0:7] signal connections and clocked by the data clock (WCK0_t, WCK0_c). The memory system (250) may receive a 16-bit data mask (DM0) serially (e.g., based on the data clock (WCK0_t, WCK0_c)) to mask certain parts of the data received from the write operation. In some examples, 16 bytes of data and a 16-bit data mask (DM0) may be received by the memory system (250), wherein each bit of the data mask (DM0) masks the received data of the corresponding byte. In Tc0-Tc2, the RDQS_t signal connection may be in a Hi-Z condition. In a read operation, the RDQS_t signal connection may be configured to provide a read data strobe (RDQS) from the memory system (250) to the host (110).

[0043] FIGS. 4a and 4b illustrate waveforms for the transmission of data through an exemplary channel in a read operation according to certain embodiments of the present disclosure. The command and address clock (CK) may be a differential signal having CK_t and CK_c signal connections. The data clock (WCK) may be a differential signal having WCK0_t and WCK0_c signal connections. The read data strobe (RDQS) may be a differential signal having RDQS_t and RDQS_c signal connections. The data mask is labeled as DM0 to indicate that DM0 corresponds to the lower byte of the DQs (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command may be provided by the host (110) for a read operation to the memory system (250). At T1, a read command can be provided to the memory system (250) by the host (110).

[0044] After a certain period of read latency (RL), the memory system (250) can toggle the read data strobe (RDQS) to provide the host (110) with clocking for receiving data for a read operation over the DQ signal connections. In Tc0-Tc2, the host (110) can receive 16 bytes of data serially over each of the DQ[0:7] signal connections and clocked by the read data strobe (RDQS_t, RDQS_c). Thus, in this example, 16 bytes of data are received by the host (110).

[0045] In Tc0-Tc2, the data mask (DM0) signal connection may be in a Hi-Z condition. In a write operation, the DM signal connection may be configured to provide a data mask from the host (110) to the memory system (250), which is clocked by WCK0_t and WCK0_c.

[0046] Various operations may be performed on rows of memory banks of a memory system. Commands for performing such operations may be transmitted to a memory system, such as a memory controller of a memory system, by a host device, for example, a memory controller of a host device. Such commands may include commands for reading from and / or writing to one or more rows of one or more banks of a memory system. Another exemplary command may be an enable command capable of enabling one or more rows of one or more memory banks for reading and / or writing data. As another example, a precharge command may deactivate a currently active row. A refresh command may refresh the charge on a row of a memory module to prevent data loss, as described.

[0047] Commands such as read, write, precharge, refresh, and enable commands can be transmitted from a host device to a memory system via a command bus, such as CA[0:n] or another command bus. The bandwidth of the command bus may be limited. For example, as the number of banks increases in memory systems such as DRAM, the command bus between the host device and the memory system may become increasingly congested. Reducing congestion can lead to improved performance and reduced power consumption in memory systems. For example, congestion on the command bus can lead to more frequent toggling of the CK clock, which can increase power consumption and reduce the number of column command slots, thereby decreasing performance.

[0048] As discussed herein, merged precharge, refresh, and enable commands can reduce bus congestion by combining precharge, refresh, enable, read, and / or write commands into a single command transmitted over the command bus. As an example, such merging can be particularly useful in DRAMs where bank hashing algorithms can be used to improve bank spread. In some cases, the number of banks may exceed 12. Bank hashing can increase the number of active banks, and a larger number of active banks may require the transmission of a larger number of precharge commands before the scheduling of refresh commands. If the same row needs to be enabled following a refresh operation, a separate, additional enable command for that row may also be transmitted. Furthermore, precharge, refresh, and enable operations may require a larger portion of the command bus bandwidth as the refresh rate increases. As a specific example, refreshes in automotive DRAM systems can be 4X, 8X, or more. As an example, in an LPDDR5 bank group (BG), a single refresh interval (tREFI) for the DRAM may include 16 scheduled refreshes, requiring a precharge operation, a refresh operation, and, in some cases, an enable operation at each interval. In some cases, performance overhead of more than 1% may occur from the transmission of separate precharge, refresh, and enable commands. Combining such commands into merge commands can reduce or eliminate performance overhead. Furthermore, smart scheduling can be implemented by a memory controller that enables flexible scheduling based on bank usage, and the number of wasted enable operations can be reduced by allowing the enable that opens the row to be completed before the row is changed, such as when a refresh operation occurs.Therefore, separate precharge, refresh, and enable commands transmitted over the command bus may require a high amount of available command bus bandwidth, which can reduce the amount of command bus bandwidth available for other commands, reduce the utilization of the memory system, and / or increase the power consumption of the memory system and / or host device. The severity of such effects may increase as the refresh rate of the memory system and / or the number of banks in the memory system increases. The reduction in command bus congestion achieved through the use of merged precharge, refresh, and enable commands can result in improved efficiency in processing refreshes per bank, a reduced number of all-bank refreshes through increased availability of command bus slots for command transmission, improvements in efficiency and latency through a reduced number of overhead cycles, and improved availability of command bus slots for transmitting other commands. Such improvements can improve memory system utilization and reduce power consumption by reducing the total number of command bus cycles. As a specific example, the number of cycles can be reduced by up to 2% and by more than 2%.

[0049] An exemplary flowchart (500) of a sequence of unmerged commands for one or more rows of one or more banks of a memory module is illustrated in FIG. 5a. For example, in block (502), a read command for bank 0, row 0, column 64 may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the read command. In block (504), a precharge command for bank 0, row 0, which may be an open row of bank 0, may be transmitted from a host to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the precharge command. In block (506), a refresh command for bank 0 may be transmitted from a host to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the refresh command. In block (508), a write command for bank 1, row 0, column 64 may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the write command. In block (510), an enable command for bank 0, row 0, which may be an open row of bank 0, may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the enable command. Thus, the sequence of commands of FIG. (500) may require the transmission of five commands via a command bus to perform the described read, precharge, refresh, write, and enable operations.

[0050] An exemplary flowchart (520) of a sequence of commands including a merge refresh command is illustrated in FIG. 5B. For example, in block (522), a read command for bank 0, row 0, and column 64 may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. Row 0 may be an open row of bank 0. Subsequently, the memory system may execute the read command. In block (524), a merge command, such as a command to perform a precharge operation and an enable operation for one or more rows such as row 0, which may be an open row of bank 0, and / or other rows, and a refresh operation for one or more banks such as bank 0 and / or other banks, may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. Subsequently, the memory system may execute the precharge operation, the refresh operation, and the enable operation. For example, the memory system may execute a precharge operation and a refresh operation before the write operation described in relation to block (526), ​​and may perform an activation operation after the write operation based on a single command described in relation to block (524). The command of block (524) may, for example, have a refresh command format and may include an indication to perform a refresh operation and an activation operation in addition to the refresh operation. In block (526), ​​a write command for bank 1, row 0, column 64 may be transmitted from a host device to a memory system, such as a memory controller of the memory system, via a bus such as a command bus. The memory system may then execute the write command. Thus, the write command of block (526) may be moved forward compared to the write command of block (508) of FIG. 5A, because the host device may not need to generate and transmit a separate refresh command.As a result of the transmission of a merge command in block (524), additional opportunities in blocks (528 and 530) may be available for the transmission of other commands from the host device to the memory system via the bus. For example, a write command transmitted in block (508) of FIG. 5a may be moved forward to block (526) of FIG. 5b, and an enable command transmitted in block (510) of FIG. 5a may not be required. Thus, up to three clock cycles of the command bus may be saved through the use of the merge refresh command, one clock cycle corresponding to the precharge command and two clock cycles corresponding to the enable command. As another example, a merge refresh command may include a command for performing a refresh operation for the first, current, bank and the second bank and a precharge operation for the first, current, row of the first bank and the corresponding second row of the second bank, without including a command for performing an activation operation.

[0051] An exemplary flowchart (540) of a sequence of commands including a merge precharge command is illustrated in FIG. 5c. For example, in block (542), a read command for bank 0, row 0, and column 64 may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. Row 0 may be, for example, an open row of bank 0. The memory system may then execute the read command. In block (544), a merge command, such as a command to perform a precharge operation, a refresh operation, and an enable operation for one or more rows such as row 0, and / or other rows, which may be open rows of one or more banks such as bank 0 and / or other banks, may be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. The memory system may then execute the precharge operation, the refresh operation, and the enable operation. For example, the memory system may execute a precharge operation and a refresh operation before the write operation described in relation to block (546), and may perform an activation operation after the write operation based on a single command described in relation to block (544). The command of block (544) may, for example, have a precharge command format and may include an indication to perform a refresh operation and an activation operation in addition to the precharge operation. In block (546), a write command for bank 1, row 0, column 64 may be transmitted from a host device to a memory system, such as a memory controller of the memory system, via a bus such as a command bus. The memory system may then execute the write command. Thus, the write command of block (546) may be moved forward compared to the write command of block (508) of FIG. 5a, so that the host device may not need to generate and transmit a separate refresh command.As a result of the transmission of a merge command in block (544), additional opportunities in blocks (548 and 550) may be available for the transmission of other commands from the host device to the memory system via the bus. For example, a write command transmitted from block (508) of FIG. 5a may be moved forward to block (546) of FIG. 5c, and an enable command transmitted from block (510) of FIG. 5a may not be required. Thus, up to three clock cycles of the command bus may be saved through the use of the merge precharge command, one clock cycle corresponding to the refresh command and two clock cycles corresponding to the enable command. As another example, a merge precharge command may include a command for performing a refresh operation for the first, current, bank and the second bank and a precharge operation for the first, current, row of the first bank and the corresponding second row of the second bank, without including a command for performing an activation operation.

[0052] An exemplary flowchart (560) of a sequence of commands including a merge read or write command is illustrated in FIG. 5d. The following example is based on a merge read command, but a sequence of similar commands may be realized as a merge write command. For example, in block (562), a merge read command, such as a command to perform a read operation, a precharge operation, a refresh operation, and an enable operation on one or more rows of one or more banks of a memory system, may be transmitted from a host device to a memory system, such as a memory controller of the memory system, via a bus such as a command bus. For example, the read operation may be a read operation for bank 0, row 0, column 64, the precharge operation may be for bank 0, row 0, the refresh operation may be for bank 0, row 0, and the enable operation may be for bank 0, row 0. Row 0 may be, for example, an open row of bank 0. A merged read command may have a read command format and may include an indication to perform a read operation, a precharge operation, a refresh operation, and an enable operation on one or more rows, such as row 0, which may be open rows of one or more banks, such as bank 0 and / or other banks. Subsequently, the memory system may execute the read operation, the precharge operation, the refresh operation, and the enable operation. For example, the memory system may execute the read operation, the precharge operation, and the refresh operation before the write operation described in relation to block (566), and may perform the enable operation after the write operation based on a single command described in relation to block (562). Thus, since a separate precharge command does not need to be transmitted from block (564), the bus may be available for the transmission of other commands from block (564).In block (566), a write command for bank 1, row 0, column 64 can be transmitted from a host device to a memory system, such as a memory controller of a memory system, via a bus such as a command bus. Subsequently, the memory system can execute the write command. Thus, the write command of block (566) can be moved forward compared to the write command of block (508) of FIG. 5a, because the host device may not need to generate and transmit a separate refresh command. As a result of the transmission of the merge command in block (562), additional opportunities in blocks (564, 568, and 570) may be available for the transmission of other commands from the host device to the memory system via the bus. For example, a write command transmitted from block (508) of FIG. 5a may be moved forward to block (566) of FIG. 5d, an enable command transmitted from block (510) of FIG. 5a may not be required, and a precharge command of block (504) may not be required. Thus, up to four clock cycles of the command bus may be saved through the use of merged read or write commands, one clock cycle corresponds to a precharge command, one clock cycle corresponds to a refresh command, and two clock cycles correspond to an enable command. As another example, a merge read or write command may include a command to perform a refresh operation for the first, current, bank and the second bank, a precharge operation for the first, current, row of the first bank and the corresponding second row of the second bank, and a write operation for the first, current, row of the first bank, without including a command to perform an enable operation. As used herein, the first row, the first bank, the second row, and the second bank may refer to any specific row or bank of the memory module and do not need to refer to the first row or the first bank and / or the second row and the second bank in a specific order of rows of the memory module.Therefore, the first row may be distinguishable from the second row, but the first row and the second row do not necessarily have to be the first and second rows in the order of the rows of the memory module. Furthermore, the first row and the second row do not necessarily have to be adjacent rows of the memory module. Likewise, the first bank may be distinguishable from the second bank, but the first bank does not necessarily have to be the first and second banks in the order of the banks of the memory module. Furthermore, the first bank and the second bank do not necessarily have to be adjacent banks of the memory module.

[0053] Various command formats may be used to generate, transmit, and receive commands for performing precharge, refresh, and enable operations on one or more rows of a memory bank. As one specific example, command message formats for transmitting commands using a command bus according to JEDEC DDR (double data rate) standards, such as LPDDR5, LPDDR6, and / or other JEDEC DDR standards, may be used. For example, specific bits of commands, such as read commands, write commands, precharge commands, or refresh commands, may be repurposed to indicate that the read command, write command, precharge command, and / or refresh command includes a command for performing one or more additional operations. FIG. 6a is a chart (600) of bits of an exemplary read command according to specific embodiments of the present disclosure. Bits 4 and 5 of the second row of the chart (600), marked as RV and AP, which correspond to command bus bits, can be used to indicate which operations should be performed based on the read command of the chart (600). The bit marked as RV can be configured as a reserved bit, and the bit marked as AP can be configured as an automatic precharge bit when the system is not configured to support merge precharge, refresh, and enable commands. For example, the bits marked as RV and AP of the second row of the chart (600) can be repurposed to indicate operations such as precharge, refresh, and enable operations that must be performed in addition to the read operation in systems that support merge precharge, refresh, and enable commands. In some embodiments, the read command of the chart (600) may be a read command formatted according to the JEDEC LPDDR standard.In some embodiments, the command of the chart (600) may be a read block (BL) 24 command, but similar modifications may be made to a write block 24 command, a read block 48 command, or a write block 48 command. For example, the write command may be modified similarly to the read operation of the chart (600), such as by modifying the same bits to indicate additional operations to be performed. FIG. 6b is a chart (620) of bit values ​​of a read command, such as the read command of the chart (600) of FIG. 6a, and corresponding operations to be performed in response to the read command, according to specific embodiments of the present disclosure. For example, if a bit marked with RV is set to 0 and a bit marked with AP is set to 0, a legacy read command, such as a backward compatible read command, may be performed. When the bit marked with RV is set to 0 and the bit marked with AP is set to 1, a read command and an auto-precharge operation can be performed on one or more rows of a bank, such as the open row of a bank indicated by the BA0, BA1, BG0, and BG1 bits. When the bit marked with RV is set to 1 and the bit marked with AP is set to 0, a read operation and an auto-precharge operation can be performed on one or more rows of a bank, such as the open row of a bank indicated by the BA0, BA1, BG0, and BG1 bits, and a refresh operation can be performed on the bank. When the bit marked with RV is set to 1 and the bit marked with AP is set to 1, a read operation and an auto-precharge operation can be performed on one or more rows of a bank, such as the open row of a bank indicated by the BA0, BA1, BG0, and BG1 bits, a refresh operation can be performed on the bank, and an enable operation can be performed on one or more rows, such as the open row of a bank.Such merge read, precharge, refresh, and / or enable commands may be transmitted over the command bus to indicate to the memory system to reopen the same row following a refresh operation, for example, by performing an enable operation on the same row to schedule additional page hits following a refresh operation on the same row. In some embodiments, the precharge and enable operations may be performed on corresponding rows of two banks of a bank pair. Likewise, in some embodiments, the refresh operation may be performed on two banks of a bank pair. In some embodiments, the bank pair may be fixed, whereas in other embodiments, the bank pair may be configurable. The read command described with reference to FIGS. 6a and 6b may be particularly useful in an 8-bank mode where only a single bank is refreshed at a time.

[0054] FIG. 7a is a chart (700) of bits of an exemplary precharge command according to specific embodiments of the present disclosure. Bits 2, 3, and 4 of the fourth row of the chart, marked R, A, and AS, which may correspond to command bus bits or other bits, may be used to indicate which operations are to be performed based on the precharge command of the chart (700). The bits marked R, A, and AS may be composed of voltage (V) bits when the system is not configured to support merge precharge, refresh, and enable commands. For example, the bits marked R, A, and AS may be repurposed to indicate operations such as refresh and enable operations that are to be performed in addition to the precharge operation. In some embodiments, the precharge command of the chart (700) may be a precharge command formatted according to the DDR JEDEC standard, in which one or more bits are repurposed. FIG. 7b is a chart (720) of bit values ​​of a precharge command, such as the precharge command of FIG. 7a (700), and corresponding actions to be performed in response to the precharge command, according to specific embodiments of the present disclosure. For example, a bit marked R may be used to indicate a refresh action, a bit marked A may be used to indicate an activation applied to a row to which the precharge action is applied, such as an open row, and a bit marked AS may be used to indicate an activation for the same memory bank to which the precharge action is applied, or for both the same memory bank and the other memory bank of a bank pair containing the memory bank to which the precharge action is applied. For example, values ​​000, 001, 010, and 100 corresponding to the R bit, A bit, and AS bit may be reserved for legacy actions, such as actions associated with the precharge command when the command is not a merge precharge command.The banks to which the merge precharge command should be applied may be indicated by the BA0, BA1, BG0, and BG1 bits of the chart (700). Such bank indication may indicate a bank pair, for example, by indicating the first bank that is a member of the bank pair with the second bank. Values ​​of 100 corresponding to the R bit, A bit, and AS bit may indicate that a precharge operation should be performed on a row of the bank, such as an open row, and / or a corresponding row of another bank that is a member of the bank pair, and that a refresh operation should be performed on the bank, and, in some cases, on another bank that forms a bank pair. Values ​​of 101 corresponding to the R bit, A bit, and AS bit may indicate that a precharge operation should be performed on the row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, such as an open row, a refresh operation should be performed on the current bank and the other bank of the bank pair, and an enable operation should be performed on the row of the current bank, such as an open row. Values ​​of 110 corresponding to the R bit, A bit, and AS bit may indicate that a precharge operation should be performed on the row of the current bank of the bank pair, such as an open row, a refresh operation should be performed on the current bank and the other bank of the bank pair, and an enable operation should be applied to the row of the other bank of the bank pair corresponding to the row of the current bank of the bank pair. Values ​​of 111 corresponding to the R bit, A bit, and AS bit may indicate that a precharge operation should be performed on a row of the current bank of the bank pair, such as an open row, a refresh operation should be performed on the current bank of the bank pair and another bank of the bank pair, and an activation operation should be applied to a row of the current bank of the bank pair and a corresponding row of another bank of the bank pair, such as an open row.In some embodiments, the bank pair may be fixed, whereas in other embodiments, the bank pair may be configurable in a merge precharge command, such as by using one or more spare bits.

[0055] FIG. 8a is a chart (800) of bits of an exemplary refresh command according to specific embodiments of the present disclosure. The refresh command may be configured to include commands for performing precharge, refresh, and enable operations on one or more rows of a specific bank of a flexible bank group or on a flexible bank of a specific bank group. Bit 5 of the second row of the chart (800) may indicate that all banks should be refreshed when set to 1. Banks to be precharged and refreshed may be indicated by the bits BA0, BA1, BG0, and BG1 of the third row of the chart (800). Bits dBA0, dBA1, dBG0, and dBG1 may indicate whether a refresh operation, a precharge and refresh operation, or a precharge, refresh, and enable operation should be performed, and the rows and / or banks to which the operations should be applied. For example, the bits labeled dBA0, dBA1, dBG0, and dBG1 may be repurposed to indicate operations such as refresh, precharge, and enable operations to be performed. In some embodiments, the refresh command of the chart (800) may be a refresh command formatted according to the DDR JEDEC standard, with one or more bits repurposed.

[0056] FIG. 8b is a chart (820) of bit values ​​of a refresh command, such as the refresh command of the chart (800) of FIG. 8a, and corresponding operations to be performed in response to the refresh command, according to specific embodiments of the present disclosure. For example, the bit values ​​and corresponding operations of FIG. 8b may correspond to a configuration of a memory device and / or host that supports a fixed bank for operations but allows the selection of banks having the same bank number from different bank groups. For example, the current bank of a bank pair to which a precharge and / or refresh operation is to be applied may be indicated by bits BA0, BA1, BG0, and BG1, while other banks of the bank pair may be indicated by BA0, BA1, dBG0, and dBG1, allowing for a flexible selection of bank groups for the bank pair using dBG0 and dBG1 along with a specific bank fixed by the values ​​of BA0 and BA1. For example, when the values ​​of the bits marked AB, dBA0, dBA1, dBG0, and dBG1 are all 1, the command may indicate that all bank refresh operations should be performed. In some embodiments, the memory system may enable or disable all bank refreshes using specific bit states, such as the specific mode register write (MRW) bit for backward compatibility. For example, the MRW bit may be written to a disabled value at runtime, or boot-up software may write the MRW bit to a disabled value. When AB, dBA0, and dBA1 are set to 100, the command may indicate that a precharge operation should be performed for the same row as the open row of the current bank and the corresponding row of the other bank in the bank pair, as indicated by the BA0, BA1, BG0, and BG1 bits, and that a refresh operation should be performed for both banks in the bank pair.If AB, dBA0, and dBA1 are set to 101, the command may indicate that a precharge operation should be performed on the same row as the open row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, a refresh operation should be performed on both banks of the bank pair, and an enable operation should be applied to the same row as the open row of the current bank indicated by the BA0, BA1, BG0, and BG1 bits. If AB, dBA0, and dBA1 are set to 110, the command may indicate that a precharge operation should be performed on the same row as the open row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, a refresh operation should be applied to both the current bank indicated by the BA0, BA1, BG0, and BG1 bits and the other bank of the bank pair indicated by the BA0, BA1, dBG0, and dBG1 bits, and an enable operation should be applied to the corresponding row of the other bank of the bank pair. The other bank of the bank pair may be a corresponding bank in a different bank group, such as a bank having the same bank number as the current bank, for example. When AB, dBA0, and dBA1 are set to 111, the command may indicate that a precharge operation should be performed on the row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, a refresh operation should be performed on both banks of the bank pair, and an enable operation should be applied to both the row of the current bank indicated by the BA0, BA1, BG0, and BG1 bits and the corresponding row of the other bank indicated by the BA0, BA1, dBG0, and dBG1 bits. Thus, if the row of the current bank 1 of bank group BG0 is precharged and enabled, the corresponding row of the corresponding bank 1 of BG1 can also be precharged and enabled.

[0057] FIG. 8c is a chart (840) of bit values ​​of a refresh command, such as the refresh command of the chart (800) of FIG. 8a, and corresponding operations to be performed in response to the refresh command, according to specific embodiments of the present disclosure. For example, the bit values ​​and corresponding operations of FIG. 8c may correspond to a configuration of a memory device and / or host that supports a fixed bank group but allows the selection of different banks within the fixed bank group to form a bank pair. For example, the current bank of the bank pair to which the precharge and / or refresh operation is to be applied may be indicated by bits BA0, BA1, BG0, and BG1, while the other bank of the refresh pair may be indicated by dBA0, dBA1, BG0, and BG1, allowing for a flexible selection of banks within the fixed bank group. Similar to the description in relation to FIG. 8b, when the values ​​of the bits marked AB, dBA0, dBA1, dBG0, and dBG1 are all 1, the command may indicate that all bank refresh operations should be performed. When AB, dBG0, and dBG1 are set to 100, the command may indicate that a precharge command should be applied to the same row as the open row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, and that refresh operations should be performed for the current bank and the other bank of the bank pair. If AB, dBG0, and dBG1 are set to 101, the command may indicate that a precharge operation should be performed on the same row as the open row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, a refresh operation should be performed on the current bank and the other bank of the bank pair, and an enable operation should be applied to the same row as the open row of the current bank indicated by the BA0, BA1, BG0, and BG1 bits.When AB, dBG0, and dBG1 are set to 110, the command may indicate that a precharge operation should be performed on the same row as the open row of the current bank of the bank pair and the corresponding row of the other bank of the bank pair, a refresh operation should be applied to the current bank indicated by the BA0, BA1, BG0, and BG1 bits and the other bank of the bank pair indicated by the dBA0, dBA1, BG0, and BG1 bits, and an enable operation should be applied to the corresponding row of the other bank of the bank pair. The other bank of the bank pair may be, for example, a different bank of the fixed bank pair indicated by dBA0 and dBA1. When AB, dBA0, and dBA1 are set to 111, the command may indicate that a precharge operation should be applied to the same row as the open row of the current bank of the bank pair and the corresponding row of the second bank of the bank pair, a refresh operation should be performed for both the current bank of the bank pair and the other bank of the bank pair, and an enable operation should be applied to the same row as the open row of the current bank of the bank pair indicated by the BA0, BA1, BG0, and BG1 bits and the corresponding row of the other bank of the bank pair indicated by the dBA0, dBA1, BG0, and BG1 bits. Thus, when the same row as the open row of the current bank of the bank group is precharged and enabled, the corresponding row of the other bank of the bank group may also be precharged and enabled.

[0058] Operations for supporting merge memory commands according to embodiments of the disclosure are described in connection with FIG. 9. A merge memory command issued by a host to a memory device of the method (900) causes the memory system (250) to perform operations by receiving a merge command from a host device, starting from block (902), to perform at least a precharge operation, a refresh operation, and an activation operation for one or more rows of the memory module by means of a memory controller coupled to the memory module. The command may be a merge memory command for instructing the memory system to perform a number of operations, such as a precharge operation, a refresh operation, and an activation operation, for example, with a single command. In some embodiments, the merge command may include (1) a command for performing a precharge and refresh operation, (2) a precharge, refresh, and write operation, or (3) only a precharge, refresh, and read operation without an activation operation. In some embodiments, the command may be a command having a write command format, a read command format, a precharge command format, or a refresh command format. For example, the command may be a read or write command that includes an indication to perform a precharge operation, a refresh operation, and an enable operation in addition to the read operation or write operation indicated by the read or write command. As another example, the command may be a precharge command that includes an indication to perform a refresh operation and an enable operation in addition to the precharge operation indicated by the precharge command. As another example, the command may be a refresh command that includes an indication to perform a precharge operation and an enable operation in addition to the refresh operation indicated by the refresh command.In some embodiments, as disclosed herein, in systems that do not support merge memory commands, one or more bits of a command used to indicate a read operation, a write operation, a precharge operation, or a refresh operation may be repurposed to indicate that additional operations, such as precharge, refresh, and enable operations, should be performed. The command may be transmitted via a command bus between a host device and a memory controller.

[0059] When the format of the command is a read command or a write command, the command may include an indication that a precharge operation and an activation operation should be performed on a first row of a first bank of the memory module and a refresh operation should be performed on a first bank of the memory module. The first row may be, for example, an open row. As another example, when the format of the command is a read command or a write command, the command may further include an indication that a precharge operation and an activation operation should be performed on a second row of a second bank of the memory module, wherein the second row corresponds to the first row, such as having the same row number as the first row, and the first and second banks are members of a bank pair.

[0060] When the format of the command is a precharge command format, the command may include a first indication that a precharge operation should be performed on a first row of a first bank of the memory module and a second row of a second bank of the memory module, a refresh operation should be performed on the first bank and the second bank, and an activation operation should be performed on a first row of the first bank of the memory module. The first row may be, for example, an open row of the first bank. The first row may be traced in memory, for example, and may be stored in a representation of the memory module or other memory, such as, because the precharge command may not include an indication of a first, or open, row in some embodiments. The second row of the second bank may correspond to the first row of the first bank, for example, having the same row number as the first row. The first and second banks may be, for example, the first and second banks of a bank pair of memory modules. Alternatively or additionally, the command may include a second indication that a precharge operation should be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed on the first bank and the second bank of the memory module, and an activation operation should be performed on the second row of the second bank of the memory module. Alternatively or additionally, the command may include a third indication that a precharge operation should be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed on the first bank and the second bank, and an activation operation should be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module.For example, the first indication may include a first bit pattern of one or more bits of the command, the second indication may include a second bit pattern of one or more bits of the command, and the third indication may include a third bit pattern of one or more bits of the command. In some embodiments, the command may include an indication that precharge, refresh, and enable operations should be performed only on a single bank and / or a row of a single bank. For example, combined precharge, refresh, and / or enable commands may indicate that precharge, refresh, and / or enable operations should be performed on a single bank and / or a row of a single bank when the memory module operates in 8-bank mode or LPDDR4 mode, such as when the memory module is configured in 8-bank mode or is an LPDDR4 memory module configured according to the LPDDR4 specification. As one specific example, the command may include an indication that a precharge operation should be performed on the first row of the first bank of the memory module, a refresh operation should be performed on the first bank of the memory module, and an activation operation should be performed on the first row of the first bank of the memory module.

[0061] When the format of the command is a refresh command format, the command may include a first indication that a precharge operation should be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed on the first bank and the second bank, and an activation operation should be performed on the first row of the first bank of the memory module. The first row may be, for example, an open row of the first bank. The first and second banks may be, for example, the first and second banks of a bank pair of the memory module. The second row of the second bank of the memory module may correspond to the first row of the first bank of the memory module, for example, having the same row number as the first row of the first bank of the memory module. Alternatively or additionally, the command may include a second indication that a precharge operation should be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed on the first bank and the second bank of the memory module, and an activation operation should be performed on the second row of the second bank of the memory module. Alternatively or additionally, the command may include a third indication that a precharge operation should be performed on the first row of the first bank and the second row of the second bank, a refresh operation should be performed on the first bank and the second bank, and an activation operation should be performed on the first row of the first bank and the second row of the second bank. For example, the first indication may include a first bit pattern of one or more bits of the command, the second indication may include a second bit pattern of one or more bits of the command, and the third indication may include a third bit pattern of one or more bits of the command. Therefore, the activation action according to the merge command may be applied only to the row of the current bank of the bank pair, only to the corresponding row of the other bank of the bank pair for the row, or to both rows of both banks of the bank pair.In some embodiments, the first bank and the second bank may be banks having the same, fixed, bank number of different bank groups, and in some embodiments, the first bank and the second bank may be banks of the same, fixed, bank group having different bank numbers. In some embodiments, one or more bits of the command may include an indication of a fixed bank number and a variable bank group for the first bank and the second bank, or an indication of a variable bank number and a fixed bank group for the first bank and the second bank. In some embodiments, both the bank number and the bank group of the first bank and the second bank may be variable and may be indicated by one or more bits of the command. In some embodiments, the host device and the memory module may be configured to support commands that include indications of fixed or variable first and second banks in merge memory commands.

[0062] In block (904), the memory controller may perform a precharge operation, a refresh operation, and an enable operation upon receiving a command. For example, based on the command, the memory controller may perform a precharge operation and an enable operation for one or more rows of one or more memory banks and a refresh operation for one or more of the memory banks. Thus, the memory controller may perform multiple operations, such as a precharge operation, a refresh operation, and an enable operation, in response to receiving a single command to perform the operations.

[0063] Operations for supporting merge memory commands according to embodiments of the disclosure are described in FIG. 10. A merge memory command issued by a host to a memory device of the method (1000) causes the memory system (250) to perform operations by generating a merge command to perform at least a precharge operation, a refresh operation, and an activation operation on one or more rows of a memory module, by a host device configured to communicate with a memory module of the memory system through a channel, starting from a block (1002). The command may be, for example, a command as described in relation to the method (900) of FIG. 9. The channel may include a command bus for transmitting commands, for example, such as the merge commands described herein, from the host device to the memory module. Generating the command may include, for example, determining one or more rows of one or more banks of a memory module on which precharge, refresh, and activation operations are to be performed.

[0064] In block (1004), a command can be transmitted to a memory module. For example, the command can be transmitted through a command bus of a channel configured to allow the host device to communicate with a memory module of the memory system.

[0065] A wireless communication device may include a memory system as exemplified in at least FIGS. 1 and 2 and may be configured to receive and output data from a memory array and to support merge memory commands for improved bus utilization in volatile memory on the memory array. A memory system according to any of the embodiments disclosed herein may be provided in or integrated therein of any processor-based device. Examples include, without limitation, set-top boxes, entertainment units, navigation devices, communication devices, fixed position data units, mobile position data units, global positioning system (GPS) devices, mobile phones, mobile phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal information terminals (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, or avionics systems.

[0066] In one or more embodiments, techniques for memory storage and retrieval may include additional embodiments, e.g., any single embodiment or any combination of embodiments described below in connection with one or more other processes or devices described elsewhere in this specification. In a first embodiment, supporting data operations may include a device configured to perform operations including receiving a merge command from a host device to perform at least a precharge operation, a refresh operation, and an enable operation on one or more rows of a memory module, and performing the precharge operation, the refresh operation, and the enable operation upon receiving the merge command.

[0067] Additionally, the device may perform or operate according to one or more aspects as described below. In some implementations, the device includes a wireless device such as a UE. In some implementations, the device includes a remote server, such as a cloud-based computing solution, that receives image data for processing to determine output image frames. In some implementations, the device may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the device. In some other implementations, the device may include a non-transient computer-readable storage medium on which program code is written, and the program code may be executable by a computer to allow the computer to perform the operations described herein with reference to the device. In some implementations, the device may include one or more means configured to perform the operations described herein. As described herein, the operations may include receiving commands, transmitting commands, precharge operations, refresh operations, enable operations, and other operations. In some implementations, the method may include one or more operations described herein in relation to the device. In some implementations, the device may include a memory controller configured to be coupled to a memory module through a first channel and to access data stored in the memory module through the first channel. The memory controller may be configured to perform or operate according to one or more embodiments as described herein.

[0068] In the second embodiment, in combination with the first embodiment, the merge command is received by the memory controller from the host device via the command bus.

[0069] In the third embodiment, in combination with one or more of the first or second embodiments, the format of the merge command is a read command format or a write command format.

[0070] In the fourth embodiment, in combination with one or more of the first to third embodiments, the merge command includes an indication that a precharge operation and an activation operation should be performed for a first row of a first bank of the memory module and a refresh operation should be performed for a first bank of the memory module.

[0071] In the fifth embodiment, in combination with one or more of the first to fourth embodiments, the format of the merge command is a precharge command format.

[0072] In the sixth embodiment, in combination with one or more of the first to fifth embodiments, the merge command includes an indication that a precharge operation should be performed on the first row of the first bank of the memory module, a refresh operation should be performed on the first bank of the memory module, and an activation operation should be performed on the first row of the first bank of the memory module.

[0073] In the seventh embodiment, in combination with one or more of the first to sixth embodiments, the merge command has a first indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row corresponding to the first row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank, and an activation operation is to be performed on a first row of the first bank of the memory module - the first bank and the second bank belong to a bank pair -; a second indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank of the memory module, and an activation operation is to be performed on a second row of the second bank of the memory module; or includes a third indication that a precharge operation should be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed for the first bank and the second bank, and an activation operation should be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module.

[0074] In the eighth embodiment, in combination with one or more of the first to seventh embodiments, the format of the merge command is the refresh command format.

[0075] In the ninth embodiment, in combination with one or more of the first to eighth embodiments, the merge command has a first indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row corresponding to the first row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank, and an activation operation is to be performed on a first row of the first bank of the memory module - the first bank and the second bank belong to a bank pair -; a second indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank of the memory module, and an activation operation is to be performed on a second row of the second bank of the memory module; It includes a third indication that a precharge operation should be performed for the first row of the first bank and the second row of the second bank, a refresh operation should be performed for the first bank and the second bank, and an activation operation should be performed for the first row of the first bank and the second row of the second bank.

[0076] In the 10th embodiment, supporting data operations may include a device configured to perform operations including generating a merge command to perform at least a precharge operation, a refresh operation, and an activation operation for one or more rows of a memory module, and transmitting the merge command to the memory module.

[0077] Additionally, the device may be performed or operated according to one or more aspects as described below. In some implementations, the device includes a wireless device such as a UE. In some implementations, the device includes a remote server, such as a cloud-based computing solution, that receives image data for processing to determine output image frames. In some implementations, the device may include at least one processor and memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the device. In some other implementations, the device may include a non-transient computer-readable storage medium on which program code is written, and the program code may be executable by a computer to allow the computer to perform the operations described herein with reference to the device. In some implementations, the device may include one or more means configured to perform the operations described herein. In some implementations, the method may include one or more operations described herein in relation to the device. In some implementations, the device may include a host device configured to communicate with a memory module through a channel. The host device may include a memory controller coupled to a channel and configured to perform or operate according to one or more of the embodiments described herein.

[0078] In the 11th embodiment, in combination with the 10th embodiment, the merge command is transmitted to the memory module by the host device via the channel's command bus.

[0079] In the 12th embodiment, in combination with one or more of the 10th to 11th embodiments, the format of the merge command is a read command format or a write command format.

[0080] In the 13th embodiment, in combination with one or more of the 10th to 12th embodiments, the merge command includes an indication that a precharge operation and an activation operation should be performed on a first row of a first bank of the memory module and a refresh operation should be performed on a first bank of the memory module.

[0081] In the 14th embodiment, in combination with one or more of the 10th to 13th embodiments, the format of the merge command is a precharge command format.

[0082] In the 15th embodiment, in combination with one or more of the 10th to 14th embodiments, the merge command includes an indication that a precharge operation should be performed on a first row of a first bank of a memory module, a refresh operation should be performed on a first bank of a memory module, and an activation operation should be performed on a first row of a first bank of a memory module.

[0083] In the 16th embodiment, in combination with one or more of the 10th to 15th embodiments, the merge command has a first indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row corresponding to the first row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank, and an activation operation is to be performed on a first row of the first bank of the memory module - the first bank and the second bank belong to a bank pair -; a second indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank of the memory module, and an activation operation is to be performed on a second row of the second bank of the memory module; or includes a third indication that a precharge operation should be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module, a refresh operation should be performed for the first bank and the second bank, and an activation operation should be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module.

[0084] In the 17th embodiment, in combination with one or more of the 10th to 16th embodiments, the format of the merge command is a refresh command format.

[0085] In the 18th embodiment, in combination with one or more of the 10th to 17th embodiments, a first indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row corresponding to the first row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank, and an activation operation is to be performed on a first row of the first bank of the memory module - the first bank and the second bank belong to a bank pair -; a second indication that a precharge operation is to be performed on a first row of the first bank of the memory module and a second row of the second bank of the memory module, a refresh operation is to be performed on the first bank and the second bank of the memory module, and an activation operation is to be performed on a second row of the second bank of the memory module; It includes a third indication that a precharge operation should be performed for the first row of the first bank and the second row of the second bank, a refresh operation should be performed for the first bank and the second bank, and an activation operation should be performed for the first row of the first bank and the second row of the second bank.

[0086] In the description of the embodiments of this specification, numerous specific details, such as examples of specific components, circuits, and processes, are presented to provide a complete understanding of the disclosure. The term “coupled” as used herein means connected through or directly connected via one or more interposed components or circuits. Additionally, in the following description and for the purposes of explanation, specific names are used to provide a complete understanding of the disclosure. However, it will be apparent to those skilled in the art that these specific details may not be required to implement the teachings disclosed herein. In other examples, well-known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of the disclosure.

[0087] Some parts of the following detailed descriptions are presented in terms of procedures, logical blocks, processing, and other symbolic representations of operations on data bits within computer memory. In this disclosure, procedures, logical blocks, processes, etc., are considered to be self-consistent sequences of steps or instructions leading to a desired result. Steps are those that require physical operations of physical quantities. Although not essential, these quantities typically take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated in a computer system.

[0088] In the drawings, a single block may be described as performing a function or functions. The function or functions performed by the block may be performed in a single component or across multiple components, and / or using hardware, software, or a combination of hardware and software. To clearly exemplify this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps are described below in general terms of their functionality. Whether such function is implemented in hardware or software depends on the design constraints imposed on the specific application and the entire system. Those skilled in the art may implement the described function in various ways for each specific application, but such implementation decisions should not be interpreted as taking it out of the scope of this disclosure. Additionally, exemplary devices may include components other than those illustrated, including well-known components such as processors, memory, etc.

[0089] As will be apparent from the following discussion, unless otherwise specifically stated, throughout this application, discussions utilizing terms such as “accessing,” “receiving,” “transmitting,” “using,” “selecting,” “determining,” “normalizing,” “multiplying,” “averaging,” “monitoring,” “comparing,” “applying,” “updating,” “measuring,” “deriving,” “settling,” “generating,” etc. refer to actions and processes of a computer system or similar electronic computing device that manipulate or convert data expressed as a physical (electronic) quantity within the registers and memories of a computer system into other data similarly expressed as a physical quantity within the registers, memories, or other such information storage, transmission, or display devices.

[0090] The terms “device” and “device” are not limited to one or a specific number of physical objects (e.g., one smartphone, one camera controller, one processing system, etc.). As used herein, a device may be any electronic device having one or more parts capable of implementing at least some parts of the present disclosure. Although the descriptions and examples herein use the term “device” to describe various aspects of the present disclosure, the term “device” is not limited to a specific configuration, type, or number of objects. As used herein, a device may include a device or a part of a device for performing the described operations.

[0091] Certain components within a device or apparatus described by terms of other similar designations referring to "means for accessing," "means for receiving," "means for transmitting," "means for using," "means for selecting," "means for determining," "means for normalizing," "means for multiplying," or one or more operations on data such as image data may refer to a processing circuit (e.g., application specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the cited function through hardware, software, or a combination of hardware configured by software.

[0092] Those skilled in the art will understand that information and signals may be represented using any of the various different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the description may be represented as voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0093] The components, functional blocks, and modules described herein in connection with FIGS. 1 and 2 include, among other examples, processors, electronic devices, hardware devices, electronic components, logic circuits, memories, software codes, firmware codes, or any combination thereof. Software should be broadly interpreted to mean, among other examples, instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, and / or functions, regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description language, or other terms. Additionally, the features discussed herein may be implemented through specialized processor circuits, through executable instructions, or through combinations thereof.

[0094] Those skilled in the art will recognize that one or more blocks (or operations) described with reference to the drawings included in this description may be combined with one or more blocks (or operations) described with reference to other drawings. For example, one or more blocks (or operations) of FIG. 3 may be combined with one or more blocks (or operations) of FIG. 1 or FIG. 2.

[0095] Those skilled in the art will further recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure of this specification may be implemented as electronic hardware, computer software, or a combination of both. To clearly exemplify this interchangeability between hardware and software, the various exemplary components, blocks, modules, circuits, and steps have been described above in terms of their functions. Whether such functions are implemented in hardware or in software depends on the design constraints imposed on the specific application and the overall system. Those skilled in the art may implement the described functions in various ways for each specific application, but such implementation decisions should not be interpreted as taking the scope of this disclosure out of reach of the art. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described in this specification is merely an example, and that components, methods, or interactions of various aspects of this disclosure may be combined or performed in ways different from those exemplified and described in this specification.

[0096] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been described generally in terms of functionality and has been illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or in software depends on the design constraints imposed on the specific application and the overall system.

[0097] Hardware and data processing devices used to implement the various exemplary logics, logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or performed as a general-purpose single- or multi-chip processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor or any conventional processor, a controller, a microcontroller, or a state machine. In some implementations, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some implementations, specific processes and methods may be performed by circuits specific to a given function.

[0098] In one or more embodiments, the described functions may be implemented in hardware, digital electronic circuits, computer software, firmware, or any combination thereof, comprising structures and structural equivalents disclosed herein. The implementations of the claimed subject matter described herein may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on computer storage media for execution by a data processing device or for controlling the operation of a data processing device.

[0099] When implemented in software, functions may be stored as one or more instructions or code on a computer-readable medium or transmitted therethrough. Processes of the method or algorithm disclosed herein may be implemented as processor-executable software modules that may reside on a computer-readable medium. Computer-readable media include both communication media and computer storage media, including any medium that may be enabled to transmit a computer program from one place to another. Storage media may be any available media that can be accessed by a computer. By example, but not by limitation, such computer-readable media may include random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and can be accessed by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and discs include CDs (compact discs), laser discs, optical discs, DVDs (digital versatile discs), floppy disks, and Blu-ray discs, wherein disks generally reproduce data magnetically, while discs reproduce data optically using a laser. Combinations of the above should also be included within the scope of computer-readable media.Additionally, the operations of the method or algorithm may reside as one or any combination or set of codes and instructions on a machine-readable medium and a computer-readable medium that can be incorporated into a computer program product.

[0100] Various modifications to the embodiments described in this disclosure may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to some other embodiments without departing from the spirit or scope of this disclosure. Accordingly, the claims are not intended to be limited to the embodiments described in this specification, but will be consistent with the broadest scope of the disclosure, principles, and novel features disclosed herein.

[0101] Additionally, those skilled in the art will readily recognize that opposite terms, such as “upper” and “lower” or “forward” and “rear” or “top” and “bottom” or “forward” and “backward,” are sometimes used for ease of describing the drawings, indicate relative positions corresponding to the orientation of the drawings on a properly oriented page, and may not reflect the proper orientation of any device as implemented.

[0102] As used herein, in various tenses of the verb “to couple,” the term “coupled to” may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B) in order to operate certain intended functions. In the case of electrical components, the term “coupled to” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected between them). In some examples, the term “coupled to” means the transfer of electrical energy between element A and element B to operate certain intended functions.

[0103] In some examples, the term "electrically coupled" means having a current, or being configurable to allow a current to flow between elements A and B. For example, elements A and B may be connected via resistors, transistors, or inductors, in addition to wires, traces, or other electrically conductive materials and components. Additionally, for radio frequency functions, elements A and B may be "electrically connected" via capacitors.

[0104] Certain features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable subcombination in multiple implementations. Furthermore, although features are described above as operating in specific combinations and may even be claimed as such initially, one or more features from the claimed combination may be omitted from the combination in some cases, and the claimed combination may relate to a subcombination or a variation of a subcombination.

[0105] Similarly, although operations are depicted in the drawings in a specific order, this should not be understood as requiring that such operations be performed in the specific order depicted or in a sequential order, or that all illustrated operations be performed, in order to achieve desired results. Additionally, the drawings may schematically depict one or more exemplary processes in the form of flowcharts. However, other operations not depicted may be included in the schematically illustrated exemplary processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together into a single software product or packaged into multiple software products. Additionally, some other implementations fall within the scope of the following claims. In some cases, the actions mentioned in the claims may be performed in a different order and still achieve desired results.

[0106] As used herein, including in the claims, the term “or” means that, when used in a list of two or more items, any one of the listed items may be employed alone, or any combination of two or more of the listed items may be employed. For example, if a configuration is described as comprising components A, B, or C, the configuration may include A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Additionally, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of” indicates a disjunctive list, for example, such that a list of “at least one of A, B, or C” implies A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any of these as any combination thereof.

[0107] The term “substantially” is defined as, as understood by those skilled in the art, as generally specified rather than entirely (and includes specified; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel). In any disclosed embodiments, the term “substantially” may be replaced with “within a [percentage] of specified,” where the percentage includes .1, 1, 5, or 10 percent.

[0108] The prior description of the present disclosure is provided to enable any person skilled in the art to use or practice the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but is to be in accordance with the broadest scope of the principles and novel features disclosed herein.

Claims

Claim 1 As a device, it includes a memory controller coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel, and the memory controller, Receiving a merge command from a host device for performing at least a precharge operation, a refresh operation, and an activation operation on one or more rows of the memory module; and A device configured to perform operations including performing the precharge operation, the refresh operation, and the activation operation upon receiving the above merge command. Claim 2 In claim 1, the device, wherein the merge command is received by the memory controller from the host device via the command bus. Claim 3 A device according to claim 1, wherein the format of the merge command is a read command format or a write command format. Claim 4 A device according to paragraph 3, wherein the merge command includes an indication that the precharge operation and the activation operation should be performed for the first row of the first bank of the memory module and the refresh operation should be performed for the first bank of the memory module. Claim 5 A device according to claim 1, wherein the format of the merge command is a precharge command format. Claim 6 A device according to claim 5, wherein the merge command includes an indication that the precharge operation is to be performed on the first row of the first bank of the memory module, the refresh operation is to be performed on the first bank of the memory module, and the activation operation is to be performed on the first row of the first bank of the memory module. Claim 7 In paragraph 5, the merge command comprises: a first indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row corresponding to the first row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank, and the activation operation shall be performed on the first row of the first bank of the memory module—the first bank and the second bank belong to a bank pair—; a second indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank of the memory module, and the activation operation shall be performed on the second row of the second bank of the memory module; A device comprising a third indication that the precharge operation is to be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation is to be performed for the first bank and the second bank, and the activation operation is to be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module. Claim 8 A device according to claim 1, wherein the format of the merge command is a refresh command format. Claim 9 In claim 8, the merge command comprises: a first indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row corresponding to the first row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank, and the activation operation shall be performed on the first row of the first bank of the memory module—the first bank and the second bank belong to a bank pair—; a second indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank of the memory module, and the activation operation shall be performed on the second row of the second bank of the memory module; A device comprising a third indication that the precharge operation shall be performed for the first row of the first bank and the second row of the second bank, the refresh operation shall be performed for the first bank and the second bank, and the activation operation shall be performed for the first row of the first bank and the second row of the second bank. Claim 10 A method comprising: receiving a merge command from a host device for performing at least one precharge operation, a refresh operation, and an activation operation on one or more rows of the memory module by means of a memory controller coupled to the memory module through a first channel and configured to access data stored in the memory module through the first channel; and performing the precharge operation, the refresh operation, and the activation operation upon receiving the merge command. Claim 11 In paragraph 10, the method wherein the merge command is received by the memory controller from the host device via the command bus. Claim 12 In paragraph 10, the method wherein the format of the above merge command is a read command format or a write command format. Claim 13 A method according to claim 12, wherein the merge command includes an indication that the precharge operation and the activation operation should be performed for the first row of the first bank of the memory module and the refresh operation should be performed for the first bank of the memory module. Claim 14 In paragraph 10, the method wherein the format of the above merge command is a precharge command format. Claim 15 A method according to claim 14, wherein the merge command includes an indication that the precharge operation is to be performed on the first row of the first bank of the memory module, the refresh operation is to be performed on the first bank of the memory module, and the activation operation is to be performed on the first row of the first bank of the memory module. Claim 16 In paragraph 14, the merge command comprises: a first indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row corresponding to the first row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank, and the activation operation shall be performed on the first row of the first bank of the memory module—the first bank and the second bank belong to a bank pair—; a second indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank of the memory module, and the activation operation shall be performed on the second row of the second bank of the memory module; A method comprising a third indication that the precharge operation is to be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation is to be performed for the first bank and the second bank, and the activation operation is to be performed for the first row of the first bank of the memory module and the second row of the second bank of the memory module. Claim 17 In paragraph 10, the method wherein the format of the above merge command is a refresh command format. Claim 18 In claim 17, the merge command comprises: a first indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row corresponding to the first row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank, and the activation operation shall be performed on the first row of the first bank of the memory module—the first bank and the second bank belong to a bank pair—; a second indication that the precharge operation shall be performed on the first row of the first bank of the memory module and the second row of the second bank of the memory module, the refresh operation shall be performed on the first bank and the second bank of the memory module, and the activation operation shall be performed on the second row of the second bank of the memory module; A method comprising a third indication that the precharge operation shall be performed for the first row of the first bank and the second row of the second bank, the refresh operation shall be performed for the first bank and the second bank, and the activation operation shall be performed for the first row of the first bank and the second row of the second bank. Claim 19 As a device, it includes a host device configured to communicate with a memory module through a channel, said host device includes a memory controller coupled to said channel, and said memory controller, Generating a merge command to perform at least a precharge operation, a refresh operation, and an activation operation on one or more rows of the above memory module; and A device configured to perform operations including transmitting the above merge command to the memory module. Claim 20 In paragraph 19, the device wherein the merge command is transmitted to the memory module by the host device via the command bus of the channel. Claim 21 In paragraph 19, the device wherein the format of the merge command is a read command format or a write command format. Claim 22 A device according to claim 21, wherein the merge command includes an indication that the precharge operation and the activation operation should be performed for the first row of the first bank of the memory module and the refresh operation should be performed for the first bank of the memory module. Claim 23 In paragraph 19, the device, wherein the format of the merge command is a precharge command format. Claim 24 In paragraph 19, the device, wherein the format of the above merge command is a refresh command format. Claim 25 A method comprising: generating a merge command for performing at least a precharge operation, a refresh operation, and an activation operation on one or more rows of the memory module by a host device configured to communicate with the memory module through a channel; and transmitting the merge command to the memory module. Claim 26 In paragraph 25, the method wherein the merge command is transmitted to the memory module by the host device through the command bus of the channel. Claim 27 In paragraph 25, the method wherein the format of the above merge command is a read command format or a write command format. Claim 28 A method according to claim 25, wherein the merge command includes an indication that the precharge operation and the activation operation should be performed for the first row of the first bank of the memory module and the refresh operation should be performed for the first bank of the memory module. Claim 29 In paragraph 25, the method wherein the format of the above merge command is a precharge command format. Claim 30 In paragraph 25, the format of the above merge command is a refresh command format.

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