Dual polarization dynamic alignment system of integrated phased arrays and the method thereof
Patent Information
- Application Number
- KR1020250023304
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-01
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Figure P1020250023304_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a dual-polarization dynamic alignment system and method for an integrated phase array, and more specifically, to a technique for effectively mitigating cross-polarization leakage (XPL) by aligning two polarization signals from a receiving dual-polarization antenna regardless of the alignment conditions between a transmitting antenna and a receiving antenna. Background Technology
[0002] Recently, there has been an increase in applications requiring high data transfer rates, such as wireless VR / AR. The 60 GHz band is suitable for these applications as it can achieve tens of Gbps. Meanwhile, dual-polarized (DP) multiple-input and multiple-output (MIMO) techniques can further improve data transfer rates by utilizing the polarization diversity of DP antennas.
[0003] However, actual implemented DP MIMO systems can face difficulties due to XPL. Because it relies on the polarization orthogonality of the antennas, isolation between the two data is drastically degraded if the transmitting and receiving antennas are not aligned. Additionally, actual fabricated DP antennas have a finite cross-polarization isolation (XPI), which is the ratio of the XPL to the amplitude of the desired co-polarization (CP) signal. Therefore, XPL removal technology capable of improving XPI in DP MIMO systems is based on Prior Art 1 (K. Dasgupta, S. Daneshgar, C. Thakkar, S. Kang, A. Chakrabarti, S. Yamada, N. Narevsky, D. Choudhury, J.E. Jaussi, B. Casper, “A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 1224-1235, Dec. 2018.) and Prior Art 2 (J. Pang, Z. Li, X. Luo, J. Alvin, R. Saengchan, AA. Fadila, K. Yanagisawa, Y. Zhang, Z. Chen, Z. Huang, X. Gu, R. Wu, Y. Wang, D. You, B. Liu, Z. Sun, Y. Zhang, H. Huang, N. Oshima, K. Motoi, S. Hori, K. Kunihiro, T. Kaneko, A. Shirane, and K. Okada, “A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems,” IEEE Journal of Solid-State Circuits, vol.56, no. 4, pp. 1310-1326, Apr. 2021.) is essential.
[0004] The system reported in Prior Art Document 1 utilizes a mixed-signal equalizer with a focus on removing XPL caused by multipath propagation. While this work successfully removed XPL over a wide bandwidth, it had limitations such as the very large size and DC power consumption of the mixed-signal equalizer, and it assumed that the transmitting and receiving antennas were aligned. Prior Art Document 2 proposes an RF leakage removal technique in the transmission mode. This technique achieves XPL removal by aligning the magnitude and phase of the leakage signal through a removal path composed of a variable gain amplifier and the insertion of a phase converter between the V-path and the H-path. However, due to the asymmetry of the XPL remover, the XPL removal bandwidth is narrow at 400 MHz, and it has only been reported for cases where misalignment between the transmitting and receiving antennas occurred at 30°. Therefore, there is a need for a technique to improve XPI and the signal-to-interference-noise ratio (SINR) by removing XPL caused by the misalignment of the transmitting and receiving antennas.
[0005] Meanwhile, a technique has been reported to dynamically control polarization by vectorially combining two polarized signals using a DP antenna. While this technique can resolve polarization misalignment by controlling the polarization of the transmitting or receiving antenna, it has the disadvantage that it cannot be applied to DP MIMO applications because it can only control a single polarization with a DP antenna. The problem to be solved
[0006] The objective of the present invention is to align dual polarization between a transmitting antenna and a receiving antenna by dynamically controlling two polarized signals.
[0007] However, the technical problems that the present invention aims to solve are not limited to the above problems, and can be expanded in various ways without departing from the technical concept and scope of the present invention. means of solving the problem
[0008] A dual-polarization dynamic alignment system of an integrated phase array according to an embodiment of the present invention comprises: a low-noise amplifier that receives a V-polarization signal and an H-polarization signal input to each phase array channel of a receiving dual-polarization antenna; a phase converter that converts the phase into four signal paths directly coupled and cross-coupled between the V-polarization signal and the H-polarization signal according to the angle of polarization misalignment; and a phase compensation attenuator that performs phase and gain control for the four signal paths.
[0009] A dual-polarization dynamic alignment method of an integrated phase array performed by a computer comprising at least one process according to an embodiment of the present invention comprises: receiving a V-polarization signal and an H-polarization signal input to each phase array channel of a receiving dual-polarization antenna; converting the phase into four signal paths that are directly coupled and cross-coupled between the V-polarization signal and the H-polarization signal according to the angle of polarization misalignment; and performing phase and gain control for the four signal paths. Effects of the invention
[0010] According to an embodiment of the present invention, cross-polarization leakage (XPL) can be effectively mitigated by dynamically controlling two polarization signals to align dual polarization between a transmitting antenna and a receiving antenna.
[0011] According to an embodiment of the present invention, cross-polarization separation (XPI) can be improved even under conditions where the transmitting antenna and the receiving antenna are not aligned up to 90° in the 60 GHz unlicensed band.
[0012] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing
[0013] Figure 1 is a schematic diagram illustrating the differences between a DPDA system according to an embodiment of the present invention and a conventional system. FIG. 2 illustrates an operation flowchart of a dual-polarization dynamic alignment method of an integrated phase array according to an embodiment of the present invention. FIGS. 3a to 3c are illustrated to explain the phase control operation of a DPDA system according to an embodiment of the present invention. Figure 4 shows a graph of XPI for gain mismatch and phase mismatch according to an embodiment of the present invention. FIGS. 5a to 5c illustrate the results of an analysis of the impact caused by a discrepancy between the main path and the cancellation path according to an embodiment of the present invention. Figure 6 shows the calculated SNR for XPI according to an embodiment of the present invention. DP This is a graph of FIG. 7 is a block diagram of a dual polarization dynamic alignment (DPDA) system of an integrated phase array according to an embodiment of the present invention. FIG. 8 illustrates a schematic diagram of a low-noise amplifier according to an embodiment of the present invention. FIG. 9 illustrates a schematic diagram of a vector-sum phase converter according to an embodiment of the present invention. Figures 10a and 10b illustrate the RMS gain and phase error calculated as a function of I / Q amplitude and phase mismatch. Figure 11 illustrates the simulated phase and gain mismatch of an orthogonal coupler in VSPS. FIGS. 12a and FIGS. 12b illustrate schematic diagrams of a variable gain cell according to an embodiment of the present invention. FIG. 13 illustrates a schematic diagram of a presented three-stage phase compensation RTA according to an embodiment of the present invention. Figure 14 shows the S of the RTA for various transistor sizes. 21 It is a city. Figures 15a and 15b are illustrated to explain a phase compensation technique in which a series capacitor is inserted into an nMOS. FIG. 16 illustrates a graph of the simulated phase response of the presented 3-stage phase compensation RTA according to an embodiment of the present invention. Figure 17 is a table showing the results of comparing the present invention with existing technology. Specific details for implementing the invention
[0014] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.
[0015] The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used herein, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements.
[0016] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.
[0017] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted.
[0019] The dual polarization dynamic alignment (DPDA) system of an integrated phase array according to an embodiment of the present invention supports the alignment of two polarization signals from a receiving dual-polarization antenna regardless of the alignment conditions between a transmitting antenna and a receiving antenna, while effectively mitigating cross-polarization leakage (XPL).
[0020] To verify the technique presented in the present invention, a receiving phase array IC with a 2V+2H configuration was fabricated using a 65nm CMOS process, and a prototype antenna-in-package (AiP) was fabricated by integrating it with a two-element dual-polarized antenna. According to experimental results, even when the alignment between the transmitting antenna and the receiving antenna is misaligned by up to 90°, the prototype AiP achieved cross-polarization separation (XPI) of 20–32dB within a 2GHz bandwidth in the 58.2GHz band when the presented technique was adopted.
[0021] The present invention will be described in detail below with reference to FIGS. 1 to 17.
[0023] Figure 1 is a schematic diagram illustrating the differences between a DPDA system according to an embodiment of the present invention and a conventional system.
[0024] The dual polarization dynamic alignment (DPDA) system of an integrated phase array according to an embodiment of the present invention (this work) presents a dual polarization dynamic alignment technique for a DP MIMO system in the 60 GHz unlicensed band. As illustrated in FIG. 1, the DPDA system according to an embodiment of the present invention extends dynamic polarization control to a DP MIMO system.
[0025] A DPDA system according to an embodiment of the present invention can align polarization between a transmitting antenna (Tx) and a receiving antenna (Rx) by dynamically controlling two polarized signals (Aligned Rx). In addition, a DPDA system according to an embodiment of the present invention can be extended to a phase array essential for improving SINR in the millimeter wave band.
[0027] FIG. 2 illustrates an operation flowchart of a dual-polarization dynamic alignment method of an integrated phase array according to an embodiment of the present invention, and FIGS. 3a to 3c illustrate the phase control operation of a DPDA system according to an embodiment of the present invention.
[0028] The method of FIG. 2 is performed by a dual polarization dynamic alignment (DPDA) system of an integrated phase array according to an embodiment of the present invention shown in FIG. 7.
[0029] Referring to FIG. 2, in step S210, the DPDA system according to an embodiment of the present invention receives a V-polarized signal and an H-polarized signal input to each phase array channel of the receiving dual-polarized antenna.
[0030] At this time, either the V-polarized signal or the H-polarized signal input to each phase array channel is input to a low-noise amplifier (LNA), split into two paths at the output of the low-noise amplifier, and can pass through two phase converters (PS) and two phase-compensated attenuators.
[0031] In step S220, the DPDA system according to an embodiment of the present invention converts the phase into four signal paths that are directly coupled and cross-coupled between the V-polarized signal and the H-polarized signal according to the angle of polarization misalignment. Subsequently, in step S230, the DPDA system according to an embodiment of the present invention performs phase and gain control for the four signal paths.
[0032] Since the polarization angle can be controlled through vector modulation of two orthogonal polarization signals, the DPDA system according to an embodiment of the present invention can be implemented with two parallel vector modulators for V polarization and H polarization, respectively.
[0033] FIG. 3a shows polarization alignment through polarization angle control, FIG. 3b shows the operation and signal diagram when 0° ≤ polarization misalignment ≤ 45°, and FIG. 3c shows the operation and signal diagram when 45° < polarization misalignment ≤ 90°. Referring to FIG. 3a through 3c, the V polarization signal and the H polarization signal are composed of four signal paths that are directly coupled or cross-coupled, and each signal path has a phase invertible gain control block (300).
[0034] The circuit presented in the DPDA system according to an embodiment of the present invention operates in two modes. The first mode is when the polarization misalignment is 0° to 45°, and the second mode is when the polarization misalignment is 45° to 90°.
[0035] Accordingly, referring again to FIG. 2, in step S220, when the polarization misalignment is 0° to 45° (first mode), the DPDA system according to the embodiment of the present invention can operate the HH path and the VV path as the main paths, and the HV path and the VH path can operate as the leakage cancellation paths.
[0036] V represents the magnitude of the polarized signal and the angle of non-polarization alignment, respectively, A V and θ V Assuming that, the magnitude of the H polarized signal and the angle of non-polarization alignment are A, respectively. H and θ H Assume that. Then, the received V polarization signal A V’ and H polarized signal A H’ Each is expressed as follows.
[0037] [Mathematical Formula 1]
[0038]
[0039] [Mathematical Formula 2]
[0040]
[0041] θ V and θ H is 0° to 45°. In step S220, the DPDA system according to an embodiment of the present invention aligns the received V-polarized signal and the received H-polarized signal by converting their phases according to a polarization misalignment of 0° to 45°, and the aligned V-polarized signal A V’’ and aligned H polarized signal A H’’ Each is expressed as follows.
[0042] [Mathematical Formula 3]
[0043]
[0044] [Mathematical Formula 4]
[0045]
[0046] In [Equation 3] and [Equation 4], the XPL cancellation conditions for the V-polarized signal and the H-polarized signal are as follows.
[0047] [Mathematical Formula 5]
[0048]
[0049] [Mathematical Formula 6]
[0050]
[0051] In [Equation 5] and [Equation 6], the leakage cancellation path gain versus the main path gain for XPL cancellation is as follows.
[0052] [Mathematical Formula 7]
[0053]
[0054] [Mathematical Formula 8]
[0055]
[0056] Then, in step S230, the DPDA system according to an embodiment of the present invention substitutes [Equation 7] and [Equation 8] into [Equation 3] and [Equation 4] and outputs as follows.
[0057] [Mathematical Formula 9]
[0058]
[0059] [Mathematical Formula 10]
[0060]
[0061] [Equation 9] and [Equation 10] indicate that the DPDA system according to the embodiment of the present invention can not only remove the XP signal using the presented technique but also compensate for the reduced CP signal caused by the polarization alignment error.
[0062] In addition, in step S220, when the polarization misalignment is 45 to 90 degrees (second mode), the DPDA system according to the embodiment of the present invention can operate the HH path and the VV path as polarization cancellation paths and operate the HV path and the VH path as main paths.
[0063] Under these conditions, the XPL power is higher than the desired CP signal power. The received V-polarized signal and the received H-polarized signal are expressed as follows, respectively.
[0064] [Mathematical Formula 11]
[0065]
[0066] [Mathematical Formula 12]
[0067]
[0068] θ V and θ H is 45° to 90°. In step S220, the DPDA system according to an embodiment of the present invention can align the received V polarized signal and the received H polarized signal by converting their phases according to a polarization misalignment of 45° to 90°, and the leakage cancellation path gain relative to the main path gain of XPL cancellation is as follows.
[0069] [Mathematical Formula 13]
[0070]
[0071] [Mathematical Formula 14]
[0072]
[0073] Then, in step S230, the DPDA system according to an embodiment of the present invention substitutes [Equation 13] and [Equation 14] into [Equation 11] and [Equation 12] and outputs as follows.
[0074] [Mathematical Formula 15]
[0075]
[0076] [Mathematical Formula 16]
[0077]
[0078] [Equation 15] and [Equation 16] show that even if XPL is greater than the CP signal, the technique presented by the DPDA system according to the embodiment of the present invention can not only eliminate the XP signal but also compensate for the reduced CP signal caused by polarization misalignment.
[0079] The technique presented by the DPDA system according to the embodiment of the present invention as described above has three advantages. First, all polarization misalignments can be aligned. As described above, polarization misalignments can be aligned from 0° to 90°, and cases greater than 90° are simple phase inversion cases from 0° to 90°. Second, it is composed of a 4-path phase inversion gain control block, so it can be implemented simply and with low power. Third, the DPDA can compensate for the reduced CP signal, thereby avoiding an increase in transmitter output.
[0081] Figure 4 shows a graph of XPI for gain mismatch and phase mismatch according to an embodiment of the present invention.
[0082] In a DPDA system, a constant gain ratio must exist between the main path and the cancellation path for XPL elimination. However, in actual systems, gain mismatches may occur, preventing complete XPL elimination. Additionally, phase mismatches occurring in the IC and package can also hinder XPL elimination. Therefore, for simplification Assuming that the polarization misalignment is from 0° to 45°, the gain of the cancellation path relative to the major path including error is as follows.
[0083] [Mathematical Formula 17]
[0084]
[0085] [Mathematical Formula 18]
[0086]
[0087] Here, △G and represents the gain and phase mismatch between the main path and the cancellation path. By substituting [Equation 17] and [Equation 18] into [Equation 3] and [Equation 4] to obtain the XPI by dividing the amplitude of the co-polarization by the amplitude of the XP signal, it can be summarized as follows.
[0088] [Mathematical Formula 19]
[0089]
[0090] Here, A XP and A CP and represent the amplitudes of the XPL and the desired CP signal, respectively. If, in the worst case, θ R Since this is the case where it is 45°, in this case, △G and The XPI is as shown in Fig. 4. To obtain an XPI greater than 30 dB in the graph, gain and phase mismatch of less than 0.3 dB and less than 2° are required.
[0091] Consequently, phase-invariant gain control is essential for the implementation of a practical DPDA system, and phase correction is required to eliminate unwanted phase mismatches present in the IC and package for high XPI.
[0093] FIGS. 5a to 5c illustrate the results of an analysis of the impact caused by a discrepancy between the main path and the cancellation path according to an embodiment of the present invention.
[0094] To achieve high XPI not only at a single frequency but also across a wide bandwidth, gain and phase mismatch with respect to bandwidth must be minimized. However, as shown in [Equation 10], if the main path and the cancellation path are asymmetric, the gain and phase slope (or group delay) with respect to frequency differ between the two paths, making it difficult to maintain high XPI across a wide bandwidth.
[0095] Figures 5a through 5c show the results of an analysis of the impact caused by the mismatch between the main path and the cancellation path. For example, considering an XPL cancellation system where the main path and the cancellation path are asymmetric because the cancellation path includes more stages, the gain bandwidth of the cancellation path is narrower and the phase slope with respect to frequency is greater compared to the main path. Consequently, even if the XPL of the main path and the cancellation path of the center frequency are set to have the same amplitude and a phase difference of 180° outside the center frequency, they deviate from the optimal setting as shown in Figures 5a and 5b.
[0096] Figure 5c shows the XPI calculated for the following three cases based on [Equation 19]. The first is the case where there is only gain mismatch at the frequency as in Figure 5a, the second is the case where there is only phase mismatch at the frequency as in Figure 5b, and the third is the case where both exist. Ideally, infinite XPI should be achieved for all frequencies in the graph, but the bandwidth at which a specific XPI can be achieved is limited due to differences in gain and group delay.
[0097] Consequently, the technique presented by the DPDA system according to the embodiment of the present invention makes it easy to achieve high XPI in broadband because the main path and the removal path are symmetrical. Furthermore, in the implementation of the DPDA system according to the embodiment of the present invention, symmetry between all paths is very important for broadband XPL removal.
[0099] Figure 6 shows the calculated SNR for XPI according to an embodiment of the present invention. DP This is a graph of
[0100] Since the XP signal acts as an interferer in a DP MIMO system, the SNR, which is the XP signal DP The SNR of a DP MIMO system considering this can be expressed as follows.
[0101] [Mathematical Formula 20]
[0102]
[0103] Here, SNR CP represents the SNR of the CP signal assuming a single-input-single-output (SISO) system. Figure 6 shows the SNR for XPI. DP This represents the SNR as XPI increases. DP deteriorates and high SNR at low XPI DP To achieve a high SNR CP It shows that is necessary. 10 -3 It can be seen that the minimum SNR of the bit-error-rate (BER) is 9.8, 16.5, and 22.5 dB for QPSK, 16-QAM, and 64-QAM modulation, respectively.
[0104] Accordingly, the present invention provides an SNR of 20 dB with a margin of 3.5 dB in the case of 16-QAM modulation. CP Assuming, an SNR of less than 0.5dB DP We aim for an XPI of 30dB or more for resolution.
[0106] FIG. 7 is a block diagram of a dual polarization dynamic alignment (DPDA) system of an integrated phase array according to an embodiment of the present invention.
[0107] FIG. 7 shows a block diagram of a DP MIMO receiving phase array IC presented in the present invention. Accordingly, a DPDA system (700) according to an embodiment of the present invention includes a low noise amplifier (LNA) (711, 712), a phase shifter (PS) (721, 722), and a phase-compensated attenuator (731, 732).
[0108] The V-polarized signal and H-polarized signal input to each phase array channel of the receiving dual-polarized antenna (701) pass through a low-noise amplifier (711 or 712) and are split into two paths at the output of the low-noise amplifier (711, 712). Each path consists of a phase converter (721, 722) and a phase compensation attenuator (731, 732), where the phase converter (721, 722) not only controls the phase for beam steering but also corrects phase errors to achieve an XPI of 30 dB or more. The phase compensation attenuator (731, 732) performs gain control for DPDA operations. Finally, the phase and gain control signals are combined in a two-stage Wilkinson power combiner for DPDA (stage 1, 740) and beamforming (stage 2, 750).
[0109] Accordingly, the DPDA system (700) according to an embodiment of the present invention is a DP MIMO phase array with built-in DPDA technology, and can also be used as a single polarization beamformer composed of four elements having two beams.
[0110] More specifically, the low-noise amplifier (711 or 712) receives the V-polarized signal and the H-polarized signal input to each phase array channel of the receiving dual-polarized antenna. The low-noise amplifier (711 or 712) is composed of stages 1 through 4, and between stages 1 and 2 and between stages 3 and 4, direct current is reused through the center tap of the transformer, and cross-coupled capacitors may be used in all stages except stage 1.
[0111] Phase converters (721, 722) convert the phase into four signal paths that are directly coupled and cross-coupled between the V-polarized signal and the H-polarized signal according to the angle of polarization misalignment. Phase compensation attenuators (731, 732) perform phase and gain control for the four signal paths.
[0112] For example, when the polarization misalignment is between 0 and 45 degrees, the phase converter (721, 722) can operate the HH path and VV path as the main path and the HV path and VH path as the leakage cancellation path. At this time, the phase converter (721, 722) can align the V polarization signal and the H polarization signal by converting the phase according to the polarization misalignment of 0 to 45 degrees, and output the aligned V polarization signal and the aligned H polarization signal. Accordingly, the phase compensation attenuator (731, 732) can dynamically align the polarization by applying the leakage cancellation path gain versus the main path gain for XPL cancellation to the aligned V polarization signal and the aligned H polarization signal.
[0113] As another example, when the polarization misalignment is between 45 and 90 degrees, the phase converter (721, 722) can operate the HH path and the VV path as polarization cancellation paths and operate the HV path and the VH path as main paths. At this time, the phase converter (721, 722) can align the V polarization signal and the H polarization signal by converting their phases according to the polarization misalignment of 45 to 90 degrees, and output the aligned V polarization signal and the aligned H polarization signal. Accordingly, the phase compensation attenuator (731, 732) can dynamically align the polarization by applying the leakage cancellation path gain versus the main path gain for XPL cancellation to the received V polarization signal and the received H polarization signal.
[0115] FIG. 8 illustrates a schematic diagram of a low-noise amplifier according to an embodiment of the present invention.
[0116] The low noise amplifier (LNA) presented in the DPDA system according to an embodiment of the present invention may be composed of four stages. DC current is reused through the center tap (810) of the transformer between the first stage (LNA 1st stage) and the second stage (LNA 2nd stage), and between the third stage (LNA 3rd stage) and the fourth stage (LNA 4th stage). Additionally, to improve gain and reverse isolation, it is designed with a common source topology canceled out using cross-coupled capacitors (820) in all stages (LNA 2nd stage, LNA 3rd stage, LNA 4th stage) except for the first stage (LNA 1st stage). The first stage (LNA 1st stage) is a transformer-based g to achieve wide 50Ω matching and low noise figures. m It was designed with a common gate topology using boosting technology.
[0117] Accordingly, the LNA presented in the DPDA system according to an embodiment of the present invention can draw a current of 21mA under a supply voltage of 1.2V.
[0119] FIG. 9 illustrates a schematic diagram of a vector-sum phase converter according to an embodiment of the present invention, FIG. 10a and FIG. 10b illustrate RMS gain and phase error calculated as a function of I / Q amplitude and phase mismatch, FIG. 11 illustrates simulated phase and gain mismatch of an orthogonal coupler in VSPS, and FIG. 12a and FIG. 12b illustrate a schematic diagram of a variable gain cell according to an embodiment of the present invention.
[0120] Referring to FIG. 9, in a DPDA system according to an embodiment of the present invention, the phase shifter (PS) is designed as a vector-sum phase shifter (VSPS) for high phase resolution and low loss. An output quadrature coupler (910) as shown in FIG. 9 performs phase conversion by combining two signals whose magnitudes are controlled by a variable gain cell. In this structure, amplitude and phase mismatch of the quadrature coupler generate phase and gain errors in the VSPS.
[0121] Figures 10a and 10b show the calculated RMS gain and phase error as a function of I / Q amplitude and phase mismatch, and Figure 11 shows the simulated phase and gain mismatch of the orthogonal coupler in this VSPS. The designed orthogonal coupler achieved an amplitude mismatch of less than 0.5 dB and a phase mismatch of less than 0.32° at 57 GHz to 66 GHz. Accordingly, it is expected that using the orthogonal coupler designed in Figures 10a and 10b and assuming ideal vector modulation will achieve an RMS gain error of less than 0.3 dB and an RMS phase error of less than 1.4°.
[0122] FIGS. 12a and 12b show schematic diagrams of a variable gain cell presented in a DPDA system according to an embodiment of the present invention. More specifically, FIG. 12a shows the entire variable gain cell, and FIG. 12b shows a 7-bit current DAC.
[0123] Referring to FIG. 12a, the proposed variable gain cell represents a structure (1210) in which two differential pairs are cross-coupled, and gain is controlled by using a complementary 7-bit current DAC to complementarily control the current flowing through each differential pair as shown in FIG. 12b. Additionally, the proposed variable gain cell provides 38.8 dB gain control with a phase change of less than 6.4° in simulation. Accordingly, the DPDA system according to an embodiment of the present invention can achieve a phase resolution of 2° by cascading with designed orthogonal couplers.
[0125] FIG. 13 illustrates a schematic diagram of a presented three-stage phase-compensated RTA according to an embodiment of the present invention, and FIG. 14 illustrates S of the RTA for various transistor sizes. 21 FIGS. 15a and FIGS. 15b are illustrated to explain a phase compensation technique in which a series capacitor is inserted into an nMOS, and FIG. 16 is a graph of the simulated phase response of a presented 3-stage phase compensation RTA according to an embodiment of the present invention.
[0126] The present invention uses a phase-compensated attenuator as a gain control block for a DPDA, taking into account power consumption and wideband design. The present invention selected a reflection-type attenuator (RTA) as the design target due to continuous voltage control and wide 50Ω matching. While classical RTAs use gain control that includes phase inversion, the RTA presented in the present invention uses only the half-phase region.
[0127] The RTA presented in the present invention differs from existing technology in two respects. First, the gate bias is controlled continuously. Second, a multi-stage phase compensation technique is proposed and adopted. Accordingly, the phase-compensated RTA presented in the present invention is configured as shown in FIG. 13. In the second stage (1310), a capacitor (C) for phase compensationCOM ) is inserted.
[0128] Figure 14 shows the S of the RTA for various transistor sizes. 21 It represents. Above a certain magnitude, the relationship between the coupler's characteristic impedance and the load reverses, causing phase inversion. Therefore, above a certain magnitude, S 21 It exhibits this minimum value and then rises again. However, in the phase inversion region, insertion loss is very high and parasitic capacitance is large, which limits the gain control range. On the other hand, when using the largest transistor (i.e., 6μm) among transistor sizes where phase inversion does not occur, the RTA has a wide gain control range with low insertion loss. Fig. 15a shows a series capacitor C for phase compensation. COM This represents the equivalent circuit of the inserted load. C COM The phase response for a load without and a load with can be expressed as follows.
[0129] [Mathematical Formula 21]
[0130]
[0131] [Mathematical Formula 22]
[0132]
[0133] R A is V GS Decreases according to and C A V for a small transistor GS Since it is constant with respect to ωC in [Equation 12] and [Equation 22] A R A becomes decreased. Meanwhile, 1 / (ωC of [Equation 22] COM R A ) increases. Accordingly, [Equation 22] can generate a trend opposite to [Equation 21].
[0134] Fig. 15b is C COM V for various values of GSThis represents the RTA phase response. In this graph, the sign of the slope is C COM It is the opposite depending on the presence or absence of, and the slope is C COM It shows that it can be controlled according to the value of. Due to this, the RTA is connected in series to C COM It can be seen that multi-stage phase compensation is possible by connecting or not connecting.
[0135] Figure 16 shows the simulated phase response of the presented 3-stage phase-compensated RTA. When only the first and third stages are controlled (V CA1 When controlling only), V GS The phase response tends to increase depending on... When controlling only the second stage (V CA2 When controlling only), V GS The phase response tends to decrease accordingly. When controlling all stages simultaneously, the phase change is reduced to a maximum of 6° with 40dB gain control.
[0136] This indicates that the wide gain control range and low phase change of the phase-compensated attenuator presented in the DPDA system according to the embodiment of the present invention are highly suitable as a gain control block for DPDA.
[0138] Figure 17 is a table showing the results of comparing the present invention with existing technology.
[0139] FIG. 17 shows a comparison with a reported 60 GHz band receiving phase array, dynamic polarization control system, and millimeter wave DP MIMO system. Here, (1) including IF, (2) at 28 GHz, (3) beamformer, (4) relative error, (5) RFFE IC, (6) baseband IC, (7) TRx, (8) calculated at data transmission rate, (9) only in the case of 30°, (10) showing a 22.5° step.
[0140] Compared to reported 60 GHz band receiving phase arrays, it can be seen that this work exhibits the most precise phase resolution and the lowest RMS gain and phase error. Compared to previous studies (
[13] -
[15] ) using dynamic polarization control techniques, this work enables simultaneous dynamic linear polarization control for V and H signals, as well as control for a single polarization signal.
[0141] Compared to previous research ([9]), this work has a narrower XIP bandwidth but consumes less power and occupies a smaller area. Also, compared to other previous research (
[10] ), this work shows lower XPI but a wider XPI bandwidth. Furthermore, compared to other previous studies ([9],
[10] ,
[25] ,
[26] ), this work is the only one that improves XPI with a polarization mismatch resolution of 22.5° under conditions where the transmitting and receiving antennas are not aligned from 0° to 90°.
[0142] Therefore, the present invention can improve XPI even under conditions where the transmitting and receiving antennas are not aligned up to 90° in the millimeter wave band (misalignment conditions).
[0144] The present invention presents DPDA technology and an application to phase arrays in the 60 GHz unlicensed frequency band using the same. The DPDA technique controls each DP signal independently to correct polarization mismatch between transmitting and receiving antennas and improves XPI. Therefore, the present invention can correct polarization mismatch even if it occurs up to 90° between new antennas.
[0145] To verify the DPDA technology, a receiving phase array IC with a 2V+2H configuration was fabricated using a 65nm CMOS process, and an AiP prototype was fabricated using a 2-element DP antenna. According to experimental results using this, it was confirmed that applying the DPDA technology according to an embodiment of the present invention improves XPI and recovers CP gain even when the transmit and receive antenna misalignment occurs between 0° and 90°. As this is the only technology that improves XPI when the polarization misalignment between the transmit and receive antennas for a dual-polarized signal is up to 90°, the present invention is expected to be applicable to wireless systems for mobile AR / VR where the polarization alignment of the transmit and receive antennas changes randomly.
[0147] The system or device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and component described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.
[0149] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.
[0151] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include hard disks, magneto-optical media, solid-state drives (SSDs), and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.
[0153] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.
[0155] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.
Claims
Claim 1 A dual-polarization dynamic alignment system of an integrated phase array comprising: a low-noise amplifier receiving V-polarized signals and H-polarized signals input to each phase array channel of a receiving dual-polarization antenna; a phase converter converting the phase into four signal paths directly coupled and cross-coupled between the V-polarized signals and the H-polarized signals according to the angle of polarization misalignment; and a phase compensation attenuator performing phase and gain control for the four signal paths. Claim 2 A dual-polarization dynamic alignment system of an integrated phase array according to claim 1, wherein either of the V-polarized signal and the H-polarized signal input to each phase array channel is input to one of the low-noise amplifiers, split into two paths at the output of the low-noise amplifier, and passes through two of the phase converters and two of the phase compensation attenuators. Claim 3 A dual-polarization dynamic alignment system of an integrated phase array according to claim 1, wherein the low-noise amplifier is composed of 1 to 4 stages, reuses direct current through the center tap of a transformer between stages 1 and 2 and between stages 3 and 4, and uses cross-coupled capacitors in all stages except stage 1. Claim 4 A dual polarization dynamic alignment system of an integrated phase array, wherein the phase converter operates the HH path and VV path as the main path and the HV path and VH path as the leakage cancellation path when the polarization misalignment is 0 to 45 degrees. Claim 5 In claim 4, the phase converter aligns the V-polarized signal and the H-polarized signal by converting their phases according to a polarization misalignment of 0 to 45 degrees, and outputs the aligned V-polarized signal and the aligned H-polarized signal, a dual-polarization dynamic alignment system of an integrated phase array. Claim 6 A dual polarization dynamic alignment system of an integrated phase array, wherein, in claim 5, the phase compensation attenuator dynamically aligns polarizations by applying the leakage cancellation path gain versus the main path gain for XPL cancellation to the aligned V polarization signal and the aligned H polarization signal. Claim 7 A dual polarization dynamic alignment system of an integrated phase array, wherein the phase converter operates the HH path and the VV path as polarization cancellation paths and operates the HV path and the VH path as main paths when the polarization misalignment is 45 to 90 degrees. Claim 8 In claim 7, the phase converter aligns the V-polarized signal and the H-polarized signal by changing their phases according to a polarization misalignment of 45 to 90 degrees, and outputs the aligned V-polarized signal and the aligned H-polarized signal, a dual-polarization dynamic alignment system of an integrated phase array. Claim 9 A dual polarization dynamic alignment system of an integrated phase array, wherein, in claim 8, the phase compensation attenuator dynamically aligns polarizations by applying the leakage cancellation path gain versus the main path gain for XPL cancellation to the received V-polarized signal and the received H-polarized signal. Claim 10 A dual-polarization dynamic alignment method of an integrated phase array performed by a computer comprising at least one process, comprising: receiving a V-polarization signal and an H-polarization signal input to each phase array channel of a receiving dual-polarization antenna; converting the phase into four signal paths directly coupled and cross-coupled between the V-polarization signal and the H-polarization signal according to the angle of polarization misalignment; and performing phase and gain control for the four signal paths. Claim 11 A dual-polarization dynamic alignment method of an integrated phase array according to claim 10, wherein either of the V-polarized signal and the H-polarized signal input to each of the phase array channels is input to one of the low-noise amplifiers and split into two paths at the output of the low-noise amplifier, passing through two of the phase converters and two of the phase compensation attenuators. Claim 12 In claim 10, the step of converting the phase is a dual polarization dynamic alignment method of an integrated phase array, wherein when the polarization misalignment is 0 to 45 degrees, the HH path and VV path are operated as the main paths, and the HV path and VH path are operated as the leakage cancellation paths. Claim 13 In claim 10, the step of converting the phase operates the HH path and VV path as polarization cancellation paths and operates the HV path and VH path as main paths when the polarization misalignment is 45 to 90 degrees, a dual polarization dynamic alignment method of an integrated phase array.