Capacitor structure and method of forming the same, and semiconductor device including the capacitor structure
Patent Information
- Application Number
- KR1020250023594
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2026-09-01
Smart Images
Figure PAT00001_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a capacitor structure and a method for forming the same, and a semiconductor device including the capacitor structure. Background Technology
[0002] A capacitor structure included in a DRAM device may comprise a capacitor including a sequentially stacked lower electrode, a dielectric film, and an upper electrode, and support films that are vertically spaced apart from each other and each contact the surface of the lower electrode. The problem to be solved
[0003] One objective of the present invention is to provide a capacitor structure having improved electrical characteristics.
[0004] Another objective of the present invention is to provide a semiconductor device comprising a capacitor structure having improved electrical characteristics.
[0005] Another objective of the present invention is to provide a method for forming a capacitor structure having improved electrical characteristics. means of solving the problem
[0006] A capacitor structure according to exemplary embodiments for achieving the above-mentioned objective comprises a first lower electrode disposed on a substrate and a lower electrode structure having a second lower electrode disposed on the sidewall of the first lower electrode and comprising an alloy of a first metal and a second metal, a dielectric pattern disposed on the surface of the lower electrode structure, and an upper electrode disposed on the surface of the dielectric pattern, wherein the second lower electrode has a thickness that varies along a vertical direction perpendicular to the upper surface of the substrate, and the weight ratio of the first metal and the second metal within the second lower electrode may be constant along the vertical direction.
[0007] A capacitor structure according to exemplary embodiments for achieving the above-mentioned objective comprises a lower electrode structure disposed on a substrate and having a first lower electrode extending in a vertical direction perpendicular to the upper surface of the substrate and a second lower electrode disposed on a side wall of the first lower electrode and comprising an alloy of niobium (Nb) and titanium (Ti), a dielectric pattern disposed on a side wall of the lower electrode structure and an upper electrode disposed on a side wall of the dielectric pattern, wherein the weight ratio of the first metal and the second metal within the second lower electrode may be constant along the vertical direction.
[0008] A semiconductor device according to exemplary embodiments for achieving other objectives described above comprises an active pattern disposed on a substrate, a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded on the upper portion of the active pattern, a bit line structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction and disposed on the central portion of the active pattern, a contact plug structure disposed on each end of the active pattern, and a capacitor structure disposed on the contact plug structure, wherein the capacitor structure comprises a lower electrode structure including a first lower electrode extending in a vertical direction perpendicular to the upper surface of the substrate and a second lower electrode (62) disposed on the side wall of the first lower electrode, having a thickness that varies along the vertical direction and comprising an alloy of a first metal and a second metal, supporting films disposed on the side wall of the lower electrode structure and spaced apart from each other in the vertical direction, a dielectric pattern disposed on the side wall of the portion of the lower electrode structure disposed between the supporting films, and an upper electrode disposed on the side wall of the dielectric pattern, wherein the first metal and the second metal within the second lower electrode The weight ratio can be constant along the above vertical direction.
[0009] A method for forming a capacitor structure according to exemplary embodiments for achieving another objective described above comprises alternately and repeatedly forming a mold film and a support film on a substrate along a vertical direction perpendicular to the upper surface of the substrate, forming a lower electrode structure that penetrates the mold film and the support film and has a first lower electrode and a second lower electrode having a single film structure covering the sidewall of the first lower electrode and comprising an alloy of a first metal and a second metal, removing the mold film through an etching process to form a first opening that exposes a portion of the second lower electrode, and sequentially forming a dielectric pattern and an upper electrode within the first opening, wherein during the etching process, the portion of the second lower electrode exposed by the first opening is also removed, so that the second lower electrode may have a thickness that varies along the vertical direction.
[0010] In exemplary embodiments, the etching process may include a wet etching process.
[0011] In exemplary embodiments, the etching process may include performing a dry etching process to partially remove the mold film and the support film to form a second opening, and performing a wet etching process to remove the mold film exposed by the second opening to form the first opening.
[0012] In exemplary embodiments, the support film comprises first to third support films arranged sequentially along the vertical direction, and during the etching process, a first recess having a first depth in the horizontal direction is formed in the second lower electrode portion formed between the substrate and the first support film, and a second recess having a second depth greater than the first depth in the horizontal direction may be formed in the second lower electrode portion formed between the second support film and the third support film.
[0013] In exemplary embodiments, the support film comprises first to third support films sequentially arranged along the vertical direction, and the thickness in the horizontal direction of the second lower electrode portion formed between the substrate and the first support film may be greater than the thickness in the horizontal direction of the second lower electrode portion formed between the second support film and the third support film.
[0014] In exemplary embodiments, the support film comprises first to third support films sequentially arranged along the vertical direction, and may include performing a first dry etching process to partially remove the third support film to partially expose the mold film, performing a first wet etching process to remove the mold film formed on the second support film, performing a second dry etching process to partially remove the second support film to partially expose the mold film, performing a second wet etching process to remove the mold film formed on the first support film, performing a third dry etching process to partially remove the first support film to partially expose the mold film, and performing a third wet etching process to remove the mold film formed on the substrate.
[0015] In exemplary embodiments, when each of the first to third wet etching processes is performed, the side of the second lower electrode is removed together, and the thickness in the horizontal direction of the second lower electrode portion formed between the first to third supporting films adjacent to each other in the vertical direction may gradually decrease from bottom to top along the vertical direction.
[0016] In exemplary embodiments, each of the first and second metals may include at least one of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), zirconium (Zr), hafnium (Hf), and niobium (Nb).
[0017] In exemplary embodiments, the first metal comprises titanium, the second metal comprises niobium, and the second lower electrode may comprise a nitride of the alloy.
[0018] In exemplary embodiments, the first lower electrode may comprise titanium silicon nitride (TiSiN). Effects of the invention
[0019] Although the lower electrode structure included in the capacitor structure according to exemplary embodiments has a thickness that varies along the vertical direction, a uniform capacitance can be secured along the vertical direction. Brief explanation of the drawing
[0020] FIGS. 1 and FIGS. 2 are cross-sectional views illustrating capacitor structures according to exemplary embodiments. FIGS. 3 to 9 are cross-sectional views illustrating a method for forming a capacitor structure according to exemplary embodiments. FIGS. 10 and FIGS. 11 are cross-sectional views for illustrating a semiconductor device according to a comparative example. FIGS. 12 and FIGS. 13 are a plan view and a cross-sectional view for illustrating a semiconductor device according to exemplary embodiments. FIGS. 14 to 29 are plan and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention
[0021] Hereinafter, a capacitor structure and a method for forming the same, a semiconductor device including the capacitor structure, and a method for manufacturing the same, according to preferred embodiments of the present invention, will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and / or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and / or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process.
[0022] [Example]
[0023] FIGS. 1 and 2 are cross-sectional views illustrating capacitor structures according to exemplary embodiments. FIG. 2 is an enlarged cross-sectional view of region X of FIG. 1.
[0024] Referring to FIGS. 1 and 2, the capacitor structure may include a capacitor (110), a support film (50), and an upper electrode plate (120) formed on a substrate (10), and the capacitor (110) may include a lower electrode structure (70), a dielectric pattern (95), and an upper electrode (105).
[0025] The substrate (10) may include, for example, semiconductor materials such as silicon, germanium, silicon-germanium, etc., or group III-V compounds such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (10) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
[0026] An interlayer insulating film (20) accommodating a first conductive pattern (25) may be formed on a substrate (10). At this time, the first conductive pattern (25) may include, for example, a contact plug, a landing pad, etc., and may be formed in multiple numbers within the interlayer insulating film (20) so as to be spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate (10). The first conductive pattern (25) may include, for example, a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities. The interlayer insulating film (20) may include, for example, an oxide such as silicon oxide or a low dielectric material.
[0027] A first etch stop layer (30) may be formed on the interlayer insulating film (20). The first etch stop layer (30) may include, for example, an insulating nitride such as silicon nitride (SiN), boron nitride (SiBN), silicon carbonitride (SiCN), etc.
[0028] The support film (50) may be formed on the first etching stop film (30) and, for example, may have a flat plate shape having upper and lower surfaces in the horizontal direction. In exemplary embodiments, the support film (50) may be formed in multiple pieces spaced apart from each other along a vertical direction perpendicular to the upper surface of the substrate (10) on the first etching stop film (30).
[0029] The support film (50) may include insulating nitrides such as silicon nitride (SiN), boron nitride (SiBN), silicon carbonitride (SiCN), etc.
[0030] The dielectric pattern (95) can be in contact with the side walls of each lower electrode structure (70) between the first etching stop layer (30) and the bottom layer support layer (50), and between the support layers (50), and can also be in contact with the upper surface of the first etching stop layer (30), the lower surface of the top layer support layer (50), and the upper and lower surfaces of each of the remaining support layers (50) excluding these.
[0031] The dielectric pattern (95) may include, for example, a metal with tetravalent outermost electrons, an oxide such as hafnium or zirconium, or a high-K dielectric material.
[0032] The upper electrode (105) can have its surface covered by a dielectric pattern (95) and can be formed between the first etching stop layer (30) and the lowest layer support layer (50), and between the support layers (50).
[0033] The upper electrode (105) may include a metal or metal nitride such as titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), zirconium (Zr), hafnium (Hf), niobium (Nb), etc.
[0034] In the following, the dielectric pattern (95) portion disposed between the first etching blocking film (30) and the lowest layer support film (50) is referred to as the first portion, the dielectric pattern (95) portion disposed between the lowest layer support film (50) and the support film (50) formed in the second layer from the top is referred to as the second portion, and the dielectric pattern (95) portion disposed between the support film (50) formed in the second layer from the top and the uppermost layer support film (50) is referred to as the third portion.
[0035] In exemplary embodiments, the first to third portions included in the genetic pattern (95) may have the same or similar crystal sizes, for example, may have a first crystal size.
[0036] The lower electrode structure (70) may have a pillar shape extending in the vertical direction through the first etching stop layer (30) and the support layers (50), and may contact the upper surface of each first conductive pattern (25). However, the concept of the present invention is not limited thereto, and the lower electrode structure (70) may have a cup shape or a cylinder shape with a hollow center.
[0037] In exemplary embodiments, the lower electrode structure (70) may include a second lower electrode (65) and a first lower electrode (62) covering the side wall and bottom surface of the second lower electrode (65).
[0038] The first lower electrode (62) may have a cup shape, for example, and may include a horizontal portion that contacts the upper surface of each first conductive pattern (25), and a vertical portion that extends in the vertical direction and is formed at the edge portion in the horizontal direction of the first lower electrode (62) and contacts it. The inner wall of the vertical portion of the first lower electrode (62) may contact the side wall of the second lower electrode (65), and the outer wall may contact the side walls of the support film (50) and the dielectric pattern (95).
[0039] The thickness of the vertical portion of the first lower electrode (62) in the horizontal direction may vary along the vertical direction.
[0040] In one embodiment, a first portion of the first lower electrode (62) that overlaps in the horizontal direction with each support film (50) or the first etching stop film (30) may have a first thickness in the horizontal direction, a second portion of the first lower electrode (62) that overlaps in the horizontal direction with the first portion of the dielectric pattern (95) may have a second thickness that is thinner than the first thickness in the horizontal direction, a third portion of the first lower electrode (62) that overlaps in the horizontal direction with the second portion of the dielectric pattern (95) may have a third thickness that is thinner than the second thickness in the horizontal direction, and a fourth portion of the first lower electrode (62) that overlaps in the horizontal direction with the third portion of the dielectric pattern (95) may have a fourth thickness that is thinner than the third thickness in the horizontal direction.
[0041] In another embodiment, the thickness of each of the second to fourth portions of the first lower electrode (62) in the horizontal direction may gradually decrease from bottom to top along the vertical direction.
[0042] In one embodiment, the inner wall of the vertical portion of the first lower electrode (62) may extend in a straight line along the vertical direction. Accordingly, the outer wall of the vertical portion of the first lower electrode (62) has the first dielectric pattern (95).
[0043] First to third recesses corresponding to each of the third parts may be formed. At this time, the first recess may have a first depth in the horizontal direction, the second recess may have a second depth in the horizontal direction that is deeper than the first depth, and the third recess may have a third depth in the horizontal direction that is deeper than the second depth.
[0044] The first lower electrode (62) may include an alloy of the first metal and the second metal, or a nitride of the alloy. Each of the first and second metals may include, for example, titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), zirconium (Zr), hafnium (Hf), niobium (Nb), etc.
[0045] In exemplary embodiments, although the thickness of the vertical portion of the first lower electrode (62) in the horizontal direction varies along the vertical direction, the ratio, e.g., weight ratio, between the first and second metals included in the first lower electrode (62) may be constant along the vertical direction.
[0046] The second lower electrode (65) is formed on the first lower electrode (62) and may extend in the vertical direction and have a constant width in the horizontal direction. In exemplary embodiments, the second lower electrode (65) may include a metal silicon nitride having a higher stiffness than the first lower electrode (62), such as titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), etc.
[0047] In exemplary embodiments, the horizontal thickness of the lower electrode structure (70) may be approximately 200 Å or more, and the horizontal thickness of the vertical portion of the first lower electrode (62) may be approximately 1 Å to 100 Å.
[0048] If the lower electrode structure (70) has a cup shape, the second lower electrode (65) may also have a cup shape, and a charging pattern including, for example, a semiconductor material such as amorphous silicon or an insulating material may be further formed in the internal space defined by the second lower electrode (65).
[0049] The upper electrode plate (120) can be formed on the lower electrode structure (70) and the uppermost support layer (50), and may include, for example, silicon-germanium doped with impurities.
[0050] The lower electrode structure (70) included in the capacitor structure according to exemplary embodiments may include a second lower electrode (65) and a first lower electrode (62) formed on the side wall and bottom surface thereof, and the thickness of the first lower electrode (62) in the horizontal direction may vary along the vertical direction rather than being constant.
[0051] However, since the first lower electrode (62) has a single-film structure containing the same conductive material, for example, in a composite film structure containing first and second films containing different conductive materials, the lower electrode structure (70) including the first lower electrode (62) can have a uniform capacitance along the vertical direction, compared to the case where the first film has a constant thickness and the second film has a variable thickness. This will be explained in more detail with reference to FIGS. 3 to 11.
[0052] Meanwhile, the second lower electrode (65) may include a material having relatively higher rigidity compared to the first lower electrode (62). Accordingly, even if the proportion of the first lower electrode (62) within the lower electrode structure (70) is partially reduced, the bending rigidity of the lower electrode structure (70) can be improved by increasing the proportion of the second lower electrode (65), which has relatively higher rigidity.
[0053] FIGS. 3 to 9 are cross-sectional views illustrating a method for forming a capacitor structure according to exemplary embodiments.
[0054] Referring to FIG. 3, an interlayer insulating film (20) accommodating a first conductive pattern (25) is formed on a substrate (10), and a first etch stop film (30) is formed on the first conductive pattern (25) and the interlayer insulating film (20). Then, a mold film (40) and a support film (50) can be alternately and repeatedly stacked on the first etch stop film (30).
[0055] The first challenge pattern (25) can be formed in multiple numbers spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate (10) on the substrate (10).
[0056] The mold film (40) may include, for example, an oxide such as silicon oxide or a low dielectric material.
[0057] Referring to FIG. 4, a first opening (55) can be formed that penetrates the support film (50), the mold film (40), and the first etching stop film (30) to expose the upper surface of each first conductive pattern (25).
[0058] In exemplary embodiments, the first opening (55) can be formed by forming an etching mask on the top layer support film (50) and then using the dry etching process.
[0059] Referring to FIG. 5, a first lower electrode film (60) can be formed on the upper surface of the first conductive pattern (25) exposed by the first opening (55), the side wall of the first opening (55), and the upper surface of the top layer support film (50).
[0060] In exemplary embodiments, the first lower electrode film (60) may be formed through a deposition process using, for example, source gases of the first metal and the second metal, and / or a nitrogen source gas. Accordingly, the first lower electrode film (60) may comprise an alloy of the first metal and the second metal or a nitride thereof.
[0061] In exemplary embodiments, the deposition process may include an atomic layer deposition (ALD) process, and accordingly, the first lower electrode film (60) may be formed conformally.
[0062] Subsequently, a second lower electrode film (63) can be formed on the first lower electrode film (60) to fill the remainder of the first opening (55). In exemplary embodiments, the second lower electrode film (63) may comprise a metallic silicon nitride, such as titanium silicon nitride.
[0063] Referring to FIG. 6, the first and second lower electrode films (60, 63) can be flattened until the upper surface of the uppermost support film (50) is exposed, thereby forming the first and second lower electrodes (62, 65) respectively, and together they can form a lower electrode structure (70).
[0064] The above planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.
[0065] Referring to FIGS. 7 and 8, for example, by performing a wet etching process to remove the mold film (40), a third opening (80) can be formed that exposes the sidewall of the first lower electrode (62), the upper surface of the first etching stop film (30), and the surface of each support film (50).
[0066] During the above wet etching process, the side of the first lower electrode (62) exposed by the third opening (80) can also be partially removed.
[0067] In exemplary embodiments, the third opening (80) can be formed by partially removing the support film (50) and the mold film (40) through a dry etching process to form a second opening that exposes the upper surface of the first etching stop film (30), and then performing the wet etching process through the second opening to further remove the mold film (40).
[0068] At this time, since the etching liquid used in the wet etching process is injected from the top of the second opening, the time during which the side wall of the first lower electrode (62) is exposed to the etching liquid can be shortened as it goes from top to bottom along the vertical direction, and accordingly, the amount of etching on the side of the first lower electrode (62) can be gradually reduced as it goes from top to bottom.
[0069] In one embodiment, the amount of etching on the side of the first lower electrode (62) portion disposed between the uppermost layer support film (50) and the support film (50) formed in the second layer from the top may be greater than the amount of etching on the side of the first lower electrode (62) portion disposed between the support film (50) formed in the second layer from the top and the lowest layer support film (50), and the amount of etching on the side of the first lower electrode (62) portion disposed between the support film (50) formed in the second layer from the top and the lowest layer support film (50) may also be greater than the amount of etching on the first lower electrode (62) portion disposed between the lowest layer support film (50) and the first etching stop film (30).
[0070] In another embodiment, the third opening (80) may be formed by partially removing the uppermost support film (50) through a first dry etching process to expose a portion of the mold film (40), then removing the portion of the mold film (40) formed on the support film (50) formed on the second layer from the top through a first wet etching process, then partially removing the support film (50) formed on the second layer from the top to expose a portion of the mold film (40) through a second dry etching process, then removing the portion of the mold film (40) formed on the lowest layer support film (50) through a second wet etching process, then partially removing the lowest layer support film (50) to expose a portion of the mold film (40) through a third dry etching process, and then removing the portion of the mold film (40) formed on the first etching stop film (30) through a third wet etching process.
[0071] At this time, the time during which the sidewall of the first lower electrode (62) is exposed to the etching solution may become shorter as it goes from top to bottom along the vertical direction, and accordingly, the amount of etching on the sides of each first lower electrode (62) portion disposed between adjacent support films (50) in the vertical direction, and the amount of etching on the sides of the first lower electrode (62) portion disposed between the lowest layer support film (50) and the first etching stop film (30) may gradually decrease as it goes from top to bottom.
[0072] Referring to FIG. 9, after forming a dielectric film (90) on the sidewalls of each lower electrode structure (70) exposed by the third opening (80), the upper surface of the first etching stop film (30), and the surface of each support film (50), an upper electrode film (100) can be formed on the dielectric film (90) to fill the remaining portion of the third opening (80).
[0073] The dielectric film (90) may include, for example, hafnium oxide, zirconium oxide, or a compound thereof.
[0074] At this time, the dielectric film (90) and the upper electrode film (100) can also be laminated on the upper surface of the lower electrode structure (70) and the upper surface of the uppermost support film (50).
[0075] Referring again to FIGS. 1 and 2, the dielectric film (90) and upper electrode film (100) portions stacked on the upper surface of the lower electrode structure (70) and the upper surface of the uppermost support film (50) can be removed.
[0076] Accordingly, within the third opening (80), the dielectric film (90) and the upper electrode film (100) may remain as the dielectric pattern (95) and the upper electrode (105), respectively.
[0077] The lower electrode structure (70), dielectric pattern (95), and upper electrode (105) can together form a capacitor (110).
[0078] Afterwards, an upper electrode plate (120) may be additionally formed on the capacitor (110).
[0079] As described above, by performing a wet etching process to remove the mold film (40), a third opening (80) can be formed that exposes the side wall of the first lower electrode (62), the upper surface of the first etching stop film (30), and the surface of each support film (50). During the wet etching process, the side of the first lower electrode (62) having a single film structure is partially removed together, so that the thickness of the side of the first lower electrode (62) exposed by the third opening (80) can be partially reduced.
[0080] If the first lower electrode (62) has a composite film structure composed of first and second films, each containing different first and second conductive materials, instead of a single film structure, then during the wet etching process to form the third opening (80), only the second film formed on the outer edge is partially removed while the first film is not removed, so the ratio of the first and second conductive materials may differ between the portion of the first lower electrode (62) where the second film is removed relatively more and the portion of the first lower electrode (62) where the second film is removed relatively less. Accordingly, the lower electrode structure (70) including the first lower electrode (62) may have a fluctuating capacitance instead of having a uniform capacitance along the vertical direction.
[0081] However, in exemplary embodiments, since the first lower electrode (62) has a single film structure containing the same conductive material, even if the first lower electrode (62) is formed to have a thickness that varies along the vertical direction by performing the wet etching process to form the third opening (80) so that the side of the first lower electrode (62) is partially removed, the ratio between the conductive materials contained in each part may not differ. Accordingly, the lower electrode structure (70) including the first lower electrode (62) can secure a uniform capacitance along the vertical direction.
[0082] FIGS. 10 and FIGS. 11 are cross-sectional views for explaining a capacitor structure according to a comparative example. FIG. 11 is an enlarged cross-sectional view of the Y region of FIG. 10. Except for the lower electrode structure (70), the capacitor structure may be substantially identical or similar to the structure described with reference to FIGS. 1 and FIG. 2, and accordingly, a detailed description thereof is omitted.
[0083] Referring to FIGS. 10 and 11, the lower electrode structure (70) may include a second lower electrode (65), a third lower electrode (64) covering the lower surface and side wall of the second lower electrode (65), and a fourth lower electrode (61) covering the surface of the third lower electrode (64).
[0084] The third lower electrode (64) can conformally cover the lower surface and side wall of the second lower electrode (65) and may include, for example, a nitride of a third metal such as titanium.
[0085] The fourth lower electrode (61) may include a horizontal portion in contact with the upper surface of the first conductive pattern (25), and a vertical portion formed on and in contact with the edge portion in the horizontal direction of the horizontal portion, and extending in the vertical direction. Similar to the first lower electrode (62), the thickness of the vertical portion in the horizontal direction of the fourth lower electrode (61) may vary along the vertical direction. The fourth lower electrode (61) may include a nitride of a fourth metal, such as niobium, for example.
[0086] As the thickness of the fourth lower electrode (61) varies along the vertical direction, the ratio of the third and fourth metals contained in the third and fourth lower electrodes (64, 61), respectively, formed between the second lower electrode (65) and the dielectric pattern (95), may vary along the vertical direction. That is, in the part where the thickness of the fourth lower electrode (61) is relatively thin, the ratio of the fourth metal contained in the fourth lower electrode (61) may be relatively low, and in the part where the thickness of the fourth lower electrode (61) is relatively thick, the ratio of the fourth metal may be relatively high.
[0087] Accordingly, the capacitance of the lower electrode structure (70) may not be uniform and may vary along the vertical direction.
[0088] FIG. 12 is a plan view illustrating a semiconductor device according to exemplary embodiments, and FIG. 13 is a cross-sectional view taken along line A-A' of FIG. 12.
[0089] The above semiconductor device is a DRAM device in which the capacitor structure described with reference to FIGS. 1 and 2 is applied. A redundant description of the capacitor structure is omitted.
[0090] In the following detailed description of the invention, among the horizontal directions parallel to the upper surface of the substrate (300), two directions that are orthogonal to each other are defined as the first and second directions (D1, D2), respectively, and a direction parallel to the upper surface of the substrate (300) and forming an acute angle with each of the first and second directions (D1, D2) is defined as the third direction (D3). Meanwhile, a direction perpendicular to the upper surface of the substrate (300) is referred to as a vertical direction.
[0091] The semiconductor device may include an active pattern (305) formed on a substrate (300), a gate structure (360), a bit line structure (595), a contact plug structure, and the capacitor structure.
[0092] Additionally, the semiconductor device may further include a device isolation pattern (310), a spacer structure (665), a fourth spacer (690), a second capping pattern (685), first and second insulation pattern structures (435, 790), fourth and fifth insulation patterns (610, 620), and a metal silicide pattern (700).
[0093] The active pattern (305) may be formed in multiple numbers such that each extends in a third direction (D3) and is spaced apart from one another along the first and second directions (D1, D2). The sidewalls of the active pattern (305) may be covered by the device isolation pattern (310). The active pattern (305) may comprise a material substantially identical to the substrate (300), and the device isolation pattern (310) may comprise an oxide, for example, silicon oxide.
[0094] Referring together with FIG. 15, a gate structure (360) may be formed within a second recess that extends in a first direction (D1) through the upper portion of an active pattern (305) and a device isolation pattern (310). The gate structure (360) may include a gate insulation pattern (330) formed on the bottom surface and side wall of the second recess, a gate electrode (340) formed on the portion of the gate insulation pattern (330) formed on the bottom surface and lower side wall of the second recess, and a gate mask (350) formed on the gate electrode (340) to fill the upper portion of the second recess.
[0095] The gate insulation pattern (330) may include an oxide such as silicon oxide, for example, the gate electrode (340) may include a metal, metal nitride, metal silicide, etc., and the gate mask (350) may include an insulating nitride such as silicon nitride, for example.
[0096] In exemplary embodiments, the gate structure (360) may be extended along a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2).
[0097] Referring to FIG. 16 and FIG. 17 together, a fourth opening (440) may be formed to penetrate the insulating film structure (430) and expose the upper surface of the active pattern (305), the device isolation pattern (310), and the gate mask (350) included in the gate structure (360), and the upper surface of the central part of the active pattern (305) in the third direction (D3) may be exposed by the fourth opening (440).
[0098] In exemplary embodiments, the bottom surface of the fourth opening (440) may be wider than the top surface of the active pattern (305) exposed by the fourth opening (440). Accordingly, the fourth opening (440) may also expose the top surface of the device isolation pattern (310) adjacent to the active pattern (305). Additionally, the fourth opening (440) may penetrate the top of the active pattern (305) and the top of the device isolation pattern (310) adjacent thereto, and accordingly, the bottom surface of the fourth opening (440) may be lower than the top surface of each edge portion of the active pattern (305) in the third direction (D3) of the active pattern (305) where the fourth opening (440) is not formed.
[0099] The bit line structure (595) may include a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) that are sequentially stacked in the vertical direction on the fourth opening (440) or the first insulating pattern structure (435). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) may together form a conductive structure, and the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) may together form an insulating structure.
[0100] The first conductive pattern (455) may include, for example, impurity-doped polysilicon, the first barrier pattern (465) may include, for example, a metal nitride such as titanium nitride or, for example, a metal silicon nitride such as titanium silicon nitride, the second conductive pattern (475) may include, for example, a metal such as tungsten, and each of the first mask (485), the second etching stop pattern (565) and the first capping pattern (585) may include, for example, an insulating nitride such as silicon nitride.
[0101] In exemplary embodiments, the bit line structure (595) may extend in a second direction (D2) on the substrate (300) and may be formed in multiple numbers spaced apart from each other along the first direction (D1).
[0102] The fourth and fifth insulating patterns (610, 620) are formed within the fourth opening (440) and can come into contact with the lower sidewall of the bit line structure (595). The fourth insulating pattern (610) may include an oxide, for example, silicon oxide, and the fifth insulating pattern (620) may include an insulating nitride, for example, silicon nitride.
[0103] The first insulating pattern structure (435) may be formed below the bit line structure (595) on the active pattern (305) and the device isolation pattern (310), and may include first to third insulating patterns (405, 415, 425) sequentially stacked along the vertical direction. At this time, the first and third insulating patterns (405, 425) may include an oxide, for example, silicon oxide, and the second insulating pattern (415) may include an insulating nitride, for example, silicon nitride.
[0104] The above contact plug structure may include a lower contact plug (675), a metal silicide pattern (700), and an upper contact plug (775) sequentially stacked along the vertical direction on an active pattern (305) and a device isolation pattern (310).
[0105] The lower contact plug (675) may contact the upper surface of each of the two edge portions in the third direction (D3) of the active pattern (305). In exemplary embodiments, the lower contact plugs (675) may be spaced apart from each other along the second direction (D2) between the bit line structures (595), and a second capping pattern (685) may be formed between the lower contact plugs (675) adjacent to each other in the second direction (D2). In this case, the second capping pattern (685) may include an insulating nitride, for example, silicon nitride.
[0106] The lower contact plug (675) may include, for example, polysilicon doped with impurities, and the metal silicide pattern (700) may include, for example, titanium silicide, cobalt silicide, nickel silicide, etc.
[0107] The upper contact plug (775) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. The second metal pattern (745) may include a metal such as tungsten, for example, and the second barrier pattern (735) may include a metal nitride such as titanium nitride, for example.
[0108] In exemplary embodiments, the upper contact plugs (775) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2) and may be arranged in a honeycomb or grid shape when viewed from above. Each upper contact plug (775) may have a circular, elliptical, or polygonal shape when viewed from above.
[0109] The spacer structure (670) may include a first spacer (600) covering the side wall of the bit line structure (595) and the side wall of the third insulation pattern (425), an air spacer (635) formed on the lower outer wall of the first spacer (600), and a third spacer (650) covering the outer wall of the air spacer (635), the side wall of the first insulation pattern structure (435), and the upper surface of the fourth and fifth insulation patterns (610, 620).
[0110] Each of the first and third spacers (600, 650) may contain an insulating nitride, such as silicon nitride, for example, and the air spacer (895) may contain air.
[0111] The fourth spacer (690) may be formed on the outer wall of the portion of the first spacer (600) formed on the upper side wall of the bit line structure (595), and may cover the top of the air spacer (635) and the upper surface of the third spacer (650). The fourth spacer (690) may include an insulating nitride, for example, silicon nitride.
[0112] Referring together to FIGS. 27 through 29, the second insulating pattern structure (790) may include a sixth insulating pattern (770) formed on the inner wall of a ninth opening (760) surrounding the upper contact plug (775) when viewed from above, penetrating the upper contact plug (775), a part of the insulating structure included in the bit line structure (595), and parts of the first, third, and fourth spacers (600, 700, 690), and a seventh insulating pattern (780) formed on the sixth insulating pattern (770) to fill the remaining part of the ninth opening (760). At this time, the top of the air spacer (635) may be closed by the sixth insulating pattern (770).
[0113] The 6th and 7th insulating patterns (770, 780) may include insulating nitrides, for example, silicon nitride.
[0114] The first etch stop layer (30) can be formed on the sixth and seventh insulating patterns (770, 780), the upper contact plug (775), and the second capping pattern (685).
[0115] The capacitor (110) can come into contact with the upper surface of the upper contact plug (775).
[0116] FIGS. 14 to 29 are plan views and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 14, 16, 19, 23 and 27 are plan views, FIG. 15 includes cross-sectional views cut along the A-A' and B-B' lines of FIG. 14, respectively, and FIGS. 17-18, 20-22, 24-26 and 28-29 are cross-sectional views cut along the A-A' line of the corresponding plan views, respectively.
[0117] The manufacturing method of the above semiconductor device is a method of manufacturing a DRAM device in which the method of forming a capacitor structure described with reference to FIGS. 3 to 9, FIG. 1, and FIG. 2 is applied, and a redundant description of the method of forming the capacitor structure is omitted.
[0118] Referring to FIGS. 14 and 15, after removing the upper part of the substrate (300) to form a first recess, a device separation pattern (310) that fills the first recess can be formed.
[0119] As a device separation pattern (310) is formed on the substrate (300), an active pattern (305) in which the sidewall is covered by the device separation pattern (310) can be defined.
[0120] Subsequently, the active pattern (305) and the device isolation pattern (310) formed on the substrate (300) may be partially etched to form a second recess extending in a first direction (D1), and then a gate structure (360) may be formed inside the second recess. In exemplary embodiments, the gate structure (360) may extend along the first direction (D1) and may be formed in multiple numbers spaced apart from each other along the second direction (D2).
[0121] Referring to FIGS. 16 and 17, an insulating film structure (430) can be formed on an active pattern (305), a device isolation pattern (310), and a gate structure (360). The insulating film structure (430) may include first to third insulating films (400, 410, 420) that are sequentially stacked.
[0122] Subsequently, an insulating film structure (430) can be patterned and used as an etching mask to partially etch the gate mask (350) included in the lower active pattern (305), device isolation pattern (310), and gate structure (360), thereby forming a fourth opening (440). In exemplary embodiments, the insulating film structure (430) remaining after the etching process may have a circular or elliptical shape when viewed from above and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the substrate (300). At this time, each insulating film structure (430) may overlap in the vertical direction with the ends of the adjacent active patterns (305) facing each other in the third direction (D3).
[0123] Referring to FIG. 18, a first conductive film (450), a first barrier film (460), a second conductive film (470), and a mask film (480) can be sequentially stacked on an insulating film structure (430), an active pattern (305) exposed by a fourth opening (440), a device isolation pattern (310), and a gate structure (360), and these can together form a conductive structure film. At this time, the first conductive film (450) can fill the fourth opening (440).
[0124] Referring to FIGS. 19 and 20, a second etch stop layer and a first capping layer can be sequentially stacked on the conductive structure film, and then the first capping layer can be etched to form a first capping pattern (585), and the second etch stop layer, mask layer (480), second conductive layer (470), first barrier layer (460), and first conductive layer (450) can be sequentially etched using this as an etching mask.
[0125] In exemplary embodiments, the first capping pattern (585) may be formed in multiple numbers so as to extend in the second direction (D2) and be spaced apart from each other along the first direction (D1).
[0126] As the above etching process is performed, a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the fourth opening (440), and a third insulating pattern (425), a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the second insulating film (410) of the insulating film structure (430) outside the fourth opening (440).
[0127] Hereinafter, the first conductive pattern (455), the first barrier pattern (465), the second conductive pattern (475), the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) that are sequentially stacked will be referred to together as a bit line structure (595). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) can form a conductive structure together, and the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) can form an insulating structure together. In exemplary embodiments, the bit line structure (595) can be extended in a second direction (D2) on the substrate (300) and can be formed in multiple numbers spaced apart from each other along a first direction (D1).
[0128] Referring to FIG. 21, after forming a first spacer film on a substrate (300) on which a bit line structure (595) is formed, fourth and fifth insulating films can be sequentially formed on the first spacer film.
[0129] The first spacer film can also cover the sidewall of the third insulating pattern (425) below the bit line structure (595) formed on the second insulating film (410), and the fifth insulating film can fill the remaining part of the fourth opening (440).
[0130] Subsequently, an etching process may be performed to etch the fourth and fifth insulating films. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as etchants, and all parts of the fourth and fifth insulating films except for the part formed within the fourth opening (440) may be removed. Accordingly, most of the surface of the first spacer film, that is, the part of the first spacer film other than the part formed within the fourth opening (440), may be exposed, and the parts of the fourth and fifth insulating films remaining within the fourth opening (440) may form the fourth and fifth insulating patterns (610, 620), respectively.
[0131] Afterward, a second spacer film can be formed on the exposed first spacer film surface and the fourth and fifth insulating patterns (610, 620) formed within the fourth opening (440), and then anisotropically etched to form a second spacer (630) covering the sidewall of the bit line structure (595) on the first spacer film surface and the fourth and fifth insulating patterns (610, 620).
[0132] Subsequently, a dry etching process using the first capping pattern (585) and the second spacer (630) as an etching mask can be performed to form a fifth opening (640) that exposes the upper surface of the active pattern (305), and the upper surface of the device isolation pattern (310) and the upper surface of the gate mask (350) can also be exposed by the fifth opening (640).
[0133] By the above dry etching process, the first spacer film portion formed on the upper surface of the first capping pattern (585) and the upper surface of the second insulating film (410) can be removed, and accordingly, a first spacer (600) covering the side wall of the bit line structure (595) can be formed. In addition, in the above dry etching process, the first and second insulating films (400, 410) can also be partially removed and remain as first and second insulating patterns (405, 415), respectively, at the bottom of the bit line structure (595). The first to third insulating patterns (405, 415, 425) sequentially stacked at the bottom of the bit line structure (595) can together form a first insulating pattern structure (435).
[0134] Referring to FIG. 22, a third spacer film is formed on the upper surface of the first capping pattern (585), the outer wall of the second spacer (630), a portion of the upper surface of the fourth and fifth insulating patterns (610, 620), and the upper surface of the active pattern (305), device isolation pattern (310), and gate mask (350) exposed by the fifth opening (640), and then the third spacer film is anisotropically etched to form a third spacer (650) that covers the side wall of the bit line structure (595).
[0135] The first to third spacers (600, 630, 650) sequentially stacked along the horizontal direction on the side wall of the bit line structure (595) may be collectively referred to as a preliminary spacer structure (660).
[0136] Afterward, a sacrificial film filling the fifth opening (640) is formed on the substrate (300) to a sufficient height, and then the upper surface of the first capping pattern (585) is flattened until the upper surface is exposed, thereby forming a sacrificial pattern (680) within the fifth opening (640).
[0137] In exemplary embodiments, the sacrifice pattern (680) may be extended in a second direction (D2) and may be formed in multiple numbers spaced apart from each other by bit line structures (595) along the first direction (D1). The sacrifice pattern (680) may include, for example, an oxide such as silicon oxide.
[0138] Referring to FIGS. 23 and 24, a second mask (not shown) comprising a plurality of sixth openings that are each extended in a first direction (D1) and spaced apart from each other in a second direction (D2) is formed on a first capping pattern (585), a sacrifice pattern (680), and a preliminary spacer structure (660), and an etching process is performed using this as an etching mask to etch the sacrifice pattern (680).
[0139] In exemplary embodiments, each of the sixth openings may overlap the area between the gate structures (360) in the vertical direction. As the etching process is performed, a seventh opening may be formed on the substrate (300) to expose the upper surface of the active pattern (305) and the device isolation pattern (310) between the bit line structures (595).
[0140] After removing the second mask, the lower contact plug membrane filling the seventh opening can be formed to a sufficient height, and the upper surface can be flattened until the upper surface of the first capping pattern (585), the sacrifice pattern (680), and the reserve spacer structure (660) is exposed. Accordingly, the lower contact plug membrane can be converted into a plurality of lower contact plugs (675) spaced apart from each other along the second direction (D2) between the bit line structures (595). Additionally, the sacrifice pattern (680) extending in the second direction (D2) between the bit line structures (595) can be separated into a plurality of parts spaced apart from each other along the second direction (D2) by the lower contact plugs (677).
[0141] Afterward, the sacrifice pattern (680) can be removed to form an eighth opening, and then a second capping pattern (685) that fills the eighth opening can be formed. In exemplary embodiments, the second capping pattern (685) can overlap the gate structure (360) in the vertical direction.
[0142] Referring to FIG. 25, the upper part of the lower contact plug (677) is removed to expose the upper part of the preliminary spacer structure (660) formed on the side wall of the bit line structure (595), and then the upper parts of the second and third spacers (630, 650) of the exposed preliminary spacer structure (660) can be removed.
[0143] Afterward, the upper part of the lower contact plug (675) can be further removed. Accordingly, the upper surface of the lower contact plug (675) can be lower than the upper surface of the second and third spacers (630, 650).
[0144] Subsequently, by forming a fourth spacer film on the first bit line structure (595), the preliminary spacer structure (660), the second capping pattern (685), and the lower contact plug (675) and anisotropically etching it, a fourth spacer (690) can be formed that covers the upper portion of the preliminary spacer structure (660) formed on each side wall in the first direction (D1) of the bit line structure (595), and accordingly, the upper surface of the lower contact plug (675) can be exposed.
[0145] Subsequently, a metal silicide pattern (700) can be formed on the upper surface of the exposed lower contact plug (675). In exemplary embodiments, the metal silicide pattern (700) can be formed by forming a first metal film on the first and second capping patterns (585, 685), the fourth spacer (690), and the lower contact plug (675), heat treating the first metal film, and then removing the unreacted portion from the first metal film.
[0146] Referring to FIG. 26, after forming a second barrier film (730) on the first and second capping patterns (585, 685), the fourth spacer (690), the metal silicide pattern (700), and the lower contact plug (675), a second metal film (740) can be formed on the second barrier film (730) to fill the space between the bit line structures (595).
[0147] Afterward, a planarization process may be additionally performed on the upper surface of the second metal film (740). The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.
[0148] Referring to FIGS. 27 and 28, an upper contact plug (775) can be formed by patterning the second metal film (740) and the second barrier film (730), and a ninth opening (760) can be formed between the upper contact plugs (775).
[0149] The ninth opening (760) can be formed by partially removing the second metal film (740) and the second barrier film (730), as well as the first and second capping patterns (585, 685), the preliminary spacer structure (660), and the fourth spacer (690).
[0150] The upper contact plug (775) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. In exemplary embodiments, the upper contact plug (775) may have a shape such as a circle, ellipse, polygon, or rounded polygon when viewed from above, and may be arranged, for example, in a honeycomb pattern along the first and second directions (D1, D2).
[0151] Meanwhile, the lower contact plug (675), metal silicide pattern (700), and upper contact plug (775) sequentially stacked on the substrate (300) can together form a contact plug structure.
[0152] Referring to FIG. 29, the second spacer (630) included in the preliminary spacer structure (660) exposed by the ninth opening (760) is removed to form an air gap, and after forming the sixth insulation pattern (770) on the bottom and side wall of the ninth opening (760), the seventh insulation pattern (780) that fills the remaining part of the ninth opening (760) can be formed.
[0153] The 6th and 7th insulation patterns (770, 780) can together form a 2nd insulation pattern structure (790).
[0154] The top of the air gap can be covered by the sixth insulation pattern (770), and thus an air spacer (635) can be formed. The first spacer (600), the air spacer (635), and the third spacer (650) can together form a spacer structure (665).
[0155] Referring again to FIGS. 12 and FIGS. 13, a capacitor (110), a first etch stop layer (30), a support layer (50), and an upper electrode plate (120) can be formed by performing processes substantially identical or similar to those described with reference to FIGS. 3 through 9.
[0156] At this time, the lower electrode structure (70) included in the capacitor (110) can come into contact with the upper surface of the upper contact plug (775).
[0157] As described above, although the present invention has been explained with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims. Explanation of the symbols
[0158] 10: Substrate 20: Interlayer insulation film 25: First Challenge Pattern 30: First etching step 40: Mold film 50: Jijimak 55, 80, 440, 640, 760, 870: 1st, 3rd, 4th, 5th, 9th, 11th openings 60, 63: First and second lower electrode membranes 62, 65, 64, 61: 1st to 4th lower electrodes 70: Lower electrode structure 90: Dielectric membrane 95: Genetic Patterns 100: Upper electrode membrane 105: Upper electrode 110: Capacitor 120: Upper electrode plate 405, 415, 425, 610, 620, 770, 780: 1st to 8th insulation patterns 10, 300: Substrate 305: Active Pattern 310: Device isolation pattern 330: Gate insulation pattern 340: Gate electrode 350: Gate Mask 360: Gate structure 400, 410, 420: First to third insulating films 430: Insulating membrane structure 450, 470: 1st, 2nd Challenge Screen 455, 475: 1st and 2nd Challenge Patterns 460, 730: 2nd, 2nd barrier membrane 465, 735: 1st and 2nd barrier patterns 480: Mask barrier 485: First Mask 565: Second etching stop pattern 585, 685: 1st and 2nd capping patterns 595: Bit line structure 600, 630, 650, 690: 1st to 4th spacers 635: Air Spacer 660: Spare spacer structure 670: Spacer structure 677: Lower contact plug 680: Sacrifice Pattern 700: Metal silicide pattern 740: Second metal film 745: Second metal pattern 775: Upper contact plug 790: Second insulation pattern structure
Claims
Claim 1 A capacitor structure comprising: a first lower electrode disposed on a substrate; and a second lower electrode disposed on the sidewall of the first lower electrode and comprising an alloy of a first metal and a second metal; a dielectric pattern disposed on the surface of the lower electrode structure; and an upper electrode disposed on the surface of the dielectric pattern, wherein the second lower electrode has a thickness that varies along a vertical direction perpendicular to the upper surface of the substrate, and the weight ratio of the first metal and the second metal within the second lower electrode is constant along the vertical direction. Claim 2 A capacitor structure according to claim 1, wherein each of the first and second metals comprises at least one of titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), iridium (Ir), zirconium (Zr), hafnium (Hf), and niobium (Nb). Claim 3 A capacitor structure according to paragraph 2, wherein the first metal comprises titanium, the second metal comprises niobium, and the second lower electrode comprises a nitride of the alloy. Claim 4 A capacitor structure according to claim 1, further comprising first to third supporting films sequentially arranged along the vertical direction on the side wall of the lower electrode structure, wherein the dielectric pattern comprises a first portion formed below the first supporting film, a second portion formed between the first supporting film and the second supporting film, and a third portion formed on the second supporting film. Claim 5 In claim 4, the second lower electrode comprises a first portion that overlaps horizontally in a horizontal direction with each of the first to third supporting films and the upper surface of the substrate, a second portion that overlaps horizontally with the first portion of the dielectric pattern, a third portion that overlaps horizontally with the second portion of the dielectric pattern, and a fourth portion that overlaps horizontally with the third portion of the dielectric pattern, wherein the thicknesses of the first to fourth portions of the second lower electrode are different capacitor structures. Claim 6 A capacitor structure in which the thickness of the second lower electrode decreases in the order of the first part, the second part, the third part, and the fourth part. Claim 7 A capacitor structure according to claim 5, further comprising a first recess having a first depth defined by the first and second parts of the second lower electrode, a second recess having a second depth deeper than the first depth defined by the first and third parts of the second lower electrode, and a third recess having a third depth deeper than the second depth defined by the first and fourth parts of the second lower electrode. Claim 8 A capacitor structure according to claim 1, further comprising support films spaced apart from each other along the vertical direction and disposed on the side wall of the lower electrode structure, wherein the thickness in the horizontal direction horizontal to the upper surface of the substrate of the second lower electrode portion disposed between the support films gradually decreases from bottom to top along the vertical direction. Claim 9 A capacitor structure comprising: a first lower electrode disposed on a substrate and extending in a vertical direction perpendicular to the upper surface of the substrate; a second lower electrode disposed on a side wall of the first lower electrode and comprising an alloy of niobium (Nb) and titanium (Ti); a dielectric pattern disposed on a side wall of the lower electrode structure; and an upper electrode disposed on a side wall of the dielectric pattern, wherein the weight ratio of the first metal and the second metal within the second lower electrode is constant along the vertical direction. Claim 10 A semiconductor device comprising: an active pattern disposed on a substrate; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded on the upper portion of the active pattern; a bit line structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction and disposed on the central portion of the active pattern; a contact plug structure disposed on each end of the active pattern; and a capacitor structure disposed on the contact plug structure, wherein the capacitor structure comprises: a first lower electrode extending in a vertical direction perpendicular to the upper surface of the substrate; and a lower electrode structure comprising a second lower electrode disposed on the side wall of the first lower electrode, having a thickness that varies along the vertical direction and comprising an alloy of a first metal and a second metal; supporting films disposed on the side wall of the lower electrode structure and spaced apart from each other in the vertical direction; a dielectric pattern disposed on the side wall of a portion of the lower electrode structure disposed between the supporting films; and an upper electrode disposed on the side wall of the dielectric pattern, wherein the weight ratio of the first metal and the second metal within the second lower electrode is constant along the vertical direction.