Capacitor structure and method of forming the same, and semiconductor device including the capacitor structure

Abstract

A capacitor structure may include: a first electrode comprising a nitride of a first metal; an interface film formed on the surface of the first electrode, doped with hydrogen or a halogen element and comprising an oxynitride of a second metal; a dielectric film structure formed on the interface film; and a second electrode formed on the dielectric film structure.

Description

Technology Field

[0001] The present invention relates to a capacitor structure and a method for forming the same, and a semiconductor device including the capacitor structure. Background Technology

[0002] A capacitor structure included in a DRAM device may comprise a capacitor comprising a sequentially stacked lower electrode, a dielectric film, and an upper electrode, and supporting films comprising an insulating material that are vertically spaced apart from each other and contact the surface of the lower electrode. At this time, parasitic capacitance may occur in the supporting film portion positioned between the upper electrode and the lower electrode. Since such parasitic capacitance can adversely affect the operating characteristics of the DRAM, measures to minimize it are required. The problem to be solved

[0003] One objective of the present invention is to provide a capacitor structure having improved electrical characteristics.

[0004] Another objective of the present invention is to provide a semiconductor device comprising a capacitor structure having improved electrical characteristics.

[0005] Another objective of the present invention is to provide a method for forming a capacitor structure having improved electrical characteristics. means of solving the problem

[0006] A capacitor structure according to exemplary embodiments for achieving the above-mentioned objective may include a lower electrode disposed on a substrate, a support film disposed on a side wall of a first portion of the lower electrode, a first interface pattern disposed on the surface of the support film and including first patterns spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate, a dielectric pattern disposed on a side wall of a second portion of the lower electrode, and an upper electrode disposed on a side wall of the dielectric pattern.

[0007] A capacitor structure according to exemplary embodiments for achieving the above-mentioned objective may comprise a lower electrode disposed on a substrate and comprising a first metal, a support film disposed on the sidewall of a first portion of the lower electrode, a first interface pattern disposed on the surface of the support film and protruding in a vertical direction perpendicular to the upper surface of the substrate and comprising a second metal different from the first metal, a dielectric pattern disposed on the sidewall of a second portion of the lower electrode, and an upper electrode disposed on the sidewall of the dielectric pattern.

[0008] A semiconductor device according to exemplary embodiments for achieving other objectives described above comprises an active pattern disposed on a substrate, a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded on the upper portion of the active pattern, a bit line structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction and disposed on the central portion of the active pattern, a contact plug structure disposed on each end of the active pattern, and a capacitor structure disposed on the contact plug structure, wherein the capacitor structure may include a lower electrode disposed on the contact plug structure, a support film disposed on the side wall of a first portion of the lower electrode, a first interface pattern disposed on the surface of the support film and comprising first patterns spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate, a dielectric pattern disposed on the side wall of a second portion of the lower electrode, and an upper electrode disposed on the side wall of the dielectric pattern.

[0009] A method for forming a capacitor structure according to exemplary embodiments for achieving another objective described above comprises alternately and repeatedly forming a mold and a support film on a substrate along a vertical direction perpendicular to the upper surface of the substrate, forming a lower electrode penetrating the mold film and the support film, removing the mold film through an etching process to form a first opening that exposes a portion of the support film and the lower electrode, and forming a first interface pattern on the surface of the support film exposed by the first opening through a first deposition process, wherein the first interface pattern may include first patterns spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate.

[0010] In exemplary embodiments, the first deposition process may include supplying a precursor onto the substrate for a certain period of time, supplying a reactant onto the substrate for a certain period of time to react the precursor and the reactant with each other, and performing a purge process on the substrate.

[0011] In exemplary embodiments, the first deposition process is a selective deposition process, and the first interface pattern may not be formed on the sidewall of the lower electrode.

[0012] In exemplary embodiments, during the first deposition process, a second interface pattern is formed on the sidewall of the lower electrode exposed by the first opening, and the second interface pattern may include second patterns spaced apart from each other along a vertical direction perpendicular to the upper surface of the substrate.

[0013] In exemplary embodiments, the number of first patterns per unit area of ​​the first interface pattern may be greater than the number of second patterns per unit area of ​​the second interface pattern.

[0014] In exemplary embodiments, prior to the first deposition process, the method further comprises forming a second interface pattern containing an oxide on the surface of the support film exposed by the first opening through a second deposition process, wherein the first deposition process may comprise forming the first interface pattern on the surface of the second interface pattern exposed by the first opening.

[0015] In exemplary embodiments, after forming the first interface pattern, a dielectric pattern (95) and an upper electrode (105) are sequentially formed within the first opening, wherein the dielectric pattern may come into contact with the first interface pattern and the support film.

[0016] In exemplary embodiments, the first interface pattern may include at least one of Nb (niobium), Ta (tantalum), V (vanadium), Mo (molybdenum), W (tungsten), Ru (ruthenium), Ti (titanium), Zr (zirconium), and Hf (hafnium). Effects of the invention

[0017] A capacitor structure according to exemplary embodiments may include a lower electrode, an upper electrode, a dielectric pattern interposed between them, and a support film disposed on the sidewall of the dielectric pattern, wherein an interface pattern comprising metal or carbon may be formed on the surface of the support film. The interface pattern can suppress the occurrence of parasitic capacitance between the upper electrode and the lower electrode by preventing charge accumulation on the surface of the support film. Accordingly, the capacitor structure and the semiconductor device including the same can secure improved electrical characteristics. Brief explanation of the drawing

[0018] FIGS. 1 to 3 are cross-sectional views illustrating capacitor structures according to exemplary embodiments. FIGS. 4 to 12 are cross-sectional views illustrating a method for forming a capacitor structure according to exemplary embodiments. FIGS. 13 and FIGS. 16 are cross-sectional views illustrating capacitor structures according to exemplary embodiments. FIGS. 17 to 21 are cross-sectional views illustrating a method for forming a capacitor structure according to exemplary embodiments. FIG. 22 is a cross-sectional view illustrating a capacitor structure according to exemplary embodiments. FIG. 23 is a cross-sectional view illustrating a method for forming a capacitor structure according to exemplary embodiments. FIGS. 24 and FIGS. 25 are a plan view and a cross-sectional view for illustrating a semiconductor device according to exemplary embodiments. FIGS. 26 to 41 are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0019] Hereinafter, a capacitor structure and a method for forming the same, a semiconductor device including the capacitor structure, and a method for manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and / or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and / or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process.

[0020] [Example]

[0021] FIGS. 1 to 3 are cross-sectional views illustrating capacitor structures according to exemplary embodiments. In this case, FIGS. 2 and FIG. 3 are enlarged cross-sectional views of region X of FIG. 1.

[0022] Referring to FIGS. 1 to 3, the capacitor structure may include a capacitor (110), a support film (50), a first etch stop film (30), and an upper electrode plate (120) formed on a substrate (10), and the capacitor (110) may include a lower electrode (65), a first interface pattern (70), a dielectric pattern (95), and an upper electrode (105).

[0023] Meanwhile, on the substrate (10), a first conductive pattern (25) in contact with the lower electrode (65) and an interlayer insulating film (20) accommodating it may be formed.

[0024] The substrate (10) may include, for example, semiconductor materials such as silicon, germanium, silicon-germanium, etc., or group III-V compounds such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (10) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0025] The first conductive pattern (25) may include, for example, a contact plug, a landing pad, etc., and may be formed in multiple numbers spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate (10) on the substrate (10). The first conductive pattern (25) may include, for example, a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities. The interlayer insulating film (20) may include, for example, an oxide such as silicon oxide or a low dielectric material.

[0026] A first etch stop layer (30) may be formed on the interlayer insulating film (20). The first etch stop layer (30) may include, for example, an insulating nitride such as silicon nitride (SiN), boron nitride (SiBN), silicon carbonitride (SiCN), etc.

[0027] The lower electrode (65) can penetrate the first etch stop layer (30) and contact the upper surface of each first conductive pattern (25), and may have a pillar shape extending in a vertical direction perpendicular to the upper surface of the substrate (10). However, the concept of the present invention is not limited thereto, and the lower electrode (65) may have a cup shape or a hollow cylinder shape. If the lower electrode (65) has a cup shape, a charge pattern including, for example, a semiconductor material such as amorphous silicon or an insulating material may be further formed in the internal space defined by the lower electrode (65).

[0028] In exemplary embodiments, the lower electrode (65) may include a conductive material such as a metal, a metal nitride, or a metal silicon nitride, for example, titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), chromium nitride (CrN), hafnium nitride (HfN), zirconium nitride (ZrN), tungsten nitride (WN), titanium silicon nitride (TiSiN), etc. Although the drawing shows the lower electrode (65) having a single film structure, the concept of the present invention is not limited thereto and may have a composite film structure including, for example, different conductive materials.

[0029] The support film (50) may be formed on the side wall of the lower electrode (65) and, for example, may have a flat plate shape having upper and lower surfaces in a horizontal direction parallel to the upper surface of the substrate (10). In exemplary embodiments, the support film (50) may be formed in multiple pieces spaced apart from each other on the first etch stop film (30) along a vertical direction perpendicular to the upper surface of the substrate (10).

[0030] The support film (50) may include insulating nitrides such as silicon nitride (SiN), boron nitride (SiBN), silicon carbonitride (SiCN), etc.

[0031] The first interface pattern (70) is formed on the lower surface of the top layer support film (50), the upper and lower surfaces of each of the remaining support films (50) excluding the top surface, and the upper surface of the first etching stop film (30), so as to partially cover them.

[0032] The first interface pattern (70) may include a plurality of first patterns formed to be spaced apart from each other along the horizontal direction. Accordingly, there may be empty spaces between the first patterns adjacent to each other in the horizontal direction, and accordingly, the lower electrodes (65) adjacent to each other in the horizontal direction may not be electrically connected to each other by the first interface pattern (70).

[0033] In exemplary embodiments, as shown in FIG. 2, the first interface pattern (70) may be formed only on the upper and lower surfaces of each support film (50) and on the upper surface of the first etching stop film (30), and may not be formed on the side wall of the lower electrode (65).

[0034] In other embodiments, as illustrated in FIG. 3, a second interface pattern (75) may be formed on the side wall of the lower electrode (65). Similar to the first interface pattern (70), the second interface pattern (75) may include a plurality of second patterns formed to be spaced apart from each other along the vertical direction. In one embodiment, the spacing between the first patterns may be smaller than the spacing between the second patterns. Accordingly, the number of the first patterns of the first interface pattern (70) per unit area may be greater than the number of the second patterns of the second interface pattern (75) per unit area.

[0035] In exemplary embodiments, the proportion of the first and second interface patterns (70, 75) on the surfaces of the support film (50) and the lower electrode (65), respectively, may be approximately 5% or less.

[0036] Each of the first patterns of the first interface pattern (70) may protrude from the lower surface of the uppermost support film (50), the upper and lower surfaces of each of the remaining support films (50) excluding the first, and the upper surface of the first etching stop film (30), and the cross-section thereof may have a shape such as a semicircle, ellipse, or square. Additionally, each of the second patterns of the second interface pattern (75) may protrude from the side wall of the lower electrode (65), and the cross-section thereof may have a shape such as a semicircle, ellipse, or square. Although the drawing shows the first patterns spaced apart from each other at regular intervals along the horizontal direction and the second patterns spaced apart from each other at regular intervals along the vertical direction, the concept of the present invention is not limited thereto, and the first patterns may be spaced apart at different intervals along the horizontal direction and the second patterns may be spaced apart at different intervals along the vertical direction.

[0037] Each of the first and second interface patterns (70, 75) may include a metal having leaky characteristics, such as a transition metal, for example. Specifically, the first interface pattern (70) may include at least one of niobium (Nb), tantalum (Ta), vanadium (V), molybdenum (Mo), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), copper (Cu), zinc (Zn), zirconium (Zr), ruthenium (Ru), rhodium (Rh), palladium (Pd), hafnium (Hf), iridium (Ir), platinum (Pt), and tungsten (W), and may include oxides, carbides, or nitrides thereof.

[0038] The dielectric pattern (95) may contact the sidewalls of each lower electrode (65) between the first etching stop layer (30) and the bottom layer support layer (50), and between the support layers (50), and may also contact the upper surface of the first etching stop layer (30), the lower surface of the top layer support layer (50), the upper and lower surfaces of each of the remaining support layers (50) excluding these, and the first interface pattern (70) formed thereon. In one embodiment, the dielectric pattern (95) may contact the second interface pattern (75) formed on the sidewalls of the lower electrodes (65).

[0039] The dielectric pattern (95) may include a metal oxide. In one embodiment, the dielectric pattern (95) may include a high-K material, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (TaO2), strontium titanium oxide (SrTiO3), barium titanium oxide (BaTiO3), etc.

[0040] The upper electrode (105) can have its surface covered by a dielectric pattern (95) and can be formed between the first etching stop layer (30) and the lowest layer lower electrode (65), and between the support layers (50).

[0041] The upper electrode (105) may contain substantially the same material as the lower electrode (70) or may contain a different material.

[0042] The upper electrode plate (120) may be formed on the lower electrode (70) and the uppermost lower electrode (65), and may include, for example, silicon-germanium doped with impurities.

[0043] As described above, the capacitor structure may comprise a capacitor (110) including a sequentially stacked lower electrode (65), a dielectric pattern (95), and an upper electrode (105), and supporting films (50) containing an insulating material that are vertically spaced apart from each other and contact the sidewalls of the lower electrode (65). At this time, parasitic capacitance may occur in the portion of the supporting film (50) formed between the upper electrode (105) and the lower electrode (65).

[0044] However, in exemplary embodiments, a first interface pattern (70) comprising a metal having leakage characteristics may be formed on the surface of each support film (50), and the first interface pattern (70) can suppress parasitic capacitance occurring between the upper electrode (105) and the lower electrode (65) by preventing charge from accumulating on the surface of each support film (50).

[0045] Meanwhile, instead of the first interface pattern (70) being formed continuously between the lower electrodes (65), it may include multiple first patterns formed spaced apart from each other along the horizontal direction, and thus, even if the first interface pattern (70) is formed, electrical short circuits between the lower electrodes (65) adjacent in the horizontal direction or leakage current from them can be prevented.

[0046] FIGS. 4 to 13 are cross-sectional views illustrating a method for forming a capacitor structure according to exemplary embodiments. FIGS. 10 and FIGS. 11 are enlarged cross-sectional views of the X region of FIG. 9.

[0047] Referring to FIG. 4, an interlayer insulating film (20) accommodating a first conductive pattern (25) is formed on a substrate (10), and a first etch stop film (30) is formed on the first conductive pattern (25) and the interlayer insulating film (20). Then, a mold film (40) and a support film (50) can be alternately and repeatedly stacked on the first etch stop film (30).

[0048] The first challenge pattern (25) can be formed in multiple numbers spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate (10) on the substrate (10).

[0049] The mold film (40) may include, for example, an oxide such as silicon oxide or a low dielectric material.

[0050] Referring to FIG. 5, a first opening (55) can be formed that penetrates the support film (50), the mold film (40), and the first etching stop film (30) to expose the upper surface of each first conductive pattern (25).

[0051] In exemplary embodiments, the first opening (55) can be formed by forming an etching mask on the top layer support film (50) and then using the dry etching process.

[0052] Referring to FIG. 6, a lower electrode film (60) that fills the first opening (55) can be formed on the upper surfaces of the first conductive pattern (25) exposed by the first opening (55) and the uppermost supporting film (50).

[0053] In exemplary embodiments, the lower electrode film (60) may comprise, for example, a metal or a metal nitride.

[0054] Referring to FIG. 7, a flattening process can be performed on the lower electrode film (60) until the upper surface of the uppermost support film (50) is exposed to form a lower electrode (65).

[0055] The above planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0056] Referring to FIG. 8, after forming a second opening that exposes the upper surface of the first etching stop layer (30) by partially removing the support layer (50) and the mold layer (40), the mold layer (40) can be removed through the second opening.

[0057] In exemplary embodiments, the mold film (40) may be removed through a wet etching process, and as the wet etching process is performed, a third opening (67) that exposes the sidewall of the lower electrode (65) may be formed. However, the support films (50) may remain on the sidewall of the lower electrode (65).

[0058] Meanwhile, the upper surface of the first etching blocking film (30) and the surface of each supporting film (50) can also be exposed through the third opening (67).

[0059] Referring to FIGS. 9 to 11, a first interface pattern (70) can be formed on the surface of each supporting film (50) exposed by the third opening (67) and on the surface of the first etching stop film (30).

[0060] The first interface pattern (70) can be formed by performing a deposition process, for example, such as an atomic layer deposition (ALD) process. By controlling the time for supplying the precursor and the reactant when performing the atomic layer deposition process, the first interface pattern (70) generated by the chemical reaction between the precursor and the reactant may be formed discontinuously instead of continuously on the surface of each support film (50) and the surface of the first etch stop film (30). Accordingly, the first interface pattern (70) may be formed to include a plurality of first patterns spaced apart from each other along the horizontal direction on the surface of each support film (50) and the surface of the first etch stop film (30).

[0061] In exemplary embodiments, as shown in FIG. 10, the first interface pattern (70) may be selectively formed only on the surface of each supporting film (50) containing an insulating material and on the surface of the first etch stop film (30). In other embodiments, as shown in FIG. 11, a second interface pattern (75) may be further formed on the surface of a lower electrode (65) containing a conductive material that is exposed by the third opening (67).

[0062] Referring to FIG. 12, after forming a dielectric film (90) on the sidewalls of each lower electrode (65) exposed by the third opening (67), the upper surface of the first etching stop film (30), the surface of each support film (50), and the surface of the first interface pattern (70), an upper electrode film (100) can be formed on the dielectric film (90) to fill the remaining portion of the third opening (67).

[0063] The dielectric film (90) may include, for example, hafnium oxide, zirconium oxide, or a compound thereof.

[0064] At this time, the dielectric film (90) and the upper electrode film (100) can also be laminated on the upper surfaces of the lower electrode (65) and the uppermost support film (50).

[0065] Referring again to FIGS. 1 to 3, the dielectric film (90), upper electrode film (100), and first interface pattern (70) portions stacked on the upper surface of the lower electrode (65) and the upper surface of the uppermost support film (50) can be removed.

[0066] Accordingly, within the third opening (67), the dielectric film (90) and the upper electrode film (100) may remain as the dielectric pattern (95) and the upper electrode (105), respectively.

[0067] The lower electrode (65), the first interface pattern (70), the dielectric pattern (95), and the upper electrode (105) can together form a capacitor (110).

[0068] Afterwards, an upper electrode plate (120) may be additionally formed on the capacitor (110).

[0069] As described above, for example, a deposition process such as an atomic layer deposition (ALD) process can be performed to form a first interface pattern (70) on the surface of each support film (50) and on the surface of the first etch stop film (30), and as the first interface pattern (70) is formed, the parasitic capacitance caused by the support film (50) and the first etch stop film (30) interposed between the lower electrode (65) and the upper electrode (105) can be reduced.

[0070] Meanwhile, by controlling the time of the deposition process, the first interface pattern (70) can be formed to include a plurality of first patterns spaced apart from each other along the horizontal direction. Accordingly, the first interface pattern (70) can be formed discontinuously rather than continuously on the surface of each support film (50) and the surface of the first etching stop film (30), and an electrical short circuit between the lower electrodes (65) adjacent to each other in the horizontal direction due to the first interface pattern (70) can be prevented, or leakage current from the lower electrodes (65) can be prevented.

[0071] FIGS. 13 to 16 are cross-sectional views for illustrating capacitor structures according to exemplary embodiments, where FIG. 13 corresponds to FIG. 1, FIGS. 14 and 15 correspond to FIG. 2, and FIG. 16 corresponds to FIG. 3. In this case, FIGS. 14 to 16 are enlarged cross-sectional views of the X region of FIG. 13.

[0072] The above capacitor structure may be substantially the same or similar as the capacitor structure described with reference to FIGS. 1 to 3, except that it further includes a third interface pattern (80), and thus redundant description is omitted.

[0073] Referring to FIGS. 13 to 16, the capacitor (110) may further include a third interface pattern (80) formed between each support film (50) and the first interface pattern (70), and between the first etch stop film (30) and the first interface pattern (70).

[0074] In exemplary embodiments, as shown in FIG. 14, the third interface pattern (80) may be in contact with the lower surface of the top layer support film (50), the upper and lower surfaces of each support film (50), and the upper surface of the first etching stop film (30), and each of the first patterns of the first interface pattern (70) may protrude in the vertical direction from the third interface pattern (80). In other embodiments, as shown in FIG. 15, the third interface pattern (80) may also be formed on the side wall of the lower electrode (65).

[0075] In exemplary embodiments, as shown in FIG. 14, the first interface pattern (70) may be formed only on the surface of the third interface pattern (80) and may not be formed on the side wall of the lower electrode (65).

[0076] In other embodiments, as illustrated in FIG. 16, a second interface pattern (75) may be further formed on the side wall of the lower electrode (65). Similar to the first interface pattern (70), the second interface pattern (75) may include a plurality of second patterns formed to be spaced apart from each other along the vertical direction. In one embodiment, the spacing between the first patterns may be smaller than the spacing between the second patterns. Accordingly, the number of the first patterns of the first interface pattern (70) per unit area may be greater than the number of the second patterns of the second interface pattern (75) per unit area.

[0077] In exemplary embodiments, the third interface pattern (80) may include an oxide, for example, silicon oxide.

[0078] FIGS. 17 to 21 are cross-sectional views illustrating a method for manufacturing a capacitor structure according to exemplary embodiments. FIG. 18 is an enlarged cross-sectional view of region X of FIG. 17, and FIGS. 20 and FIG. 21 are enlarged cross-sectional views of region X of FIG. 19.

[0079] Since the method for manufacturing the above capacitor structure includes substantially identical or similar processes to those described with reference to FIGS. 4 to 12 and FIGS. 1 to 3, a redundant description thereof is omitted.

[0080] Referring to FIG. 17, after performing processes substantially identical or similar to those described with reference to FIG. 4 to FIG. 8, a third interface pattern (80) can be formed on each support film (50) and the first etch stop film (30) exposed by the third opening (67).

[0081] In exemplary embodiments, the third interface pattern (80) may be formed by performing a deposition process, such as an atomic layer deposition process, for example. In one embodiment, the third interface pattern (80) may be selectively deposited only on the surface of a structure containing an insulating material. Accordingly, as shown in FIG. 17, the third interface pattern (80) may be formed only on the lower surface of the top layer support film (50) exposed by the third opening (67), the upper and lower surfaces of each of the remaining support films (50) excluding this, and the upper surface of the first etch stop film (30). In another embodiment, as shown in FIG. 18, the third interface pattern (80) may also be formed on the sidewall of the lower electrode (65) exposed by the third opening (67).

[0082] Referring to FIGS. 19 to 21, a first interface pattern (70) can be formed on the surface of a third interface pattern (80) by performing processes that are substantially identical or similar to the processes described with reference to FIGS. 9 to 11.

[0083] In exemplary embodiments, as shown in FIG. 20, the first interface pattern (70) may be formed only on the surface of the third interface pattern (80). In other embodiments, as shown in FIG. 21, the second interface pattern (75) may be formed on the surface of the lower electrode (65) exposed by the third opening (67). In yet another embodiment, the third interface pattern (80) may also be formed on the sidewall of the lower electrode (65), and the second interface pattern (70) may be further formed on the surface of the portion of the third interface pattern (80) formed on the sidewall of the lower electrode (65).

[0084] Subsequently, the manufacturing of the semiconductor device can be completed by performing processes that are substantially identical or similar to the processes described with reference to FIG. 12 and FIG. 1 to 3.

[0085] FIG. 22 is a cross-sectional view for illustrating a capacitor structure according to exemplary embodiments, corresponding to FIG. 1. The capacitor structure may be substantially identical or similar to the capacitor structure described with reference to FIG. 1 through 3, except that it further includes first and second doping regions (30d, 50d), and thus redundant description is omitted.

[0086] Referring to FIG. 22, a first doping region (30d) may be formed on the upper part of the first etching stop layer (30), and a second doping region (50d) may be formed on the lower part of the uppermost support layer (50) and on the upper and lower parts of the remaining support layers (50) excluding the uppermost support layer (50).

[0087] Each of the first and second doping regions (30d, 50d) may be doped with carbon, for example, and accordingly, each of the first and second doping regions may include an insulating carbonitride such as, for example, carbon-doped silicon nitride (SiN), boron nitride (SiBN), silicon carbonitride (SiCN), etc.

[0088] In a capacitor structure according to exemplary embodiments, the first and second doping regions (30d, 50d) respectively included in the support film (50) and the first etch stop film (30) may have leakage characteristics. Accordingly, parasitic capacitance occurring between the upper electrode (105) and the lower electrode (65) in the support film (50) portion can be suppressed.

[0089] FIG. 23 is a cross-sectional view illustrating a method for manufacturing a capacitor structure according to exemplary embodiments. Since the method for manufacturing the capacitor structure includes processes that are substantially identical or similar to the processes described with reference to FIGS. 4 to 12 and FIGS. 1 to 3, a redundant description thereof is omitted.

[0090] Referring to FIG. 23, an interlayer insulating film (20) accommodating a first conductive pattern (25) can be formed on a substrate (10), and a first deposition process can be performed on the interlayer insulating film (20) and the first conductive pattern (25) to form a first etch stop film (30). At this time, a first doping region (30d) can be formed on the upper part of the first etch stop film (30).

[0091] In exemplary embodiments, the first doping region (30d) may be formed by using, for example, a carbon source gas together in the first deposition process. In other embodiments, the first doping region (30d) may be formed by performing an ion implantation process, for example, to implant carbon therein, after forming the first etch stop layer (30).

[0092] Subsequently, a second deposition process can be performed on the first etching stop layer (30) to alternately and repeatedly stack the mold layer (40) and the support layer (50). At this time, a second doping region (50d) may be formed on the lower part of the uppermost support layer (50), and on the upper and lower parts of the support layers (50) excluding it.

[0093] In exemplary embodiments, the second doping region (50d) may be formed, for example, by using a carbon source gas together in the second deposition process.

[0094] Subsequently, the manufacturing of the semiconductor device can be completed by performing processes that are substantially identical or similar to the processes described with reference to FIGS. 5 to 12 and FIGS. 1 to 3.

[0095] FIG. 24 is a plan view illustrating a semiconductor device according to exemplary embodiments, and FIG. 25 is a cross-sectional view taken along line A-A' of FIG. 24.

[0096] The above semiconductor device is a DRAM device in which the capacitor structure described with reference to FIGS. 1 to 3 is applied, and a redundant description of the capacitor structure is omitted.

[0097] In the following detailed description of the invention, among the horizontal directions parallel to the upper surface of the substrate (300), two directions that are orthogonal to each other are defined as the first and second directions (D1, D2), respectively, and a direction parallel to the upper surface of the substrate (300) and forming an acute angle with each of the first and second directions (D1, D2) is defined as the third direction (D3). Meanwhile, a direction perpendicular to the upper surface of the substrate (300) is referred to as a vertical direction.

[0098] The semiconductor device may include an active pattern (305) formed on a substrate (300), a gate structure (360), a bit line structure (595), a contact plug structure, and the capacitor structure.

[0099] Additionally, the semiconductor device may further include a device isolation pattern (310), a spacer structure (665), a fourth spacer (690), a second capping pattern (685), first and second insulation pattern structures (435, 790), fourth and fifth insulation patterns (610, 620), and a metal silicide pattern (700).

[0100] The active pattern (305) may be formed in multiple numbers such that each extends in a third direction (D3) and is spaced apart from one another along the first and second directions (D1, D2). The sidewalls of the active pattern (305) may be covered by the device isolation pattern (310). The active pattern (305) may comprise a material substantially identical to the substrate (300), and the device isolation pattern (310) may comprise an oxide, for example, silicon oxide.

[0101] Referring together with FIG. 27, a gate structure (360) may be formed within a second recess that extends in a first direction (D1) through the upper portion of an active pattern (305) and a device isolation pattern (310). The gate structure (360) may include a gate insulation pattern (330) formed on the bottom surface and side wall of the second recess, a gate electrode (340) formed on the portion of the gate insulation pattern (330) formed on the bottom surface and lower side wall of the second recess, and a gate mask (350) formed on the gate electrode (340) to fill the upper portion of the second recess.

[0102] The gate insulation pattern (330) may include an oxide such as silicon oxide, for example, the gate electrode (340) may include a metal, metal nitride, metal silicide, etc., and the gate mask (350) may include an insulating nitride such as silicon nitride, for example.

[0103] In exemplary embodiments, the gate structure (360) may be extended along a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2).

[0104] Referring to FIGS. 28 and FIGS. 29 together, a fourth opening (440) may be formed to penetrate the insulating film structure (430) and expose the upper surface of the active pattern (305), the device isolation pattern (310), and the gate mask (350) included in the gate structure (360), and the upper surface of the central part of the active pattern (305) in the third direction (D3) may be exposed by the fourth opening (440).

[0105] In exemplary embodiments, the bottom surface of the fourth opening (440) may be wider than the top surface of the active pattern (305) exposed by the fourth opening (440). Accordingly, the fourth opening (440) may also expose the top surface of the device isolation pattern (310) adjacent to the active pattern (305). Additionally, the fourth opening (440) may penetrate the top of the active pattern (305) and the top of the device isolation pattern (310) adjacent thereto, and accordingly, the bottom surface of the fourth opening (440) may be lower than the top surface of each edge portion of the active pattern (305) in the third direction (D3) of the active pattern (305) where the fourth opening (440) is not formed.

[0106] The bit line structure (595) may include a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) that are sequentially stacked in the vertical direction on the fourth opening (440) or the first insulating pattern structure (435). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) may together form a conductive structure, and the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) may together form an insulating structure.

[0107] The first conductive pattern (455) may include, for example, impurity-doped polysilicon, the first barrier pattern (465) may include, for example, a metal nitride such as titanium nitride or, for example, a metal silicon nitride such as titanium silicon nitride, the second conductive pattern (475) may include, for example, a metal such as tungsten, and each of the first mask (485), the second etching stop pattern (565) and the first capping pattern (585) may include, for example, an insulating nitride such as silicon nitride.

[0108] In exemplary embodiments, the bit line structure (595) may extend in a second direction (D2) on the substrate (300) and may be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0109] The fourth and fifth insulating patterns (610, 620) are formed within the fourth opening (440) and can come into contact with the lower sidewall of the bit line structure (595). The fourth insulating pattern (610) may include an oxide, for example, silicon oxide, and the fifth insulating pattern (620) may include an insulating nitride, for example, silicon nitride.

[0110] The first insulating pattern structure (435) may be formed below the bit line structure (595) on the active pattern (305) and the device isolation pattern (310), and may include first to third insulating patterns (405, 415, 425) sequentially stacked along the vertical direction. At this time, the first and third insulating patterns (405, 425) may include an oxide, for example, silicon oxide, and the second insulating pattern (415) may include an insulating nitride, for example, silicon nitride.

[0111] The above contact plug structure may include a lower contact plug (675), a metal silicide pattern (700), and an upper contact plug (775) sequentially stacked along the vertical direction on an active pattern (305) and a device isolation pattern (310).

[0112] The lower contact plug (675) may contact the upper surface of each of the two edge portions in the third direction (D3) of the active pattern (305). In exemplary embodiments, the lower contact plugs (675) may be spaced apart from each other along the second direction (D2) between the bit line structures (595), and a second capping pattern (685) may be formed between the lower contact plugs (675) adjacent to each other in the second direction (D2). In this case, the second capping pattern (685) may include an insulating nitride, for example, silicon nitride.

[0113] The lower contact plug (675) may include, for example, polysilicon doped with impurities, and the metal silicide pattern (700) may include, for example, titanium silicide, cobalt silicide, nickel silicide, etc.

[0114] The upper contact plug (775) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. The second metal pattern (745) may include a metal such as tungsten, for example, and the second barrier pattern (735) may include a metal nitride such as titanium nitride, for example.

[0115] In exemplary embodiments, the upper contact plugs (775) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2) and may be arranged in a honeycomb or grid shape when viewed from above. Each upper contact plug (775) may have a circular, elliptical, or polygonal shape when viewed from above.

[0116] The spacer structure (670) may include a first spacer (600) covering the side wall of the bit line structure (595) and the side wall of the third insulation pattern (425), an air spacer (635) formed on the lower outer wall of the first spacer (600), and a third spacer (650) covering the outer wall of the air spacer (635), the side wall of the first insulation pattern structure (435), and the upper surface of the fourth and fifth insulation patterns (610, 620).

[0117] Each of the first and third spacers (600, 650) may contain an insulating nitride, such as silicon nitride, for example, and the air spacer (895) may contain air.

[0118] The fourth spacer (690) may be formed on the outer wall of the portion of the first spacer (600) formed on the upper side wall of the bit line structure (595), and may cover the top of the air spacer (635) and the upper surface of the third spacer (650). The fourth spacer (690) may include an insulating nitride, for example, silicon nitride.

[0119] Referring together to FIGS. 39 to 41, the second insulating pattern structure (790) may include a sixth insulating pattern (770) formed on the inner wall of a ninth opening (760) surrounding the upper contact plug (775) when viewed from above, penetrating the upper contact plug (775), a part of the insulating structure included in the bit line structure (595), and parts of the first, third, and fourth spacers (600, 700, 690), and a seventh insulating pattern (780) formed on the sixth insulating pattern (770) to fill the remaining part of the ninth opening (760). At this time, the top of the air spacer (635) may be closed by the sixth insulating pattern (770).

[0120] The 6th and 7th insulating patterns (770, 780) may include insulating nitrides, for example, silicon nitride.

[0121] The first etch stop layer (30) can be formed on the sixth and seventh insulating patterns (770, 780), the upper contact plug (775), and the second capping pattern (685).

[0122] The capacitor (110) can come into contact with the upper surface of the upper contact plug (775).

[0123] FIGS. 26 to 41 are plan views and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 26, 28, 31, 35 and 39 are plan views, FIG. 27 includes cross-sectional views cut along the A-A' and B-B' lines of FIG. 26, respectively, and FIGS. 29-30, 32-34, 36-38 and 40-41 are cross-sectional views cut along the A-A' line of the corresponding plan views, respectively.

[0124] The method for manufacturing the above semiconductor device is a method for manufacturing a DRAM device in which the method for forming a capacitor structure described with reference to FIGS. 4 to 12 and FIGS. 1 to 3 is applied, and a redundant description of the method for forming the capacitor structure is omitted.

[0125] Referring to FIGS. 26 and 27, after removing the upper part of the substrate (300) to form a first recess, a device separation pattern (310) that fills the first recess can be formed.

[0126] As a device separation pattern (310) is formed on the substrate (300), an active pattern (305) in which the sidewall is covered by the device separation pattern (310) can be defined.

[0127] Subsequently, the active pattern (305) and the device isolation pattern (310) formed on the substrate (300) may be partially etched to form a second recess extending in a first direction (D1), and then a gate structure (360) may be formed inside the second recess. In exemplary embodiments, the gate structure (360) may extend along the first direction (D1) and may be formed in multiple numbers spaced apart from each other along the second direction (D2).

[0128] Referring to FIGS. 28 and 29, an insulating film structure (430) can be formed on an active pattern (305), a device isolation pattern (310), and a gate structure (360). The insulating film structure (430) may include first to third insulating films (400, 410, 420) that are sequentially stacked.

[0129] Subsequently, an insulating film structure (430) can be patterned and used as an etching mask to partially etch the gate mask (350) included in the lower active pattern (305), device isolation pattern (310), and gate structure (360), thereby forming a fourth opening (440). In exemplary embodiments, the insulating film structure (430) remaining after the etching process may have a circular or elliptical shape when viewed from above and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the substrate (300). At this time, each insulating film structure (430) may overlap in the vertical direction with the ends of the adjacent active patterns (305) facing each other in the third direction (D3).

[0130] Referring to FIG. 30, a first conductive film (450), a first barrier film (460), a second conductive film (470), and a mask film (480) can be sequentially stacked on an insulating film structure (430), an active pattern (305) exposed by a fourth opening (440), a device isolation pattern (310), and a gate structure (360), and these can together form a conductive structure film. At this time, the first conductive film (450) can fill the fourth opening (440).

[0131] Referring to FIGS. 31 and 32, a second etch stop layer and a first capping layer can be sequentially stacked on the conductive structure film, and then the first capping layer can be etched to form a first capping pattern (585), and the second etch stop layer, mask layer (480), second conductive layer (470), first barrier layer (460), and first conductive layer (450) can be sequentially etched using this as an etching mask.

[0132] In exemplary embodiments, the first capping pattern (585) may be formed in multiple numbers so as to extend in the second direction (D2) and be spaced apart from each other along the first direction (D1).

[0133] As the above etching process is performed, a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the fourth opening (440), and a third insulating pattern (425), a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a first mask (485), a second etching stop pattern (565), and a first capping pattern (585) may be formed sequentially on the second insulating film (410) of the insulating film structure (430) outside the fourth opening (440).

[0134] Hereinafter, the first conductive pattern (455), the first barrier pattern (465), the second conductive pattern (475), the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) that are sequentially stacked will be referred to together as a bit line structure (595). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) can form a conductive structure together, and the first mask (485), the second etching stop pattern (565), and the first capping pattern (585) can form an insulating structure together. In exemplary embodiments, the bit line structure (595) can be extended in a second direction (D2) on the substrate (300) and can be formed in multiple numbers spaced apart from each other along a first direction (D1).

[0135] Referring to FIG. 33, after forming a first spacer film on a substrate (300) on which a bit line structure (595) is formed, fourth and fifth insulating films can be sequentially formed on the first spacer film.

[0136] The first spacer film can also cover the sidewall of the third insulating pattern (425) below the bit line structure (595) formed on the second insulating film (410), and the fifth insulating film can fill the remaining part of the fourth opening (440).

[0137] Subsequently, an etching process may be performed to etch the fourth and fifth insulating films. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as etchants, and all parts of the fourth and fifth insulating films except for the part formed within the fourth opening (440) may be removed. Accordingly, most of the surface of the first spacer film, that is, the part of the first spacer film other than the part formed within the fourth opening (440), may be exposed, and the parts of the fourth and fifth insulating films remaining within the fourth opening (440) may form the fourth and fifth insulating patterns (610, 620), respectively.

[0138] Afterward, a second spacer film can be formed on the exposed first spacer film surface and the fourth and fifth insulating patterns (610, 620) formed within the fourth opening (440), and then anisotropically etched to form a second spacer (630) covering the sidewall of the bit line structure (595) on the first spacer film surface and the fourth and fifth insulating patterns (610, 620).

[0139] Subsequently, a dry etching process using the first capping pattern (585) and the second spacer (630) as an etching mask can be performed to form a fifth opening (640) that exposes the upper surface of the active pattern (305), and the upper surface of the device isolation pattern (310) and the upper surface of the gate mask (350) can also be exposed by the fifth opening (640).

[0140] By the above dry etching process, the first spacer film portion formed on the upper surface of the first capping pattern (585) and the upper surface of the second insulating film (410) can be removed, and accordingly, a first spacer (600) covering the side wall of the bit line structure (595) can be formed. In addition, in the above dry etching process, the first and second insulating films (400, 410) can also be partially removed and remain as first and second insulating patterns (405, 415), respectively, at the bottom of the bit line structure (595). The first to third insulating patterns (405, 415, 425) sequentially stacked at the bottom of the bit line structure (595) can together form a first insulating pattern structure (435).

[0141] Referring to FIG. 34, a third spacer film can be formed on the upper surface of the first capping pattern (585), the outer wall of the second spacer (630), a portion of the upper surface of the fourth and fifth insulating patterns (610, 620), and the upper surface of the active pattern (305), device isolation pattern (310), and gate mask (350) exposed by the fifth opening (640), and then the third spacer film can be anisotropically etched to form a third spacer (650) that covers the side wall of the bit line structure (595).

[0142] The first to third spacers (600, 630, 650) sequentially stacked along the horizontal direction on the side wall of the bit line structure (595) may be collectively referred to as a preliminary spacer structure (660).

[0143] Afterward, a sacrificial film filling the fifth opening (640) is formed on the substrate (300) to a sufficient height, and then the upper surface of the first capping pattern (585) is flattened until the upper surface is exposed, thereby forming a sacrificial pattern (680) within the fifth opening (640).

[0144] In exemplary embodiments, the sacrifice pattern (680) may be extended in a second direction (D2) and may be formed in multiple numbers spaced apart from each other by bit line structures (595) along the first direction (D1). The sacrifice pattern (680) may include, for example, an oxide such as silicon oxide.

[0145] Referring to FIGS. 35 and 36, a second mask (not shown) comprising a plurality of sixth openings that are each extended in a first direction (D1) and spaced apart from each other in a second direction (D2) is formed on a first capping pattern (585), a sacrifice pattern (680), and a preliminary spacer structure (660), and an etching process is performed using this as an etching mask to etch the sacrifice pattern (680).

[0146] In exemplary embodiments, each of the sixth openings may overlap the area between the gate structures (360) in the vertical direction. As the etching process is performed, a seventh opening may be formed on the substrate (300) to expose the upper surface of the active pattern (305) and the device isolation pattern (310) between the bit line structures (595).

[0147] After removing the second mask, the lower contact plug membrane filling the seventh opening can be formed to a sufficient height, and the upper surface can be flattened until the upper surface of the first capping pattern (585), the sacrifice pattern (680), and the reserve spacer structure (660) is exposed. Accordingly, the lower contact plug membrane can be converted into a plurality of lower contact plugs (675) spaced apart from each other along the second direction (D2) between the bit line structures (595). Additionally, the sacrifice pattern (680) extending in the second direction (D2) between the bit line structures (595) can be separated into a plurality of parts spaced apart from each other along the second direction (D2) by the lower contact plugs (677).

[0148] Afterward, the sacrifice pattern (680) can be removed to form an eighth opening, and then a second capping pattern (685) that fills the eighth opening can be formed. In exemplary embodiments, the second capping pattern (685) can overlap the gate structure (360) in the vertical direction.

[0149] Referring to FIG. 37, the upper part of the lower contact plug (677) is removed to expose the upper part of the preliminary spacer structure (660) formed on the side wall of the bit line structure (595), and then the upper parts of the second and third spacers (630, 650) of the exposed preliminary spacer structure (660) can be removed.

[0150] Afterward, the upper part of the lower contact plug (675) can be further removed. Accordingly, the upper surface of the lower contact plug (675) can be lower than the upper surface of the second and third spacers (630, 650).

[0151] Subsequently, by forming a fourth spacer film on the first bit line structure (595), the preliminary spacer structure (660), the second capping pattern (685), and the lower contact plug (675) and anisotropically etching it, a fourth spacer (690) can be formed that covers the upper portion of the preliminary spacer structure (660) formed on each side wall in the first direction (D1) of the bit line structure (595), and accordingly, the upper surface of the lower contact plug (675) can be exposed.

[0152] Subsequently, a metal silicide pattern (700) can be formed on the upper surface of the exposed lower contact plug (675). In exemplary embodiments, the metal silicide pattern (700) can be formed by forming a first metal film on the first and second capping patterns (585, 685), the fourth spacer (690), and the lower contact plug (675), heat treating the first metal film, and then removing the unreacted portion from the first metal film.

[0153] Referring to FIG. 38, after forming a second barrier film (730) on the first and second capping patterns (585, 685), the fourth spacer (690), the metal silicide pattern (700), and the lower contact plug (675), a second metal film (740) can be formed on the second barrier film (730) to fill the space between the bit line structures (595).

[0154] Afterward, a planarization process may be additionally performed on the upper surface of the second metal film (740). The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0155] Referring to FIGS. 39 and 40, an upper contact plug (775) can be formed by patterning the second metal film (740) and the second barrier film (730), and a ninth opening (760) can be formed between the upper contact plugs (775).

[0156] The ninth opening (760) can be formed by partially removing the second metal film (740) and the second barrier film (730), as well as the first and second capping patterns (585, 685), the preliminary spacer structure (660), and the fourth spacer (690).

[0157] The upper contact plug (775) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. In exemplary embodiments, the upper contact plug (775) may have a shape such as a circle, ellipse, polygon, or rounded polygon when viewed from above, and may be arranged, for example, in a honeycomb pattern along the first and second directions (D1, D2).

[0158] Meanwhile, the lower contact plug (675), metal silicide pattern (700), and upper contact plug (775) sequentially stacked on the substrate (300) can together form a contact plug structure.

[0159] Referring to FIG. 41, the second spacer (630) included in the preliminary spacer structure (660) exposed by the ninth opening (760) is removed to form an air gap, and after forming the sixth insulation pattern (770) on the bottom and side wall of the ninth opening (760), the seventh insulation pattern (780) that fills the remaining part of the ninth opening (760) can be formed.

[0160] The 6th and 7th insulation patterns (770, 780) can together form a 2nd insulation pattern structure (790).

[0161] The top of the air gap can be covered by the sixth insulation pattern (770), and thus an air spacer (635) can be formed. The first spacer (600), the air spacer (635), and the third spacer (650) can together form a spacer structure (665).

[0162] Referring again to FIGS. 24 and 25, a capacitor (110), a first etch stop layer (30), a support layer (50), and an upper electrode plate (120) can be formed by performing processes substantially identical or similar to those described with reference to FIGS. 4 to 12 and FIGS. 1 to 3.

[0163] At this time, the lower electrode (65) included in the capacitor (110) can come into contact with the upper surface of the upper contact plug (775).

[0164] As described above, although the present invention has been explained with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims. Explanation of the symbols

[0165] 10: Substrate 20: Interlayer insulation film 25: First Challenge Pattern 30: First etching step 30d, 50d: 1st and 2nd doping zones 40: Mold film 50: Jijimak 55, 67, 440, 640, 760, 870: 1st, 3rd, 4th, 5th, 9th, 11th openings 60: Lower electrode membrane 65: Lower electrode 70, 75, 80: First to third interface patterns 90: Dielectric membrane 95: Genetic Patterns 100: Upper electrode membrane 105: Upper electrode 110: Capacitor 120: Upper electrode plate 405, 415, 425, 610, 620, 770, 780: 1st to 8th insulation patterns 10, 300: Substrate 305: Active Pattern 310: Device isolation pattern 330: Gate insulation pattern 340: Gate electrode 350: Gate Mask 360: Gate structure 400, 410, 420: First to third insulating films 430: Insulating membrane structure 450, 470: 1st, 2nd Challenge Screen 455, 475: 1st and 2nd Challenge Patterns 460, 730: 2nd, 2nd barrier membrane 465, 735: 1st and 2nd barrier patterns 480: Mask barrier 485: First Mask 565: Second etching stop pattern 585, 685: 1st and 2nd capping patterns 595: Bit line structure 600, 630, 650, 690: 1st to 4th spacers 635: Air Spacer 660: Spare spacer structure 670: Spacer structure 677: Lower contact plug 680: Sacrifice Pattern 700: Metal silicide pattern 740: Second metal film 745: Second metal pattern 775: Upper contact plug 790: Second insulation pattern structure

Claims

Claim 1 A capacitor structure comprising: a lower electrode disposed on a substrate; a support film disposed on the side wall of a first portion of the lower electrode; a first interface pattern disposed on the surface of the support film and including first patterns spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate; a dielectric pattern disposed on the side wall of a second portion of the lower electrode; and an upper electrode disposed on the side wall of the dielectric pattern. Claim 2 In claim 1, the first interface pattern comprises at least one of Nb (niobium), Ta (tantalum), V (vanadium), Mo (molybdenum), W (tungsten), Ru (ruthenium), Ti (titanium), Zr (zirconium), and Hf (hafnium), forming a capacitor structure. Claim 3 In claim 1, the first interface pattern is disposed on the upper and lower surfaces of the support film, respectively, and is a capacitor structure in contact with the dielectric pattern. Claim 4 A capacitor structure according to claim 1, further comprising a second interface pattern disposed between the sidewall of the second portion of the lower electrode and the dielectric pattern, wherein the second interface pattern comprises second patterns spaced apart from each other along a vertical direction perpendicular to the upper surface of the substrate. Claim 5 A capacitor structure according to claim 4, wherein the number of first patterns per unit area of ​​the first interface pattern is greater than the number of second patterns per unit area of ​​the second interface pattern. Claim 6 A capacitor structure according to claim 1, further comprising a second interface pattern comprising an oxide disposed between the surface of the support film and the first interface pattern, wherein the first interface pattern is disposed on the surface of the second interface pattern. Claim 7 A capacitor structure according to claim 6, further comprising a third interface pattern disposed between the sidewall of the second portion of the lower electrode and the dielectric pattern, wherein the third interface pattern comprises second patterns spaced apart from each other along a vertical direction perpendicular to the upper surface of the substrate. Claim 8 A capacitor structure comprising: a lower electrode disposed on a substrate and comprising a first metal; a support film disposed on the sidewall of a first portion of the lower electrode; a first interface pattern disposed on the surface of the support film and protruding in a vertical direction perpendicular to the upper surface of the substrate, comprising a second metal different from the first metal; a dielectric pattern disposed on the sidewall of a second portion of the lower electrode; and an upper electrode disposed on the sidewall of the dielectric pattern. Claim 9 In claim 8, the first interface pattern is disposed on the upper and lower surfaces of the support film, and the capacitor structure protrudes upward and downward from the upper and lower surfaces of the support film, respectively. Claim 10 A semiconductor device comprising: an active pattern disposed on a substrate; a gate structure extending in a first direction parallel to the upper surface of the substrate and embedded on the upper portion of the active pattern; a bit line structure extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction and disposed on the central portion of the active pattern; a contact plug structure disposed on each end of the active pattern; and a capacitor structure disposed on the contact plug structure, wherein the capacitor structure comprises: a lower electrode disposed on the contact plug structure; a support film disposed on the side wall of a first portion of the lower electrode; a first interface pattern disposed on the surface of the support film and comprising first patterns spaced apart from each other along a horizontal direction parallel to the upper surface of the substrate; a dielectric pattern disposed on the side wall of a second portion of the lower electrode; and an upper electrode disposed on the side wall of the dielectric pattern.

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