Display and Driving Methode of the Display

Abstract

The embodiments relate to a display device and a driving method thereof, comprising: a display panel on which pixels are arranged; a memory that stores image data input in frame units in synchronization with a data enable signal; a timing control unit that reads and outputs the image data from the memory; and a data driving unit that converts the image data output from the timing control unit into a data voltage and applies it to the pixels, wherein the timing control unit reads the image data from the memory in synchronization with the data enable signal.

Description

Technology Field

[0001] The present invention relates to a display device and a driving method thereof. Background Technology

[0002] The pixels of the display device include a light-emitting element and a driving circuit that controls the amount of current of the light-emitting element. The driving circuit may include a driving transistor.

[0003] Although the electrical characteristics of the driving transistor must be uniform across all pixels, they may differ between pixels due to process variations, device characteristic variations, and degradation over driving time. To compensate for these variations, external compensation may be applied, which senses the electrical characteristics of the driving transistor—e.g., threshold voltage—in an external circuit and compensates the data voltage based on the sensed characteristics, and internal compensation may be applied, which samples the gate-source voltage of the driving transistor within the pixel and compensates the data voltage by the sampled voltage.

[0004] As the display driving time increases, gate bias stress on the driving transistor accumulates, which can cause the threshold voltage to shift to a negative voltage. This threshold voltage shift can lead to image quality degradation, such as afterimages. The problem to be solved

[0005] The embodiments provide a display device and a driving method thereof that senses a threshold voltage of a driving transistor and delays the shift of the threshold voltage by adjusting a black offset voltage when the threshold voltage is shifted.

[0006] The embodiments provide a display device and a driving method thereof that determine a grayscale change based on data voltage between adjacent frames and adaptively adjust a black offset voltage when a grayscale other than black is displayed after a black grayscale.

[0007] The embodiments provide a display device and a driving method thereof that determine a grayscale change by comparing the data voltage of a current frame applied from the outside with the data voltage of a previous frame stored in a frame memory, and adjust the black offset voltage according to the grayscale change.

[0008] The embodiments provide a display device and a driving method thereof that synchronizes the read cycle of a previous frame data voltage stored in a frame memory with the input cycle of a current frame data voltage. means of solving the problem

[0009] A display device according to one embodiment may include a display panel on which pixels are arranged, a memory that stores image data input in synchronization with a data enable signal in frame units, a timing control unit that reads and outputs the image data from the memory, and a data driving unit that converts the image data output from the timing control unit into a data voltage and applies it to the pixels.

[0010] The above timing control unit can read the image data from the memory in synchronization with the data enable signal.

[0011] The period of the above data enable signal can be varied.

[0012] The above timing control unit can output the image data in synchronization with an internal clock signal having a fixed period.

[0013] The timing control unit can read image data of a first frame from the memory in synchronization with the data enable signal, and write image data of a second frame input in synchronization with the data enable signal to the memory.

[0014] The above timing control unit can compensate the image data of the first frame based on the change in grayscale of the image data of the first frame and the image data of the second frame.

[0015] The timing control unit can determine an offset voltage for the image data of the first frame based on the grayscale change and output the first image data compensated based on the grayscale voltage corresponding to the image data of the first frame and the offset voltage.

[0016] The above timing control unit can increase the offset voltage if the grayscale change is greater than a preset threshold.

[0017] The above timing control unit can increase the offset voltage when the image data of the first frame corresponds to a black gradation and the image data of the second frame does not correspond to the black gradation but to a low gradation smaller than a preset threshold.

[0018] The pixel may include a light-emitting element and a driving transistor that controls a driving current applied to the light-emitting element.

[0019] The timing control unit above can increase the offset voltage when the threshold voltage of the driving transistor is negatively shifted to below a preset threshold value.

[0020] The above memory reads the image data in synchronization with a system clock having a fixed period and a synchronization control signal, wherein the period of the synchronization control signal may be variable in response to the data enable signal.

[0021] The timing control unit may include an image processing unit that outputs a control signal based on a change in the grayscale of a second image data input in synchronization with a first image data read from the memory and a data enable signal, and a compensation unit that outputs a compensation value of the first image data in response to the control signal.

[0022] The above compensation unit can perform a first mode compensation that varies the offset voltage of the first image data based on a threshold voltage shift of a driving transistor provided in the pixel, and a second mode compensation that varies the offset voltage in response to the control signal.

[0023] A display device according to another embodiment may include a display panel on which pixels are arranged, a memory that stores first image data input from the outside in frame units, a timing control unit that reads and outputs second image data stored in the memory, and a data driving unit that converts the image data output from the timing control unit into a data voltage and applies it to the pixels.

[0024] The timing control unit reads the second image data in synchronization with the input period of the first image data, and the input period of the first image data can be varied.

[0025] The above timing control unit can output the image data in synchronization with an internal clock signal having a fixed period.

[0026] A driving method for a display device according to one embodiment comprises the step of the timing control unit writing the first image data to the memory when the first image data is input from the outside.

[0027] While the first image data is being input, the method may include the step of reading a second image data from the memory in synchronization with the input period of the first image data, the step of compensating the first image data based on the grayscale change of the first image data and the second image data, and the step of outputting the compensated first image data.

[0028] The input period of the first image data is variable, and the read period of the second image data can be variable in response to the variation of the input period of the first image data.

[0029] The step of outputting the compensated first image data may include the step of outputting the compensated first image data in synchronization with an internal clock signal having a fixed period.

[0030] The step of compensating the first image data may include a step of determining a grayscale voltage corresponding to the grayscale of the first image data, a step of determining an offset voltage based on the change in grayscale, and a step of adding the offset voltage to the grayscale voltage. Effects of the invention

[0031] The display device and the driving method according to the embodiments can delay the shift of the threshold voltage of the driving transistor, thereby reducing stress on the driving transistor, preventing image degradation, and increasing the lifespan of the pixel.

[0032] The display device and the driving method according to the embodiments can prevent the contrast ratio from decreasing even when there is a sudden change in gradation, and can prevent flashing phenomena occurring at low gradations.

[0033] The display device and the driving method according to the embodiments can predict the flashing diffusion area and prevent flashing phenomena for the corresponding pixel and adjacent pixels.

[0034] The display device and the driving method according to the embodiments can stably perform a comparison of the data voltages of the current frame and the previous frame even when the external data voltage input period varies, by synchronizing the input period of the current frame data voltage with the read period of the previous frame data voltage stored in the frame memory. Brief explanation of the drawing

[0035] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment. FIG. 2 is a block diagram showing the configuration of a display device according to another embodiment. FIG. 3 is a circuit diagram of a pixel according to one embodiment. FIG. 4 is a timing diagram showing a driving method of a display device according to one embodiment. FIGS. 5 to 7 are drawings for explaining a method for compensating image data according to one embodiment. FIGS. 8 and 9 are drawings for explaining a method of compensating image data according to another embodiment. FIG. 10 is a block diagram showing the configuration of a timing control unit according to one embodiment. FIG. 11 is a diagram showing a method of driving an image processing unit according to one embodiment. FIG. 12 is a drawing for explaining the comparison of read and write times of a memory according to one embodiment. FIG. 13 is a diagram showing a method of driving an image processing unit according to another embodiment. FIG. 14 is a drawing for explaining the comparison of read and write times of a memory according to another embodiment. FIG. 15 is a block diagram showing the configuration of a timing control unit according to one embodiment in more detail. Specific details for implementing the invention

[0036] Hereinafter, embodiments are described with reference to the drawings. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "joined" to another component, it means that it may be directly connected / joined to the other component or that a third component may be placed between them.

[0037] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all of one or more combinations that the associated components may define.

[0038] Terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present embodiments, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0039] Terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0040] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0042] FIG. 1 is a block diagram showing the configuration of a display device according to one embodiment. FIG. 2 is a block diagram showing the configuration of a display device according to another embodiment.

[0043] Referring to FIG. 1, the display device (1) includes a timing control unit (10), a memory (11), a gate driving unit (20), a data driving unit (30), a power supply unit (40), and a display panel (50).

[0044] The timing control unit (10) can receive image data (DATA) and a synchronization signal from an external host system, etc. The image data (DATA) may include multiple grayscale data. The synchronization signal may include, for example, a dot clock (DCLK) that determines the transmission speed of the image data (DATA), a data enable signal (DE) that indicates the valid interval of the image data (DATA), a vertical synchronization signal (Vsync) that defines the duration of one frame, and a horizontal synchronization signal (Hsync) that defines the horizontal duration for programming the data voltage (Vdata) to one pixel row within one frame.

[0045] The timing control unit (10) can process image data (DATA) and synchronization signals to suit the operating conditions of the display panel (50). The timing control unit (10) can generate and output a gate driving control signal (CONT1), a data driving control signal (CONT2), and a power supply control signal (CONT3) based on the synchronization signal.

[0046] The memory (11) can be implemented as a DDR SDRAM (Double data rate synchronous dynamic random access memory) capable of reading and writing predetermined data. The memory (11) can read or write image data (DATA) independently or under the control of a timing control unit (10), etc.

[0047] For example, the memory (11) is a frame memory and / or line memory and can write image data (DATA) input from an external host system, etc., in frame units and / or line units. The memory (11) can directly receive and write image data (DATA) received from an external host system, etc., or receive and write it through the timing control unit (10). In addition, the memory (11) can provide previously stored image data (DATA) to the timing control unit (10) in response to a read request from the timing control unit (10).

[0048] In one embodiment, the memory (11) may be provided as a separate component outside the timing control unit (10) as shown in FIG. 1. However, in another embodiment, the memory (11) may be provided inside the timing control unit (10) as shown in FIG. 2.

[0049] The gate driver (20) can generate gate signals based on a gate driving control signal (CONT1) input from the timing control unit (10). The gate driver (20) can provide the generated gate signals to pixels (PX) through a plurality of gate lines (GL). In one embodiment, a single pixel (PX) may be configured to receive a plurality of gate signals having different waveforms. In this embodiment, the gate driver (20) can provide the plurality of gate signals to pixels (PX) of a corresponding pixel row through the gate line (GL).

[0050] The gate driving unit (20) may be configured in the form of a gate in panel mounted on a display panel (50). The gate driving unit (20) may be positioned on one side of the display panel (50) as illustrated, or on both sides of the display panel (50) (e.g., left and right). Depending on the driving method, panel design method, etc., the gate driving unit (20) may be positioned on both sides of the display panel (50) (e.g., left and right) as illustrated, or connected to two or more of the four sides of the display panel (50).

[0051] The data driving unit (30) can generate data signals based on image data (DATA) output from the timing control unit (10) and a data driving control signal (CONT2). The data driving unit (30) can provide the generated data signals to pixels (PX) through a plurality of data lines (DL).

[0052] The power supply unit (40) can generate a high-potential driving voltage (ELVDD) and a low-potential driving voltage (ELVSS) to be supplied to the display panel (50) based on a power supply control signal (CONT3). The power supply unit (40) can supply the generated driving voltages (ELVDD, ELVSS) to the pixels (PX) through corresponding voltage lines (PL1, PL2). Additionally, the power supply unit (40) can further generate a reference voltage, etc., required for driving the pixels (PX) and further supply it to the pixels (PX) through corresponding voltage lines.

[0053] A plurality of pixels (PX) (or, referred to as sub-pixels) are arranged in a display panel (50). The pixels (PX) may be arranged in a matrix form, for example, on the display panel (50). Pixels (PX) arranged in a single pixel row are connected to the same gate line (GL), and pixels (PX) arranged in a single pixel column are connected to the same data line (DL). The pixels (PX) may emit light with a brightness corresponding to the gate signal and data signal supplied through the gate line (GL) and the data line (DL).

[0054] In one embodiment, each pixel (PX) may display any one of red, green, and blue. In another embodiment, each pixel (PX) may display any one of cyan, magenta, and yellow. In various embodiments, each pixel (PX) may display any one of red, green, blue, and white.

[0056] FIG. 3 is a circuit diagram of a pixel according to one embodiment. In the embodiment of FIG. 3, a pixel (PXi) placed in the i-th pixel row is described as an example. Here, i is any natural number greater than or equal to 1 and less than or equal to the total number of pixel rows.

[0057] Referring to FIG. 3, a pixel (PXi) according to one embodiment may include a driving transistor (DT), a light-emitting element (LD) connected to the driving transistor (DT), and a control circuit for controlling the amount of driving current to be applied to the light-emitting element (LD) through the driving transistor (DT). For example, the control circuit may include first and second transistors (T1, T2) and a storage capacitor (Cst).

[0058] The first electrode of the driving transistor (DT) is configured to receive a high potential driving voltage (ELVDD) (connected to the high potential driving voltage line (PL1)), and the second electrode is connected to the light-emitting element (LD) through the second node (N2). The gate electrode of the driving transistor (DT) is connected to the first node (N1). The driving transistor (DT) is turned on according to the voltage applied to the first node (N1) to control the amount of driving current flowing from the high potential driving voltage (ELVDD) to the light-emitting element (LD).

[0059] The first electrode of the first transistor (T1) is connected to the data line (DL), and the second electrode is connected to the gate electrode of the driving transistor (DT) through the first node (N1). The gate electrode of the first transistor (T1) is connected to the first gate line (GL1) to receive a first gate signal. The first gate signal is a scan signal (SCi) and may be a control signal applied to program a data voltage (Vdata) to a pixel (PXi). The first transistor (T1) is turned on according to the scan signal (SCi) applied to the first gate line (GL1) and can transmit the data voltage (Vdata) applied to the data line (DL) to the first node (N1). This first transistor (T1) may be named a switching transistor.

[0060] The first electrode of the second transistor (T2) is connected to the read-out line (RVL), and the second electrode is connected to the second node (N2). The gate electrode of the second transistor (T2) is connected to the second gate line (GL2) to receive a second gate signal. The second gate signal is a sensing signal (SNi) and may be a control signal applied to apply a reference voltage to the pixel (PXi) or to sense the electrical characteristics of the pixel (PXi). The second transistor (T2) is turned on according to the sensing signal (SNi) applied to the second gate line (GL2), thereby electrically connecting the read-out line (RVL) and the second node (N2). When a reference voltage (Vref) is applied to the read-out line (RVL), the reference voltage (Vref) can be applied to the second node (N2) through the second transistor (T2) that is turned on. When the read-out line (RVL) is not connected to the reference voltage (Vref), an electrical signal (e.g., current, voltage) applied to the second node (N2) can flow through the read-out line (RVL) and be transmitted to the data driver (30, FIG. 1) and / or the timing controller (10, FIG. 1), etc. The transmitted electrical signal can be used to detect the electrical characteristics or changes in electrical characteristics of the pixel (PXi). This second transistor (T2) may be named an initialization transistor and / or a sensing transistor.

[0061] A storage capacitor (Cst) is connected between a node (N1) and a second node (N2). The storage capacitor (Cst) can store a voltage corresponding to the voltage difference between the first node (N1) and the second node (N2), that is, the gate-source voltage (Vgs) of the driving transistor (DT). For example, the storage capacitor (Cst) can store a voltage corresponding to the voltage difference between the data voltage (Vdata) applied to the data line (DL) and the second node (N2), and maintain the stored voltage for one frame period to stabilize the gate-source voltage of the driving transistor (DT).

[0062] The light-emitting element (LD) can have its anode electrode connected to the second node (N2) and its cathode electrode connected to the low-potential driving voltage line (PL2) (configured to receive the low-potential driving voltage (ELVSS)). When the driving transistor (DT) is turned on, a current path is formed between the high-potential driving voltage (ELVDD) and the low-potential driving voltage (ELVSS), allowing driving current to flow to the light-emitting element (LD). The light-emitting element (LD) can emit light with a brightness corresponding to the amount of the applied driving current.

[0063] In the embodiment illustrated in FIG. 3, the pixel (PXi) may be composed of N-type transistors. In this embodiment, the transistors (DT, T1, T2) may be turned on when the gate signal is at a high level and turned off when the gate signal is at a low level. In another embodiment, the pixel (PXi) may be composed of P-type transistors. In this embodiment, the transistors (DT, T1, T2) may be turned on when the gate signal is at a low level and turned off when the gate signal is at a high level. In yet another embodiment, the pixel (PXi) may be a hybrid type including both N-type and P-type transistors.

[0065] FIG. 4 is a timing diagram showing a driving method of a display device according to one embodiment.

[0066] Referring to FIGS. 1 through 4 together, in one embodiment, the display device (1) may be driven in frame units. The length of one frame (Frame N, Frame N+1, Frame N+2) may be defined as one cycle of a vertical synchronization signal (Vsync). Each frame (Frame N, Frame N+1, Frame N+2) may include an active period (AT) during which the vertical synchronization signal (Vsync) is applied at an on level (e.g., high level) and a vertical blank period (VB) during which the vertical synchronization signal (Vsync) is applied at an off level (e.g., low level). The active period (AT) may be the period required to display one frame of image data (DATA).

[0067] One period of the horizontal synchronization signal (Hsync) can define one horizontal period (1H) within one frame (Frame N, Frame N+1, Frame N+2). The on-level (e.g., high level) interval of the horizontal synchronization signal (Hsync), i.e., the pulse width (W), can correspond to the time required to write data to the pixels (PX) of one pixel row.

[0068] During the active period (AT), video data (DATA) is input to the timing control unit (10) along with a data enable signal (DE) from an external host device, etc. At this time, the video data (DATA) input is video data (DATA) for the next frame of the current frame.<N+1> It can be.

[0069] The data enable signal (DE) may indicate a valid input interval for image data (DATA). For example, the pulse width (W) of the data enable signal (DE) may be the same as the pulse width (W) of the horizontal synchronization signal (Hsync). Image data (DATA) may be applied in pixel row units in synchronization with the data enable signal (DE) (DATA1, DATA2, DATAi-1, DATAi). During the ON level interval of the data enable signal (DE), image data (DATA) corresponding to each pixel (PX) may be input sequentially in synchronization with the dot clock (DCLK).

[0070] Meanwhile, during the active period (AT), image data (DATA) for the current frame from memory (11) <n>) can be read. Image data (DATA) for the current frame <n>) is the data voltage (Vdata) through the timing control unit (10) and the data driving unit (30). <n>It can be converted to ). Converted data voltage (Vdata <n>)) can be applied to pixels (PX) in synchronization with gate signals (SC1, SC2, 쪋, SCi-1, SCi) that are sequentially applied to pixel rows.

[0071] During the vertical blanking period (VB), image data (DATA) is not applied to the timing control unit (10) in response to a data enable signal (DE) at an off level (e.g., low level). Additionally, data voltage (Vdata) is not applied to the pixels (PX) during the vertical blanking period (VB). Instead, electrical characteristics of the pixels (PX), such as the threshold voltage of the driving transistor (DT), mobility, and driving voltage of the light-emitting element (LD), can be sensed during the vertical blanking period (VB). The sensed electrical characteristics can be converted into sensing data and applied to the data driving unit (30) and / or the timing control unit (10), and the image data (DATA) of the next frame<N+1> It can be used to compensate for ).

[0072] In one embodiment, the display device (1) may be driven in a variable refresh rate mode in which the driving frequency can be varied. For example, the display device (1) may be driven at a refresh rate higher or lower than a predetermined reference refresh rate. When the display device (1) is driven at a rate lower than the reference refresh rate, it may be called "low-speed driving," and when it is driven at a rate higher than the reference refresh rate, it may be called "high-speed driving." The refresh rate may be determined according to the type of image displayed, but is not limited thereto.

[0073] A variable refresh rate mode can be implemented by changing the frequency of other synchronization signals, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), or a data enable signal (DE), adjusting the supply timing, or masking pulses. In this variable refresh rate mode, the length of a frame can be varied. For example, the length of a frame can be varied by fixing the length of the active period (AT) and varying the length of the vertical blank period (VB), or by fixing the length of the vertical blank period (VB) and varying the length of the active period (AT). Alternatively, the length of a frame can be varied by varying both the length of the active period (AT) and the length of the vertical blank period (VB).

[0074] In one embodiment, the period (frequency) of a clock signal, such as a data enable signal (DE), may be varied irregularly in real time due to a communication environment or frequency conversion, etc. Due to the variation in period, the length of one horizontal period (1H) defined by the data enable signal (DE) may be varied as illustrated. Accordingly, the image data (DATA) of the next frame<N+1> ) can be input to the timing control unit (10) at irregular intervals in response to a data enable signal (DE) with a variable period.

[0075] Despite the periodic variation of the clock signal, the timing control unit (10) transmits the image data (DATA) of the current frame to the data driving unit (30) according to a regular period. <n>It must supply regular and stable image data (DATA <n>For the supply of ), the timing control unit (10) may use a separate internal clock signal (iDE) having a fixed period. The timing control unit (10) synchronizes with the internal clock signal (iDE) to obtain image data (DATA) from the memory (11). <n>) can be loaded and applied to the data driving unit (30).

[0077] FIGS. 5 to 7 are drawings for explaining a method for compensating image data according to one embodiment. Specifically, FIG. 5 is a drawing showing a negative shift of a threshold voltage, FIG. 6 is a drawing for explaining a black offset voltage compensation method, and FIG. 7 is a drawing for explaining a horizontal crosstalk compensation method using a black offset voltage.

[0078] Referring to FIG. 3, when driving stress accumulates in the driving transistor (DT), the threshold voltage (Vth) can be shifted to a negative voltage as shown in FIG. 5. The shift in the threshold voltage (Vth) changes the gate-source voltage (Vgs) of the driving transistor (DT) for the same data voltage (Vdata). Accordingly, the amount of current (Ids) flowing through the light-emitting element (LD) changes, and the brightness of the pixel (PX) may decrease.

[0079] This shift in threshold voltage (Vth) can be accelerated when a high gate-source voltage (Vgs) is applied to the driving transistor (DT). Therefore, to reduce the stress applied to the driving transistor (DT), compensation can be performed to lower the gate-source voltage (Vgs) of the driving transistor (DT).

[0080] For example, as shown in FIG. 6, the gate voltage of the driving transistor (DT) in the black gradation can be set to a voltage lower than the source voltage. At this time, if the gate voltage is increased, the gate-source voltage (Vgs) of the driving transistor (DT) is reduced. That is, when the threshold voltage (Vth) is negatively shifted below a predetermined threshold value, the stress on the driving transistor (DT) can be reduced by increasing the data voltage (Vdata) in the black gradation by a predetermined black offset voltage (or offset voltage).

[0081] The black offset voltage can be varied according to the threshold voltage (Vth) sensing result of the driving transistor (DT), and the black offset voltage can be set within a preset margin. The black offset voltage can be added to the voltage corresponding to the black gradation within a range where the brightness of the black gradation is not increased.

[0082] This black offset voltage can be further utilized to prevent horizontal crosstalk (HCT). Referring to FIG. 7, any image may include a black grayscale region (BA) and a white grayscale region (WA) adjacent in the row direction. Due to parasitic capacitance between pixels (PX) placed in the black grayscale region (BA) and pixels (PX) placed in the white grayscale region (WA), horizontal crosstalk may occur in which the brightness is reduced in the black grayscale region (BA) and the white grayscale region (WA).

[0083] To eliminate such horizontal crosstalk, compensation can be applied to reduce the data voltage difference between the white grayscale region (WA) and the black grayscale region (BA). For example, the data voltage difference between the white grayscale region (WA) and the black grayscale region (BA) can be reduced by increasing the data voltage of the black grayscale by the black offset voltage. Since the reduction in the data voltage difference reduces the influence of parasitic capacitance, horizontal crosstalk can be prevented. Therefore, the black offset voltage may also be referred to as the horizontal crosstalk compensation voltage.

[0085] FIGS. 8 and 9 are drawings for explaining a method of compensating image data according to another embodiment. Specifically, FIG. 8 is a drawing for explaining a flashing phenomenon, and FIG. 9 is a drawing for explaining a flashing compensation method using a black offset voltage.

[0086] Referring to FIG. 3 and FIG. 8 together, in one embodiment, any image may be an image in which black gradation and low gradation, for example, low gray gradation, alternate between adjacent frames. For example, black gradation may be displayed in the first to third frames (Frame 1, Frame 2, Frame 3), low gray that is not black may be displayed in the fourth and fifth frames (Frame 4, Frame 5), and black gradation may be displayed in the sixth and seventh frames (Frame 6, Frame 7).

[0087] In the first to third frames (Frame 1, Frame 2, Frame 3), the black grayscale voltage may be 0V and the black offset voltage (Δ) may be 0.1V. Due to black offset voltage compensation, the data voltage (Vdata) applied to the gate electrode of the driving transistor (DT) is 0.1V, which is the black offset voltage (Δ) added to the black grayscale voltage (0V). The voltage of the source electrode of the driving transistor (DT), i.e., the second node (N2), may be 2V, which is the reference voltage (Vref). Accordingly, during the first to third frames (Frame 1, Frame 2, Frame 3), the gate-source voltage (Vgs) of the driving transistor (DT) may be -1.9V.

[0088] In the fourth frame (Frame 4), a data voltage (Vdata) of 2.3V corresponding to the low grayscale may be applied to the gate electrode of the driving transistor (DT). Due to the increase in the gate electrode voltage and the increase in the driving current, and the resulting parasitic capacitance, the voltage of the source electrode may be increased stepwise while the low grayscale is displayed. For example, in the fourth frame (Frame 4), the voltage of the source electrode may be increased from the reference voltage (Vref) to 2.15V, and in the fifth frame (Frame 5), the voltage of the source electrode may be increased to 2.2V. In the fourth frame (Frame 4), the gate-source voltage (Vgs) of the driving transistor (DT) is 0.15V, and in the fifth frame (Frame 5), the gate-source voltage (Vgs) of the driving transistor (DT) becomes 0.1V.

[0089] Changes in the gate-source voltage (Vgs) cause a flashing phenomenon (or flicker phenomenon) in which the brightness of the image changes between adjacent frames. Additionally, an increase in the source voltage of the driving transistor (DT) reduces the gate-source voltage of the driving transistor (DT), causing a decrease in brightness and contrast ratio in which the light-emitting element (LD) cannot emit light at the required brightness.

[0090] To improve the flashing phenomenon, a black offset voltage (Δ) may be further utilized. Specifically, when the gradation changes abruptly between adjacent frames, the data voltage difference between adjacent frames can be reduced by increasing the black offset voltage (Δ) in advance.

[0091] Specifically, referring to FIG. 9, when the image of the current frame, the third frame (Frame 3), is black, and the image of the next frame, the fourth frame (Frame 4), is a non-black gradation or a gradation that has a difference greater than (or greater than or equal to) a preset threshold of black, the black offset voltage (Δ) for the current frame, the third frame (Frame 3), can be increased (e.g., 0.3V). That is, the data voltage (Vdata) applied to the pixel (PX) in the third frame (Frame 3) becomes 0.3V. Subsequently, when a data voltage (Vdata) of 2.3 is applied in the fourth frame (Frame 4), the difference in data voltage between the third frame (Frame 3) and the fourth frame (Frame 4) is relatively reduced. This reduction in data voltage difference reduces the effect of parasitic capacitance, so flashing between adjacent frames, brightness degradation, and contrast ratio reduction can be improved.

[0093] FIG. 10 is a block diagram showing the configuration of a timing control unit according to one embodiment.

[0094] Referring to FIG. 10, a timing control unit (10) according to one embodiment may include an image processing unit (101) and a compensation unit (102).

[0095] The image processing unit (101) receives image data (DATA) from an external host device, etc.<N+1> ) can be received. In FIG. 10, when the current frame is the Nth frame, the image data (DATA) of the N+1th frame, which is the next frame, can be received.<N+1> An example where ) is input is illustrated. Image data (DATA<N+1> ) may include RGB gradation data for each of a plurality of pixels (PX), and may be input sequentially in synchronization with each pulse of the dot clock (DCLK) while the data enable signal (DE) is applied to the ON level.

[0096] Image data (DATA<N+1> ) can be stored in memory (11). Memory (11) is image data (DATA) input from the outside.<N+1> ) can be stored frame by frame. Image data of the N+1th frame (DATA<N+1> When ) is input and stored, the memory (11) contains the current frame, that is, the image data (DATA) of the Nth frame. <n>) is stored in advance.

[0097] In one embodiment, image data (DATA<N+1> ) is input to the image processing unit (101), undergoes the necessary processing steps, and can be stored in memory (11) by the write operation of the image processing unit (101). In another embodiment, image data (DATA<N+1> ) may be stored directly in memory (11) without passing through the image processing unit (101).

[0098] The image processing unit (101) has image data (DATA) of the current frame stored in memory (11) <n>) can be read. The image processing unit (101) can read the read image data (DATA <n>) can be processed to suit the operating conditions of the data driving unit (30) and output to the data driving unit (30).

[0099] In one embodiment, the image processing unit (101) has image data (DATA <n>The image processing unit (101) can perform additional operations necessary for compensation of the next frame of image data (DATA) input from the outside.<N+1> ) and the video data of the read current frame (DATA <n>You can determine whether compensation is needed by comparing ).

[0100] For example, the image processing unit (101) has image data (DATA) of the next frame.<N+1> ) and the image data of the current frame (DATA <n>The grayscale values ​​of the image can be compared, and when the difference in grayscale values ​​is greater than a preset threshold (or greater than or equal to), it can be determined that compensation is required. Alternatively, the image processing unit (101) can compare the image data (DATA) of the current frame. <n>) is a black gradation, and the image data of the next frame (DATA<N+1> When ) is not a black level (for example, when it is a low-gradation image that is greater than the black level but smaller than a preset threshold), it can be determined that compensation is required. Image data (DATA <n>, DATA<N+1> The comparison of grayscale values ​​of ) can be performed in pixel (PX) units or in pixel row units.

[0101] If it is determined that compensation is necessary, the image processing unit (101) may transmit a control signal (CS) to the compensation unit (102). The control signal (CS) may be a digital signal indicating whether compensation is necessary through a logic level. According to an embodiment, the control signal (CS) may include specific information necessary to determine the compensation value, such as the difference in grayscale values, image data of the next frame (DATA<N+1> It may include grayscale values, etc. However, the embodiments are not limited thereto.

[0102] The compensation unit (102) is image data (DATA <n>, DATA<N+1> It is possible to determine and output the compensation value (comp) for ).

[0103] In one embodiment, the compensation unit (102) may perform a first mode compensation (default comp) that outputs a compensation value (comp) in response when a negative shift of the threshold voltage (Vth) is detected. Specifically, the compensation unit (102) may receive sensing data (Vsen) from the data driving unit (30) or a separate sensing unit, etc. The sensing data (Vsen) may include, for example, the threshold voltage (Vth) of the driving transistor (DT). The compensation unit (102) may determine a compensation value (comp) in response to the shift value of the threshold voltage (Vth). For example, the compensation value (comp) may be an offset voltage for the black gradation, i.e., a black offset voltage.

[0104] Additionally, in one embodiment, the compensation unit (102) can perform a second mode compensation (adaptive comp) by outputting a compensation value (comp) in response when a control signal (CS) indicating that compensation is required is received from the image processing unit (101) through a comparison of grayscale values ​​between adjacent frames. Specifically, the compensation unit (102) can determine a compensation value (comp) in response when a predetermined control signal (CS) is input from the image processing unit (101). The compensation value (comp) is, in particular, image data (DATA) in low grayscale. <n>, DATA<N+1> It may be an offset voltage to prevent flashing phenomena caused by abrupt changes in gradation. In this embodiment, the compensation value (comp) may be an offset voltage for the black gradation, i.e., a black offset voltage.

[0105] The compensation value (comp) output from the compensation unit (102) is the image data (DATA) output from the image processing unit (101) through the addition (or subtraction) circuit. <n>It can be added to (or subtracted from) the image data (DATA') compensated in this way. <n>By providing ) to the data driving unit (30), the image quality of the display panel (50) can be improved.

[0106] For determining and outputting such compensation values ​​(comp), the compensation unit (102) may include a look-up table containing one or more predetermined compensation values ​​(comp) corresponding to a threshold voltage (Vth) and / or a grayscale value.

[0107] As explained with reference to Fig. 4, image data (DATA<N+1> ) can be input sequentially synchronized with the dot clock (DCLK) during the ON level interval of the data enable signal (DE). At this time, the period of a clock signal such as the data enable signal (DE) may vary irregularly in real time due to the communication environment or frequency conversion, etc. Accordingly, the image data (DATA) of the next frame<N+1> ) can be input irregularly to the image processing unit (101) in response to a data enable signal (DE) with a variable period.

[0108] On the other hand, regular and stable image data (DATA) to the data driving unit (30) <n>For the supply of ), the timing control unit (10) may use a separate internal clock signal (iDE) having a fixed period. The image processing unit (101) synchronizes with the internal clock signal (iDE) to obtain image data (DATA) from the memory (11) <n>) can be loaded and applied to the data driving unit (30).

[0109] In the above embodiment, image data (DATA <n>, DATA<N+1> For compensation based on the grayscale values ​​of ), the image data of the current frame (DATA <n>) and the image data of the next frame (DATA<N+1> The grayscale values ​​of ) must be compared. However, as mentioned above, if the external clock signal and the internal clock signal are not synchronized, the image data of the current frame (DATA <n>At the time ) is loaded, the image data of the next frame (DATA<N+1> ) may not be input. In that case, the image data of the current frame (DATA <n>When determining whether to compensate for ), the image data of the next frame (DATA<N+1> It may be impossible to compare the grayscale values ​​with ).

[0110] In one embodiment, for correct grayscale value comparison, the timing control unit (10), i.e., the image processing unit (101), synchronizes with the data enable signal (DE) applied from the outside and retrieves image data (DATA) from the memory (11). <n>It can be configured to load ). This is explained in detail below.

[0112] FIG. 11 is a diagram showing a method of driving an image processing unit according to one embodiment. FIG. 12 is a diagram for explaining the comparison of read and write times of a memory according to one embodiment.

[0113] Referring to FIGS. 10 and FIGS. 11 together, the timing control unit (10) receives image data (DATA) of the next frame from the outside.<N+1> It can receive ) and the data enable signal (DE). The image data (DATA) of the next frame<N+1> ) can be sequentially input in pixel row units during horizontal periods (1H) that constitute one frame.

[0114] In one embodiment, the pulse width (W) of the data enable signal (DE) is fixed, but the length of the horizontal period (1H) can be varied by varying the length of the off-level period. Accordingly, image data (DATA) corresponding to each pixel row<N+1> ) can be entered at irregular intervals.

[0115] Image data (DATA<N+1> When the period of the data enable signal (DE) is variable while ) is sequentially applied on a pixel row basis, the entire pixel row, i.e., one frame's worth of image data (DATA<N+1> The time required for the entire input (i.e., the active period (AT, Fig. 4)) is also variable. For example, one frame of video data (DATA<N+1> The time required for all inputs to be entered can vary from about 8.3ms to about 25ms, as shown in FIG. 12 (variable refresh rate mode).

[0116] When the image processing unit (101) operates based on a separate internal clock signal (iDE) having a fixed period, the image processing unit (101) synchronizes with the internal clock signal (iDE) to obtain the image data (DATA) of the current frame from the memory (11) <n>) reads image data (DATA) from memory (11) during the off-level period of the internal clock signal (iDE). Specifically, the image processing unit (101) reads image data (DATA) from memory (11) during the off-level period of the internal clock signal (iDE). <n>) can be read pixel row by row.

[0117] Image data (DATA according to a fixed period <n>When loading ), image data (DATA) in units of one pixel row <n>The time required to read ) is fixed, and consequently, one frame's worth of video data (DATA <n>The time taken to read ) is also fixed. For example, one frame of video data (DATA <n>The time to lead ) can be about 8.3ms, as shown in Fig. 12.

[0118] In this way, image data (DATA<N+1> The input time of ), that is, the write time of the memory (11) and the image data (DATA <n>If the read time of ) that is, the read time of the memory (11) is different, at a predetermined time point (t), the image processing unit (101) [retrieves] the image data (DATA) of the current frame <n>At the time of reading ), the image data of the next frame (DATA<N+1> ) may not be received. Then, the image processing unit (101) receives the image data (DATA) of the current frame. <n>) and the image data of the next frame (DATA<N+1> Since the grayscale values ​​of ) cannot be compared, it is not possible to determine whether to compensate.

[0120] FIG. 13 is a diagram showing a method of driving an image processing unit according to another embodiment. FIG. 14 is a diagram for explaining the comparison of read and write times of a memory according to another embodiment.

[0121] Comparing with FIGS. 11 and 12, in the embodiment of FIG. 13, the image processing unit (101) synchronizes with a data enable signal (DE) applied from the outside to image data (DATA) from the memory (11). <n>) reads the image data (DATA) from the memory (11) during the off-level period of the data enable signal (DE) applied from the outside. Specifically, the image processing unit (101) reads the image data (DATA) from the memory (11) during the off-level period of the data enable signal (DE) applied from the outside. <n>) can be read pixel row by row.

[0122] The time allocated to read the memory (11), i.e., the read time, can be varied in response to a variation in one horizontal period (1H). That is, when the length of one horizontal period (1H) decreases, the read time can be shortened in response to a decrease in the length of the low-level section of the data enable signal (DE). Or, when the length of one horizontal period (1H) decreases, the read time can be increased in response to a decrease in the length of the low-level section of the data enable signal (DE).

[0123] When the physical read speed of the memory (11) is fixed, one pixel row of image data (DATA <n>The time required to read ) is fixed. Image data (DATA) equivalent to one pixel row <n>After the read of ) is completed, the image processing unit (101) may operate in a hold state (or standby state) until the rising edge of the next data enable signal (DE) is detected.

[0124] In this way, image data (DATA) according to a variable period corresponding to the data enable signal (DE) <n>When loading ), one frame's worth of video data (DATA <n>While reading ), the image processing unit (101) can repeat read and hold operations as shown in FIG. 14. One frame of image data (DATA <n>The time required to read ) is one frame's worth of next image data (DATA<N+1> The time taken to input ) can vary between approximately 8.3ms and approximately 25ms.

[0125] In this embodiment, image data (DATA of the current frame) from memory (11) <n>At the time of reading ) the image data of the next frame (DATA<N+1> ) can be stably obtained. Accordingly, the image processing unit (101) has the image data (DATA) of the current frame. <n>) and the image data of the next frame (DATA<N+1> You can determine whether to compensate by comparing the grayscale values ​​of ).

[0126] In one embodiment, the start time of the compensation control operation may be synchronized with the falling edge of the data enable signal (DE). Alternatively, in one embodiment, the end time of the compensation control operation may be synchronized with the rising edge of the next pulse of the data enable signal (DE). However, the embodiments are not limited thereto.

[0128] FIG. 15 is a block diagram showing the configuration of a timing control unit according to one embodiment in more detail.

[0129] Referring to FIG. 15, a timing control unit (10) according to one embodiment may include an image processing unit (101) and a compensation unit (102).

[0130] The image processing unit (101) receives image data (DATA) from the outside<N+1> Can receive ). Image data (DATA<N+1> ) can be input in synchronization with the ON level interval of the data enable signal (DE). The image processing unit (101) receives the received image data (DATA<N+1> ) can be written to memory (11).

[0131] In one embodiment, the memory (11) may operate based on a system clock and a synchronization control signal. Here, the system clock may be a clock signal of a fixed period generated internally by the timing control unit (10). Additionally, the synchronization control signal may be a clock signal of a variable period applied externally, for example, a data enable signal (DE) or a predetermined clock signal corresponding to the variable period of the data enable signal (DE). When the period of the data enable signal (DE) is variable, the memory (11) responds to the synchronization control signal and, according to the variable period, stores image data (DATA <n>) can be output to the image processing unit (101). At this time, the output from the memory (11) is synchronized with the off level interval of the data enable signal (DE).

[0132] Image data (DATA) from memory (11) <n>When ) is read, the image processing unit (101) receives image data (DATA) received from the outside.<N+1> Compares the grayscale value with the image data (DATA) received from the outside.<N+1> Image data with read grayscale values ​​of ) <n>When the grayscale value of ) is greater than (or exceeds) a preset threshold value, the image processing unit (101) can output a control signal (CS). The control signal (CS) may be, for example, a predetermined bit signal indicating the result of checking the grayscale value, and may be named a black check bit.

[0133] In another embodiment, the image processing unit (101) receives the read image data (DATA <n>) is a black gradation, and the received image data (DATA<N+1> It can determine whether ) is a black gradation. Read image data (DATA <n>) is a black gradation, and the received image data (DATA<N+1> When ) is not a black gradation, the image processing unit (101) can output a black check bit.

[0134] In another embodiment, the image processing unit (101) receives the read image data (DATA <n>) is a black gradation, and the received image data (DATA<N+1> When ) is not a black gradation, the received image data (DATA<N+1> It can further determine whether ) is a low grayscale smaller than a preset threshold. Received image data (DATA<N+1> When the low grayscale is smaller than the preset threshold, the image processing unit (101) can output a black check bit.

[0135] The compensation unit (102) is image data (DATA <n>, DATA<N+1> It is possible to determine and output the compensation value (comp) for ).

[0136] In one embodiment, the compensation unit (102) may perform either a first mode compensation or a second mode compensation in response to a black check bit output from the image processing unit (101). For example, when a black check bit is not input, the compensation unit (102) may perform a first mode compensation (default comp) that controls the black offset voltage based on a negative shift of the threshold voltage. Then, when a black check bit is input, the compensation unit (102) performs image data (DATA) of the next frame.<N+1> A second mode compensation (adaptive comp) that controls the black offset voltage based on the grayscale change of ) can be performed.

[0137] When second mode compensation is performed, the compensation unit (102), through the compensation area determination unit (1021), the corresponding image data (DATA <n>A pixel (PX) to be displayed and its surrounding pixels can be determined as a compensation area. Here, the compensation area may be an area where the flashing phenomenon of the pixel (PX) can be spread, and may include one or more other pixels adjacent to the pixel (PX). The compensation unit (102) may select a compensation value (comp) from a look-up table (1022) in which preset compensation values ​​corresponding to the change in grayscale value are stored, and output the selected compensation value (comp) as a compensation value (comp) for the pixels (PX) included in the compensation area.

[0138] In response to a black check bit via a multiplexer, one of the compensation values ​​(comp) according to the first mode compensation or the second mode compensation may be output from the compensation unit (102). The output compensation value (comp) is the image data (DATA) output from the image processing unit (101) via an addition (or subtraction) circuit. <n>It can be added to (or subtracted from) the image data (DATA') compensated in this way. <n>By providing ) to the data driving unit (30), the image quality of the display panel (50) can be improved.

[0140] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the technical configuration of the present invention described above may be implemented in other specific forms without altering the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Furthermore, the scope of the present invention is defined by the claims set forth below rather than by the detailed description above. Additionally, all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0141] 1: Display device 10: Timing control unit 11: Memory 20: Gate drive unit 30: Data driver 40: Power supply 50: Display panel< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

Claim 1 A display device comprising: a display panel on which pixels are arranged; a memory for storing image data input in frame units in synchronization with a data enable signal; a timing control unit for reading and outputting the image data from the memory; and a data driving unit for converting the image data output from the timing control unit into a data voltage and applying it to the pixels, wherein the timing control unit reads the image data from the memory in synchronization with the data enable signal. Claim 2 A display device according to claim 1, wherein the period of the data enable signal is variable. Claim 3 In paragraph 2, the timing control unit outputs the image data in synchronization with an internal clock signal having a fixed period, a display device. Claim 4 A display device according to claim 1, wherein the timing control unit reads image data of a first frame from the memory in synchronization with the data enable signal and writes image data of a second frame input in synchronization with the data enable signal to the memory. Claim 5 In paragraph 4, the timing control unit compensates the image data of the first frame based on the change in grayscale of the image data of the first frame and the image data of the second frame, a display device. Claim 6 A display device according to claim 5, wherein the timing control unit determines an offset voltage for the image data of the first frame based on the grayscale change, and outputs the first image data compensated based on the grayscale voltage corresponding to the image data of the first frame and the offset voltage. Claim 7 In claim 6, the timing control unit increases the offset voltage when the grayscale change is greater than a preset threshold value, in a display device. Claim 8 A display device according to claim 6, wherein the timing control unit increases the offset voltage when the image data of the first frame corresponds to a black gradation and the image data of the second frame does not correspond to the black gradation but to a low gradation smaller than a preset threshold. Claim 9 In claim 6, the pixel comprises: a light-emitting element; and a driving transistor that controls a driving current applied to the light-emitting element, and the timing control unit increases the offset voltage when the threshold voltage of the driving transistor is negatively shifted to less than a preset threshold value, a display device. Claim 10 A display device according to claim 1, wherein the memory reads the image data in synchronization with a system clock having a fixed period and a synchronization control signal, and the synchronization control signal has a variable period corresponding to the data enable signal. Claim 11 A display device according to claim 1, wherein the timing control unit comprises: an image processing unit that outputs a control signal based on a grayscale change of a second image data input in synchronization with a first image data read from the memory and a data enable signal; and a compensation unit that outputs a compensation value of the first image data in response to the control signal. Claim 12 A display device according to claim 11, wherein the compensation unit performs a first mode compensation that varies the offset voltage of the first image data based on a threshold voltage shift of a driving transistor provided in the pixel, and a second mode compensation that varies the offset voltage in response to the control signal. Claim 13 A display device comprising: a display panel on which pixels are arranged; a memory for storing first image data input from the outside in frame units; a timing control unit for reading and outputting second image data previously stored from the memory; and a data driving unit for converting the image data output from the timing control unit into a data voltage and applying it to the pixels, wherein the timing control unit reads the second image data in synchronization with the input period of the first image data, and the input period of the first image data is variable. Claim 14 In paragraph 13, the timing control unit outputs the image data in synchronization with an internal clock signal having a fixed period, a display device. Claim 15 A method for driving a display device comprising a memory for storing image data in frame units and a timing control unit for reading and outputting image data from said memory, wherein the timing control unit comprises: a step of writing the first image data to said memory when first image data is input from an external source; a step of reading a second image data from said memory in synchronization with the input period of the first image data while the first image data is being input; a step of compensating the first image data based on a change in grayscale of the first image data and the second image data; and a step of outputting the compensated first image data. Claim 16 A method according to claim 15, wherein the input period of the first image data is variable, and the read period of the second image data is variable in correspondence with the variation of the input period of the first image data. Claim 17 In claim 15, the step of outputting the compensated first image data comprises the step of outputting the compensated first image data in synchronization with an internal clock signal having a fixed period. Claim 18 In claim 15, the step of compensating the first image data comprises: determining a grayscale voltage corresponding to the grayscale of the first image data; determining an offset voltage based on the change in grayscale; and adding the offset voltage to the grayscale voltage.

Images