Semiconductor device

Abstract

According to embodiments of the present disclosure, a semiconductor device may comprise a substrate, an insulating layer disposed on the substrate and including an outer boundary, a passivation layer disposed on the insulating layer and including an inner boundary located inside the outer boundary, a dummy pattern layer having a lower surface that forms the same plane as the lower surface of the passivation layer and overlaps with at least a portion of the area between the outer boundary and the inner boundary, and having one side located inside the inner boundary, and a redistribution pattern layer disposed on the dummy pattern layer.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to semiconductor devices. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. As the electronics industry develops to a high degree, there is an increasing demand for higher integration in semiconductor devices.

[0003] To meet the requirements for high integration, a semiconductor device may include a Re-Distribution Layer (RDL) pattern. The re-distribution pattern is electrically connected to chip pads and can extend from an area where chip pads are located to another area. The problem to be solved

[0004] The problems of the embodiments of the present disclosure are not limited to those mentioned in this specification, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] The embodiments of the present disclosure can provide a semiconductor device capable of preventing degradation of device characteristics due to process defects. means of solving the problem

[0006] Embodiments of the present disclosure may provide a semiconductor device comprising: a substrate; an insulating layer disposed on the substrate and including an outer boundary; a passivation layer disposed on the insulating layer and including an inner boundary located inside the outer boundary; a dummy pattern layer having a lower surface that forms the same plane as the lower surface of the passivation layer and overlaps with at least a portion of the area between the outer boundary and the inner boundary, and having one side located inside the inner boundary; and a redistribution pattern layer disposed on the dummy pattern layer.

[0007] Embodiments of the present disclosure may provide a semiconductor device comprising a substrate including a chip region and a scribe lane region, an insulating layer disposed on the substrate, a dummy pattern layer disposed on the insulating layer in the scribe lane region, a passivation layer located on the insulating layer and at least a portion of which overlaps the dummy pattern layer, and a redistribution pattern layer disposed overlapping the upper surface of the dummy pattern layer on the outer side of the side of the passivation layer, wherein one side of the dummy pattern layer is located on the inner side of the side of the passivation layer. Effects of the invention

[0008] According to the embodiments of the present disclosure, it is possible to prevent the degradation of the device characteristics of a semiconductor device due to process defects.

[0009] The effects of the embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0010] The content of this disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are provided solely for illustrative purposes and are not intended to limit the content of this disclosure. FIG. 1 is a drawing showing a wafer in which semiconductor devices according to embodiments of the present disclosure are integrated. Figure 2 is an enlarged view of area A of Figure 1. Figure 3 is a drawing showing an example of the cross-sectional structure of the I-I' section of Figure 2. FIGS. 4 to 6 are drawings showing other examples of the cross-sectional structure of the I-I' section of FIG. 2. FIGS. 7 to 12 are drawings illustrating examples of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 3. FIGS. 13 to 16 are drawings illustrating examples of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 4. FIG. 17 is a diagram showing an example of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 5. FIG. 18 is a diagram showing an example of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 6. Specific details for implementing the invention

[0011] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0012] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0013] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0014] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0015] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0017] FIG. 1 is a drawing showing a wafer (1) on which semiconductor devices according to embodiments of the present disclosure are integrated.

[0018] Referring to FIG. 1, the wafer (1) may include a chip region (CHR) and a scribe lane region (SR).

[0019] The chip regions (CHR) may be regions that become individual semiconductor chips after the wafer (1) is diced. Each chip region (CHR) may have integrated circuits to function as individual semiconductor chips. The chip region (CHR) may include a cell region (CR) and a guard ring region (GR). The guard ring region (GR) may be continuous with the side of the cell region (CR).

[0020] The scribe lane area (SR) may extend intersectingly in a first direction (FD) and a second direction (SD) to surround the sides of each chip area (CHR). The first direction (FD) and the second direction (SD) may be substantially perpendicular to each other. The scribe lane area (SR) may be continuous with the chip area (CHR). In a dicing process, the wafer (1) may be diced along a cutting line within the scribe lane area (SR) using a laser, a blade, etc.

[0021] The scribe lane area (SR) may include a redistribution alignment key area (AR). The redistribution alignment key area (AR) may be defined as an area where a redistribution alignment key is placed. The redistribution alignment key may be used for alignment for etching a redistribution pattern layer during the manufacturing process of a semiconductor device.

[0022] The rewiring alignment key area (AR) may be located between adjacent chip areas (CHR). Although FIG. 1 is illustrated as the rewiring alignment key area (AR) being located between adjacent chip areas (CHR) in the first direction (FD), the location where the rewiring alignment key area (AR) is placed is not limited thereto.

[0023] Referring to FIG. 1, a first semiconductor device and a second semiconductor device adjacent thereto may be included in a portion of the wafer (1). The area between the first semiconductor device and the second semiconductor device may be defined as area A.

[0024] Figure 2 is an enlarged view of area A of Figure 1.

[0025] Area A may include a portion of the first semiconductor device and a portion of the second semiconductor device.

[0026] Referring to FIG. 2, the first semiconductor device may include a first chip region (CHR1) and a portion of a first scribe lane region (SR1) that is continuous therewith. The first chip region (CHR1) may include a first cell region (CR1) and a first guard ring region (GR1). The first guard ring region (GR1) may be continuous with the first cell region (CR1). The first guard ring region (GR1) may include a first guard ring (110). The first guard ring (110) may extend to surround the edge of the first cell region (CR1).

[0027] Although two first guard rings (110) are shown in the first guard ring area (GR1) in FIG. 2, the first guard ring area (GR1) is not necessarily limited thereto and may have various numbers of first guard rings (110).

[0028] Referring to FIG. 2, the second semiconductor device may include a second chip region (CHR2) and a portion of a second scribe lane region (SR2) that is continuous therewith. The second chip region (CHR2) may include a second cell region (CR2) and a second guard ring region (GR2). The second guard ring region (GR2) may be continuous with the second cell region (CR2). The second guard ring region (GR2) may include a second guard ring (210). The second guard ring (210) may extend to surround the edge of the second cell region (CR2).

[0029] Although two second guard rings (210) are shown in the second guard ring area (GR2) in FIG. 2, the second guard ring area (GR2) is not necessarily limited thereto and may be equipped with various numbers of second guard rings (210).

[0030] A rewiring alignment key region (AR) may be placed on a portion of the first scribe lane region (SR1) and the second scribe lane region (SR2). A rewiring alignment key (RK) may be placed in the rewiring alignment key region (AR). The rewiring alignment key (RK) may be used for alignment for etching a rewiring pattern layer during the manufacturing process of a semiconductor device.

[0031] Although three rewiring alignment keys (RK) are shown in the rewiring alignment key area (AR) in FIG. 2, the rewiring alignment key area (AR) is not necessarily limited thereto and may have various numbers of rewiring alignment keys (RK).

[0032] In one embodiment, the rewiring alignment key (RK) may be arranged in a bar shape on a plane defined by a first direction (FD) and a second direction (SD), as shown in FIG. 2, but is not limited thereto.

[0033] Figure 3 is a drawing showing an example of the cross-sectional structure of the I-I' section of Figure 2.

[0034] Referring to FIG. 3, the first semiconductor device may include a first substrate (101), a first guard ring (110), a first insulating layer (120), a first dummy pattern layer (130), a first passivation layer (140), a first redistribution insulating layer (150), and a first redistribution pattern layer (160).

[0035] The first semiconductor device may include a first outer boundary (124). In one embodiment, the first outer boundary (124) may be the outermost boundary among the boundaries of the first semiconductor device. In one embodiment, the outer boundary of the first insulating layer (120) may be the same as the first outer boundary (124). In one embodiment, the first outer boundary (124) may be located within the first scribe lane region (SR1). The first passivation layer (140) may include a first inner boundary (143) within the first scribe lane region (SR1). The first inner boundary (143) may be a boundary among the boundaries of the first semiconductor device that is adjacent to the first guard ring region (GR1) than the first outer boundary (124).

[0036] The first outer boundary (124) may extend in a third direction (VD). The first inner boundary (143) may extend in a third direction (VD). The third direction (VD) may be substantially perpendicular to the first direction (FD).

[0037] The first substrate (101) may be located within the first chip region (CHR1) and the first scribe lane region (SR1). The first chip region (CHR1) may include the first cell region (CR1) and the first guard ring region (GR1).

[0038] A first guard ring (110) and a first insulating layer (120) may be disposed on the first substrate (101). The first substrate (101) may include a semiconductor substrate such as a silicon wafer or a Silicon On Insulator (SOI) wafer. The first substrate (101) may include a compound semiconductor substrate such as a group III-V semiconductor substrate, for example, GaAs. The first substrate (101) may include single-crystal silicon, polysilicon, amorphous silicon, single-crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0039] The first guard ring (110) may be disposed on the first substrate (101). The first guard ring (110) may be disposed within the first guard ring region (GR1). The first guard ring (110) may be disposed inside the first inner boundary (143). The first guard ring (110) may include a plurality of first guard metal contacts (111) and a first guard metal layer (112).

[0040] In one embodiment, the first guard metal contact (111) and the first guard metal layer (112) may comprise tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination of two or more of these. Although in FIG. 3, the first guard ring (110) comprises four first guard metal contacts (111) and four first guard metal layers (112), it is not necessarily limited thereto, and the first guard ring (110) may have an varying number of first guard metal contacts (111) and first guard metal layers (112).

[0041] Among the plurality of first guard metal layers (112), the first guard metal layer furthest apart from the first substrate (101) in the third direction (VD) can be defined as the first upper guard metal layer (113).

[0042] The first upper guard metal layer (113) may be disposed on the first upper metal inter-insulating layer (123). The upper surface of the first upper guard metal layer (113) may be in the same plane as the upper surface of the first dummy pattern layer (130). The first upper guard metal layer (113) may contain the same material as the first dummy pattern layer (130). In one embodiment, the first upper guard metal layer (113) may contain aluminum (Al).

[0043] A first insulating layer (120) may be disposed on a first substrate (101). The first insulating layer (120) may include a first interlayer insulating layer (121), a first lower metal-to-metal insulating layer (122), and a first upper metal-to-metal insulating layer (123).

[0044] The first interlayer insulating layer (121) may include at least two selected from the group consisting of silicon (Si), oxygen (O), nitrogen (N), carbon (C), boron (B), phosphorus (P), and hydrogen (H). The first interlayer insulating layer (121) may include an insulating material with excellent step coverage and gap-fill characteristics. In one embodiment, the first interlayer insulating layer (121) may include an oxide such as TEOS (tetraethyl orthosilicate) or BPSG (borophosphosilicate glass).

[0045] A first lower metal-to-metal insulating layer (122) may be disposed on a first interlayer insulating layer (121). The first lower metal-to-metal insulating layer (122) may include a plurality of first lower capping layers (124) and a plurality of first lower metal-to-metal dielectric layers (125).

[0046] Although two first lower metal-to-metal insulating layers (122) are shown in FIG. 3, they are not necessarily limited thereto and may have various numbers of first lower metal-to-metal insulating layers (122).

[0047] A first lower intermetallic dielectric layer (125) may be disposed on the first lower capping layer (124). In one embodiment, the first lower capping layer (124) may comprise a nitride comprising silicon (Si), carbon (C), and nitrogen (N). In one embodiment, the first lower intermetallic dielectric layer (125) may comprise an oxide with a low dielectric constant.

[0048] A first upper metal-inter-insulating layer (123) may be disposed on a first lower metal-inter-insulating layer (122). The first upper metal-inter-insulating layer (123) may include a first upper capping layer (126) and a first upper metal-inter-insulating layer (127).

[0049] In one embodiment, the first upper capping layer (126) may comprise substantially the same material as the first lower capping layer (124). In one embodiment, the first upper intermetallic dielectric layer (127) may be composed of a different configuration from the first lower intermetallic dielectric layer (125). In one embodiment, the first upper intermetallic dielectric layer (127) may comprise an oxide with excellent step coverage and gap-fill properties. In one embodiment, the first upper intermetallic dielectric layer (127) may comprise an oxide layer such as TEOS (tetraethyl orthosilicate).

[0050] A first dummy pattern layer (130) may be disposed on the first upper metal-inter-insulating layer (123). The first dummy pattern layer (130) may be in the same plane as the lower surface of the first passivation layer (140). The first dummy pattern layer (130) may overlap with at least a portion of the area between the first outer boundary (124) and the first inner boundary (143). One side of the first dummy pattern layer (130) may be located inside the first inner boundary (143).

[0051] The first dummy pattern layer (130) may have a first width (W1). The first dummy pattern layer (130) may be located within the first scribe lane area (SR1). The first dummy pattern layer (130) may be placed on the first insulating layer (120). In one embodiment, the first dummy pattern layer (130) may include aluminum (Al).

[0052] A first passivation layer (140) may be disposed on the first insulating layer (120). The first passivation layer (140) may be located inside the first outer boundary (124). The first passivation layer (140) may include a first inner boundary (143) located inside the first outer boundary (124).

[0053] The first passivation layer (140) may include a first passivation oxide layer (141) and a first passivation nitride layer (142). In one embodiment, the first passivation layer (140) may include an oxide, a nitride, or a combination thereof. In one embodiment, the first passivation oxide layer (141) may include a High Density Plasma Oxide (HDP) oxide.

[0054] A first redistribution insulation layer (150) may be disposed on the first passivation layer (140). In one embodiment, the first redistribution insulation layer (150) may include silicon oxide.

[0055] A first redistribution pattern layer (160) may be disposed on a first dummy pattern layer (130). The first redistribution pattern layer (160) may be located within a first scribe lane area (SR1). The lower surface of the first redistribution pattern layer (160), which is coplanar with the upper surface of the first dummy pattern layer (130), may have a second width (W2). In one embodiment, the first width (W1) may be larger than the second width (W2).

[0056] The distance from the upper surface of the first redistribution insulation layer (150) to the first dummy pattern layer (130) may be greater than the distance from the uppermost surface of the first redistribution pattern layer (160) to the first dummy pattern layer (130). The first redistribution pattern layer (160) may contact the upper surface of the first dummy pattern layer (130) between the first outer boundary (124) and the first inner boundary (143). The first redistribution pattern layer (160) may contact the side of the first passivation layer (140) between the first outer boundary (124) and the first inner boundary (143).

[0057] The first redistribution pattern layer (160) may be located on the outer side of the first passivation layer (140). The first redistribution pattern layer (160) may be placed overlapping the upper surface of the first dummy pattern layer (130).

[0058] Referring again to FIG. 3, the second semiconductor device may include a second substrate (201), a second guard ring (210), a second insulating layer (220), a second dummy pattern layer (230), a second passivation layer (240), a second redistribution insulating layer (250), and a second redistribution pattern layer (260).

[0059] The second semiconductor device may include a second outer boundary (224). In one embodiment, the second outer boundary (224) may be the outermost boundary among the boundaries of the second semiconductor device. In one embodiment, the outer boundary of the second insulating layer (220) may be the same as the second outer boundary (224). In one embodiment, the second outer boundary (224) may be located within the second scribe lane region (SR2). The second passivation layer (240) may include a second inner boundary (243) within the second scribe lane region (SR2). The second inner boundary (243) may be a boundary among the boundaries of the second semiconductor device that is closer to the second guard ring region (GR2) than the second outer boundary (224).

[0060] The second outer boundary (224) may be extended in the third direction (VD). The second inner boundary (243) may be extended in the third direction (VD).

[0061] The second substrate (201) may be located within the second chip region (CHR2) and the second scribe lane region (SR2). The second chip region (CHR2) may include the second cell region (CR2) and the second guard ring region (GR2).

[0062] A second guard ring (210) and a second insulating layer (220) may be disposed on the second substrate (201). The second substrate (201) may comprise substantially the same material as the first substrate (101).

[0063] The second guard ring (210) may be disposed on the second substrate (201). The second guard ring (210) may be disposed within the second guard ring region (GR2). The second guard ring (210) may be disposed inside the second inner boundary (243). The second guard ring (210) may include a plurality of second guard metal contacts (211) and a second guard metal layer (212).

[0064] In one embodiment, the second guard metal contact (211) or the second guard metal layer (212) may comprise substantially the same material as the first guard metal contact (111) or the second guard metal layer (112). Although in FIG. 3, the second guard ring (210) comprises four second guard metal contacts (211) and four second guard metal layers (212), the second guard ring (210) may have various numbers of second guard metal contacts (211) and second guard metal layers (212), although it is not necessarily limited thereto.

[0065] Among the plurality of second guard metal layers (212), the second guard metal layer furthest apart from the second substrate (201) in the third direction (VD) can be defined as the second upper guard metal layer (213).

[0066] The second upper guard metal layer (213) may be disposed on the second upper metal inter-insulating layer (223). The upper surface of the second upper guard metal layer (213) may be in the same plane as the upper surface of the second dummy pattern layer (230). The second upper guard metal layer (213) may contain the same material as the second dummy pattern layer (230). In one embodiment, the second upper guard metal layer (211) may contain substantially the same material as the first upper guard metal layer (111).

[0067] A second insulating layer (220) may be disposed on the second substrate (201). The second insulating layer (220) may include a second interlayer insulating layer (221), a second lower metal-to-metal insulating layer (222), and a second upper metal-to-metal insulating layer (223).

[0068] The second interlayer insulation layer (221) may contain substantially the same material as the first interlayer insulation layer (121).

[0069] A second lower metal-to-metal insulating layer (222) may be disposed on the second inter-layer insulating layer (221). The second lower metal-to-metal insulating layer (222) may include a plurality of second lower capping layers (224) and a plurality of second lower metal-to-metal dielectric layers (225).

[0070] Although two second lower metal-to-metal insulating layers (222) are shown in FIG. 3, they are not necessarily limited thereto and may have various numbers of second lower metal-to-metal insulating layers (222).

[0071] A second lower intermetallic dielectric layer (225) may be disposed on the second upper capping layer (224). In one embodiment, the second lower capping layer (224) may comprise substantially the same material as the first lower capping layer (124). In one embodiment, the second lower intermetallic dielectric layer (225) may comprise substantially the same material as the first lower intermetallic dielectric layer (125).

[0072] A second upper metal-inter-insulating layer (223) may be disposed on the second lower metal-inter-insulating layer (222). The second upper metal-inter-insulating layer (223) may include a second upper capping layer (226) and a second upper metal-inter-insulating layer (227).

[0073] In one embodiment, the second upper capping layer (226) may comprise substantially the same material as the first upper capping layer (126). In one embodiment, the second upper intermetallic dielectric layer (227) may be composed of a different configuration from the second lower intermetallic dielectric layer (225). In one embodiment, the second upper intermetallic dielectric layer (225) may comprise substantially the same material as the first upper intermetallic dielectric layer (127).

[0074] A second dummy pattern layer (230) may be disposed on the second upper metal-inter-insulating layer (223). The second dummy pattern layer (230) may be in the same plane as the lower surface of the second passivation layer (240). The second dummy pattern layer (230) may overlap with at least a portion of the area between the second outer boundary (224) and the second inner boundary (243). One side of the second dummy pattern layer (230) may be located inside the second inner boundary (243).

[0075] The second dummy pattern layer (230) may have a third width (W3). The second dummy pattern layer (230) may be located within the second scribe lane area (SR2). The second dummy pattern layer (230) may be placed on the second insulating layer (220). In one embodiment, the second dummy pattern layer (230) may comprise substantially the same material as the first dummy pattern layer (130).

[0076] A second passivation layer (240) may be disposed on the second insulation layer (220). The second passivation layer (240) may be located inside the second inner boundary (224). The second passivation layer (240) may include a second outer boundary (243) located inside the second inner boundary (224).

[0077] The second passivation layer (240) may include a second passivation oxide layer (241) and a second passivation nitride layer (242). In one embodiment, the second passivation layer (240) may include substantially the same material as the first passivation layer (141). In one embodiment, the second passivation oxide layer (241) may include substantially the same material as the first passivation oxide layer (141).

[0078] A second redistribution insulation layer (250) may be disposed on the second passivation layer (240). The second redistribution insulation layer (250) may comprise substantially the same material as the first redistribution insulation layer (150).

[0079] A second redistribution pattern layer (260) may be disposed on a second dummy pattern layer (230). The second redistribution pattern layer (260) may be located within a second scribe lane area (SR2). The lower surface of the second redistribution pattern layer (260), which is coplanar with the upper surface of the second dummy pattern layer (230), may have a fourth width (W4). In one embodiment, the third width (W3) may be larger than the fourth width (W4).

[0080] The distance from the upper surface of the second redistribution insulation layer (250) to the second dummy pattern layer (230) may be greater than the distance from the uppermost surface of the second redistribution pattern layer (260) to the second dummy pattern layer (230). The second redistribution pattern layer (260) may contact the upper surface of the second dummy pattern layer (230) between the second outer boundary (224) and the second inner boundary (243). The second redistribution pattern layer (260) may contact the side of the second passivation layer (240) between the second outer boundary (224) and the second inner boundary (243).

[0081] The second redistribution pattern layer (260) may be located on the outer side of the second passivation layer (240). The second redistribution pattern layer (260) may be placed overlapping the upper surface of the second dummy pattern layer (230).

[0082] Figure 4 is a drawing showing another example of the cross-sectional structure of the I-I' section of Figure 2.

[0083] In describing the following embodiments, descriptions of configurations substantially identical to the previous embodiments will be omitted.

[0084] Referring to FIG. 4, the first semiconductor device may include a first substrate (101), a first guard ring (110), a first insulating layer (120), a first dummy pattern layer (130), a first passivation layer (140), a first redistribution insulating layer (150), a first redistribution pattern layer (160), and a first lower dummy pattern layer (170).

[0085] The first lower dummy pattern layer (170) may include a plurality of first dummy metal contacts (171) and a plurality of first dummy metal layers (172) connected to the plurality of first dummy metal contacts (171). The uppermost first dummy metal contact (171) among the plurality of first dummy metal contacts (171) may be connected to the lower surface of the first dummy pattern layer (130).

[0086] In one embodiment, the first dummy metal contact (171) and the first dummy metal layer (172) may comprise tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), aluminum (Al), copper (Cu), tantalum (Ta), tantalum nitride (TaN), gold (Au), or a combination of two or more of these.

[0087] Referring again to FIG. 4, the second semiconductor device may include a second substrate (201), a second guard ring (210), a second insulating layer (220), a second dummy pattern layer (230), a second passivation layer (240), a second redistribution insulating layer (250), a second redistribution pattern layer (260), and a second lower dummy pattern layer (270).

[0088] The second lower dummy pattern layer (270) may include a plurality of second dummy metal contacts (271) and a plurality of second dummy metal layers (272) connected to the plurality of second dummy metal contacts (271). The uppermost second dummy metal contact (271) among the plurality of second dummy metal contacts (271) may be connected to the lower surface of the second dummy pattern layer (230).

[0089] In one embodiment, the second dummy metal contact (271) or the second dummy metal layer (272) may comprise substantially the same material as the first dummy metal contact (171) or the first dummy metal layer (172).

[0090] Figure 5 is a drawing showing another example of the cross-sectional structure of the I-I' section of Figure 2.

[0091] Referring to FIG. 5, the first semiconductor device may include a first substrate (101), a first guard ring (110), a first insulating layer (120), a first dummy pattern layer (130), a first passivation layer (140), a first redistribution insulating layer (150), and a first redistribution pattern layer (160).

[0092] One side of the first dummy pattern layer (130) may be located inside the first inner boundary (143). One side of the first dummy pattern layer (130) may be located inside the side of the first passivation layer (140). The other side of the first dummy pattern layer (130) may be located between the first outer boundary (124) and the first inner boundary (143). The other side of the first dummy pattern layer (130) may be located outside the side of the first passivation layer (140).

[0093] The first dummy pattern layer (130) may have a fifth width (W5). In one embodiment, the fifth width (W5) may be larger than the second width (W2).

[0094] Referring again to FIG. 5, the second semiconductor device may include a second substrate (201), a second guard ring (210), a second insulating layer (220), a second dummy pattern layer (230), a second passivation layer (240), a second redistribution insulating layer (250), and a second redistribution pattern layer (260).

[0095] One side of the second dummy pattern layer (230) may be located inside the second inner boundary (243). One side of the second dummy pattern layer (230) may be located inside the side of the second passivation layer (240). The other side of the second dummy pattern layer (230) may be located between the second outer boundary (224) and the second inner boundary (243). The other side of the second dummy pattern layer (230) may be located outside the side of the second passivation layer (240).

[0096] The second dummy pattern layer (230) may have a sixth width (W6). In one embodiment, the sixth width (W6) may be larger than the fourth width (W4).

[0097] Figure 6 is a drawing showing another example of the cross-sectional structure of the I-I' section of Figure 2.

[0098] Referring to FIG. 6, the first semiconductor device may include a first substrate (101), a first guard ring (110), a first insulating layer (120), a first dummy pattern layer (130), a first passivation layer (140), a first redistribution insulating layer (150), and a first redistribution pattern layer (160).

[0099] The first guard ring (110) may include a first upper guard metal layer (113). In one embodiment, the first upper guard metal layer (113) may be connected to one side of the first dummy pattern layer (130).

[0100] Referring again to FIG. 6, the second semiconductor device may include a second substrate (201), a second guard ring (210), a second insulating layer (220), a second dummy pattern layer (230), a second passivation layer (240), a second redistribution insulating layer (250), and a second redistribution pattern layer (260).

[0101] The second guard ring (210) may include a second upper guard metal layer (213). In one embodiment, the second upper guard metal layer (213) may be connected to one side of the first dummy pattern layer (230).

[0102] FIGS. 7 to 12 are drawings illustrating examples of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 3.

[0103] Referring to FIG. 7, a first guard metal contact (111) and a second guard metal contact (211) may be formed on a substrate (10). The first guard metal contact (111) may be located in a first guard ring region (GR1). The second guard metal contact (211) may be located in a second guard ring region (GR2). A first guard metal layer (112) may be formed on the first guard metal contact (111). A second guard metal layer (212) may be formed on the second guard metal contact (211).

[0104] Referring again to FIG. 7, the first guard metal contact (111), the second guard metal contact (211), the first guard metal layer (112), and the second guard metal layer (212) may not be formed in the rewiring alignment key area (AR).

[0105] Referring to FIG. 8, an interlayer insulating layer (21) may be formed on a substrate (10). A lower metal-to-metal insulating layer (22) may be formed on the interlayer insulating layer (21). The lower metal-to-metal insulating layer (22) may include a lower capping layer (23) and a lower metal-to-metal dielectric layer (24).

[0106] A first guard metal contact (111) and a second guard metal contact (211) may be formed by penetrating the lower capping layer (23) and the lower metal dielectric layer (24). A first guard metal layer (112) may be formed on the first guard metal contact (111). A second guard metal layer (212) may be formed on the second guard metal contact (211).

[0107] Referring to FIG. 9, an upper metal-inter-insulating layer (25) may be formed on a lower metal-inter-insulating layer (22). The upper metal-inter-insulating layer (25) may include an upper capping layer (26) and an upper metal-inter-insulating layer (27). That is, an insulating layer (20) may be formed on a substrate (10). The insulating layer (20) may include an interlayer insulating layer (21), a lower metal-inter-insulating layer (22), and an upper metal-inter-insulating layer (25).

[0108] A first guard metal contact (111) and a second guard metal contact (211) can be formed by penetrating the upper capping layer (26) and the upper metal inter-dielectric layer (27).

[0109] Referring to FIG. 10, a first upper guard metal layer (113) may be formed on a first guard metal contact (111). A second upper guard metal layer (213) may be formed on a second guard metal contact (211). A dummy pattern layer (30) may be formed on an insulating layer (20) within a scribe lane area (SR). The dummy pattern layer (30) may include a first dummy pattern layer (130) and a second dummy pattern layer (230). The upper surface of the dummy pattern layer (30) may have a seventh width (W7).

[0110] A passivation layer (40) may be formed on an insulating layer (20). The passivation layer (40) may include a passivation oxide layer (41) and a passivation nitride layer (42).

[0111] Referring to FIG. 11, a redistribution insulation layer (50) may be formed on the passivation layer (40). The redistribution insulation layer (50) may include a first redistribution insulation layer (150) and a second redistribution insulation layer (250).

[0112] A redistribution via region (VR) may be formed by penetrating a portion of the redistribution insulation layer (50) and the passivation layer (40). The redistribution via region (VR) may be formed through anisotropic etching. In one embodiment, the redistribution via region (VR) may be in the shape of a bar, but is not limited thereto. The lower surface of the redistribution via region (VR) may be in contact with a portion of the upper surface of the dummy pattern layer (30). The lower surface of the redistribution via region (VR) may have an eighth width (W8).

[0113] Since the seventh width (W7) on the upper surface of the dummy pattern layer (30) is formed to be larger than the eighth width (W8) on the lower surface of the redistribution via region (VR), the dummy pattern layer (30) can act as a buffer during the etching process. Accordingly, the insulating layer (20) placed below the dummy pattern layer (30) may not be etched. Therefore, by preventing stress from concentrating in the redistribution via region (VR), process defects such as cracks or delamination can be controlled, thereby preventing degradation of device characteristics.

[0114] Referring to FIG. 12, a conductive material (60) may be formed on the upper surface of the dummy pattern layer (30), the side of the passivation layer (40), and a portion of the side and upper surface of the redistribution insulation layer (50). In one embodiment, the conductive material (60) may include aluminum (Al).

[0115] Since the conductive material (60) is bonded to the dummy pattern layer (30), stress concentration in the redistribution via region (VR) is relieved, thereby controlling process defects such as cracks or delamination in the lower part of the redistribution via region (VR) and preventing degradation of device characteristics.

[0116] Referring again to FIG. 3, a portion of the conductive material (60) can be removed through an etching process. Accordingly, a first redistribution pattern layer (160) and a second redistribution pattern layer (260) can be formed. The first redistribution pattern layer (160) can be located on the first dummy pattern layer (130). The second redistribution pattern layer (260) can be located on the second dummy pattern layer (230).

[0117] The distance from the upper surface of the first redistribution insulation layer (150) to the upper surface of the first dummy pattern layer (130) may be greater than the distance from the uppermost surface of the first redistribution pattern layer (160) to the upper surface of the first dummy pattern layer (130). The distance from the upper surface of the second redistribution insulation layer (250) to the upper surface of the second dummy pattern layer (230) may be greater than the distance from the uppermost surface of the second redistribution pattern layer (260) to the second dummy pattern layer (230).

[0118] FIGS. 13 to 16 are drawings illustrating examples of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 4.

[0119] Referring to FIG. 13, a first guard metal contact (111), a second guard metal contact (211), a first dummy metal contact (171), and a second dummy metal contact (271) may be formed on a substrate (10). The first guard metal contact (111) may be located in a first guard ring region (GR1). The second guard metal contact (211) may be located in a second guard ring region (GR2). The first dummy metal contact (171) may be located in a first scribe lane region (SR1). The second dummy metal contact (271) may be located in a second scribe lane region (SR2).

[0120] A first guard metal layer (112) may be formed on a first guard metal contact (111). A second guard metal layer (212) may be formed on a second guard metal contact (211). A first dummy metal layer (172) may be formed on a first dummy metal contact (171). A second dummy metal layer (272) may be formed on a second dummy metal contact (271).

[0121] Referring to FIG. 14, an interlayer insulating layer (21) may be formed on a substrate (10). A lower metal-to-metal insulating layer (22) may be formed on the interlayer insulating layer (21). The lower metal-to-metal insulating layer (22) may include a lower capping layer (23) and a lower metal-to-metal dielectric layer (24).

[0122] A first guard metal contact (111), a second guard metal contact (211), a first dummy metal contact (171), and a second dummy metal contact (271) may be formed by penetrating the lower capping layer (23) and the lower metal inter-dielectric layer (24). A first guard metal layer (112) may be formed on the first guard metal contact (111). A second guard metal layer (212) may be formed on the second guard metal contact (211). A first dummy metal layer (172) may be formed on the first dummy metal contact (171). A second dummy metal layer (272) may be formed on the second dummy metal contact (271).

[0123] Referring to FIG. 15, an upper metal-inter-insulating layer (25) may be formed on a lower metal-inter-insulating layer (22). The upper metal-inter-insulating layer (25) may include an upper capping layer (26) and an upper metal-inter-insulating layer (27). That is, an insulating layer (20) may be formed on a substrate (10). The insulating layer (20) may include an interlayer insulating layer (21), a lower metal-inter-insulating layer (22), and an upper metal-inter-insulating layer (25).

[0124] A first guard metal contact (111), a second guard metal contact (211), a first dummy metal contact (171), and a second dummy metal contact (271) can be formed by penetrating the upper capping layer (26) and the upper metal inter-dielectric layer (27).

[0125] Referring to FIG. 16, a first upper guard metal layer (113) may be formed on a first guard metal contact (111). A second upper guard metal layer (213) may be formed on a second guard metal contact (211). A dummy pattern layer (30) may be formed on an insulating layer (20) within a scribe lane area (SR). The dummy pattern layer (30) may include a first dummy pattern layer (130) and a second dummy pattern layer (230). A first dummy pattern layer (130) may be placed on a first dummy metal contact (171). A second dummy pattern layer (230) may be placed on a second dummy metal contact (271).

[0126] Referring again to FIG. 4 and FIG. 11, a redistribution insulating layer (50) may be formed on the passivation layer (40). The redistribution insulating layer (50) may include a first redistribution insulating layer (150) and a second redistribution insulating layer (250).

[0127] A redistribution via region (VR) may be formed by penetrating a portion of the redistribution insulation layer (50) and the passivation layer (40). The lower surface of the redistribution via region (VR) may come into contact with a portion of the upper surface of the dummy pattern layer (30). The lower surface of the redistribution via region (VR) may have an eighth width (W8).

[0128] Referring again to FIG. 4 and FIG. 12, a conductive material (60) may be formed on the upper surface of the dummy pattern layer (30), the side of the passivation layer (40), and a part of the side and upper surface of the redistribution insulation layer (50).

[0129] Referring again to FIG. 4, a portion of the conductive material (60) can be removed through an etching process. Accordingly, a first redistribution pattern layer (160) and a second redistribution pattern layer (260) can be formed. The first redistribution pattern layer (160) can be located on the first dummy pattern layer (130). The second redistribution pattern layer (260) can be located on the second dummy pattern layer (230).

[0130] FIG. 17 is a diagram showing an example of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 5.

[0131] The semiconductor device illustrated in FIG. 17 can be formed in the same way as the method of manufacturing the semiconductor device described with reference to FIG. 7 to 9.

[0132] Referring to FIG. 17, a first upper guard metal layer (113) may be formed on a first guard metal contact (111). A second upper guard metal layer (213) may be formed on a second guard metal contact (211). A first dummy pattern layer (130) and a second dummy pattern layer (230) may be formed on an insulating layer (20) within a scribe lane area (SR).

[0133] Referring again to FIG. 5 and FIG. 11, a redistribution insulating layer (50) may be formed on the passivation layer (40). The redistribution insulating layer (50) may include a first redistribution insulating layer (150) and a second redistribution insulating layer (250).

[0134] A redistribution via region (VR) may be formed by penetrating a portion of the redistribution insulation layer (50) and the passivation layer (40). The lower surface of the redistribution via region (VR) may come into contact with a portion of the upper surface of the dummy pattern layer (30). The lower surface of the redistribution via region (VR) may have an eighth width (W8).

[0135] Referring again to FIG. 5 and FIG. 12, a conductive material (60) may be formed on the upper surface of the dummy pattern layer (30), on the side and part of the upper surface of the passivation layer (40), and on the side and part of the upper surface of the redistribution insulation layer (50).

[0136] Referring again to FIG. 5, a portion of the conductive material (60) can be removed through an etching process. Accordingly, a first redistribution pattern layer (160) and a second redistribution pattern layer (260) can be formed. The first redistribution pattern layer (160) may be located on a portion of the upper surface of the first dummy pattern layer (130). The second redistribution pattern layer (260) may be located on a portion of the upper surface of the second dummy pattern layer (230).

[0137] FIG. 18 is a diagram showing an example of a method for forming a semiconductor device according to an embodiment disclosed in FIG. 6.

[0138] The semiconductor device illustrated in FIG. 18 can be formed in the same way as the method of manufacturing the semiconductor device described with reference to FIG. 7 to 9.

[0139] Referring to FIG. 18, a first dummy pattern layer (130) and a second dummy pattern layer (230) can be formed on an insulating layer (20) within a scribe lane area (SR).

[0140] A first upper guard metal layer (113) may be formed on the uppermost first guard metal contact (111) among a plurality of first guard metal contacts (111). In one embodiment, the first upper guard metal layer (113) may be connected to one side of the first dummy pattern layer (130).

[0141] A second upper guard metal layer (213) may be formed on the uppermost second guard metal contact (211) among a plurality of second guard metal contacts (211). In one embodiment, the second upper guard metal layer (213) may be connected to one side of the second dummy pattern layer (230).

[0142] Referring again to FIG. 6 and FIG. 11, a redistribution insulating layer (50) may be formed on the passivation layer (40). The redistribution insulating layer (50) may include a first redistribution insulating layer (150) and a second redistribution insulating layer (250).

[0143] A redistribution via region (VR) may be formed by penetrating a portion of the redistribution insulation layer (50) and the passivation layer (40). The lower surface of the redistribution via region (VR) may come into contact with a portion of the upper surface of the dummy pattern layer (30). The lower surface of the redistribution via region (VR) may have an eighth width (W8).

[0144] Referring again to FIG. 6 and FIG. 12, a conductive material (60) may be formed on the upper surface of the dummy pattern layer (30), the side of the passivation layer (40), and a part of the side and upper surface of the redistribution insulation layer (50).

[0145] Referring again to FIG. 6, a portion of the conductive material (60) can be removed through an etching process. Accordingly, a first redistribution pattern layer (160) and a second redistribution pattern layer (260) can be formed. The first redistribution pattern layer (160) may be located on a portion of the upper surface of the first dummy pattern layer (130). The second redistribution pattern layer (260) may be located on a portion of the upper surface of the second dummy pattern layer (230).

[0146] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments.

Claims

Claim 1 A semiconductor device comprising: a substrate; an insulating layer disposed on the substrate and including an outer boundary; a passivation layer disposed on the insulating layer and including an inner boundary located inwardly to the outer boundary; a dummy pattern layer having a lower surface that forms the same plane as the lower surface of the passivation layer and overlaps with at least a portion of the region between the outer boundary and the inner boundary, and having one side located inwardly to the inner boundary; and a redistribution pattern layer disposed on the dummy pattern layer. Claim 2 A semiconductor device according to claim 1, wherein the redistribution pattern layer contacts the upper surface of the dummy pattern layer and the side of the passivation layer between the outer boundary and the inner boundary. Claim 3 A semiconductor device according to claim 2, further comprising a redistribution insulating layer on the passivation layer, wherein the distance from the upper surface of the redistribution insulating layer to the upper surface of the dummy pattern layer is greater than the distance from the uppermost surface of the redistribution pattern layer to the upper surface of the dummy pattern layer. Claim 4 A semiconductor device according to claim 1, wherein the passivation layer comprises a high-density plasma (HDP) oxide, a nitride, or a combination thereof. Claim 5 A semiconductor device according to claim 1, further comprising a dummy metal contact connected to the lower surface of the dummy pattern layer. Claim 6 A semiconductor device according to claim 1, wherein the other side of the dummy pattern layer is located between the outer boundary and the inner boundary. Claim 7 A semiconductor device according to claim 1, further comprising a guard ring disposed on the substrate and located inside the inner boundary. Claim 8 A semiconductor device according to claim 7, wherein the guard ring comprises an upper guard metal layer, and the upper surface of the upper guard metal layer forms a coplanar plane with the upper surface of the dummy pattern layer. Claim 9 In claim 8, the semiconductor device wherein the upper guard metal layer comprises the same material as the dummy pattern layer. Claim 10 In claim 8, the upper guard metal layer is connected to the dummy pattern layer in a semiconductor device. Claim 11 A semiconductor device comprising: a substrate including a chip region and a scribe lane region; an insulating layer disposed on the substrate; a dummy pattern layer disposed on the insulating layer in the scribe lane region; a passivation layer located on the insulating layer, at least a portion of which overlaps the dummy pattern layer; and a redistribution pattern layer disposed overlapping the dummy pattern layer on the outer side of the side of the passivation layer, wherein one side of the dummy pattern layer is located on the inner side of the side of the passivation layer. Claim 12 In claim 11, the semiconductor device wherein the rewiring pattern layer contacts the side of the passivation layer. Claim 13 A semiconductor device according to claim 11, further comprising a redistribution insulating layer on the passivation layer, wherein the distance from the upper surface of the redistribution insulating layer to the upper surface of the dummy pattern layer is greater than the distance from the uppermost surface of the redistribution pattern layer to the upper surface of the dummy pattern layer. Claim 14 In claim 11, the passivation layer comprises a high-density plasma (HDP) oxide, a nitride, or a combination thereof in a semiconductor device. Claim 15 A semiconductor device according to claim 11, further comprising a dummy metal contact connected to the lower surface of the dummy pattern layer. Claim 16 A semiconductor device according to claim 11, wherein the other side of the dummy pattern layer is located outside the side of the passivation layer. Claim 17 A semiconductor device according to claim 11, further comprising a guard ring disposed on the substrate and located on the inner side of the side of the passivation layer. Claim 18 A semiconductor device according to claim 17, wherein the guard ring comprises an upper guard metal layer, and the upper surface of the upper guard metal layer forms a coplanar plane with the upper surface of the dummy pattern layer. Claim 19 In claim 18, the semiconductor device wherein the upper guard metal layer comprises the same material as the dummy pattern layer. Claim 20 A semiconductor device according to claim 18 in which the upper guard metal layer is connected to the dummy pattern layer.

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