Semiconductor devices including multiple dies

Abstract

A semiconductor device comprises: a cell stack comprising a plurality of semiconductor patterns spaced apart in a first horizontal direction and a vertical direction; a plurality of word lines extending in the first horizontal direction surrounding the plurality of semiconductor patterns; a plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; and a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and spaced apart in the vertical direction; a peripheral circuit stack disposed on the cell stack comprising a peripheral circuit board disposed on the upper surface of the cell stack; and a peripheral circuit transistor disposed on the peripheral circuit board; a connection via extending in the vertical direction through the peripheral circuit board; a front pad disposed on the upper surface of the peripheral circuit stack and electrically connected to the connection via; and a rear pad disposed on the bottom surface of the cell stack and electrically connected to the connection via.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device having a stacked structure of a plurality of dies. Background Technology

[0002] To improve the performance and storage capacity of semiconductor devices, semiconductor devices having a structure in which multiple semiconductor dies are stacked are widely used. In order to provide high-capacity semiconductor devices, increased integration density is required. A three-dimensional semiconductor device that increases memory capacity by stacking multiple memory cells vertically on a substrate is being proposed. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a semiconductor device having a structure in which a plurality of semiconductor dies are stacked, including a three-dimensional semiconductor device capable of having increased memory capacity. means of solving the problem

[0004] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a cell stack comprising a plurality of semiconductor patterns spaced apart in a first horizontal direction and a vertical direction; a plurality of word lines extending in the first horizontal direction surrounding the plurality of semiconductor patterns; a plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; and a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and spaced apart in the vertical direction; a peripheral circuit stack disposed on the cell stack comprising a peripheral circuit board disposed on the upper surface of the cell stack; and a peripheral circuit transistor disposed on the peripheral circuit board; a connection via extending in the vertical direction through the peripheral circuit board; a front pad disposed on the upper surface of the peripheral circuit stack and electrically connected to the connection via; and a rear pad disposed on the bottom surface of the cell stack and electrically connected to the connection via.

[0005] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a cell stack comprising a plurality of semiconductor patterns spaced apart in a first horizontal direction and a vertical direction; a plurality of word lines extending in the first horizontal direction surrounding the plurality of semiconductor patterns; a plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and spaced apart in the vertical direction; a cover insulating layer disposed to cover the plurality of word lines; and a bottom insulating layer disposed on the bottom surface of the plurality of word lines; a peripheral circuit stack disposed on the cell stack comprising a peripheral circuit board disposed on the upper surface of the cell stack; and a peripheral circuit transistor disposed on the peripheral circuit board; a connection via extending in the vertical direction through the peripheral circuit board; a front pad disposed on the upper surface of the peripheral circuit stack and electrically connected to the connection via; and a back pad disposed on the bottom surface of the cell stack and disposed on the bottom surface of the bottom insulating layer and electrically connected to the connection via.

[0006] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises a plurality of dies stacked in a vertical direction, wherein each of the plurality of dies comprises: a cell stack comprising a plurality of semiconductor patterns spaced apart in a first horizontal direction and in the vertical direction; a plurality of word lines extending in the first horizontal direction surrounding the plurality of semiconductor patterns; a plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and spaced apart in the vertical direction; a cover insulating layer disposed to cover the plurality of word lines; and a bottom insulating layer disposed on the bottom surface of the plurality of word lines; a peripheral circuit stack disposed on the cell stack comprising a peripheral circuit board disposed on the upper surface of the cell stack; and a peripheral circuit transistor disposed on the peripheral circuit board; a connection via extending in the vertical direction through the peripheral circuit board; and a front pad disposed on the upper surface of the peripheral circuit stack and electrically connected to the connection via. and includes a rear pad disposed on the bottom surface of the cell stack and electrically connected to the connection via.

[0007] A method for manufacturing a semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: providing a peripheral circuit stack including a peripheral circuit board and a peripheral circuit transistor disposed on the peripheral circuit board; forming a cell stack on a cell wafer, wherein the cell stack comprises: a plurality of semiconductor patterns disposed spaced apart in a first horizontal direction and a vertical direction; a plurality of word lines extending in the first horizontal direction surrounding the plurality of semiconductor patterns; a plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; and a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and disposed spaced apart in the vertical direction; bonding the cell stack and the peripheral circuit stack; forming a connection via extending in the vertical direction through the peripheral circuit stack; removing the cell wafer; forming a front pad electrically connected to the connection via on the upper surface of the peripheral circuit stack; and forming a rear pad electrically connected to the connection via on the bottom surface of the cell stack.

[0008] In exemplary embodiments, the cell stack may further include an upper wiring layer electrically connected to the plurality of word lines or the plurality of cell capacitors; and an upper insulating layer covering the upper wiring layer.

[0009] In exemplary embodiments, the step of bonding the cell stack and the peripheral circuit stack may include the step of bonding the cell stack and the peripheral circuit stack such that the bottom surface of the peripheral circuit board contacts the upper insulating layer.

[0010] In exemplary embodiments, the upper wiring layer may include a landing pad wiring layer in contact with the bottom surface of the connection via.

[0011] In exemplary embodiments, prior to the step of forming the connection via, the method may further include the step of forming a connection via hole penetrating a portion of the peripheral circuit board and the upper insulating layer; and the step of forming a connection via insulating layer on the inner wall of the connection via hole.

[0012] In exemplary embodiments, in the step of forming the connection via hole, the upper surface of the landing pad wiring layer may be exposed at the bottom of the connection via hole.

[0013] In exemplary embodiments, the cell stack may further include a cover insulating layer covering the plurality of word lines and the plurality of cell capacitors; and a cell connection via extending in the vertical direction through the cover insulating layer and electrically connected to the landing pad wiring layer.

[0014] In exemplary embodiments, the cell connection via is positioned at a location that vertically overlaps with the landing pad wiring layer, and the connection via may be positioned at a location that vertically overlaps with the landing pad wiring layer.

[0015] In exemplary embodiments, after the step of removing the cell wafer from the cell stack, the method may further include the step of removing a portion of the cover insulating layer from the bottom surface of the cell stack to form a via hole; and the step of forming the cell connection via within the via hole.

[0016] In exemplary embodiments, after the step of removing the cell wafer, the step of bonding the cell stack and the peripheral circuit stack may be performed. Effects of the invention

[0017] According to the technical concept of the present invention, each semiconductor die includes a cell stack and a peripheral circuit stack comprising a three-dimensional semiconductor device, and includes a connection via extending through the peripheral circuit stack, and a plurality of dies can be stacked vertically through a front pad and a rear pad. The semiconductor device can have high integration density while having excellent electrical performance. Brief explanation of the drawing

[0018] FIG. 1 is a schematic diagram showing a semiconductor device according to exemplary embodiments. Figure 2 is a cross-sectional view of the AA' portion of Figure 1. Figure 3 is a circuit diagram showing a memory cell array included within the cell stack of Figure 1. Figure 4 is a perspective view showing the schematic configuration of the memory cell array of Figure 3. Figure 5 is a cross-sectional view of the B1-B1' section of Figure 4. Figure 6 is a cross-sectional view of the B2-B2' section of Figure 4. FIG. 7 is a cross-sectional view showing a semiconductor device according to exemplary embodiments. FIG. 8 is a cross-sectional view showing a semiconductor device according to exemplary embodiments. FIG. 9 is a cross-sectional view showing a semiconductor device according to exemplary embodiments. FIG. 10 is a schematic diagram showing a semiconductor device according to exemplary embodiments. FIGS. 11a to 11h are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 12a to 12f are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 13a to 13f are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 14a to 14e are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0019] FIG. 1 is a schematic diagram showing a semiconductor device (100) according to exemplary embodiments. FIG. 2 is a cross-sectional view of the AA' portion of FIG. 1. FIG. 3 is a circuit diagram showing a memory cell array (MCA) included in the cell stack of FIG. 1. FIG. 4 is a perspective view showing the schematic configuration of the memory cell array of FIG. 3. FIG. 5 is a cross-sectional view of the B1-B1' portion of FIG. 4. FIG. 6 is a cross-sectional view of the B2-B2' portion of FIG. 4.

[0020] Referring to FIGS. 1 to 6, the semiconductor device (100) may include a cell stack (CS) and a peripheral circuit stack (PS) on the cell stack (CS). The semiconductor device (100) may be a semiconductor device with a POC (periphery over cell) structure in that the peripheral circuit stack (PS) is disposed on the cell stack (CS).

[0021] In exemplary embodiments, the cell stack (CS) may be a memory cell region of a DRAM device. In exemplary embodiments, the cell stack (CS) may include a plurality of memory cells stacked in the vertical direction (Z). Each memory cell may include a cell transistor (CTR) and a cell capacitor (CAP), and the cell transistor (CTR) and the cell capacitor (CAP) may be arranged in the horizontal direction. The cell stack (CS) may include a DRAM device with a 1T-1C (1 transistor - 1 capacitor) structure in which one cell transistor (CTR) is electrically connected to one cell capacitor (CAP).

[0022] In exemplary embodiments, the peripheral circuit stack (PS) may be a core region or a peripheral circuit region of a DRAM device. The peripheral circuit stack (PS) may include a cell transistor (CTR) and a peripheral circuit transistor (PTR) for delivering signals and / or power to a cell capacitor (CAP) included in the cell stack (CS). In exemplary embodiments, the peripheral circuit transistor (PTR) may include various circuits such as a command decoder, control logic, address buffer, row decoder, column decoder, sense amplifier, and data input / output circuit.

[0023] In exemplary embodiments, the peripheral circuit stack (PS) can be attached to the cell stack (CS) by a bonding method. In exemplary embodiments, the peripheral circuit stack (PS) can be attached to the cell stack (CS) by an oxide bonding method.

[0024] In exemplary embodiments, the semiconductor device (100) may include a cell region (CELL) and a connection region (CON). The cell region (CELL) may be a region where a cell transistor (CTR), a cell capacitor (CAP), and a peripheral circuit transistor (PTR) are placed, and the connection region (CON) may be a region where a connection via (TV), a back pad (PAD1), and a front pad (PAD2) are placed.

[0025] In exemplary embodiments, a connection via (TV) placed in a connection area (CON) may extend in the vertical direction (Z) through at least a portion of the peripheral circuit stack (PS). A rear pad (PAD1) may be placed on the bottom surface of a cell stack (CS) and may be electrically connected to a connection via (TV) through a cell connection via (CTV). A front pad (PAD2) may be placed on the top surface of a peripheral circuit stack (PS) and may be electrically connected to a connection via (TV).

[0026] In exemplary embodiments, the cell stack (CS) has a first surface (CSa) which is a rear surface and a second surface (CSb) which is a front surface, and the peripheral circuit stack (PS) has a first surface (PSa) which is a rear surface and a second surface (PSb) which is a front surface, and the first surface (PSa) of the peripheral circuit stack (PS) may be disposed on the second surface (CSb) of the cell stack (CS). This structure may be referred to as a structure in which the front surface (e.g., the second surface (CSb)) of the cell stack (CS) and the rear surface (e.g., the first surface (PSs)) of the peripheral circuit stack (PS) are bonded.

[0027] Here, the front side of the cell stack (CS) may refer to the upper surface of the cell stack (CS) formed on the cell wafer during the process of forming the cell stack (CS), and the rear side of the cell stack (CS) may refer to the bottom surface of the cell stack (CS) that contacts the cell wafer during the process of forming the cell stack (CS). Additionally, the rear side of the peripheral circuit stack (PS) may refer to the bottom surface of the peripheral circuit board (160), and the front side of the peripheral circuit stack (PS) may refer to the upper surface of the peripheral circuit stack (PS) positioned opposite to the bottom surface of the peripheral circuit board (160).

[0028] In exemplary embodiments, the cell stack (CS) may include a memory cell array (MCA) illustrated in FIGS. 3 through 6. The memory cell array (MCA) may include a plurality of sub-cell arrays (SCA). The plurality of sub-cell arrays (SCA) may be spaced apart along a second horizontal direction (Y).

[0029] A sub-cell array (SCA) may include a plurality of bit lines (BL), a plurality of word lines (WL), and a plurality of memory cells (MC). Each of the plurality of memory cells (MC) may include a cell transistor (TR) and a cell capacitor (CAP) connected thereto. Each of the plurality of memory cells (MC) may have a 1 transistor-1 capacitor (1T1C) structure.

[0030] Multiple word lines (WL) may be extended along the second horizontal direction (Y) and spaced apart from each other along the first horizontal direction (X) and the vertical direction (Z). Multiple bit lines (BL) may be extended along the vertical direction (Z) and spaced apart from each other along the first horizontal direction (X) and the second horizontal direction (Y), respectively. A cell transistor (TR) may be placed between one word line (WL) and one bit line (BL).

[0031] The gate of the cell transistor (TR) can be connected to the word line (WL), and the source of the cell transistor (TR) can be connected to the bit line (BL) through the first contact (DC). The cell transistor (TR) can be connected to the cell capacitor (CAP) through the second contact (BC). The drain of the cell transistor (TR) is connected to the first electrode of the cell capacitor (CAP) through the second contact (BC), and the second electrode of the cell capacitor (CAP) can be connected to the plate electrode (PP).

[0032] Within a single sub-cell array (SCA), multiple cell transistors (TR) may be positioned so as to overlap each other in the vertical direction (Z). Within a single sub-cell array (SCA), multiple cell capacitors (CAP) may be positioned so as to overlap each other in the vertical direction (Z). A single cell transistor (TR) and a single cell capacitor (CAP) may be positioned side by side at the same vertical level, and multiple memory cells (MC) composed of a single cell transistor (TR) and a single cell capacitor (CAP) may be stacked in the vertical direction (Z). The storage capacity of the sub-cell array (SCA) may vary depending on the number of memory cells (MC) or layers (e.g., the number or layers of cell capacitors (CAP)) stacked in the vertical direction (Z).

[0033] As illustrated in FIG. 4, a plurality of semiconductor patterns (AP) may be extended along a first horizontal direction (X) and spaced apart in a second horizontal direction (Y) and a vertical direction (Z). In exemplary embodiments, the plurality of semiconductor patterns (AP) may be made of, for example, an undoped semiconductor material or a doped semiconductor material. In some embodiments, the plurality of semiconductor patterns (AP) may be made of polysilicon. In some embodiments, the plurality of semiconductor patterns (AP) may include amorphous metal oxides, polycrystalline metal oxides, or combinations of amorphous metal oxides and polycrystalline metal oxides, and may include, for example, at least one of an In-Ga oxide (IGO), an In-Zn oxide (IZO), or an In-Ga-Zn oxide (IGZO). In other embodiments, the plurality of semiconductor patterns (AP) may include 2D material semiconductors, for example, said 2D material semiconductors may include MoS2, WSe2, graphene, carbon nanotubes, or a combination thereof.

[0034] A plurality of word lines (WL) are spaced apart in the vertical direction (Z) and can be placed on the upper surface, bottom surface, and side wall of each of the plurality of semiconductor patterns (AP) and extended in the second horizontal direction (Y). One of the word lines (WL) can surround the plurality of semiconductor patterns (AP) spaced apart along the second horizontal direction (Y) and extend in the second horizontal direction (Y). Two of the word lines (WL) that are spaced apart from each other in the vertical direction (Z) can be placed at a position where they overlap each other in the vertical direction (Z). As the plurality of word lines (WL) are arranged in a manner that surrounds the upper surface, bottom surface, and side wall of the semiconductor pattern (AP), the semiconductor device (100) can be referred to as a gate all around type device. In exemplary embodiments, a plurality of word lines (WL) may include at least one of Ti, TiN, TiAlC, TiAlN, TiSiN, Mo, MoN, MoSiN, W, WN, WSiN, Ta, TaN, TaSiN, and LaN.

[0035] In exemplary embodiments, a gate insulating layer (GI) may be interposed between a word line (WL) and a semiconductor pattern (AP). The gate insulating layer (GI) may be composed of at least one selected from a high-k dielectric material and a ferroelectric material having a dielectric constant higher than that of silicon oxide. In exemplary embodiments, the gate insulating layer (GI) is among hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanium oxide (PbZrTiO), strontium tantalum bismuth oxide (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). It consists of at least one selected material.

[0036] A first end of a plurality of semiconductor patterns (AP) may be connected to a plurality of bit lines (BL). The plurality of bit lines (BL) may be extended in a vertical direction (Z) and spaced apart in a second horizontal direction (Y). The plurality of bit lines (BL) may be any one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0037] In exemplary embodiments, the cell capacitor (CAP) may include a first electrode (EL1), a capacitor dielectric layer (DL), and a second electrode (EL2). The cell capacitor (CAP) may be a metal-insulator-metal (MIM) type capacitor.

[0038] In exemplary embodiments, the first electrode (EL1) may be connected to and disposed at the second end of the semiconductor pattern (AP), and the first electrode (EL1) may have a bar shape or a pillar shape extending in the first horizontal direction (X). In other embodiments, the first electrode (EL1) may have a cup shape rotated 90 degrees. In exemplary embodiments, a plurality of first electrodes (EL1) may be disposed in a position where they overlap each other in the vertical direction (Z).

[0039] In exemplary embodiments, the capacitor dielectric layer (DL) may be disposed on the first electrode (EL1) and may be conformally disposed, for example, on the top surface, bottom surface, and side wall of the first electrode (EL1).

[0040] In exemplary embodiments, the second electrode (EL2) may be disposed on the capacitor dielectric layer (DL) and may be conformally disposed on the top surface, bottom surface, and side wall of the capacitor dielectric layer (DL). For example, the capacitor dielectric layer (DL) may be interposed between the first electrode (EL1) and the second electrode (EL2).

[0041] In exemplary embodiments, the first electrode (EL1) and the second electrode (EL2) may comprise a doped semiconductor material, a conductive metal nitride such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, a metal such as ruthenium, iridium, titanium or tantalum, or a conductive metal oxide such as iridium oxide or niobium oxide. In exemplary embodiments, the capacitor dielectric layer (DL) may be composed of at least one selected from a high-k dielectric material and a ferroelectric material having a dielectric constant higher than that of silicon oxide. In some embodiments, the capacitor dielectric layer (DL) is hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), nib zirconium titanium oxide (PbZrTiO), strontium tantalum bismuth oxide (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). It is composed of at least one material selected from among.

[0042] A plate electrode (PP) may be disposed on one side of a cell capacitor (CAP) extending in a vertical direction (Z) and a second horizontal direction (Y). The second electrode (EL2) of the cell capacitor (CAP) may be electrically connected to the plate electrode (PP).

[0043] In other embodiments, memory components such as a variable resistor memory element, a phase change memory element, or a magnetic memory element may be placed instead of a cell capacitor (CAP).

[0044] In exemplary embodiments, the cell stack (CS) may further include a plurality of word line pad portions (WLP), and each of the plurality of word line pad portions (WLP) may be connected to a plurality of word lines (WL). The plurality of word line pad portions (WLP) may have different lengths in the horizontal direction, and accordingly, the plurality of word line pad portions (WLP) may have a stepped shape.

[0045] In exemplary embodiments, an insulating layer (120) may be disposed on the upper and lower surfaces of a plurality of word lines (WL) and on the upper surface of a plurality of word line pad portions (WLP). In exemplary embodiments, the insulating layer (120) may be disposed to cover the entire memory cell (MC) and may be disposed to electrically isolate some components of each memory cell (MC) from other components.

[0046] In exemplary embodiments, the insulating layer (120) may include a bottom insulating layer (122), a cover insulating layer (124), and an upper insulating layer (126). In exemplary embodiments, the bottom insulating layer (122) may be placed on the bottom surface of the lowest word line (WL), the cover insulating layer (124) may be placed between a plurality of word lines (WL) and on the upper surface of a plurality of word line pad portions (WLP), and the upper insulating layer (126) may be formed on the cover insulating layer (124).

[0047] In FIG. 2, the insulating layer (120) is shown to include a bottom insulating layer (122), a cover insulating layer (124), and an upper insulating layer (126), but the detailed structure of the insulating layer (120) may vary depending on the manufacturing process of the memory cell (MC). For example, the insulating layer (120) may be formed as a stacked structure of a plurality of insulating layers, and the boundaries between some insulating layers may be clearly identifiable or may not be identifiable.

[0048] The cell stack (CS) may further include an upper wiring layer (130) surrounded by an insulating layer (120). The upper wiring layer (130) may be electrically connected to components constituting the memory cell (MC) of the cell stack (CS), such as a bit line (BL), a word line (WL), or a cell capacitor (CAP). In exemplary embodiments, the upper wiring layer (130) may be placed on the upper surface of a cover insulating layer (124), and an upper insulating layer (126) may be placed on the upper wiring layer (130). In exemplary embodiments, the upper wiring layer (130) may be formed as a stacked structure of two or more metal wiring layers having different vertical levels from each other, and may be formed as a stacked structure of a plurality of insulating layers such that the upper insulating layer (126) covers two or more metal wiring layers.

[0049] In exemplary embodiments, a portion of the upper wiring layer (130) may be electrically connected to the word line pad portion (WLP) through a word line contact (WLC). The word line contact (WLC) may extend in the vertical direction (Z) through the cover insulation layer (124), and the sidewalls of the word line contact (WLC) may be surrounded by the cover insulation layer (124). The word line contact (WLC) may have a length that varies according to the vertical level of the corresponding word line pad portion (WLP). In some embodiments, the word line contact (WLC) may have a width at the top surface that is greater than the width at the bottom surface, and may have a width that gradually decreases in the direction from the top surface of the word line contact (WLC) toward the bottom surface, but the technical concept of the present invention is not limited thereto.

[0050] The upper wiring layer (130) may further include a landing pad wiring layer (132) disposed in a connection area (CON). In some embodiments, a connection via (TV) may be placed on the upper surface of the landing pad wiring layer (132), and the upper surface of the landing pad wiring layer (132) and the bottom surface of the connection via (TV) may be in contact.

[0051] In exemplary embodiments, the peripheral circuit stack (PS) may include a peripheral circuit board (160) and a peripheral circuit transistor (PTR) disposed on the peripheral circuit board (160).

[0052] In exemplary embodiments, the peripheral circuit board (160) may be positioned at a vertical level higher than the cell stack (CS). In exemplary embodiments, the peripheral circuit board (160) may be positioned on the upper surface of the cell stack (CS), for example, on the upper surface of the upper insulating layer (126). In exemplary embodiments, the bottom surface of the peripheral circuit board (160) may be in contact with the upper surface of the upper insulating layer (126).

[0053] In exemplary embodiments, the peripheral circuit board (160) may comprise silicon, for example, single-crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the peripheral circuit board (160) may comprise at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP.

[0054] A peripheral circuit transistor (PTR) may be disposed on the upper surface of the peripheral circuit board (160). The peripheral circuit transistor (PTR) may include at least one of a planar transistor, a FinFET transistor, a multi-bridge channel transistor, and a buried channel array transistor.

[0055] A peripheral circuit transistor (PTR) and wiring patterns (WP1, WP2) electrically connected to the peripheral circuit board (160) may be disposed on the upper surface of the peripheral circuit board (160), and a wiring insulating layer (170) covering the peripheral circuit transistor (PTR) and wiring patterns (WP1, WP2) may be disposed on the upper surface of the peripheral circuit board (160).

[0056] In exemplary embodiments, the via hole (160H) may be positioned to penetrate the surrounding circuit board (160), and a via insulating layer (162) may be positioned within the via hole (160H). A through-via contact (180) may be extended in the vertical direction (Z) through the via insulating layer (162), and wiring patterns (WP1, WP2) may be electrically connected to the upper wiring layer (130) by the through-via contact (180).

[0057] In exemplary embodiments, the through-via contact (180) may have a width on the upper surface that is greater than the width on the lower surface. For example, the through-via contact (180) may have a horizontal width that gradually decreases from the upper surface of the through-via contact (180) toward the lower surface, but the technical concept of the present invention is not limited thereto.

[0058] The through-via contact (180) can function as an electrical connection member for electrically connecting a peripheral circuit transistor (PTR) placed on the upper surface of a peripheral circuit board (160) to a memory cell (MC) placed within a cell stack (CS). For example, through the through-via contact (180), the peripheral circuit transistor (PTR) placed on the upper surface of the peripheral circuit board (160) can be electrically connected to a bit line (BL), word line (WL), or plate electrode (PP) of the memory cell (MC), and can provide power and electrical signals for driving the memory cell (MC).

[0059] A connection via (TV) may be disposed in a connection area (CON) of a semiconductor device (100), and the connection via (TV) may extend in a vertical direction (Z) through at least a portion of a peripheral circuit stack (PS). In exemplary embodiments, a connection via hole (TVH) may extend in a vertical direction (Z) through a peripheral circuit board (160) and a first insulating layer (172), and the bottom portion of the connection via hole (TVH) may extend into the upper insulating layer (126) of a cell stack (CS). The upper surface of a landing pad wiring layer (132) may be exposed at the bottom portion of the connection via hole (TVH).

[0060] A connection via insulating layer (TVI) may be conformally disposed on the inner wall of a connection via hole (TVH), and a connection via (TV) that fills the interior of the connection via hole (TVH) may be disposed on the connection via insulating layer (TVI). A portion of the connection via insulating layer (TVI) may be disposed between the connection via (TV) and the peripheral circuit board (160) so that the connection via (TV) can be electrically insulated from the peripheral circuit board (160).

[0061] In exemplary embodiments, the connection via (TV) may comprise a combination of copper, copper alloy, titanium, silver, platinum, etc. In exemplary embodiments, the connection via insulating layer (TVI) may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0062] In exemplary embodiments, a connection via (TV) can be formed by attaching a peripheral circuit stack (PS) to a cell stack (CS), forming a connection via hole (TVH) that penetrates the peripheral circuit stack (PS), and then filling the connection via hole (TVH) with a metallic material.

[0063] In some embodiments, the width of the connection via (TV) on the top surface may be greater than the width on the bottom surface. The width of the connection via (TV) may gradually decrease in the direction from the top surface toward the bottom surface.

[0064] In some embodiments, the connection via (TV) may have an upper surface positioned at the same level as the upper surface of the first insulating layer (172). The bottom portion of the connection via (TV) may be covered by the upper insulating layer (126), and in some embodiments, a connection via insulating layer (TVI) may be interposed between the bottom portion of the connection via (TV) and the upper insulating layer (126). The bottom surface of the connection via (TV) may be positioned at a vertical level lower than the bottom surface of the peripheral circuit stack (PS), and the bottom surface of the connection via (TV) may be in contact with the upper surface of the landing pad wiring layer (132) in the cell stack (CS).

[0065] In some embodiments, a second wiring pattern (WP2) is disposed on the upper surface of a connection via (TV), and a second insulating layer (174) may be disposed on the upper surface of the second wiring pattern (WP2). A front pad (PAD2) may be disposed on the second insulating layer (174), and the front pad (PAD2) may be electrically connected to the connection via (TV) through the second wiring pattern (WP2).

[0066] In other embodiments, the second wiring pattern between the upper surface of the connection via (TV) and the front pad (PAD2) may be omitted, and the upper surface of the connection via (TV) may come into direct contact with the front pad (PAD2).

[0067] The cell stack (CS) may further include a cell connection via (CTV) electrically connected to the landing pad wiring layer (132). The cell connection via (CTV) may extend in the vertical direction (Z) through the cover insulation layer (124) at a position that vertically overlaps the landing pad wiring layer (132), and the upper surface of the cell connection via (CTV) may come into contact with the landing pad wiring layer (132). The lower surface of the cell connection via (CTV) may extend through the bottom insulation layer (122) and come into contact with the rear pad (PAD1).

[0068] In some embodiments, the width of the cell connection via (CTV) at the top surface may be greater than the width at the bottom surface. The width of the cell connection via (CTV) may gradually decrease in the direction from the top surface toward the bottom surface.

[0069] In some embodiments, as shown in FIG. 4, a plurality of cell connection vias (CTVs) may be arranged to correspond to one landing pad wiring layer (132) or one rear pad (PAD1). A plurality of cell connection vias (CTVs) may be electrically connected in common to one rear pad (PAD1). However, the technical concept of the present invention is not limited thereto, and a cell connection via (CTV) may be arranged to correspond to one rear pad (PAD1).

[0070] In exemplary embodiments, cell connection vias (CTVs) may be formed together in at least a portion of the etching process and the metal layer filling process for forming word line contacts (WLCs). In exemplary embodiments, a portion of the cover insulating layer (124) may be removed to form a contact hole (WLCH) and a via hole (CTVH), and a word line contact (WLC) and a cell connection via (CTV) may be formed using a conductive material within the contact hole (WLCH) and the via hole (CTVH), respectively. However, the method of manufacturing the cell connection vias (CTVs) is not limited to the description above.

[0071] In exemplary embodiments, the word line contact (WLC) and cell connection via (CTV) may comprise tungsten, tungsten nitride, titanium, titanium nitride, ruthenium, cobalt, cobalt nitride, molybdenum, molybdenum nitride, or a combination thereof.

[0072] According to exemplary embodiments, the semiconductor device (100) includes a cell stack (CS) comprising a three-dimensional semiconductor device and a peripheral circuit stack (PS) disposed on the cell stack (CS), and includes a connection via (TV) extending through the peripheral circuit stack (PS), and a rear pad (PAD1) and a front pad (PAD2) may be electrically connected to the connection via (TV). The semiconductor device (100) may have high integration density while having excellent electrical performance.

[0073] FIG. 7 is a cross-sectional view showing a semiconductor device (100A) according to exemplary embodiments.

[0074] Referring to FIG. 7, the upper wiring layer (130) may include a first landing pad wiring layer (132_1) and a second landing pad wiring layer (132_2). The second landing pad wiring layer (132_2) may be electrically connected to the first landing pad wiring layer (132_1) at a vertical level higher than the first landing pad wiring layer (132_1).

[0075] In exemplary embodiments, the first landing pad wiring layer (132_1) may have a bottom surface in contact with the top surface of the cell connection via (CTV), and the second landing pad wiring layer (132_2) may have a top surface in contact with the bottom surface of the connection via (TV).

[0076] In exemplary embodiments, the cell connection via (CTV) may have a width at the top surface that is smaller than the width at the bottom surface, and, for example, may have a width that gradually increases in the direction from the top surface of the cell connection via (CTV) toward the bottom surface.

[0077] In exemplary embodiments, a cell connection via (CTV) can be formed by removing a portion of the bottom insulating layer (122) and a portion of the cover insulating layer (124) from the bottom surface (first surface (CSa)) of the cell stack (CS) to form a via hole (CTVH), and filling the via hole (CTVH) with a conductive material. In the etching process for forming the via hole (CTVH), the bottom surface of the first landing pad wiring layer (132_1) may be exposed at the end of the via hole (CTVH), and the cell connection via (CTV) may have an end that contacts the bottom surface of the first landing pad wiring layer (132_1).

[0078] In exemplary embodiments, the cell connection via (CTV) may comprise a combination of copper, copper alloy, titanium, silver, platinum, etc. In some embodiments, the cell connection via (CTV) may comprise tungsten, tungsten nitride, titanium, titanium nitride, ruthenium, cobalt, cobalt nitride, molybdenum, molybdenum nitride, or a combination thereof.

[0079] In exemplary embodiments, cell connection vias (CTVs) may be arranged so that one cell connection via (CTV) corresponds to one back pad (PAD1). In other embodiments, a plurality of cell connection vias (CTVs) may be arranged so that one landing pad wiring layer (132) or one back pad (PAD1) corresponds to one, and the plurality of cell connection vias (CTVs) may be electrically connected in common to one back pad (PAD1).

[0080] FIG. 8 is a cross-sectional view showing a semiconductor device (100B) according to exemplary embodiments.

[0081] Referring to FIG. 8, the semiconductor device (100B) may include a cell stack (CS) and a peripheral circuit stack (PS) on the cell stack (CS). The cell stack (CS) has a first surface (CSa) which is a rear surface and a second surface (CSb) which is a front surface, and the peripheral circuit stack (PS) has a first surface (PSa) which is a rear surface and a second surface (PSb) which is a front surface, and the second surface (PSb) of the peripheral circuit stack (PS) may be disposed on the second surface (CSb) of the cell stack (CS). This structure may be referred to as a structure in which the front surface of the cell stack (CS) (e.g., the second surface (CSb)) and the front surface of the peripheral circuit stack (PS) (e.g., the second surface (PSb)) are bonded.

[0082] Here, the front or second surface (CSb) of the cell stack (CS) may refer to the upper surface of the cell stack (CS) formed on the cell wafer during the process of forming the cell stack (CS). Here, the front or second surface (CSb) of the cell stack (CS) may include the upper surface of the upper insulating layer (126). The rear or first surface (CSa) of the cell stack (CS) may refer to the bottom surface of the cell stack (CS) that contacts the cell wafer during the process of forming the cell stack (CS). Here, the rear or first surface (CSa) of the cell stack (CS) may refer to the bottom surface of the bottom insulating layer (122).

[0083] Here, when a peripheral circuit transistor (PTR) is placed on a second surface of a peripheral circuit board (160) and the first surface of the peripheral circuit board (160) is a surface opposite to the second surface, the rear surface or first surface (PSa) of the peripheral circuit stack (PS) may refer to the first surface of the peripheral circuit board (160) (e.g., the top surface of the peripheral circuit board (160) shown in FIG. 8). The front surface or second surface (PSb) of the peripheral circuit stack (PS) may refer to the surface of the peripheral circuit stack (PS) placed opposite to the first surface of the peripheral circuit board (160) (e.g., the bottom surface of the peripheral circuit stack (PS) shown in FIG. 8).

[0084] In exemplary embodiments, the peripheral circuit stack (PS) may include a wiring insulation layer (170) covering a peripheral circuit transistor (PTR) and a wiring pattern (WP), and the wiring insulation layer (170) may include a first insulation layer (172) positioned close to a peripheral circuit board (160) and a second insulation layer (174) in which the first insulation layer (172) is positioned between the peripheral circuit board (160) and the second insulation layer (174).

[0085] In exemplary embodiments, a connection via (TV) may be disposed within a connection via hole (TVH) that extends in the vertical direction (Z) through the first insulating layer (172) and the peripheral circuit board (160). A connection via insulating layer (TVI) may be disposed on the sidewall of the connection via (TV) within the connection via hole (TVH). A portion of the connection via insulating layer (TVI) may be disposed between the connection via (TV) and the peripheral circuit board (160) so that the connection via (TV) may be electrically insulated from the peripheral circuit board (160).

[0086] In exemplary embodiments, the width of the connection via (TV) on the top surface may be smaller than the width on the bottom surface. The width of the connection via (TV) may gradually increase in the direction from the top surface of the connection via (TV) toward the bottom surface.

[0087] In exemplary embodiments, the cell stack (CS) and the peripheral circuit stack (PS) may be attached to each other by a metal-oxide hybrid bonding method. In exemplary embodiments, a bonding pad (BP) may be provided at the interface between the cell stack (CS) and the peripheral circuit stack (PS). The first bonding pad (BP) may be placed within the cell stack (CS) and may have an upper surface that is placed at the same level as the upper surface of the upper insulating layer (126) included in the cell stack (CS). The second bonding pad (BP) may be placed within the peripheral circuit stack (PS) and may have a bottom surface that is placed at the same level as the bottom surface of the second insulating layer (174) included in the peripheral circuit stack (PS).

[0088] In exemplary embodiments, the upper surface of the first bonding pad (BP1) and the lower surface of the second bonding pad (BP2) may be in contact, and the contact interface between the upper surface of the first bonding pad (BP1) and the lower surface of the second bonding pad (BP2) may be positioned in substantially the same plane as the contact interface between the upper surface of the upper insulating layer (126) and the lower surface of the second insulating layer (174) (in other words, positioned in substantially the same vertical level and connected continuously).

[0089] In exemplary embodiments, the cell connection via (CTV) may extend in the vertical direction (Z) through the cover insulation layer (124) at a position that overlaps vertically with the landing pad wiring layer (132), and the upper surface of the cell connection via (CTV) may be in contact with the landing pad wiring layer (132). The lower surface of the cell connection via (CTV) may be extended through the bottom insulation layer (122) and may be in contact with the rear pad (PAD1).

[0090] In some embodiments, the width of the cell connection via (CTV) at the top surface may be greater than the width at the bottom surface. The width of the cell connection via (CTV) may gradually decrease in the direction from the top surface toward the bottom surface.

[0091] In some embodiments, as shown in FIG. 8, a plurality of cell connection vias (CTVs) may be arranged to correspond to one landing pad wiring layer (132) or one back pad (PAD1). A plurality of cell connection vias (CTVs) may be electrically connected in common to one back pad (PAD1). However, the technical concept of the present invention is not limited thereto, and a cell connection via (CTV) may be arranged to correspond to one back pad (PAD1).

[0092] FIG. 9 is a cross-sectional view showing a semiconductor device (100C) according to exemplary embodiments.

[0093] Referring to FIG. 9, the semiconductor device (100C) may have a structure in which the front surface of a cell stack (CS) (e.g., a second surface (CSb)) and the front surface of a peripheral circuit stack (PS) (e.g., a second surface (PSb)) are bonded. In exemplary embodiments, a bonding pad (BP) is provided at the interface between the cell stack (CS) and the peripheral circuit stack (PS), and the cell stack (CS) and the peripheral circuit stack (PS) may be attached to each other by a metal-oxide hybrid bonding method.

[0094] In exemplary embodiments, the via hole (160H) may be positioned to penetrate the surrounding circuit board (160), and a via insulating layer (162) may be positioned within the via hole (160H). The via insulating layer (162) may function as an etching stopper in a grinding process to reduce the thickness of the surrounding circuit board (160), thereby making it possible for the surrounding circuit board (160) to be ground down to a relatively small thickness.

[0095] In exemplary embodiments, the width of the connection via (TV) on the top surface may be greater than the width on the bottom surface. In the direction from the top surface of the connection via (TV) toward the bottom surface, the width of the connection via (TV) may gradually decrease.

[0096] In exemplary embodiments, some of the wiring patterns (WP2) may be referred to as landing pad wiring patterns (WP_L). For example, the bottom surface of a connection via (TV) may be placed on the top surface of the landing pad wiring pattern (WP_L) and may come into contact with the top surface of the landing pad wiring pattern (WP_L). In exemplary embodiments, in a process of removing a portion of the peripheral circuit board (160) and a portion of the first insulating layer (126) to form a connection via hole (TVH) extending in the vertical direction (Z), the landing pad wiring pattern (WP_L) may be used as an etch stop layer.

[0097] In some embodiments, the connection via (TV) may have a top surface positioned at the same level as the top surface of the peripheral circuit board (160). The bottom surface of the connection via (TV) may be positioned at the same level as the bottom surface of the first insulating layer (172).

[0098] FIG. 10 is a schematic diagram showing a semiconductor device (1) according to exemplary embodiments.

[0099] Referring to FIG. 10, the semiconductor device (1) may include a plurality of semiconductor dies (10) stacked in a vertical direction (Z). Each of the plurality of semiconductor dies (10) may be positioned so as to overlap each other in the vertical direction (Z), and each of the plurality of semiconductor dies (10) may be electrically connected to each other.

[0100] In exemplary embodiments, a plurality of semiconductor dies (10) may include memory chips and, for example, DRAM devices. In exemplary embodiments, a plurality of semiconductor dies (10) may be high bandwidth memory devices. In exemplary embodiments, a plurality of semiconductor dies (10) may not be placed on a buffer die, and the semiconductor device (1) may be a bufferless semiconductor device.

[0101] In other exemplary embodiments, a plurality of semiconductor dies (10) may be attached to a buffer die, and the buffer die may include a logic chip. In exemplary embodiments, a plurality of semiconductor dies (10) may be attached to a portion of an interposer, and a logic chip may be mounted on another portion of the interposer.

[0102] In exemplary embodiments, the number of multiple semiconductor dies (10) stacked in the vertical direction (Z) is not limited to the number exemplarily shown in FIG. 10. For example, the number of multiple semiconductor dies (10) may be 2 to 5, or 7 to 100. In exemplary embodiments, each semiconductor die (10) may include at least one of the semiconductor devices (100, 100A, 100B, 100C) described with reference to FIG. 1 to 9.

[0103] In exemplary embodiments, each of the plurality of semiconductor dies (10) may be attached or bonded to one another by a metal-oxide hybrid bonding method. In exemplary embodiments, a front pad (14P) included in one semiconductor die (10) may be in contact with a rear pad (16P) included in another semiconductor die (10) placed directly above the one semiconductor die (10), and a front insulating layer (14I) included in one semiconductor die (10) may be in contact with a rear insulating layer (16I) included in another semiconductor die (10) placed directly above the one semiconductor die (10).

[0104] In exemplary embodiments, a plurality of semiconductor dies (10) may include a first die (C1), a second die (C2), a third die (C3), a fourth die (C4), a fifth die (C5), and a sixth die (C6) stacked in a vertical direction (Z). In exemplary embodiments, a front pad (14P) included in the first die (C1) may contact a rear pad (16P) included in the second die (C2), and a front insulating layer (14I) included in the first die (C1) may contact a rear insulating layer (16I) included in the second die (C2). Additionally, a front pad (14P) included in the second die (C2) may contact a rear pad (16P) included in the third die (C3), and a front insulating layer (14I) included in the second die (C2) may contact a rear insulating layer (16I) included in the third die (C3). In this way, a plurality of semiconductor dies (10) can be stacked in the vertical direction (Z) by a metal-oxide hybrid bonding method.

[0105] In exemplary embodiments, a front pad (14P) included in one semiconductor die (10) may correspond to a front pad (PAD2) included in a semiconductor device (100, 100A, 100B, 100C) described with reference to FIGS. 1 through 9, and a rear pad (16P) included in one semiconductor die (10) may correspond to a rear pad (PAD1) included in a semiconductor device (100, 100A, 100B, 100C) described with reference to FIGS. 1 through 9. The front pad (14P) and the rear pad (16P) included in one semiconductor die (10) may be electrically connected by a connection via (TV) and a cell connection via (CTV) included in a semiconductor device (100, 100A, 100B, 100C) described with reference to FIGS. 1 through 9.

[0106] FIGS. 11a to 11h are schematic diagrams illustrating a method of manufacturing a semiconductor device (100) according to exemplary embodiments.

[0107] Referring to FIG. 11a, a peripheral circuit board (160) may be provided. The peripheral circuit board (160) may include a first surface (160F1) and a second surface (160F2). A mask pattern is formed on the second surface (160F2) of the peripheral circuit board (160), and a portion of the peripheral circuit board (160) is removed using the mask pattern as an etching mask to form a via hole (160H). Subsequently, a via insulating layer (162) may be formed within the via hole (160H) using an insulating material.

[0108] A peripheral circuit transistor (PTR) may be formed on a peripheral circuit board (160), and a first wiring pattern (WP1) electrically connected to the peripheral circuit transistor (PTR) and a first insulating layer (172) covering the peripheral circuit transistor (PTR) may be formed. In exemplary embodiments, the first insulating layer (172) may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant dielectric material.

[0109] In exemplary embodiments, the peripheral circuit transistor (PTR) may include at least one of a planar transistor, a FinFET transistor, a multi-bridge channel transistor, and a buried channel array transistor.

[0110] Referring to FIG. 11b, a first carrier substrate (210) can be attached to a first insulating layer (172). In exemplary embodiments, an interface insulating layer (212) is formed on the first carrier substrate (210), and the first carrier substrate (210) and a peripheral circuit board (160) can be attached to each other so that the interface insulating layer (212) contacts the upper surface of the first insulating layer (172).

[0111] In exemplary embodiments, the interfacial insulating layer (212) may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0112] In some exemplary embodiments, the interfacial insulating layer (212) and the first insulating layer (172) may be bonded to each other by an oxide bonding method. In some embodiments, plasma treatment may be performed on the surfaces of the interfacial insulating layer (212) and the first insulating layer (172). In some embodiments, surface treatment using a chemical may be performed on the surfaces of the interfacial insulating layer (212) and the first insulating layer (172). In some embodiments, high-temperature annealing treatment may be performed on the surfaces of the interfacial insulating layer (212) and the first insulating layer (172).

[0113] Referring to FIG. 11c, the structure to which the first insulating layer (172) and the first carrier substrate (210) are attached can be inverted.

[0114] Subsequently, a grinding process may be performed to remove a portion of the peripheral circuit board (160) from the first surface (160F1) of the peripheral circuit board (160). The grinding process may be performed until the upper surface of the via insulating layer (162) is exposed. By the grinding process, the thickness of the peripheral circuit board (160) may be reduced and the upper surface level of the peripheral circuit board (160) may be lowered.

[0115] In some embodiments, the via insulating layer (162) may be used as an etch stop layer in the grinding process. For example, the grinding process may be performed until the upper surface of the via insulating layer (162) is exposed, and the upper surface of the via insulating layer (162) and the lowered first surface (160F1) may be placed on the same plane.

[0116] Referring to FIG. 11d, a memory cell (MC) can be formed on a cell wafer (110).

[0117] In exemplary embodiments, a structure in which a plurality of memory cells (MC) are arranged in two dimensions on a cell wafer (110) may be formed. For example, the plurality of memory cells (MC) may include cell transistors (CTR) and cell capacitors (CAP) arranged in a vertical direction (Z) (see FIG. 4 and FIG. 5). In exemplary embodiments, a plurality of semiconductor patterns (AP) may be spaced apart in the vertical direction (Z), a plurality of word lines (WL) may surround the plurality of semiconductor patterns (AP) and extend in a first horizontal direction (X), and a plurality of bit lines (BL) may be connected to a first end of the plurality of semiconductor patterns (AP) and connected in the vertical direction (Z). A plurality of cell capacitors (CAP) may be connected to a second end opposite to the first end of the plurality of semiconductor patterns (AP). A plurality of word lines (WL) may include word line pad portions (WLP) having different lengths in a second horizontal direction (Y). The cover insulation layer (124) can cover a plurality of word lines (WL) and word line pad portions (WLP).

[0118] Referring to FIG. 11e, a mask pattern can be formed on the upper surface of the cover insulating layer (124), and a part of the cover insulating layer (124) can be removed to form a contact hole (WLC) that exposes the upper surface of the word line pad portion (WLP). Subsequently, a word line contact (WLC) can be formed within the contact hole (WLC) by filling the contact hole (WLC) with a conductive material.

[0119] In some embodiments, a via hole (CTVH) may be formed by removing a portion of the cover insulating layer (124) placed in the connection area (CON) during the process of forming the contact hole (WLC). The via hole (CTVH) may extend in the vertical direction (Z) through the cover insulating layer (124) and the bottom insulating layer (122), and the top surface of the cell wafer (110) may be exposed at the bottom of the via hole (CTVH). In some embodiments, a cell connection via (CTV) may be formed within the via hole (CTVH) by filling the via hole (CTVH) with a conductive material during the process of forming the word line contact (WLC) within the contact hole (WLC).

[0120] In some other embodiments, the process of forming the cell connection via (CTV) may be formed before or after the formation of the word line contact (WLC).

[0121] In exemplary embodiments, during the etching process of the via hole (CTVH), the upper side of the via hole (CTVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the via hole (CTVH) may be formed to be larger than the bottom width. In this case, the cell connection via (CTV) placed within the via hole (CTVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the cover insulating layer (124), is larger than the width of the bottom surface or second end, which is placed at the same level as the bottom surface of the bottom insulating layer (122).

[0122] Subsequently, an upper wiring layer (130) may be formed on the cover insulation layer (124), and an upper insulation layer (126) covering the upper wiring layer (130) may be formed. In exemplary embodiments, the upper wiring layer (130) may be formed as a stacked structure of two or more metal wiring layers having different vertical levels from each other, and the upper insulation layer (126) may be formed as a stacked structure of a plurality of insulation layers so as to cover two or more metal wiring layers.

[0123] A portion of the upper wiring layer (130) may be positioned to be vertically overlapping with the cell connection via (CTV) and may be electrically connected to the cell connection via (CTV). Such an upper wiring layer (130) may be referred to as a landing pad wiring layer (132).

[0124] Referring to FIG. 11f, the cell wafer (110) and the peripheral circuit board (160) can be bonded.

[0125] In exemplary embodiments, a peripheral circuit board (160) can be bonded to a cell wafer (110) such that the peripheral circuit board (160) is positioned at a vertical level higher than the memory cell (MC) placed on the cell wafer (110).

[0126] In exemplary embodiments, the bottom surface of the peripheral circuit board (160) may be attached to the upper surface of the upper insulating layer (126) so that the peripheral circuit board (160) is positioned at a vertical level higher than the cell wafer (110). In some exemplary embodiments, a bonding insulating layer may be formed on the bottom surface of the peripheral circuit board (160), and the peripheral circuit board (160) may be bonded to the cell wafer (110) in such a manner that the bonding insulating layer is bonded to the upper surface of the upper insulating layer (126).

[0127] Subsequently, a through-via contact (180) penetrating the via insulating layer (162) may be further formed. The through-via contact (180) may extend into the cell stack (CS) through the via insulating layer (162) and may be electrically connected to the upper wiring layer (130).

[0128] Afterward, a portion of the surrounding circuit board (160), a portion of the first insulating layer (172), and a portion of the upper insulating layer (126) can be removed to form a connection via hole (TVH). The upper surface of the landing pad wiring layer (132) may be exposed at the bottom of the connection via hole (TVH).

[0129] A connection via insulating layer (TVI) can be formed by conformally forming an insulating material on the inner wall of a connection via hole (TVH). The connection via insulating layer (TVI) can cover the entire sidewall of the connection via hole (TVH). At least a portion of the upper surface of the landing pad wiring layer (132) at the bottom of the connection via hole (TVH) may not be covered by the connection via insulating layer (TVI). In exemplary embodiments, the connection via insulating layer (TVI) may be formed using silicon oxide, silicon nitride, or silicon oxynitride.

[0130] Subsequently, a connection via (TV) can be formed using a metallic material inside the connection via hole (TVH). In exemplary embodiments, the connection via (TV) can be formed by an electroplating or electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc., on the inner wall of the connection via hole (TVH) before forming the connection via (TV).

[0131] In exemplary embodiments, during the etching process of the connection via hole (TVH), the upper side of the connection via hole (TVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the connection via hole (TVH) may be formed to be larger than the bottom width. In this case, the connection via (TV) placed within the connection via hole (TVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the first insulating layer (172), is larger than the width of the bottom surface or second end, which is placed at a lower level than the bottom surface of the surrounding circuit board (160).

[0132] Referring to FIG. 11g, a second wiring pattern (WP2) and a second insulating layer (174) can be formed on the upper surface of a connection via (TV) and a first insulating layer (172). A portion of the second wiring pattern (WP2) can be positioned to be vertically overlapping with the connection via (TV), and the second wiring pattern (WP2) can be electrically connected to the connection via (TV).

[0133] Afterwards, a front pad (PAD2) electrically connected to a second wiring pattern (WP2) can be formed on the second insulating layer (174).

[0134] In exemplary embodiments, the front pad (PAD2) may be formed by an electroplating process or an electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc. before forming the front pad (PAD2).

[0135] Referring to FIG. 11h, the structure in which the peripheral circuit stack (PS) and the cell stack (CS) are joined can be inverted. Then, the cell wafer (110) (see FIG. 11g) can be removed to expose the bottom insulating layer (122). As the bottom insulating layer (122) is exposed, the end of the cell connection via (CTV) can also be exposed.

[0136] Referring again to FIG. 2, a rear pad (PAD1) can be formed on the bottom surface of the bottom insulating layer (122). In exemplary embodiments, the rear pad (PAD1) can be formed by an electroplating process or an electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer can be further formed by a sputtering process using copper, titanium, silver, platinum, etc., before forming the rear pad (PAD1).

[0137] A semiconductor device (100) can be completed by the aforementioned process.

[0138] In a method for manufacturing a semiconductor device (100) according to exemplary embodiments, a peripheral circuit stack (PS) and a cell stack (CS) are attached, a connection via (TV) is formed to penetrate the peripheral circuit stack (PS), and then the cell wafer (110) can be removed. The semiconductor device (100) can have high integration density while having excellent electrical performance.

[0139] FIGS. 12a to 12f are schematic diagrams illustrating a method for manufacturing a semiconductor device (100A) according to exemplary embodiments.

[0140] Referring to FIG. 12a, a plurality of memory cells (MC) can be formed on a cell wafer (110) in a manner similar to that described with reference to FIG. 11d and FIG. 11e, and a word line contact (WLC) connected to the word line pad portion (WLP) of the plurality of memory cells (MC) can be formed.

[0141] In the embodiment described in FIG. 12a, the method described with reference to FIG. 11d and FIG. 11e may differ in that a cell connection via (CTV) is not formed on the connection area (CON).

[0142] Subsequently, an upper wiring layer (130) can be formed and an upper insulation layer (126) can be formed. Additionally, in the process for forming the upper wiring layer (130), a landing pad wiring layer (132) can be formed on the connection area (CON).

[0143] Referring to FIG. 12b, a second carrier substrate (220) can be attached to the upper surface of the upper insulating layer (126). In exemplary embodiments, an interface insulating layer (222) is formed on the second carrier substrate (220), and the second carrier substrate (220) and the cell wafer (110) can be attached to each other so that the interface insulating layer (222) contacts the upper surface of the upper insulating layer (126).

[0144] Afterward, the cell wafer (110) can be removed and the upper surface of the bottom insulating layer (122) can be exposed.

[0145] Referring to FIG. 12c, a mask pattern can be formed on the upper surface of the bottom insulating layer (122), and the mask pattern can be used as an etching mask to remove a portion of the bottom insulating layer (122) and the cover insulating layer (124) placed in the connection area (CON) to form a via hole (CTVH). The via hole (CTVH) can be extended in the vertical direction (Z) through the cover insulating layer (124) and the bottom insulating layer (122), and the upper surface of the landing pad wiring layer (132) can be exposed at the bottom of the via hole (CTVH).

[0146] Subsequently, a cell connection via (CTV) can be formed within the via hole (CTVH) by filling the via hole (CTVH) with a conductive material.

[0147] In exemplary embodiments, the cell connection via (CTV) may be formed by an electroplating or electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc. on the inner wall of the via hole (CTVH) before forming the cell connection via (CTV).

[0148] In other exemplary embodiments, cell connection vias (CTVs) may be formed using at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer stacking process using tungsten, tungsten nitride, titanium, titanium nitride, ruthenium, cobalt, cobalt nitride, molybdenum, molybdenum nitride, or a combination thereof.

[0149] In exemplary embodiments, during the etching process of the via hole (CTVH), the upper side of the via hole (CTVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the via hole (CTVH) may be formed to be larger than the bottom width. In this case, the cell connection via (CTV) placed within the via hole (CTVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the bottom insulating layer (122), is larger than the width of the bottom surface or second end, which is placed at the same level as the bottom surface of the cover insulating layer (124).

[0150] Afterwards, a rear pad (PAD1) electrically connected to a cell connection via (CTV) can be formed on the upper surface of the bottom insulating layer (122).

[0151] Referring to FIG. 12d, a third carrier substrate (230) can be attached to the upper surface of the bottom insulating layer (122). In exemplary embodiments, an interface insulating layer (232) is formed on the third carrier substrate (230), and the third carrier substrate (230) and the second carrier substrate (220) can be attached to each other so that the interface insulating layer (232) contacts the upper surface of the bottom insulating layer (122).

[0152] The structure to which the third carrier substrate (230) and the second carrier substrate (220) are attached can be inverted. Afterward, the second carrier substrate (220) and the interface insulating layer (222) can be removed to expose the upper surface of the upper insulating layer (126).

[0153] Afterwards, the third carrier substrate (230) and the peripheral circuit board (160) can be bonded.

[0154] In exemplary embodiments, a peripheral circuit board (160) can be bonded to a third carrier substrate (230) such that the peripheral circuit board (160) is positioned at a vertical level higher than the memory cell (MC) placed on the third carrier substrate (230).

[0155] In exemplary embodiments, the bottom surface of the peripheral circuit board (160) may be attached to the upper surface of the upper insulating layer (126) so that the peripheral circuit board (160) is positioned at a vertical level higher than the third carrier board (230). In some exemplary embodiments, a bonding insulating layer may be formed on the bottom surface of the peripheral circuit board (160), and the peripheral circuit board (160) may be bonded to the upper insulating layer (126) in such a manner that the bonding insulating layer is bonded to the upper surface of the upper insulating layer (126).

[0156] Subsequently, a through-via contact (180) penetrating the via insulating layer (162) may be further formed. The through-via contact (180) may extend into the cell stack (CS) through the via insulating layer (162) and may be electrically connected to the upper wiring layer (130).

[0157] Referring to FIG. 12e, a connection via hole (TVH) can be formed by removing a portion of the peripheral circuit board (160), a portion of the first insulating layer (172), and a portion of the upper insulating layer (126). The upper surface of the landing pad wiring layer (132) may be exposed at the bottom of the connection via hole (TVH).

[0158] An insulating layer (TVI) can be formed by conformally forming an insulating material on the inner wall of a connection via hole (TVH). Subsequently, a connection via (TV) can be formed inside the connection via hole (TVH) using a metallic material.

[0159] In exemplary embodiments, during the etching process of the connection via hole (TVH), the upper side of the connection via hole (TVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the connection via hole (TVH) may be formed to be larger than the bottom width. In this case, the connection via (TV) placed within the connection via hole (TVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the first insulating layer (172), is larger than the width of the bottom surface or second end, which is placed at a lower level than the bottom surface of the surrounding circuit board (160).

[0160] Referring to FIG. 12f, a second wiring pattern (WP2) and a second insulating layer (174) can be formed on the upper surface of the connection via (TV) and the first insulating layer (172). Subsequently, a front pad (PAD2) electrically connected to the second wiring pattern (WP2) can be formed on the second insulating layer (174).

[0161] A semiconductor device (100A) can be completed by the aforementioned process.

[0162] In a method for manufacturing a semiconductor device (100A) according to exemplary embodiments, a peripheral circuit stack (PS) and a cell stack (CS) are attached, and then a connection via (TV) may be formed to pass through the peripheral circuit stack (PS). The semiconductor device (100A) may have high integration density while having excellent electrical performance.

[0163] FIGS. 13a to 13f are schematic diagrams illustrating a method for manufacturing a semiconductor device (100B) according to exemplary embodiments.

[0164] Referring to FIG. 13a, a mask pattern is formed on a second surface (160F2) of a peripheral circuit board (160), and a portion of the peripheral circuit board (160) is removed using the mask pattern as an etching mask to form a via hole (160H). Subsequently, a via insulating layer (162) can be formed within the via hole (160H) using an insulating material.

[0165] Subsequently, a peripheral circuit transistor (PTR) can be formed on the second surface (160F2) of the peripheral circuit board (160), and a first wiring pattern (WP1) electrically connected to the peripheral circuit transistor (PTR) and a first insulating layer (172) covering the peripheral circuit transistor (PTR) can be formed.

[0166] Referring to FIG. 13b, a connection via hole (TVH) can be formed by removing a portion of the peripheral circuit board (160) and a portion of the first insulating layer (172). The connection via hole (TVH) can be formed with a vertical height that extends into the interior of the peripheral circuit board (160) and does not completely penetrate the peripheral circuit board (160).

[0167] Subsequently, an insulating material may be conformally formed on the inner wall of the connection via hole (TVH) to form a connection via insulating layer (TVI). The connection via insulating layer (TVI) may cover the entire sidewall of the connection via hole (TVH). At least a portion of the upper surface of the surrounding circuit board (160) at the bottom of the connection via hole (TVH) may not be covered by the connection via insulating layer (TVI). In exemplary embodiments, the connection via insulating layer (TVI) may be formed using silicon oxide, silicon nitride, or silicon oxynitride.

[0168] Subsequently, a connection via (TV) can be formed using a metallic material inside the connection via hole (TVH). In exemplary embodiments, the connection via (TV) can be formed by an electroplating or electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc., on the inner wall of the connection via hole (TVH) before forming the connection via (TV).

[0169] In exemplary embodiments, during the etching process of the connection via hole (TVH), the upper side of the connection via hole (TVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the connection via hole (TVH) may be formed to be larger than the bottom width. In this case, the connection via (TV) placed within the connection via hole (TVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the first insulating layer (172), is larger than the width of the bottom surface or second end, which is placed at a lower level than the upper surface of the surrounding circuit board (160).

[0170] A second wiring pattern (WP2) and a second insulating layer (174) can be formed on the upper surface of the connection via (TV) and the first insulating layer (172). A portion of the second wiring pattern (WP2) may be positioned to be vertically overlapping with the connection via (TV), and the second wiring pattern (WP2) may be electrically connected to the connection via (TV).

[0171] Afterwards, a portion of the second insulating layer (174) can be removed to form a pad opening, and a second bonding pad (BP2) can be formed within the pad opening.

[0172] In exemplary embodiments, the second bonding pad (BP2) may be formed by an electroplating process or an electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc. on the inner wall of the pad opening before forming the second bonding pad (BP2).

[0173] In exemplary embodiments, the second bonding pad (BP2) may have an upper surface disposed in the same plane as the upper surface of the second insulating layer (174).

[0174] Referring to FIG. 13c, the peripheral circuit board (160) can be flipped over, and a grinding process can be performed to remove a portion of the peripheral circuit board (160) from the first surface (160F1) of the peripheral circuit board (160).

[0175] In exemplary embodiments, the grinding process may be performed until the upper surface or second end of the connection via (TV) is exposed. Accordingly, the upper surface or second end of the connection via (TV) and the lowered first surface (160F1) may be placed on the same plane.

[0176] Referring to FIG. 13d, a plurality of memory cells (MC) can be formed on a cell wafer (110) by performing the process described with reference to FIG. 11d and FIG. 11e, and an upper wiring layer (130) electrically connected to the plurality of memory cells (MC) and an upper insulating layer (126) covering the upper wiring layer (130) can be formed.

[0177] Afterwards, a portion of the upper insulating layer (126) is removed to form a pad opening, and a first bonding pad (BP1) can be formed within the pad opening.

[0178] In exemplary embodiments, the first bonding pad (BP1) may be formed by an electroplating process or an electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc. on the inner wall of the pad opening before forming the first bonding pad (BP1).

[0179] In exemplary embodiments, the first bonding pad (BP1) may have an upper surface disposed in the same plane as the upper surface of the upper insulating layer (126).

[0180] Referring to FIG. 13e, a peripheral circuit board (160) and a cell wafer (110) can be bonded. In exemplary embodiments, the peripheral circuit board (160) can be bonded onto the cell wafer (110) such that the upper surface of the first bonding pad (BP1) and the lower surface of the second bonding pad (BP2) are in contact, and the upper surface of the upper insulating layer (126) and the lower surface of the second insulating layer (174) are in contact.

[0181] Referring to FIG. 13f, the cell wafer (110) can be removed and a rear pad (PAD1) can be formed on the bottom surface of the bottom insulating layer (122).

[0182] A semiconductor device (100B) can be completed by the aforementioned process.

[0183] In a method for manufacturing a semiconductor device (100B) according to exemplary embodiments, a peripheral circuit stack (PS) and a cell stack (CS) may be attached in a front-to-front junction structure by bonding pads (BP). The semiconductor device (100B) may have high integration density while having excellent electrical performance.

[0184] FIGS. 14a to 14e are schematic diagrams illustrating a method for manufacturing a semiconductor device (100C) according to exemplary embodiments.

[0185] Referring to FIG. 14a, a mask pattern is formed on a second surface (160F2) of a peripheral circuit board (160), and a portion of the peripheral circuit board (160) is removed using the mask pattern as an etching mask to form a via hole (160H). Subsequently, a via insulating layer (162) can be formed using an insulating material within the via hole (160H).

[0186] Subsequently, a peripheral circuit transistor (PTR) can be formed on the second surface (160F2) of the peripheral circuit board (160), and a first wiring pattern (WP1) electrically connected to the peripheral circuit transistor (PTR) and a first insulating layer (172) covering the peripheral circuit transistor (PTR) can be formed.

[0187] Subsequently, a second wiring pattern (WP2) and a second insulating layer (174) can be formed on the upper surface of the first insulating layer (172). A portion of the second insulating layer (174) can be removed to form a pad opening, and a second bonding pad (BP2) can be formed within the pad opening.

[0188] Referring to FIG. 14b, the peripheral circuit board (160) can be flipped over, and a grinding process can be performed to remove a portion of the peripheral circuit board (160) from the first surface (160F1) of the peripheral circuit board (160).

[0189] In exemplary embodiments, the grinding process may be performed until the upper surface of the via insulating layer (162) is exposed. Accordingly, the upper surface of the via insulating layer (162) and the lowered first surface (160F1) may be placed on the same plane.

[0190] Referring to FIG. 14c, a peripheral circuit board (160) and a cell wafer (110) can be bonded. In exemplary embodiments, the peripheral circuit board (160) can be bonded onto the cell wafer (110) such that the upper surface of the first bonding pad (BP1) and the lower surface of the second bonding pad (BP2) are in contact, and the upper surface of the upper insulating layer (126) and the lower surface of the second insulating layer (174) are in contact.

[0191] Referring to FIG. 14d, a connection via hole (TVH) can be formed by removing a portion of the peripheral circuit board (160) and a portion of the first insulating layer (172). The connection via hole (TVH) can be extended in the vertical direction (Z) through the peripheral circuit board (160) and the first insulating layer (172), and the upper surface of the landing pad wiring pattern (WP_L) can be exposed at the bottom of the connection via hole (TVH).

[0192] Subsequently, an insulating material can be conformally formed on the inner wall of the connection via hole (TVH) to form a connection via insulating layer (TVI). The connection via insulating layer (TVI) can cover the entire side wall of the connection via hole (TVH). At least a portion of the upper surface of the landing pad wiring pattern (WP_L) at the bottom of the connection via hole (TVH) may not be covered by the connection via insulating layer (TVI).

[0193] Subsequently, a connection via (TV) can be formed using a metallic material inside the connection via hole (TVH). In exemplary embodiments, the connection via (TV) can be formed by an electroplating or electroless plating process using copper or a copper alloy. In exemplary embodiments, a seed layer may be further formed by a sputtering process using copper, titanium, silver, platinum, etc., on the inner wall of the connection via hole (TVH) before forming the connection via (TV).

[0194] In exemplary embodiments, during the etching process of the connection via hole (TVH), the upper side of the connection via hole (TVH) may be exposed to the etching atmosphere for a longer period, and accordingly, the upper width of the connection via hole (TVH) may be formed to be larger than the bottom width. In this case, the connection via (TV) placed within the connection via hole (TVH) may be formed such that the width of the upper surface or first end, which is placed at the same level as the upper surface of the surrounding circuit board (160), is larger than the width of the bottom surface or second end, which is placed at a lower level than the bottom surface of the first insulating layer (172).

[0195] Referring to FIG. 14e, a front pad (PAD2) electrically connected to a connection via (TV) can be formed on the upper surface of a peripheral circuit board (160).

[0196] Afterward, the cell wafer (110) can be removed, and a back pad (PAD1) electrically connected to a cell connection via (CTV) can be formed on the bottom surface of the exposed bottom insulating layer (122).

[0197] A semiconductor device (100C) can be completed by the aforementioned process.

[0198] In a method for manufacturing a semiconductor device (100C) according to exemplary embodiments, a peripheral circuit stack (PS) and a cell stack (CS) are attached in a front-to-front junction structure by a bonding pad (BP), and then a connection via (TV) may be formed to penetrate the peripheral circuit stack (PS). The semiconductor device (100C) may have high integration density while having excellent electrical performance.

[0199] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0200] MC: Memory Cell CTR: Cell Transistor CAP: Cell capacitor PTR: Peripheral circuit transistor TV: Access via CTV: Cell Access Via

Claims

Claim 1 As a cell stack, A plurality of semiconductor patterns spaced apart in the first horizontal and vertical directions; A plurality of word lines surrounding the plurality of semiconductor patterns and extending in the first horizontal direction; A plurality of bit lines connected to each first end of the plurality of semiconductor patterns and extending in the vertical direction; and A cell stack comprising a plurality of cell capacitors connected to each second end of the plurality of semiconductor patterns and spaced apart in the vertical direction; and a peripheral circuit stack disposed on the cell stack, A peripheral circuit board disposed on the upper surface of the cell stack; and A semiconductor device comprising: a peripheral circuit stack including a peripheral circuit transistor disposed on the peripheral circuit board; a connection via extending in the vertical direction through the peripheral circuit board; a front pad disposed on the upper surface of the peripheral circuit stack and electrically connected to the connection via; and a back pad disposed on the lower surface of the cell stack and electrically connected to the connection via. Claim 2 In paragraph 1, A semiconductor device comprising: an upper wiring layer electrically connected to the plurality of word lines or the plurality of cell capacitors; and an upper insulating layer covering the upper wiring layer, wherein the peripheral circuit stack is disposed on the upper insulating layer. Claim 3 A semiconductor device in which the bottom surface of the peripheral circuit board and the upper surface of the upper insulating layer are in contact in paragraph 2. Claim 4 A semiconductor device according to paragraph 2, wherein the upper wiring layer further comprises a landing pad wiring layer in contact with the bottom surface of the connection via. Claim 5 A semiconductor device according to claim 4, further comprising a connection via insulating layer disposed within a connection via hole penetrating a portion of the peripheral circuit board and the upper insulating layer, and disposed on the sidewall of the connection via. Claim 6 A semiconductor device according to claim 5, wherein the connection via insulating layer contacts the upper surface of the landing pad wiring layer, and a portion of the connection via insulating layer is disposed between the connection via and the peripheral circuit board. Claim 7 A semiconductor device according to claim 4, wherein the cell stack further comprises: a cover insulating layer covering the plurality of word lines and the plurality of cell capacitors; and a cell connection via extending in the vertical direction through the cover insulating layer, electrically connected to the landing pad wiring layer, and electrically connected to the back pad. Claim 8 A semiconductor device according to claim 7, wherein the cell connection via is positioned at a location that vertically overlaps with the landing pad wiring layer, and the connection via is positioned at a location that vertically overlaps with the landing pad wiring layer. Claim 9 A semiconductor device according to claim 7, wherein the width of the upper surface of the connection via is greater than the width of the bottom surface of the connection via, and the width of the upper surface of the cell connection via is greater than the width of the bottom surface of the cell connection via. Claim 10 A semiconductor device according to claim 7, wherein the width of the upper surface of the connection via is greater than the width of the bottom surface of the connection via, and the width of the upper surface of the cell connection via is smaller than the width of the bottom surface of the cell connection via.

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