Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device may include a stack comprising alternately stacked first insulating films and second insulating films; channel structures extending through the stack; and gate lines positioned between the channel structures and the first insulating films, each comprising annular portions surrounding the channel structures and line portions connecting the annular portions.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] The integration density of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as the improvement of integration density in semiconductor devices that form memory cells as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices that stack memory cells on a substrate are being proposed. In addition, various structures and manufacturing methods are being developed to improve the operational reliability of such semiconductor devices. The problem to be solved

[0003] An embodiment of the present invention provides a semiconductor device having a stable structure and improved characteristics and a method for manufacturing a semiconductor device. means of solving the problem

[0004] A semiconductor device according to an embodiment of the present invention may include a stack comprising first insulating films and second insulating films that are alternately stacked; channel structures extending through the stack; and gate lines located between the channel structures and the first insulating films, each comprising annular portions that surround the channel structures and line portions that connect the annular portions.

[0005] A semiconductor device according to an embodiment of the present invention may include: first channel structures arranged in a first direction and a second direction intersecting the first direction; first word lines stacked along the side walls of the first channel structures, each including first annular portions surrounding the first channel structures and first line portions connecting the first annular portions; second channel structures arranged in the first direction and the second direction; second word lines stacked along the side walls of the second channel structures, each including second annular portions surrounding the second channel structures and second line portions connecting the second annular portions; a first pad stack including first word line pads connected to the first word lines; and a second pad stack including second word line pads connected to the second word lines.

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a stack comprising alternately stacked first insulating films and second insulating films; forming first openings extending through the stack; etching the first insulating films through the first openings to form second openings surrounding the first openings; forming sacrificial films within the first openings and the second openings; forming at least one trench within at least one of the sacrificial films; etching the first insulating films through the at least one trench to form third openings connecting the second openings; and forming gate lines within the second openings and the third openings.

[0007] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include: forming a stack comprising first insulating films and second insulating films that are alternately stacked; forming first openings extending through a cell region of the stack; etching the first insulating films through the first openings to form second openings; etching the first insulating films through the second openings to form third openings connecting adjacent second openings; forming gate lines including annular portions located within the second openings and line portions located within the third openings; forming a slit in a pad region of the stack; and replacing the first insulating films in the pad region with pads through the slit. Effects of the invention

[0008] By stacking memory cells in three dimensions, the integration density of the semiconductor device can be improved. In addition, a semiconductor device with a stable structure and improved reliability can be provided. Brief explanation of the drawing

[0009] FIGS. 1a to 1c are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 2a to 2c are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 3a and FIGS. 3b are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 4a and FIGS. 4b are drawings showing the structure of a semiconductor device according to one embodiment of the present invention. FIG. 5 is a diagram showing the structure of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a diagram showing the structure of a semiconductor device according to one embodiment of the present invention. FIG. 7 is a diagram showing the structure of a semiconductor device according to one embodiment of the present invention. FIGS. 8a to 13a and FIGS. 8b to 13b are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 14a to 18a and FIGS. 14b to 18b are drawings for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 19 is a configuration diagram of a semiconductor device according to one embodiment of the present invention. FIG. 20 is a configuration diagram of a semiconductor device according to one embodiment of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0012] FIGS. 1a to 1c are drawings showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 1a is a plan view, FIG. 1b is a cross-sectional view AA' of FIG. 1a, and FIG. 1c is a cross-sectional view BB' of FIG. 1a.

[0013] Referring to FIGS. 1a through 1c, a semiconductor device may include a stack (ST), first channel structures (CH1), second channel structures (CH2), first gate lines (GL1) and second gate lines (GL2). The stack (ST) may include first insulating films (11) and second insulating films (12) that are alternately stacked. The first insulating films (11) may include a material with a high etch selectivity ratio with respect to the second insulating films (12). As an example, the first insulating films (11) may include a nitride and the second insulating films (12) may include an oxide.

[0014] The first channel structures (CH1) can be extended through a stack (ST). In a plane defined by a first direction (I) and a second direction (II) intersecting the first direction (I), the first channel structures (CH1) can be arranged in the first direction (I) and the second direction (II). The first channel structures (CH) adjacent to the second direction (II) can be arranged staggered. In a cross-section defined by a first direction (I) and a third direction (III), the first channel structures (CH1) can be extended through a stack (ST) to the third direction (III). The third direction (III) can be a direction intersecting the first direction (I) and the second direction (II), and can be a vertical direction.

[0015] The first channel structure (CH1) may include a first channel film (13A), a first memory film (14A), and a first insulating core (15A). The first memory film (14A) may wrap around the sidewall of the first channel film (13A), and the first insulating core (15A) may be located within the first channel film (13A). The first memory film (14A) may include at least one of a tunneling film, a data storage film, and a blocking film. The tunneling film may wrap around the sidewall of the first channel film (13A), the data storage film may wrap around the tunneling film, and the blocking film may wrap around the data storage film. As an example, the data storage film may include a floating gate, polysilicon, nitride, charge trap material, variable resistor material, etc. The blocking film may include a high dielectric constant material and may be a single film or a multilayer film.

[0016] The second channel structures (CH2) can be extended through a stack (ST). The second channel structures (CH2) can be arranged similarly to the first channel structures (CH1) and can have a similar structure. The second channel structures (CH2) may include a second channel film (13B), a second memory film (14B), and a second insulating core (15B).

[0017] The distance between the first channel structures (CH1) and the distance between the second channel structures (CH2) may be substantially the same. The distance between the centers of adjacent first channel structures (CH1) may be a first distance (D1), and the distance between the centers of adjacent second channel structures (CH2) may be a second distance (D2). The first distance (D1) and the second distance (D2) may be substantially the same. The third distance (D3) between the centers of adjacent first channel structures (CH1) and second channel structures (CH2) may be substantially the same as the first distance (D1) and / or the second distance (D2).

[0018] The first gate lines (GL1) can be stacked along the sidewalls of the first channel structures (CH1). The first gate lines (GL1) can be located between the first channel structures (CH1) and the first insulating films (11). The stacked first gate lines (GL1) can be separated from each other by the second insulating films (12).

[0019] The first gate line (GL1) may include first annular sections (RP1) and first line sections (LP1). The first annular sections (RP1) may each wrap around the first channel structures (CH1), and the first line sections (LP1) may connect the first annular sections (RP1). The first line sections (LP1) may connect the first annular sections (RP1) in a radial manner. As an example, a plurality of first annular sections (RP1) may be located around a single first annular section (RP1). A single first annular section (RP1) may be located at the center of a hexagon, and first annular sections (RP1) may be located at six vertices. By extending the first line sections (LP1) from the first annular section (RP1) located at the center to the first annular sections (RP1) of the vertices, the first annular sections (RP1) can be connected in a radial manner.

[0020] The first line sections (LP1) may be located between the first annular sections (RP1) facing each other. In an embodiment, the outer side walls (OSW) of the first annular sections (RP1) located at the outermost edge do not face the first annular sections (RP), while the inner side walls (ISW) face the first annular sections (RP1). Accordingly, the first line sections (LP1) may be connected to the inner side walls (ISW) of the first annular sections (RP) located at the outermost edge, but the first line sections (LP1) may not be connected to the outer side walls (OSW).

[0021] The second gate lines (GL2) can be stacked along the sidewalls of the second channel structures (CH2). The second gate lines (GL2) can be located between the second channel structures (CH2) and the first insulating films (11). The stacked second gate lines (GL2) can be separated from each other by the second insulating films (12). The first gate line (GL1) and the second gate line (GL2) located on the same layer can be separated from each other by the first insulating film (11).

[0022] The second gate line (GL2) may have a shape similar to the first gate line (GL1). The second gate line (GL2) may include second annular sections (RP2) and second line sections (LP2) connecting the second annular sections (RP2). The second line sections (LP2) may be located between the facing second annular sections (RP2). Since the outer side walls of the outermost second annular sections (RP2) face the first annular sections (RP1), the second line sections (LP2) may not be connected to the outer side walls.

[0023] The distance between the first annular sections (RP1) and the distance between the second annular sections (RP2) may be substantially the same. The distance between the centers of adjacent first annular sections (RP1) may be a first distance (D1), and the distance between adjacent second annular sections (RP2) may be a second distance (D2). The first distance (D1) and the second distance (D2) may be substantially the same. The third distance (D3) between the centers of adjacent first and second annular sections may be substantially the same as the first distance (D1) and / or the second distance (D2).

[0024] The first and second gate lines (GL1, GL2) may be source selection lines, word lines, or drain selection lines. As an example, a plurality of word lines may be stacked between at least one source selection line and at least one drain selection line.

[0025] According to the structure described above, the first gate line (GL1) may include first annular sections (RP1) and first line sections (LP1), and the second gate line (GL2) may include second annular sections (RP2) and second line sections (LP2). Since the line sections (LP1, LP2) are not connected to the outer sidewalls (OSW) of the outermost annular sections (RP1, RP2), the first gate line (GL1) and the second gate line (GL2) can be separated without a separate slit. The first gate line (GL1) and the second gate line (GL2) can be separated while maintaining a uniform spacing between the annular sections (RP1, RP2).

[0027] FIGS. 2a to 2c are drawings illustrating the structure of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions that overlap with the previously described contents may be omitted.

[0028] Referring to FIG. 2a, the semiconductor device may include a gate line (GL) and a pad (PD). The semiconductor device may further include a channel structure (CH), a first insulating film (21), a contact plug (CT), and a slit structure (SLS). The first insulating film (21) may be part of the stack (ST) described earlier with reference to FIG. 1a through 1c.

[0029] Gate lines (GL), channel structures (CH), and a first insulating film (21) may be located in a cell region (CR), and pads (PD), contact plugs (CT), and slit structures (SLS) may be located in a pad region (PR). The cell region (CR) is a region where memory cells are stacked. Gate lines (GL) may be stacked in the cell region (CR), and memory cells may be located in the region where channel structures (CH) and gate lines (GL) intersect. The pad region (PR) is a region where interconnections for driving each of the stacked gate lines (GL) are located. Pads (PD) may be stacked in the pad region (PR), and contact plugs (CT) may be connected to each of the pads (PD).

[0030] The gate line (GL) may include annular portions (RP) surrounding the channel structures (CH) and line portions (LP) connecting the annular portions (RP). The channel structure (CH) may include a channel film (23), a memory film (24) surrounding the channel film (23), and an insulating core (25) within the channel film (23).

[0031] A pad (PD) may be positioned adjacent to a gate line (GL) in a first direction (I). The pad (PD) may be electrically connected to the gate line (GL) and may be connected to line sections (LP). The pad (PD) may be positioned between a pair of slit structures (SLS), and the pad (PD) may have a plate shape. In a second direction (II), the gate line (GL) may have a first width (W1) and the pad (PD) may have a second width (W2). The first width (W1) and the second width (W2) may be different, and the second width (W2) may be smaller than the first width (W1).

[0032] Referring to FIGS. 2b and 2c, the semiconductor device may include first to third gate lines (GL1 to GL3), first to third pads (PD1 to PD3), and first to third contact plugs (CT1 to CT3). The first to third pads (PD1 to PD3) may each be connected to the first to third gate lines (GL1 to GL3). The first to third contact plugs (CT1 to CT3) may extend to different depths and may each be connected to the first to third pads (PD1 to PD3).

[0033] Referring to FIG. 2b, the first to third pads (PD1 to PD3) may be stacked in a stepped shape. The first to third pads (PD1 to PD3) may have different lengths in the first direction (I). The first pad (PD1) may have a longer length than the second pad (PD2), and the second pad (PD2) may have a longer length than the third pad (PD3). A first contact plug (CT1) may be connected to the portion of the first pad (PD1) that is not covered by the second pad (PD2). A second contact plug (CT2) may be connected to the portion of the second pad (PD2) that is not covered by the third pad (PD3).

[0034] Referring to FIG. 2c, the first to third pads (PD1 to PD3) may have substantially the same length in the first direction (I). The first contact plug (CT1) may penetrate the second and third pads (PD2, PD3) and may be electrically connected to the first pad (PD1). The first contact plug (CT1) may be insulated from the second and third pads (PD2, PD3). The second contact plug (CT1) may penetrate the third pad (PD3) and may be electrically connected to the second pad (PD2). The second contact plug (CT2) may be insulated from the third pad (PD3).

[0035] According to the structure described above, pads (PDs) can be connected to each of the gate lines (GL). By applying a driving bias through contact plugs (CT), the gate lines (GL) can be driven individually.

[0037] FIGS. 3A and FIGS. 3B are drawings showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view of FIG. 3A's CC'.

[0038] Referring to FIGS. 3a and 3b, the semiconductor device may include first gate lines (GL1), second gate lines (GL2), first channel structures (CH1), second channel structures (CH2), a stack (ST), a first pad stack (PST1), a second pad stack (PST2), first contact plugs (CT1), second contact plugs (CT2), a first slit structure (SLS1), a second slit structure (SLS2), a first wiring (ML1), a second wiring (ML2), and an interlayer insulating film (IL).

[0039] The laminate (ST) may include first insulating films (31) and second insulating films (32) that are alternately laminated. First channel structures (CH1) and second channel structures (CH2) may extend through the laminate (ST). The first channel structure (CH1) may include a first channel film (33A), a first memory film (34A), and a first insulating core (35A).

[0040] The first pad stack (PST1) may have a stepped shape and may include alternately stacked first pads (PD1) and second insulating films (32). The second pad stack (PST2) may have a stepped shape and may include alternately stacked second pads (PD2) and second insulating films (32). The stack (ST), the first pad stack (PST1), and the second pad stack (PST2) may share the second insulating films (32).

[0041] A stack (ST) and a first pad stack (PST1) may be adjacent in a first direction (I), and a stack (ST1) and a second pad stack (PST2) may be adjacent in a first direction (I). A first pad stack (PST1) and a second pad stack (PST2) may be adjacent in a second direction (II). At least two pad stacks (PST1, PST2) may be positioned correspondingly on one stack (ST).

[0042] First and second slit structures (SLS1, SLS2) may be located between first and second pad stacks (PST1, PST2). The first and second slit structures (SLS1, SLS2) may extend in a first direction (I). At least one first slit structure (SLS1) may be located between a pair of second slit structures (SLS2). As an example, the first slit structure (SLS1) may be located inside a memory block, and the second slit structure (SLS2) may be located at the boundary between memory blocks.

[0043] The first gate lines (GL1) can be stacked along the sidewalls of the first channel structures (CH1). The stacked first gate lines (GL1) can be connected to the first pad stack (PST1) and each can be connected to the first pads (PD1). The second gate lines (GL2) can be stacked along the sidewalls of the second channel structures (CH2). The stacked second gate lines (GL2) can be connected to the second pad stack (PST2) and each can be connected to the second pads (PD2).

[0044] The first gate lines (GL1) may be a first source select line (SSL1), a first word line (WL1), or a first drain select line (DSL1). As an embodiment, the first gate lines (GL1) may include at least one first source select line (SSL1), first word lines (WL1), and at least one first drain select line (DSL1). The first word lines (WL1) may be located between at least one first source select line (SSL1) and at least one first drain select line (DSL1).

[0045] The first word line (WL1), the first drain selection line (DSL1), and the first source selection line (SSL1) may have similar forms. The first word line (WL1) may include first annular sections surrounding the first channel structures (CH1) and first line sections connecting the first annular sections. The first drain selection line (DSL1) may include third annular sections surrounding the first channel structures (CH1) and third line sections connecting the third annular sections. The first source selection line (SSL1) may include fourth annular sections surrounding the first channel structures (CH1) and fourth line sections connecting the fourth annular sections.

[0046] The first word line (WL1) can be connected to the first word line contact plug (WLCT1) through the first word line pad (WLPD1). The first drain select line (DSL1) can be connected to the first drain contact plug (DCT1) through the first drain pad (DPD1). The first source select line (SSL1) can be connected to the first source contact plug (SCT1) through the first source pad (SPD1). The first word line pad (WLPD1), the first drain pad (DPD1), and the first source pad (SPD1) can be stacked in a stepped form.

[0047] The first gate line (GL1) and the second gate line (GL2) may belong to the same memory block or to different memory blocks. If the first and second gate lines (GL1, GL2) belong to the same memory block, the same driving bias may be applied to word lines of the same level. The driving bias may include a program voltage, a pass voltage, a read voltage, etc. As an example, the first word line pad (WLPD1) of the first word line (WL1) belonging to the first gate line (GL1) and the second word line pad of the second word line belonging to the second gate line (GL2) may be located at the same level, and the first word line contact plug (CT1) and the second word line contact plug connected to the first word line pad (WLPD1) and the second word line pad located at the same level may be electrically connected by the first wiring (ML1). Through this, the first word line (WL1) and the second word line located at the same level can be electrically connected. Likewise, the first source pad (SPD1) and the first source contact plug (SCT1) and the second source contact plug connected to the second source pad located at the same level can be electrically connected by the second wiring (ML2), and the first source select line (SSL1) and the second source select line located at the same level can be electrically connected. The first and second wirings (ML1, ML2) can cross the first slit structure (SLS1) and can extend in the second direction (II).

[0048] According to the structure described above, stacked first gate lines (GL1) can be connected to a first pad stack (PST1), and stacked second gate lines (GL2) can be connected to a second pad stack (PST2). The first gate line (GL1) and the second gate line (GL2) located at the same level can be separated without a slit structure. The first pad (PD1) and the second pad (PD2) located at the same level can be separated by a first slit structure (SLS1). The first pad (PD1) and the second pad (PD2) located at the same level can be connected using wiring (ML1, ML2).

[0050] FIGS. 4a and 4b are drawings showing the structure of a semiconductor device according to an embodiment of the present invention. FIG. 4a is a plan view, and FIG. 4b is a cross-sectional view DD' of FIG. 4a.

[0051] Referring to FIGS. 4a and 4b, the semiconductor device may include first gate lines (GL1), second gate lines (GL2), first channel structures (CH1), second channel structures (CH2), a stack (ST), a first pad stack (PST1), a second pad stack (PST2), first contact plugs (CT1), second contact plugs (CT2), an insulating spacer (SP), a first slit structure (SLS1), a second slit structure (SLS2), a first wiring (ML1) and a second wiring (ML2).

[0052] The laminate (ST) may include first insulating films (41) and second insulating films (42) that are alternately laminated. First channel structures (CH1) and second channel structures (CH2) may extend through the laminate (ST). The first channel structure (CH1) may include a first channel film (43A), a first memory film (44A), and a first insulating core (45A).

[0053] A first pad stack (PST1) may include first pads (PD1) and second insulating films (42) that are alternately stacked. A second pad stack (PST2) may include second pads (PD2) and second insulating films (42) that are alternately stacked. A stack (ST), a first pad stack (PST1), and a second pad stack (PST2) may share the second insulating films (42). At least two pad stacks (PST1, PST2) may be positioned correspondingly in a single stack (ST). At least one first slit structure (SLS1) may be positioned between a pair of second slit structures (SLS2).

[0054] The first gate lines (GL1) may be stacked along the sidewalls of the first channel structures (CH1). The stacked first gate lines (GL1) may be connected to the first pad stack (PST1) and each may be connected to the first pads (PD1). The first gate lines (GL1) may include at least one first source select line (SSL1), first word lines (WL1), and at least one first drain select line (DSL1). The second gate lines (GL2) may be stacked along the sidewalls of the second channel structures (CH2). The stacked second gate lines (GL2) may be connected to the second pad stack (PST2) and each may be connected to the second pads (PD2). The second gate lines (GL1) may include at least one second source select line, second word lines, and at least one second drain select line.

[0055] The first pad stack (PST1) may include a flat top surface, and the first contact plugs (CT1) may extend through the first pad stack (PST1) to different depths. The first source contact plug (SCT1) may penetrate the first drain select line (DSL1) and the first word lines (WL1) and may be connected to the first source select line (SSL1). The sidewall of the first source contact plug (SCT1) may be wrapped with an insulating spacer (SP), and the first source contact plug (SCT1) may be insulated from the first drain select line (DSL1) and the first word lines (WL1) by the insulating spacer (SP). The first word line contact plugs (WLCT1) may penetrate the first drain select line (DSL1) and may be connected to the first word lines (WL1), respectively. The side wall of the first wordline contact plug (WLCT) can be wrapped with an insulating spacer (SP), and the first wordline contact plugs (WLCT1) can be insulated from the first drain select line (DSL1) by the insulating spacer (SP).

[0056] The second pad stack (PST2) may include a flat top surface, similar to the first pad stack (PST1). The second contact plugs (CT2) may extend through the second pad stack (PST2) to different depths.

[0057] The first gate line (GL1) and the second gate line (GL2) may belong to the same memory block or to different memory blocks. The first word line pad (WLPD1) of the first word line (WL1) belonging to the first gate line (GL1) and the second word line pad of the second word line belonging to the second gate line (GL2) may be located at the same level, and the first word line contact plug (CT1) and the second word line contact plug connected to the first word line pad (WLPD1) and the second word line pad located at the same level may be electrically connected by the first wiring (ML1). Likewise, the first source contact plug (SCT1) and the second source contact plug connected to the first source pad (SPD1) and the second source pad located at the same level may be electrically connected by the second wiring (ML2).

[0058] According to the structure described above, stacked first gate lines (GL1) can be connected to a first pad stack (PST1), and stacked second gate lines (GL2) can be connected to a second pad stack (PST2). The first gate line (GL1) and the second gate line (GL2) located at the same level can be separated without a slit structure. The first pad (PD1) and the second pad (PD2) located at the same level can be separated by a first slit structure (SLS1). The first pad (PD1) and the second pad (PD2) located at the same level can be connected using wiring (ML1, ML2).

[0060] FIG. 5 is a diagram showing the structure of a semiconductor device according to one embodiment of the present invention.

[0061] Referring to FIG. 5, the semiconductor device may include a first memory block (MB1) and a second memory block (MB2). A memory block may be a unit of an erase operation. The first memory block (MB1) may include a first gate line (G11), a second gate line (G12), a first pad stack (PST11), a second pad stack (PST12), first contact plugs (CT11), and second contact plugs (CT12). The first gate line (G11) and the second gate line (G12) located at the same level may be separated from each other. The first gate lines (GL11) may each be connected to the first pads (PD11), and the first pads (PD11) may each be connected to the first contact plugs (CT11). The second gate lines (GL12) can each be connected to the second pads (PD12), and the second pads (PD12) can each be connected to the second contact plugs (CT12).

[0062] The second memory block (MB2) may include a first gate line (G21), a second gate line (G22), a first pad stack (PST21), a second pad stack (PST22), first contact plugs (CT21), and second contact plugs (CT22). The first gate line (G21) and the second gate line (G22) located at the same level may be separated from each other. The first gate lines (GL21) may be connected to the first pads (PD21), and the first pads (PD21) may be connected to the first contact plugs (CT21). The second gate lines (GL22) may be connected to the second pads (PD22), and the second pads (PD22) may be connected to the second contact plugs (CT22).

[0063] The first memory block (MB1) and the second memory block (MB2) may be adjacent in the second direction (II). The second gate line (GL12) of the first memory block (MB1) and the first gate line (GL21) of the second memory block (MB2) may be adjacent in the second direction (II). A slit structure is not located between the second gate line (GL12) and the first gate line (GL21), and the second gate line (GL12) and the first gate line (GL21), located at the same level, may be electrically separated without a slit structure.

[0064] At the boundary between the first memory block (MB1) and the second memory block (MB2), a second slit structure (SLS2) may be positioned between the second pad stack (PST12) of the first memory block (MB1) and the first pad stack (PST21) of the second memory block (MB2). The second pad stack (PDST12) and the first pad stack (PDST21) may be separated by the second slit structure (SLS2). The second slit structure (SLS2) may not be positioned between the second gate line (GL12) and the first gate line (GL21).

[0065] The first wiring (ML11) may be for connecting word lines located at the same level among the first and second gate lines (GL11, GL12) within the first memory block (MB1). The first wiring (ML12) may be for connecting source select lines located at the same level among the first and second gate lines (GL11, GL12) within the first memory block (MB1). The second wiring (ML21) may be for connecting word lines located at the same level among the first and second gate lines (GL21, GL22) within the second memory block (MB2). The second wiring (ML22) may be for connecting source select lines located at the same level among the first and second gate lines (GL21, GL22) within the second memory block (MB2).

[0066] According to the structure described above, the first gate line (GL11) and the second gate line (GL12) belonging to the first memory block (MB1) can be separated without a separate slit structure. The second gate line (GL12) belonging to the first memory block (MB1) and the first gate line (GL21) belonging to the second memory block (MB2) can be separated without a separate slit structure.

[0068] FIG. 6 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions that overlap with the previously described contents may be omitted.

[0069] Referring to FIG. 6, the semiconductor device may include a substrate (SUB), a transistor (TR), a first interconnection structure (IC1), a first interlayer insulating film (IL1), a source structure (60), gate lines (GL), a stack (ST), a channel structure (CH), a second interconnection structure (IC2), and a second interlayer insulating film (IL2). Peripheral circuits may be located at the bottom of the memory cell array.

[0070] A transistor (TR) may be located on a substrate (SUB). The transistor (TR) may belong to a peripheral circuit. As an example, the peripheral circuit may include a row decoder, a page buffer, an input / output circuit, a logic circuit, etc. The first interconnection structure (IC1) may be formed within the first interlayer insulating film (IL1) and may be electrically connected to the peripheral circuit. The first interconnection structure (IC1) may include vias, wiring, etc.

[0071] A source structure (60) may be positioned on a first interlayer insulating film (IL1), and a stack (ST) may be positioned on the source structure (60). The stack (ST) may include first insulating films (61) and second insulating films (62) that are alternately stacked. Channel structures (CH) may extend through the stack (ST) and may be connected to the source structure (60). The channel structure (CH) may include a channel film (63), a memory film (64), and an insulating core (65). Gate lines (GL) may be stacked along the sidewalls of the channel structures (CH). The gate lines (GL) may include annular portions that surround the channel structures (CH) and line portions that connect the annular portions.

[0072] The second interconnection structure (IC2) may be located within the second interlayer insulating film (IL2) and may be connected to a channel structure (CH), etc. The second interconnection structure (IC2) may include vias, wiring, etc.

[0073] According to the structure described above, the integration density of the semiconductor device can be increased by positioning peripheral circuits at the bottom of the memory cell array. Additionally, since the gate line (GL) includes annular portions and line portions, gate lines (GL) located at the same level can be separated without a slit structure.

[0075] FIG. 7 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention. Hereinafter, descriptions that overlap with the previously described contents may be omitted.

[0076] Referring to FIG. 7, the semiconductor device may include a first semiconductor structure (S1), a second semiconductor structure (S2), and a bonding structure (BS). The first semiconductor structure (S1) may include peripheral circuits, and the second semiconductor structure (S2) may include a memory cell array.

[0077] The first semiconductor structure (S1) may include a substrate (SUB), a transistor (TR), a first interlayer insulating film (IL1), and a first interconnection structure (IC1). The transistor (TR) may belong to a peripheral circuit. The first interconnection structure (IC1) may be located within the first interlayer insulating film (IL1) and may include vias, wiring, etc. The first interconnection structure (IC1) may be electrically connected to a peripheral circuit.

[0078] The second semiconductor structure (S2) may include a source structure (70), a stack (ST), a channel structure (CH), a second interlayer insulating film (IL2), and a second interconnection structure (IC2). The stack (ST) may include first insulating films (71) and second insulating films (72) that are alternately stacked. The source structure (70) may be located on the upper or lower side of the stack (ST). The channel structure (CH) may extend through the stack (ST) and may be connected to the source structure (70). The channel structure (CH) may include a channel film (73), a memory film (74), and an insulating core (75). Gate lines (GL) may be stacked along the sidewalls of the channel structures (CH). The gate lines (GL) may include annular portions that surround the channel structures (CH) and line portions that connect the annular portions.

[0079] A bonding structure (BS) may be located between a first semiconductor structure (S1) and a second semiconductor structure (S2). The first semiconductor structure (S1) and the second semiconductor structure (S2) may be manufactured separately and may be electrically connected by the bonding structure (BS). A memory cell array including gate lines (GL) and a peripheral circuit including a transistor (TR) may be electrically connected through the bonding structure (BS).

[0080] The bonding structure (BS) may include a first bonding film (BL1), a second bonding film (BL2), a first bonding pad (BP1), and a second bonding pad (BP2). The first bonding film (BL1) and the second bonding film (BL2) may be in contact, and the first bonding pad (BP1) and the second bonding pad (BP2) may be in contact. The first bonding film (BL1) and the second bonding film (BL2) may include SiCN, TEOS (Tetra Ethyl Ortho Silicate), etc. The first bonding pad (BP1) may be electrically connected to a first interconnection structure (IC1), and the second bonding pad (BP2) may be electrically connected to a second interconnection structure (IC2). A memory cell array and a peripheral circuit may be electrically connected through the first bonding pad (BP1) and the second bonding pad (BP2).

[0081] According to the structure described above, the first semiconductor structure (S1) and the second semiconductor structure (S2) are bonded vertically, thereby increasing the integration density of the semiconductor device. Additionally, since the gate line (GL) includes annular portions and line portions, gate lines (GL) located on the same layer can be separated without a slit structure.

[0083] FIGS. 8a to 13a and FIGS. 8b to 13b are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure a of each number is a plan view, and figure b of each number is a cross-sectional view EE' of figure a.

[0084] Referring to FIGS. 8a and 8b, a laminate (ST) comprising first insulating films (81) and second insulating films (82) that are alternately stacked can be formed. The first insulating films (81) may comprise a material with a high etching selectivity ratio with respect to the second insulating films (82). As an example, the first insulating films (81) may comprise a nitride and the second insulating film (82) may comprise an oxide.

[0085] Next, first openings (OP1) can be formed through the stack (ST). The first openings (OP1) are used as passages for forming gate lines and may be channel holes in which a channel structure is formed in a subsequent process. Next, first insulating films (81) can be etched through the first openings (OP1) to form second openings (OP2). The second openings (OP2) may surround the first openings (OP1).

[0086] Referring to FIGS. 9a and 9b, sacrificial films (83) may be formed within the first openings (OP1) and the second openings (OP2). The first openings (OP1) and the second openings (OP2) may be filled by the sacrificial films (83). The sacrificial film (83) may include a first portion (83A) within the first opening (OP1) and second portions (83B) within the second openings (OP2). The sacrificial films (83) may include a material with a high etch selectivity ratio with respect to the first and second insulating films (81, 82). As an example, the sacrificial films (83) may include a carbon film and / or a tungsten film.

[0087] Referring to FIG. 10a and FIG. 10b, at least one trench (T) can be formed within at least one of the sacrificial membranes (83). Sacrificial membranes (83) arranged in a first direction (I) may form a column, and trenches (T) may be formed in some of the columns among the sacrificial membranes (83) arranged in multiple columns. As an example, the sacrificial membranes (83) may be grouped into first to third columns (CL1 to CL3). Sacrificial membranes (83) belonging to the first column (CL1) may be arranged along the first direction (I). Sacrificial membranes (83) belonging to the second column (CL2) may be arranged staggered with respect to the sacrificial membranes (83) of the first column (CL1). The sacrificial membranes (83) belonging to the third column (CL3) may be arranged alternately with the sacrificial membranes (83) of the second column (CL2). When connecting the first to third columns (CL1~CL3) to form a gate line, trenches (T) may be formed only on the sacrificial membranes (83) belonging to the second column (CL2), excluding the first and third columns (CL1, CL3) located at the edge.

[0088] A trench (T) may be formed within a single sacrificial membrane (83). The trench (T) may have a radial shape extending from the center of the sacrificial membrane (83) toward surrounding sacrificial membranes (83). As an example, six sacrificial membranes (83) may be located around a single sacrificial membrane (83), and the trench (T) may have a shape extending in six directions from the center of the sacrificial membrane (83). The trench (T) may be located in a first part (83A) within the sacrificial membrane (83) and may not be located in a second part (83B). In a plane, the second part (83B) may be exposed through the end of the trench (T) extending toward surrounding sacrificial membranes (83).

[0089] Referring to FIGS. 11a and 11b, the sacrificial film (83) can be etched through the trench (T) to expose the first insulating films (81). The second portions (83B) can be selectively etched through the trench (T), and the first insulating films (81) can be partially exposed. Subsequently, the first insulating film (81) can be selectively etched to expose the surrounding sacrificial film (83). Through this, third openings (OP3) connecting the second openings (OP2) can be formed, and the second portions (83B) of the surrounding sacrificial films (83) can be exposed through the third openings (OP3).

[0090] Referring to FIGS. 12a and 12b, the sacrificial membranes (83) can be removed. By doing so, the first and second openings (OP1, OP2) can be reopened, and the second openings (OP2) can be interconnected through the third openings (OP3).

[0091] Next, gate lines (84) can be formed within the second openings (OP2) and the third openings (OP3). A conductive film can be deposited within the second openings (OP2) and the third openings (OP3) through the first opening (OP1), and the portion of the conductive film formed within the first opening (OP1) can be etched to form the gate lines (84). The gate lines (84) may include annular portions (84A) within the second openings (OP2) and line portions (84B) within the third openings (OP3). The annular portions (84A) may be connected by the line portions (84B). The gate lines (84) may include a metal such as tungsten or molybdenum.

[0092] Referring to FIG. 13a and FIG. 13b, channel structures (CH) can be formed within the first openings (OP1). A memory film (86), a channel film (85), and an insulating core (87) can be formed within the first openings (OP1). As an example, a first blocking film can be formed within the first openings (OP1), a second blocking film, a data storage film, and a tunneling film can be formed on the first blocking film, and a channel film (85) can be formed on the tunneling film.

[0093] According to the manufacturing method described above, first and second openings (OP1, OP2) can be formed using channel holes, and third openings (OP3) connecting the second openings (OP2) can be formed using trenches (T). Through this, gate lines (84) connecting annular sections (84A) and line sections (84B) connecting the annular sections (84A) can be formed. The annular sections (84A) connected by the line sections (84B) can form a single gate line (84), and the annular sections (84A) not connected by the line sections (84B) belong to different gate lines (84). Thus, mutually separated gate lines (84) can be formed without a slit structure.

[0095] FIGS. 14a to 18a and FIGS. 14b to 18b are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure a of each number is a plan view, and figure b of each number is a cross-sectional view of figure a'.

[0096] Referring to FIGS. 14a and 14b, a laminate (ST) can be formed comprising first insulating films (91) and second insulating films (92) that are alternately stacked. The laminate (ST) may include a cell region (CR) and a pad region (PR).

[0097] Next, first openings (OP1) can be formed extending through the cell region (CR) of the stack (ST). Next, second openings (OP2) can be formed by etching the first insulating films (81) through the first openings (OP1). The second openings (OP2) can surround the first openings (OP1).

[0098] Referring to FIGS. 15a and 15b, the first insulating films (91) can be etched through the second openings (OP2) to form third openings (OP3) that connect adjacent second openings (OP2). As an example, the third openings (OP3) can be formed by forming sacrificial films within the first and second openings (OP1, OP2), forming trenches within the sacrificial films, and etching the sacrificial films and the first insulating films (91) through the trenches.

[0099] Referring to FIGS. 16a and 16b, gate lines (94) can be formed within the second openings (OP2) and the third openings (OP3). The gate lines (94) may include annular sections (94A) within the second openings (OP2) and line sections (94B) within the third openings (OP3). The annular sections (94A) may be connected by the line sections (94B). Subsequently, channel structures (CH) can be formed within the first openings (OP1). A memory film (96), a channel film (95), and an insulating core (97) can be formed within the first openings (OP1).

[0100] Referring to FIG. 17a and FIG. 17b, a stack (ST) can be patterned into a step shape. As an example, a mask pattern can be formed on the stack (ST), and the stack (ST) can be etched using the mask pattern as an etching barrier. A step shape can be formed by alternately repeating the mask reduction process and the etching process. Subsequently, an interlayer insulating film (98) can be formed on the stack (ST).

[0101] Next, a slit (SL) can be formed in the pad region (PR) of the laminate (ST). The slit (SL) may extend along the first direction (I) and may not be formed in the cell region (CR).

[0102] Referring to FIG. 18a and FIG. 18b, the first insulating films (91) can be replaced with pads (99) through the slit (SL). As an example, the first insulating films (91) can be removed through the slit (SL), and conductive films can be formed in the regions where the first insulating films (91) have been removed. The conductive films may include metals such as tungsten or molybdenum. Through this, pads (99) connected to gate lines (94) can be formed. Subsequently, a slit structure (SLS) can be formed within the slit.

[0103] Next, contact plugs (CTs) connected to each of the pads (99) can be formed. The contact plugs (CTs) can be extended to different depths through the interlayer insulating film (98). Next, wiring can be formed to connect the contact plugs (CTs) connected to the pads (99) located at the same level.

[0104] For reference, in this embodiment, the case in which the stack (ST) is patterned in a stepped shape has been described, but the present invention is not limited thereto. It is also possible to form contact plugs (CT) so that the stack (ST) maintains a flat upper surface and extends through the stack (ST). In this embodiment, the case in which pads (99) are formed after gate lines (84) have been described has been described, but the present invention is not limited thereto, and the process sequence described above may be changed. As an example, it is also possible to form pads (99) before forming gate lines (84).

[0105] According to the manufacturing method described above, gate lines (94) can be formed using channel holes, and the gate lines (94) can be separated from each other without a slit structure. Additionally, by forming a slit only in the pad area (PR), pads (99) connected to each of the gate lines (94) can be formed.

[0107] The structure and manufacturing method according to the aforementioned embodiments can be applied to semiconductor devices of various structures. FIGS. 19 and 20 show a schematic configuration of a semiconductor device to which the aforementioned embodiments can be applied.

[0109] FIG. 19 is a configuration diagram of a semiconductor device according to one embodiment of the present invention.

[0110] Referring to FIG. 19, a semiconductor device may include a substrate (SUB), a peripheral circuit (PC), and a memory cell array (CA). Here, the peripheral circuit (PC) and the memory cell array (CA) may be formed on the same substrate.

[0111] The substrate (SUB) may include a semiconductor material. As an example, the semiconductor material may include at least one of a group IV semiconductor, a group III-V compound semiconductor, and a group II-VI compound semiconductor. Here, the group IV semiconductor may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon germanium (SiGe). The group III-V compound semiconductor may include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. The group II-VI compound semiconductor may include ZnS, ZnO, or CdS.

[0112] The substrate (SUB) may include a dielectric film. The substrate (SUB) may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate (SUB) may include an organic material. As an example, the substrate (SUB) may include graphene.

[0113] The substrate (SUB) may be a bulk wafer or an epitaxial film grown by selective epitaxial growth (SEG). The substrate (SUB) may be a film formed by Metal Induced Lateral Crystallization (MILC) and may partially contain metal. The substrate (SUB) may have a single-crystal, polycrystalline, or amorphous state. The substrate (SUB) may contain impurities of Group II, Group III, Group IV, Group V, or Group VI. As an example, the substrate (SUB) may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0114] Peripheral circuitry (PC) may be located between a substrate (SUB) and a memory cell array (CA). Peripheral circuitry (PC) may include a row decoder, a column decoder, a page buffer, a logic circuit, a control circuit, a sense amplifier, an input / output circuit, etc. As an example, peripheral circuitry (PC) may include an NMOS transistor, a PMOS transistor, a register, a capacitor, etc. Peripheral circuitry (PC) may further include an interconnection structure. The interconnection structure may be used as a path for transmitting an operating voltage and may include a contact plug, wiring, etc.

[0115] A memory cell array (CA) may include memory cells. As an example, the memory cell array (CA) may include memory strings connected between a source line and a bit line, and each memory string may include stacked memory cells. As an example, the memory cell array (CA) may include memory cells connected between a word line and a bit line. The memory cell array (CA) may further include an interconnection structure.

[0117] FIG. 20 is a configuration diagram of a semiconductor device according to one embodiment of the present invention.

[0118] Referring to FIG. 20, the semiconductor device may include a substrate (SUB), a peripheral circuit (PC), a bonding structure (BS), and a memory cell array (CA). Here, the peripheral circuit (PC) and the memory cell array (CA) may be bonded after being formed on separate substrates, respectively. The semiconductor device may further include a support base (SP_B).

[0119] The substrate (SUB) may be used as a support during the process of forming the peripheral circuit (PC). The support base (SP_B) may be used as a support during the process of forming the memory cell array (CA). As an example, after manufacturing a first wafer containing the memory cell array (CA) and a second wafer containing the peripheral circuit (PC), the first wafer and the second wafer may be electrically connected by a bonding structure (BS). After bonding, the support base (SP_B) of the first wafer may be removed at least partially. The support base (SP_B) may be completely removed or may remain partially on the memory cell array (CA).

[0120] The support base (SP_B) may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GEOI) substrate, etc. The support base (SP_B) may be a bulk wafer, an epitaxial film grown by selective epitaxial growth (SEG), or a film formed by metal-induced lateral crystallization (MILC). The support base (SP_B) may have a single-crystal, polycrystalline, or amorphous state. The support base (SP_B) may contain impurities of Group II, Group III, Group IV, Group V, or Group VI.

[0121] The bonding structure (BS) may be intended to connect a memory cell array (CA) and a peripheral circuit (PC). As an example, the memory cell array (CA) and the peripheral circuit (PC) may be bonded using a wafer-on-wafer bonding method, a chip-on-wafer bonding method, a chip-on-chip bonding method, etc. The bonding structure (BS) may include bonding pads, a bonding film, a bonding interface, etc. The bonding pads may include metals and / or alloys such as copper or aluminum. The bonding interfaces may include non-metal-non-metal interfaces, metal-metal interfaces, etc. The memory cell array (CA) and the peripheral circuit (PC) may be electrically connected by the bonding structure (BS).

[0122] For reference, it is also possible for interconnection structures included in the memory cell array (CA) and / or peripheral circuit (PC) to be directly connected without bonding pads. As an example, a bonding film included in the memory cell array (CA) and a bonding film included in the peripheral circuit (PC) can be bonded to form a bonding interface, and an interconnection structure included in the memory cell array (CA) and an interconnection structure included in the peripheral circuit (PC) can be directly connected. Through this, contact plugs, wiring, etc. formed on different wafers can be electrically connected without separate bonding pads.

[0123] Other configurations may be the same or similar as those described earlier with reference to FIG. 19.

[0124] Meanwhile, the semiconductor device may have a structure that combines the embodiments described above with reference to FIGS. 19 and 20, or a partially modified structure. In the embodiments described with reference to FIGS. 19 and 20, the positions of the memory cell array (CA) and the peripheral circuit (PC) may be changed. In the embodiments described with reference to FIGS. 19 and 20, at least one memory cell array (CA) and / or at least one peripheral circuit (PC) may be additionally bonded. As an embodiment, a part of the peripheral circuit (PC) may be located within the memory cell array (CA).

[0126] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, this is merely for the purpose of explaining embodiments according to the concept of the present invention, and the present invention is not limited to the above embodiments. Within the scope of the technical concept of the present invention, various forms of substitution, modification, change, and combination of the embodiments may be made by those skilled in the art to which the present invention belongs, and such are also to be considered to be within the scope of the present invention. Explanation of the symbols

[0127] 11: First insulating layer 12: Second insulating layers 13A: 1st channel membrane 13B: Second channel membrane 14A: 1st memory layer 14B: Second Memory Sheet 15A: First insulation core 15B: Second insulation core 21: First insulating layer 23: Channel Block 24: Memory Mark 25: Insulation core 31: First insulating layer 32: Second insulating layer 33A: 1st channel membrane 34A: 1st memory layer 35A: 1st insulation core 41: First insulating layer 42: Second insulating layer 43A: 1st channel membrane 44A: 1st memory layer 45A: 1st insulation core 60: Source structure 61: First insulating layer 62: Second insulating layer 63: Channel Block 64: Memory Sheet 65: Insulation core 70: Source structure 71: First insulating layer 72: Second insulating layer 73: Channel Block 74: Memory film 75: Insulating core 81: First insulating layer 82: Second insulating layer 83: Sacrifice screen 84: Gate Line 84A: Annular part 84B: Line section 85: Channel Block 86: Memory film 87: Insulation core 91: First insulating layer 92: Second insulating layer 94: Gate Line 94A: Annular part 94B: Line section 95: Channel Block 96: Memory Mark 97: Insulation core 98: Interlayer insulation film 99: Pad

Claims

Claim 1 A semiconductor device comprising: a laminate including first insulating films and second insulating films alternately stacked; channel structures extending through the laminate; and gate lines positioned between the channel structures and the first insulating films, each including annular portions surrounding the channel structures and line portions connecting the annular portions. Claim 2 In claim 1, the above line portions are a semiconductor device that connects the above annular portions in a radial form. Claim 3 A semiconductor device according to claim 1, further comprising a pad stack including alternately stacked pads and insulating films; and contact plugs each connected to the pads, wherein the pads and the gate lines are each connected. Claim 4 In paragraph 3, the above pads are stacked in a stepped form in a semiconductor device. Claim 5 In paragraph 3, the pad stack comprises a flat upper surface, and the contact plugs extend through the pad stack to different depths in a semiconductor device. Claim 6 A semiconductor device according to claim 1, wherein the gate lines comprise at least one source selection line; at least one drain selection line; and word lines stacked between the at least one source selection line and the at least one drain selection line. Claim 7 A semiconductor device comprising: first channel structures arranged in a first direction and a second direction intersecting the first direction; first word lines stacked along the side walls of the first channel structures, each including first annular portions surrounding the first channel structures and first line portions connecting the first annular portions; second channel structures arranged in the first direction and the second direction; second word lines stacked along the side walls of the second channel structures, each including second annular portions surrounding the second channel structures and second line portions connecting the second annular portions; a first pad stack including first word line pads connected to the first word lines; and a second pad stack including second word line pads connected to the second word lines. Claim 8 A semiconductor device according to claim 7, wherein the distance between the centers of the first channel structures is a first distance, the distance between the centers of the second channel structures is a second distance, the distance between the centers of adjacent first channel structures and second channel structures is a third distance, and the third distance is substantially the same as the first distance. Claim 9 In paragraph 8, the first distance, the second distance, and the third distance are substantially the same semiconductor device. Claim 10 A semiconductor device according to claim 7, wherein the distance between the centers of the first annular portions is a first distance, the distance between the centers of the second annular portions is a second distance, the distance between the centers of adjacent first and second annular portions is a third distance, and the third distance is substantially the same as the first distance. Claim 11 In paragraph 10, the first distance, the second distance, and the third distance are substantially the same semiconductor device. Claim 12 A semiconductor device according to claim 9, further comprising: first wordline contact plugs each connected to the first wordline pads; and second wordline contact plugs each connected to the second wordline pads. Claim 13 In claim 12, the first pad stack comprises a flat upper surface, and the first wordline contact plugs extend through the first pad stack to different depths in a semiconductor device. Claim 14 A semiconductor device according to claim 12, further comprising wiring connecting a first wordline contact plug and a second wordline contact plug connected to a first wordline pad and a second wordline pad located at the same level. Claim 15 In claim 7, the first wordline pads are a semiconductor device stacked in a stepped shape. Claim 16 A semiconductor device according to claim 7, further comprising a slit structure located between the first pad stack and the second pad stack. Claim 17 In claim 7, the first word lines and the second word lines belong to the same memory block, and the first word line and the second word line located at the same level are electrically connected in a semiconductor device. Claim 18 In claim 7, the first word lines and the second word lines belong to different memory blocks, and the first word line and the second word line located at the same level are electrically separated semiconductor devices. Claim 19 A semiconductor device according to claim 7, further comprising a first drain selection line including third annular portions that each surround the first channel structures and third line portions that connect the third annular portions. Claim 20 In claim 19, the semiconductor device further comprises a first drain pad connected to the first drain selection line in the first pad stack. Claim 21 A semiconductor device according to claim 7, further comprising a first source selection line including fourth annular portions that each surround the first channel structures and fourth line portions that connect the fourth annular portions. Claim 22 A semiconductor device according to claim 21, wherein the first pad stack further comprises a first source pad connected to the first source selection line. Claim 23 A method for manufacturing a semiconductor device comprising: forming a stack including first insulating films and second insulating films that are alternately stacked; forming first openings extending through the stack; etching the first insulating films through the first openings to form second openings that surround the first openings; forming sacrificial films within the first openings and the second openings; forming at least one trench within at least one of the sacrificial films; etching the first insulating films through the at least one trench to form third openings that connect the second openings; and forming gate lines within the second openings and the third openings. Claim 24 A method for manufacturing a semiconductor device according to claim 23, wherein each of the gate lines comprises annular portions located within the second openings and line portions located within the third openings. Claim 25 A method for manufacturing a semiconductor device according to claim 23, wherein at least one trench has a radial shape extending from the center of a sacrificial membrane toward surrounding sacrificial membranes. Claim 26 A method for manufacturing a semiconductor device according to claim 23, wherein six sacrificial membranes are positioned around at least one sacrificial membrane, and the trench has a radial shape extending toward the six sacrificial membranes. Claim 27 In claim 26, a method for manufacturing a semiconductor device wherein at least one sacrificial membrane is connected to six sacrificial membranes by six third openings. Claim 28 A method for manufacturing a semiconductor device according to claim 23, further comprising the step of removing the sacrificial films after forming the third openings. Claim 29 A method for manufacturing a semiconductor device according to claim 23, further comprising the step of forming channel structures within the first openings. Claim 30 A method for manufacturing a semiconductor device according to claim 23, wherein the sacrificial membranes comprise: a first column comprising first sacrificial membranes arranged along the first direction; a second column comprising second sacrificial membranes arranged alternately with the first sacrificial membranes; and a third column comprising third sacrificial membranes arranged alternately with the second sacrificial membranes. Claim 31 In claim 30, the step of forming at least one trench is a method for manufacturing a semiconductor device that forms at least one trench such that each of the second sacrificial films is located within the trench. Claim 32 A method for manufacturing a semiconductor device comprising: forming a stack including first insulating films and second insulating films that are alternately stacked; forming first openings extending through a cell region of the stack; etching the first insulating films through the first openings to form second openings; etching the first insulating films through the second openings to form third openings connecting adjacent second openings; forming gate lines including annular portions located within the second openings and line portions located within the third openings; forming a slit in a pad region of the stack; and replacing the first insulating films in the pad region with pads through the slit. Claim 33 A method for manufacturing a semiconductor device according to claim 32, further comprising the step of forming contact plugs connected to each of the pads. Claim 34 A method for manufacturing a semiconductor device according to claim 33, further comprising the step of forming wiring that connects contact plugs connected to pads located at the same level. Claim 35 A method for manufacturing a semiconductor device according to claim 32, further comprising the step of forming channel structures within the first openings. Claim 36 A method for manufacturing a semiconductor device according to claim 32, further comprising the step of forming a slit structure within the slit.

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