Storage device and operating method of the same
Patent Information
- Application Number
- KR1020250097093
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-25
- Filing Date
- 2025-07-18
- Publication Date
- 2026-09-01
Smart Images
Figure PAT00002_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to a storage device and a method of operating the same, and more specifically, to a storage device and a method of operating the same that allocates a portion of a cache memory for data stored in another cache memory. Background Technology
[0003] Memory devices store data upon write requests and output stored data upon read requests. For example, memory devices are classified into volatile memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), in which stored data is lost when the power supply is cut off, and non-volatile memory devices, such as flash memory devices, PRAM (Phase-change RAM), MRAM (Magnetic RAM), and RRAM (Resistive RAM), which retain stored data even when the power supply is cut off.
[0004] A memory device can update mapping information between logical and physical addresses based on write requests and logical addresses received from a host device. However, the space of the cache memory storing mapping information is limited, and the map update operation of flushing the mapping information stored in the cache memory can cause overhead and degrade the durability of the memory device. Therefore, a technique to increase the cycle of the map update operation may be required. The problem to be solved
[0006] An embodiment of the present invention provides a storage device that allocates a portion of a cache memory for data stored in another cache memory, and a method of operating the same. means of solving the problem
[0008] According to one embodiment of the present invention, a storage device is provided. The storage device comprises a first memory device for storing data, a second memory device including a first cache memory for storing mapping information and a second cache memory for storing segments, and a memory controller configured to update the mapping information in response to a write request received from an external host device, wherein the memory controller is configured to allocate a first region among the regions of the second cache memory for the mapping information in response to determining that the size of the workload corresponding to the write request is smaller than or equal to a first threshold value.
[0009] According to one embodiment of the present invention, a storage device is provided. The storage device comprises a first memory device for storing data, a second memory device including a first cache memory for storing mapping information and a second cache memory for storing segments, and a memory controller configured to allocate a first region among the regions of the second cache memory for the mapping information, wherein the memory controller is configured to determine whether there is a cache hit of a segment corresponding to the write request in response to receiving a write request from an external host device, modify the segment in response to a cache hit of the segment, and update the mapping information in response to a cache miss of the segment.
[0010] According to one embodiment of the present invention, a method of operation of a storage device is provided. The method of operation includes the steps of: allocating a first region among regions of a second cache memory that stores segments for the mapping information of a first cache memory that stores mapping information; receiving a write request from an external host device; determining whether there is a cache hit of a segment corresponding to the write request within the first region in response to receiving the write request; modifying the segment in response to a cache hit of the segment; and updating the mapping information in response to a cache miss of the segment. Effects of the invention
[0012] According to one embodiment of the present technology, a storage device that allocates a portion of a cache memory for data stored in another cache memory and a method of operating the same are provided.
[0013] In addition, a storage device and a method of operation thereof are provided, which increase the map update cycle and provide improved write performance by allocating a portion of another cache memory for workloads satisfying locality conditions. Brief explanation of the drawing
[0015] FIG. 1 is a block diagram of an electronic system according to one embodiment of the present invention. FIG. 2 is a block diagram of a storage device according to one embodiment of the present invention. FIG. 3 is a flowchart illustrating a method of operation of a storage device according to an embodiment of the present invention. FIG. 4 is a drawing illustrating a storage device according to some embodiments of the present invention. FIG. 5 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. FIG. 6 is a drawing illustrating a storage device according to some embodiments of the present invention. FIG. 7 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. FIG. 8 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. FIG. 9 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. FIG. 10 is a drawing illustrating a second memory device according to some embodiments of the present invention. FIG. 11 is a block diagram of a memory card system to which a storage device according to some embodiments of the present invention is applied. FIG. 12 is a drawing illustrating an electronic system according to some embodiments of the present invention. Specific details for implementing the invention
[0016] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the embodiments of the present invention.
[0017] In the following, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another.
[0019] FIG. 1 is a block diagram of an electronic system according to an embodiment of the present invention. Referring to FIG. 1, the electronic system (10) may be a computing system configured to process various information or to store processed information as data. In some embodiments, the electronic system (10) may be implemented as a personal computer (PC), notebook, laptop, server, workstation, tablet PC, smartphone, digital camera, black box, etc.
[0020] The electronic system (10) may include a host device (11) and a storage device (100). The host device (11) can control the general operations of the electronic system (10). More specifically, the host device (11) can control the operations of other components constituting the electronic system (10). The host device (11) may be implemented as a general-purpose processor, a dedicated processor, or an application processor (AP).
[0021] A host device (11) can communicate with a storage device (100). For example, the host device (11) can request a program operation, a read operation, an erase operation, etc. from the storage device (100). The host device (11) can transmit a host request (REQ), data (DATA), and a logical address (ADD) to the storage device (100) for a program operation of the storage device (100). For example, the host device (11) can transmit a host request (REQ) and a logical address (ADD) to the storage device (100) for a write operation of the storage device (100). The set of host requests (REQ), data (DATA), and logical addresses (ADD) provided by the host device (11) to the storage device (100) can be referred to as a workload.
[0022] In some embodiments, a host request (REQ) for a write operation (or write request) may refer to a sequential write operation or a random write operation. A sequential write operation may be an operation in which data with consecutive logical addresses is written sequentially to the storage device (100). Additionally, a random write operation may be an operation in which data with non-consecutive logical addresses is written to the storage device (100).
[0023] The storage device (100) can store data. For example, it can store data under the control of the host device (11). In some embodiments, the storage device (100) may include at least one of a Solid State Device (SSD), embedded memory, and removable external memory. When the storage device (100) is an SSD, the storage device (100) may be a device that follows the Non-Volatile Memory Express (NVMe) standard. When the storage device (100) is embedded memory or removable external memory, the storage device (100) may be a device that follows the Universal Flash Storage (UFS) or embedded Multi-Media Card (eMMC) standard. The host device (11) and the storage device (100) may each generate packets based on the adopted standard protocol and transmit the generated packets to each other.
[0024] The storage device (100) may include a memory controller (110), a first memory device (120), and a second memory device (130). The memory controller (110) may control the operation of the storage device (100). For example, the memory controller (110) may control the operation of the storage device (100) according to an internal policy or in response to a host request (REQ). The memory controller (110) may store data (DATA) in the first memory device (120) or read data (DATA) stored in the first memory device (120) according to an internal policy or in response to a host request (REQ).
[0025] The memory controller (110) may generate a program command in response to a host request (REQ) corresponding to a program operation received from the host device (11) and provide the generated program command to the first memory device (120). The memory controller (110) may generate a write command in response to a host request (REQ) corresponding to a write operation received from the host device (11) and provide the generated write command to the first memory device (120).
[0026] The memory controller (110) can store mapping information between a logical address (ADD) and a physical address in a second memory device (130) and update the mapping information in response to a write request. For example, the memory controller (110) can provide a write command, a physical address, and data (DATA) to the first memory device (120) in response to a write request and update the mapping information between the logical address (ADD) and the physical address in the second memory device (130). In some embodiments, the mapping information stored in the second memory device (130) may include P2L (physical to logical) mapping information.
[0027] The memory controller (110) can perform a map update operation. For example, the memory controller (110) can perform a map update operation that flushes mapping information stored in the second memory device (130) to the first memory device (120) and erases mapping information stored in the second memory device (130). The map update operation may cause significant overhead and a decrease in the durability of the second memory device (130).
[0028] The memory controller (110) may perform a map update operation in response to various factors. For example, the memory controller (110) may perform a map update operation in response to a determination that there is insufficient additional space to update mapping information within the second memory device (130). Accordingly, the size of the space within the second memory device (130) for storing mapping information may be directly related to the cycle of the map update operation and, consequently, to the performance of the storage device (100) or electronic system (10) and the durability of the storage device (100). Therefore, within the limited space of the second memory device (130), it is necessary to secure additional space or area for mapping information.
[0029] A more detailed description of the memory controller (110) securing additional space or area for mapping information will be described later with reference to FIGS. 2 through 9.
[0030] The first memory device (120) can store data (DATA) under the control of the memory controller (110). For example, the first memory device (120) can store metadata including user data received from the host device (11) and mapping information or segments received from the second memory device (130) by a map update operation.
[0031] The first memory device (120) may be a non-volatile memory device such as NAND Flash memory, but the scope of the invention is not limited thereto. The first memory device (120) may be one of various devices capable of retaining stored data even when the power supply is cut off, such as PRAM (Phase-change Random Access Memory), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory), etc.
[0032] The second memory device (130) can store mapping information or segments under the control of the memory controller (110). In some embodiments, the second memory device (130) can temporarily store mapping information between a logical address (ADD) and a physical address, and provide the stored mapping information to the first memory device (120) by a map update operation.
[0033] The second memory device (130) may be one of various devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), etc.
[0034] Because the operating speed of the second memory device (130) (e.g., the speed of a write operation or the speed of a read operation) is relatively faster than the operating speed of the first memory device (120), the memory controller (110) can quickly store or update mapping information in the second memory device (130). Accordingly, the storage device (100) can use a portion of the second memory device (130) to cache mapping information. A more detailed explanation of this will be given later with reference to FIGS. 2 and FIGS. 3.
[0035] In FIG. 1, the second memory device (130) is exemplarily described as being placed outside the memory controller (110), but the scope of the invention is not limited thereto. The second memory device (130) may be included within the memory controller (110).
[0037] FIG. 2 is a block diagram of a storage device according to an embodiment of the present invention. Referring to FIG. 2, the storage device (100) may include a memory controller (110), a first memory device (120), and a second memory device (130). Since the memory controller (110), the first memory device (120), and the second memory device (130) of FIG. 2 are similar to the memory controller (110), the first memory device (120), and the second memory device (130) of FIG. 1, a redundant description thereof will be omitted below.
[0038] The second memory device (130) may include a first cache memory (131) and a second cache memory (132). The first cache memory (131) may store mapping information (MP), and the second cache memory (132) may store segments (e.g., L2 segments) (SG).
[0039] For the sake of understanding the present invention, the first cache memory (131) and the second cache memory (132) are illustrated as different cache memories, but the scope of the present invention is not limited thereto. The first cache memory (131) and the second cache memory (132) may be implemented as a single cache memory. Additionally, the second memory device (130) may include at least two or more cache memories as needed. A more detailed description of an embodiment in which the first cache memory (131) and the second cache memory (132) are implemented as a single cache memory will be given later with reference to FIG. 10.
[0040] In some embodiments, the first cache memory (131) may be used as a cache area for storing mapping information (MP) for a write operation of the storage device (100), and the second cache memory (132) may be used as a cache area for storing segments (SG) for a read operation of the storage device (100). For example, the first cache memory (131) may store and update mapping information (MP) between the physical address and the logical address (ADD) of data (DATA) to be stored in the first memory device (120), and the second cache memory (132) may cache segments (SG) of data to be read from the first memory device (120).
[0041] The memory controller (110) may use a portion of the second cache memory (132) to process write requests (WREQ) (or a workload of write requests (WREQ)). For example, when requests received from the host device (11) are mainly write requests (WREQ) or the workload of read requests is small, the memory controller (110) may allocate a portion of the regions of the second cache memory (132) (e.g., first and second regions (R1, R2)) (e.g., first region (R1)) for mapping information (MP), load segments corresponding to write requests (WREQ), and cache them. The write requests and read requests may be host requests (REQ) of FIG. 1 indicating a write operation and a read operation, respectively.
[0042] In some embodiments, the sizes of the regions of the second cache memory (132) (e.g., first and second regions (R1, R2)) may be varied as needed. Additionally, the second memory device (130) may include at least three cache memories, and the memory controller (110) may, for example, allocate at least one of the at least three cache memories as the first region (R1).
[0043] In some embodiments, the memory controller (110) may, instead of updating the mapping information (MP) stored in the first cache memory (131) based on the write request (WREQ), load a segment corresponding to the write request (WREQ) into the first area (R1) or modify a segment that is already loaded. By allocating the first area (R1) for the mapping information (MP) (i.e., by loading or modifying a segment corresponding to the write request (WREQ) into the first area (R1) instead of updating the mapping information (MP)), the memory controller (110) can process more write requests (WREQ) and their workload until all available space in the first cache memory (131) is exhausted (i.e., until all space for updating the mapping information (MP) is exhausted). Thus, the update frequency of the mapping information (MP) is reduced, and the cycle of the map update operation can be increased.
[0044] However, if the memory controller (110) indiscriminately allocates a portion of the first cache memory (131) (e.g., the first area (R1)) for mapping information (MP), it may cause performance degradation of the storage device (100). For example, if the workload of write requests (WREQ) has low locality (i.e., if the number of segments corresponding to the write requests (WREQ) is large or the size of the workload exceeds a threshold), not all segments corresponding to the write requests (WREQ) can be loaded into the first area (R1), and thus map update operations may occur more frequently. Therefore, since the memory controller (110) must perform map update operations at a shorter interval than when it does not allocate a portion of the first cache memory (131) (e.g., the first area (R1)) for mapping information (MP), the performance of the storage device (100) may be further degraded.
[0045] Accordingly, the memory controller (110) performs a comparison operation of the size and threshold of the workload corresponding to the write request (WREQ) and, based on the result of the comparison operation, may selectively allocate a portion of the first cache memory (131) (e.g., a first region (R1)) for mapping information (MP). For example, the memory controller (110) may allocate a portion of the first cache memory (131) (e.g., a first region (R1)) for mapping information (MP) in response to a determination that the size of the workload corresponding to the write request (WREQ) is smaller than or equal to the threshold (i.e., that the locality is greater).
[0046] Additionally, the memory controller (110) deals off a portion of the first cache memory (131) (e.g., the first region (R1)) in response to determining that the size of the workload corresponding to the write request (WREQ) is greater than a threshold value, and the segments corresponding to the write request (WREQ) can no longer be loaded or modified in the deallocated first region (R1). A more detailed explanation of this will be given later with reference to FIG. 3.
[0048] FIG. 3 is a flowchart illustrating a method of operation of a storage device according to an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, a memory controller (110) may selectively allocate a portion of a first cache memory (131) (e.g., a first region (R1)) for mapping information (MP) based on the result of a comparison operation of the size of a workload and a threshold value corresponding to a write request (WREQ).
[0049] In step S110, the memory controller (110) may receive a write request (WREQ) from an external host device (11). In some embodiments, the write request (WREQ) may correspond to one or more logical addresses. That is, the workload corresponding to the write request (WREQ) may include at least one logical address. At least one logical address may correspond to at least one segment.
[0050] In step S120, the memory controller (110) can determine whether the size of the workload corresponding to the write request (WREQ) is smaller than or equal to the first threshold value (TH1). For example, the memory controller (110) can determine the number of segments (i.e., the size of the workload) corresponding to the write request (WREQ) based on the write request (WREQ) and the logical address (ADD) received from an external host device (11), and determine the locality of the workload corresponding to the write request (WREQ) by determining whether the number of segments or the size of the workload is smaller than or equal to the first threshold value (TH1). If the number of segments (or the size of the workload) is small, the locality of the workload corresponding to the write request (WREQ) is large, and if the number of segments is large, the locality may be small.
[0051] In step S130, the memory controller (110) may allocate a first region (R1) for mapping information (MP) in response to determining that the size of the workload is smaller than or equal to a first threshold value (TH1) (i.e., that the locality is large). For example, the memory controller (110) may allocate a first region (R1) among the regions of the second cache memory (132) (e.g., first and second regions (R1, R2)) for mapping information (MP).
[0052] In some embodiments, the memory controller (110) stores data (DATA) corresponding to a write request (WREQ) in the first memory device (120), and loads the segment corresponding to the write request (WREQ) into the first area (R1), or modifies the already loaded segment.
[0053] In some embodiments, the memory controller (110) may update mapping information (MP) corresponding to a write request (WREQ) in the first cache memory (131) in response to determining that the size of the workload is greater than the first threshold value (TH1) (i.e., that locality is small).
[0054] In some embodiments, the memory controller (110) may determine whether the first area (R1) is in an allocable state as a requirement for allocating the first area (R1) for mapping information (MP). If the first area (R1) is in an allocable state, the memory controller (110) may allocate the first area (R1) for mapping information (MP). However, if the first area (R1) is not in an allocable state (i.e., in an unallocable state), the memory controller (110) may not allocate the first area (R1) for mapping information (MP) until the first area (R1) becomes allocable again. A more detailed description of the allocable state of the first area (R1) will be given later with reference to FIGS. 6 and 7.
[0056] FIG. 4 is a diagram illustrating a storage device according to some embodiments of the present invention. Referring to FIG. 2 and FIG. 4, the memory controller (110) can modify a segment or update mapping information (MP) depending on whether there is a cache hit in the first region (R1).
[0057] In response to receiving a write request (WREQ) from an external host device (11), the memory controller (110) may load a segment corresponding to the write request (WREQ) into the first area (R1) or modify a segment already loaded in the first area (R1). In some embodiments, the operation of loading a segment into the first area (R1) may require a greater overhead than the operation of modifying a segment already loaded in the first area (R1). Therefore, when a segment corresponding to the write request (WREQ) is not loaded into the first area (R1), the operation of updating mapping information (MP) in the first cache memory (131) may require a shorter write time than the operation of loading a segment into the first area (R1), and consequently provide better write performance.
[0058] In some embodiments, the memory controller (110) determines whether there is a cache hit for a segment corresponding to a write request (WREQ), and if there is a cache miss (i.e., if the segment corresponding to the write request is not loaded in the first area (R1), it can first update the mapping information (MP) and then load the segment into the first area (R1) as a background operation.
[0059] The first cache memory (131) stores mapping information (MP), and the mapping information (MP) may include a plurality of mapping items (MP1 to MPn). Each of the plurality of mapping items (MP1 to MPn) may indicate mapping relationships between logical addresses and physical addresses. Additionally, the second cache memory (132) may include first and second regions (R1, R2), and the first and second regions (R1, R2) may each store a plurality of segments (SGa to SGm, SG1 to SGp). n, m, and p are arbitrary natural numbers.
[0060] In some embodiments, when the memory controller (110) receives a read request corresponding to at least one of the segments loaded in the first region (R1) from an external host device (not shown), it performs a read operation of data (DATA) stored in the first memory device (120) based on the segment and can provide the read data (DATA) to the external host device (not shown).
[0061] The operations described below (operations 1 through 5 (① to ⑤)) are exemplary to aid in understanding the present invention, and the scope of the present invention is not limited thereto.
[0062] In the first operation (①), the memory controller (110) can determine whether there is a cache hit. For example, the memory controller (110) can determine whether there is a cache hit indicating whether a segment corresponding to a write request (WREQ) received from an external host device (11) is loaded into the first area (R1).
[0063] In the second operation (②), the memory controller (110) can modify the segment in response to a cache hit (i.e., when the segment corresponding to the write request (WREQ) is loaded into the first area (R1). For example, if the segment corresponding to the write request (WREQ) is segment a (SGa), the memory controller (110) determines that segment a (SGa) is loaded into the first area (R1) (i.e., a cache hit) and can modify segment a (SGa).
[0064] In the third operation (③), the memory controller (110) can update the mapping information (MP) in response to a cache miss (i.e., when there is no segment corresponding to the write request within the first area (R1). For example, in response to the cache miss, the memory controller (110) can modify the first mapping entry (MP1) regarding the logical address and physical address corresponding to the write request (WREQ) among the mapping information (MP) stored in the first cache memory (131).
[0065] In the fourth operation (④), the memory controller (110) can load a segment into the first area (R1). For example, the memory controller (110) can load the m-th segment (SGm) corresponding to the write request (WREQ) into the first area (R1) after updating the mapping information (MP) (e.g., the first mapping item (MP1)) corresponding to the write request (WREQ). The memory controller (110) can reduce overhead and improve write performance by loading the m-th segment (SGm) into the first area (R1) as a background operation after updating the mapping information (MP), instead of immediately loading the m-th segment (SGm) into the first area (R1) in response to a cache miss.
[0066] In the fifth operation (⑤), the memory controller (110) may invalidate a portion of the mapping information. For example, the memory controller (110) may invalidate the first mapping entry (MP1) corresponding to the write request (WREQ) in response to receiving an additional write request (WREQ) for the m segment (SGm) after loading the m segment (SGm) into the first area (R1). By invalidating the first mapping entry (MP1), the memory controller (110) may secure more space within the first cache memory (131).
[0067] In some embodiments, if the memory controller (110) loads the m-th segment (SGm) into the first region (R1) and does not receive an additional write request (WREQ) for the m-th segment (SGm) until a subsequent map update operation, the first mapping entry (MP1) may be retained (without invalidating).
[0069] FIG. 5 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. Referring to FIG. 4 and FIG. 5, the memory controller (110) may modify a segment (SG) already loaded in a first area (R1) or update mapping information (MP) based on whether there is a cache hit.
[0070] In step S210, the memory controller (110) may receive a write request (WREQ). For example, the memory controller (110) may receive a write request (WREQ) corresponding to at least one segment (SG).
[0071] In step S220, the memory controller (110) can determine whether there is a cache hit. For example, the memory controller (110) can determine whether there is a cache hit indicating whether the segment (SG) corresponding to the write request (WREQ) is loaded into the first area (R1).
[0072] In some embodiments, the memory controller (110) may determine a cache miss (i.e., without determining whether there is a cache hit) and perform the operation of step S240 if the received write request (WREQ) is the first write request (WREQ) received after the first area (R1) is allocated. Since there may not be any segments (SG) loaded within the first area (R1) when the first area (R1) is first allocated, it may be unnecessary to determine whether there is a cache hit.
[0073] In some embodiments, the number of segments (SG) corresponding to a write request (WREQ) may be one or more. For example, when the number of segments (SG) is two or more, the memory controller (110) may determine whether there is a cache hit for all of the segments (SG). In other words, the memory controller (110) may determine whether there is a cache hit based on whether all of the segments (SG) corresponding to the write request (WREQ) are loaded into the first area (R1). The memory controller (110) may determine a cache miss in response to determining that at least one of the segments (SG) is not loaded into the first area (R1).
[0074] In some embodiments, the memory controller (110) can determine whether a cache hit occurs when a portion of the second cache memory (132) (e.g., the first region (R1)) is allocated for mapping information (MP). The memory controller (110) can allocate the first region (R1) for mapping information (MP) when the size of the workload (or the number of segments (SG)) corresponding to the write request (WREQ) is less than or equal to a threshold value. Thus, when the size of the workload (or the number of segments (SG)) corresponding to the write request (WREQ) is less than or equal to a threshold value, the memory controller (110) can determine whether a cache hit occurs for the segments (SG). When the size of the workload (or the number of segments (SG)) is greater than a threshold value, the memory controller (110) can deallocate the first region (R1), and then perform a map update operation or update the mapping information (MP).
[0075] In step S230, the memory controller (110) may modify a segment (SG) in response to a cache hit. For example, the memory controller (110) may modify a segment (SG) in response to a determination that the segment (SG) corresponding to a write request (WREQ) is already loaded in the first area (R1). In some embodiments, when the number of segments (SG) is two or more, the memory controller (110) may modify all segments (SG).
[0076] In step S240, the memory controller (110) can update mapping information (MP) in response to a cache miss. For example, the memory controller (110) can update mapping information (MP) in response to a cache miss by modifying a portion of the logical address and physical address corresponding to the write request (WREQ) among the mapping information (MP) stored in the first cache memory (131).
[0077] In step S250, the memory controller (110) can load a segment (SG) into the first area (R1). For example, the memory controller (110) can load the segment (SG) corresponding to the write request (WREQ) into the first area (R1) after updating the mapping information (MP) corresponding to the write request (WREQ). By loading the segment (SG) as a background operation after updating the mapping information (MP) rather than immediately loading the segment (SG) into the first area (R1) in response to a cache miss, the memory controller (110) can reduce the overhead of the storage device (100) and improve overall write performance.
[0078] In some embodiments, when the number of segments (SG) corresponding to a write request (WREQ) is at least two, the memory controller (110) can load all of the segments (SG) into the first area (R1). When some of the two or more segments (SG) are already loaded into the first area (R1), the memory controller (110) can load the remaining segments (SG) into the first area (R1).
[0079] In some embodiments, the memory controller (110) may, after loading a segment (SG) into the first region (R1), invalidate a portion of the mapping information (MP) corresponding to the write request (WREQ) (or segment (SG)).
[0080] The memory controller (110) may repeat steps S210 through S250. In some embodiments, after a segment (SG) is loaded in step S250, when a subsequent write request (WREQ) corresponding to the same segment (SG) is received, the memory controller (110) may modify the segment (SG) in response to a cache hit.
[0082] FIG. 6 is a diagram illustrating a storage device according to some embodiments of the present invention. Referring to FIG. 6, the memory controller (110) may deallocate a portion (e.g., a first region (R1)) of the second cache memory (132) allocated for mapping information (MP) in response to determining that an event has occurred.
[0083] Referring to FIGS. 2 through 5, the memory controller (110) may allocate a portion (e.g., a first region (R1)) of a second cache memory (132) that stores segments (loaded during a read operation) for mapping information (MP). Instead of updating the mapping relationship between the logical address and the physical address corresponding to the write request (WREQ) in the mapping information (MP), the memory controller (110) may increase the map update cycle and, consequently, improve the performance of the storage device (100) by storing the segment corresponding to the write request (WREQ) in the first region (R1).
[0084] However, indiscriminately allocating a portion of the second cache memory (132) for mapping information (MP) may cause performance degradation. For example, as described below, allocating a portion of the second cache memory (132) for mapping information (MP) when specific events occur may cause performance degradation.
[0085] In some embodiments, when the workload corresponding to the write request (WREQ) has low locality and requires the loading or modification of many segments, it may require more overhead than the operation of updating mapping information (MP) in the first cache memory (131) and cause inefficient use of space. For example, when the size (or number of segments) of the workload corresponding to the write request (WREQ) exceeds a threshold value, loading or modifying the segments corresponding to the write request (WREQ) into a part of the second cache memory (132) (e.g., the first area (R1)) may be inefficient.
[0086] In some embodiments, when the write request (WREQ) is a sequential write operation, it may be more efficient to update or save the mapping information (MP) in a different way.
[0087] Additionally, allocating the second cache memory (132) for mapping information (MP) of a write operation implies using an additional component (e.g., the second cache memory (132)) in addition to the first cache memory (131) during a write operation, which may increase the power consumption of the entire storage device (100). Therefore, when a power reduction request is received from an external host device (11), allocating a portion of the second cache memory (132) (e.g., the first area (R1)) for mapping information (MP) may be restricted or not permitted.
[0088] In some embodiments, when the storage device (100) performs internal operations (e.g., garbage collection operation, free-block operation, etc.) that require a significant amount of space in the second cache memory (132), allocating a portion of the second cache memory (132) (e.g., the first area (R1)) may be restricted or not allowed.
[0089] The events described above are explained by way of example to aid in understanding the present invention, and the scope of the present invention is not limited thereto.
[0090] The memory controller (110) may deallocate a portion of the second cache memory (132) (e.g., a first area (R1)) in response to determining that an event (e.g., at least one of the events described above) has occurred. For example, the memory controller (110) may deallocate the first area (R1) allocated for mapping information (MP) and, when a subsequent write request (WREQ) is received, update the mapping information (MP) stored in the first cache memory (131).
[0091] In some embodiments, the memory controller (110) may set a portion of the second cache memory (132) (e.g., the first region (R1)) to be unallocable during a specific time interval in response to a determination that an event (e.g., at least one of the events described above) has occurred. An unallocable state may refer to a state in which a portion of the second cache memory (132) (e.g., the first region (R1)) is not allocated even if the requirements for allocating it for mapping information (MP) are met. Since the event may occur repeatedly during a specific time interval, the memory controller (110) may set a portion of the second cache memory (132) (e.g., the first region (R1)) to be unallocable in response to the first occurrence of the event.
[0092] The memory controller (110) may perform a countdown operation to make a portion of the second cache memory (132) (e.g., the first region (R1)) unallocable during a specific time interval. For example, the memory controller (110) may perform a countdown operation in response to deallocating the first region (R1) and make the first region (R1) unallocable during the countdown operation.
[0093] After the count operation is completed (i.e., after the count becomes 0), the memory controller (110) may set the first area (R1) to be allocable or reallocate it for mapping information (MP). When the first area (R1) is in an allocable state, the memory controller (110) may allocate the second cache memory (132) (e.g., the first area (R1)) for mapping information (MP) in response to determining that the requirements for allocating a portion of the second cache memory (132) (e.g., the first area (R1)) for mapping information (MP) are met.
[0094] In some embodiments, the memory controller (110) may perform a countdown operation for different time intervals (or counts) for each type of event. For example, the memory controller (110) may perform a countdown operation for a first time interval (or first count) in response to a determination that a first type of event among a plurality of types of events has occurred, and perform a countdown operation for a second time interval (or second count) in response to a determination that a second type of event has occurred.
[0095] In some embodiments, the memory controller (110) may make available a portion of the second cache memory (132) (e.g., the first region (R1)) that is exceptionally unallocable during a countdown operation (i.e., before the countdown operation is completed or before the count reaches 0). Because there is a possibility that an event may occur repeatedly during a specific time period, the memory controller (110) may make a portion of the second cache memory (132) (e.g., the first region (R1)) unallocable during a specific time period (i.e., until the countdown operation is completed), but if there is no or little possibility that the event may occur repeatedly during a specific time period, the memory controller (110) may make available a portion of the second cache memory (132) (e.g., the first region (R1)) that is in an unallocable state.
[0096] In some embodiments, the memory controller (110) may store information about the sizes of workloads corresponding to each subsequent write request (WREQ) during a countdown operation (i.e., while the first region (R1) is in an unallocable state). For example, the memory controller (110) may update information about whether the sizes of workloads (or the number of segments) corresponding to each subsequent write request (WREQ) are each less than or equal to a first threshold value.
[0097] In some embodiments, the memory controller (110) may make the first region (R1) allocable before the countdown operation is completed, based on information regarding the sizes of workloads corresponding to each subsequent write request (WREQ). For example, the memory controller (110) may make the first region (R1) allocable before the countdown operation is completed in response to determining that the number of subsequent write requests (WREQ) containing workloads (or a number of segments) of a size smaller than or equal to a first threshold is greater than a second threshold.
[0098] The memory controller (110) includes a counter (111) and can store workload information (WI). In some embodiments, the counter (111) performs a countdown operation and, when the countdown operation is completed (i.e., when the count reaches 0), can provide a signal to the memory controller (110) indicating the completion of the countdown operation. Additionally, the memory controller (110) can store information regarding the sizes of workloads corresponding to subsequent write requests (WREQ) as workload information (WI).
[0099] In some embodiments, the memory controller (110) may perform a map update operation in response to determining that the remaining space of the first region (R1) is smaller than a threshold value. For example, because the space of the first region (R1) is limited, the number of segments that can be loaded into the first region (R1) may be limited. Accordingly, the memory controller (110) may determine whether additional segments can be loaded into the first region (R1) by determining whether the remaining space of the first region (R1) is smaller than a threshold value. When the remaining space of the first region (R1) is smaller than a threshold value, the memory controller (110) may perform a map update operation to flush all segments loaded into the first region (R1) to the first memory device (120).
[0100] The operations described below (operations 1 through 7 (① to ⑦)) are exemplary to aid in understanding the present invention, and the scope of the present invention is not limited thereto.
[0101] In the first operation (①), the memory controller (110) may deallocate the first area (R1). For example, the memory controller (110) may deallocate the first area (R1) in response to determining that an event (e.g., at least one of the events described above) has occurred.
[0102] In the second operation (②), the memory controller (110) may perform a map update operation. For example, the memory controller (110) may determine that an event has occurred and, in response to deallocating the first area (R1), perform a map update operation. To perform the map update operation, the memory controller (110) may control the second memory device (130) to flush the mapping information (MP) stored in the first cache memory (131) and the segments loaded in the first area (R1) within the second cache memory (132) to the first memory device (120).
[0103] In the third operation (③), the second memory device (130) may perform a flush operation. For example, the second memory device (130) may flush the mapping information (MP) stored in the first cache memory (131) and the segments loaded in the first area (R1) within the second cache memory (132) to the first memory device (120) under the control of the memory controller (110). After the flush operation is performed, the segments loaded in the first area (R1) may not exist. The first memory device (120) may store the flushed mapping information (MP) and segments as metadata (MD).
[0104] In the fourth operation (④), the memory controller (110) or the counter (111) may perform a countdown operation. For example, the memory controller (110) or the counter (111) may perform a countdown operation in response to determining that an event has occurred. The memory controller (110) or the counter (111) may determine the number of counts for the countdown operation based on the type of event. Thus, the memory controller (110) or the counter (111) may perform the countdown operation for different time intervals depending on the type of event.
[0105] In the fifth operation (⑤), the memory controller (110) can set the first area (R1) to be unallocable during the countdown operation. Therefore, the memory controller (110) cannot reallocate the first area (R1) for mapping information (MP) until the countdown operation is completed (i.e., until the count reaches 0).
[0106] In the sixth operation (⑥), the memory controller (110) may store workload information (WI). For example, the memory controller (110) may store information about the sizes of workloads corresponding to each subsequent write request (WREQ) during the countdown operation (i.e., while the first area (R1) is in an unallocable state). For example, the memory controller (110) may update the workload information (WI) with information about whether the number of segments corresponding to each subsequent write request (WREQ) is less than or equal to the first threshold value.
[0107] In the seventh operation (⑦), the memory controller (110) may determine whether to make the first area (R1) allocable based on the workload information (WI). For example, the memory controller (110) may determine whether to make the first area (R1) allocable before the countdown operation is completed based on the workload information (WI). For example, the memory controller (110) may determine, by referring to the workload information (WI), whether the number of subsequent write requests (WREQ) containing a number of segments smaller than or equal to the first threshold is greater than the second threshold, and may determine whether to make the first area (R1) allocable before the countdown operation is completed based on the result.
[0109] FIG. 7 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. Referring to FIG. 6 and FIG. 7, the memory controller (110) may set the first area (R1) to be unallocable and, exceptionally, set the first area (R1) to be re-allocable.
[0110] In step S310, the memory controller (110) may deallocate the first area (R1). For example, the memory controller (110) may deallocate the first area (R1) allocated for mapping information (MP) in response to determining that an event (e.g., at least one of the events described in FIG. 6) has occurred.
[0111] In some embodiments, the memory controller (110) may perform a map update operation in response to deallocating the first region (R1). For example, the memory controller (110) may perform a map update operation to flush all segments corresponding to a write request (WREQ) loaded in the first region (R1) to the first memory device (120) in response to deallocating the first region (R1).
[0112] In step S320, the memory controller (110) may perform a countdown operation. For example, the memory controller (110) may perform a countdown operation in response to determining that an event has occurred.
[0113] In some embodiments, the memory controller (110) may determine the number of counts for a countdown operation based on the type of event. For example, the memory controller (110) may perform a countdown operation for a first number of counts when a first type of event occurs among the types of events, and perform a countdown operation for a second number of counts when a second type of event occurs. Accordingly, the memory controller (110) or the counter (111) may perform a countdown operation for different time intervals depending on the type of event.
[0114] In step S330, the memory controller (110) may set the first region (R1) to be unallocable. For example, the memory controller (110) may set the first region (R1) to be unallocable during a countdown operation. Therefore, the memory controller (110) may not be able to reallocate the first region (R1) for mapping information (MP) until the countdown operation is completed (i.e., until the count reaches 0).
[0115] In some embodiments, while the first region (R1) is in an unallocable state, the memory controller (110) may not be able to allocate the first region (R1) for mapping information (MP) even if the requirements for allocating the first region (R1) are met (e.g., when the number of segments corresponding to a write request (WREQ) is less than or equal to a threshold value).
[0116] In step S340, the memory controller (110) can determine whether the count has reached 0. For example, the memory controller (110) can decrease the count by a unit number during the countdown operation and determine whether the countdown operation is completed when the count reaches 0. The memory controller (110) can keep the first region (R1) in an unallocable state until the count reaches 0.
[0117] In step S350, the memory controller (110) may determine whether to make the first region (R1) allocable. For example, the memory controller (110) may determine whether to make the first region (R1) allocable exceptionally in response to a determination that the count has not reached 0 (i.e., the countdown operation has not been completed).
[0118] In some embodiments, the memory controller (110) may store information regarding the sizes of workloads corresponding to subsequent write requests (WREQ) respectively during a countdown operation (i.e., while the first area (R1) is in an unallocable state). Based on the information regarding the sizes of workloads corresponding to subsequent write requests (WREQ), the memory controller (110) may determine whether to make the first area (R1) allocable before the countdown operation is completed.
[0119] For example, the memory controller (110) may make the first region (R1) allocatable before the countdown operation is completed in response to determining that the number of subsequent write requests (WREQ) containing a number of segments smaller than or equal to the first threshold is greater than the second threshold.
[0120] In response to the memory controller (110) deciding not to set it to allocable, the memory controller (110) may repeat step S340. The memory controller (110) may determine again whether the count has reached 0.
[0121] In step S360, the memory controller (110) may determine that the count has reached 0 or may set the first area (R1) to be allocable in response to setting the first area (R1) to be allocable. The memory controller (110) may re-allocate the first area (R1) for mapping information (MP) in response to determining that the requirements for allocating the first area (R1) for mapping information (MP) are met.
[0123] FIG. 8 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. Referring to FIG. 2 and FIG. 8, the memory controller (110) may modify a segment (SG) loaded in a first region (R1) or update mapping information (MP) in a first cache memory (131) based on whether there is a cache hit.
[0124] In step S410, the memory controller (110) may receive a write request (WREQ) from an external host device (11). Before receiving the write request (WREQ), the memory controller (110) may allocate some of the regions of the second cache memory (132) (e.g., the first region (R1)) for mapping information (MP) corresponding to the write request (WREQ). However, when processing the workload corresponding to the write request (WREQ) (i.e., when performing a write operation of data (DATA)), the memory controller (110) needs to decide whether to update the mapping information (MP) of the first cache memory (131) or to modify the segment (SG) loaded in the first region (R1).
[0125] In step S420, the memory controller (110) can determine whether there is a cache hit. For example, the memory controller (110) can determine whether there is a cache hit by determining whether a segment (SG) corresponding to a write request (WREQ) has already been loaded into the first area (R1). Based on whether there is a cache hit, the memory controller (110) can determine whether to update the mapping information (MP) of the first cache memory (131) or to modify the segment (SG) loaded into the first area (R1).
[0126] In step S430, the memory controller (110) can modify the segment (SG) in response to a cache hit. For example, the memory controller (110) can modify the segment (SG) loaded in the first area (R1) in response to a cache hit determining that the segment (SG) corresponding to the write request (WREQ) in the first area (R1) has already been loaded.
[0127] In step S440, the memory controller (110) may update mapping information (MP) in response to a cache miss. For example, the memory controller (110) may update the mapping information (MP) stored in the first cache memory (131) in response to a cache miss in which it determines that the segment (SG) corresponding to the write request (WREQ) in the first area (R1) has not been loaded. In some embodiments, after updating the mapping information (MP), the memory controller (110) may load the segment corresponding to the write request (WREQ) in the first area (R1) as a background operation.
[0129] FIG. 9 is a flowchart illustrating a method of operation of a storage device according to some embodiments of the present invention. Referring to FIG. 6 and FIG. 9, the memory controller (110) can deallocate the first area (R1) when an event occurs.
[0130] In step S510, the memory controller (110) may determine that an event has occurred. For example, the memory controller (110) may determine that at least one of various types of events has occurred.
[0131] In some embodiments, the event may include determining that the size of the segment corresponding to the write request (WREQ) is larger than the threshold size, that the write request (WREQ) is a sequential write operation, and receiving a power reduction request from an external host device, but this is exemplary and the scope of the invention is not limited thereto.
[0132] In step S520, the memory controller (110) may deallocate the first area (R1). For example, the memory controller (110) may deallocate the first area (R1) allocated for mapping information (MP) in response to a determination that an event (e.g., at least one of the event types described above) has occurred.
[0133] In step S530, the memory controller (110) may perform a countdown operation. For example, the memory controller (110) may perform a countdown operation in response to determining that an event has occurred. The memory controller (110) may set the first area (R1) to be unallocable during the countdown operation. Therefore, the memory controller (110) may not be able to reallocate the first area (R1) for mapping information (MP) until the countdown operation is completed (i.e., until the count reaches 0).
[0134] In some embodiments, the memory controller (110) may determine the number of counts for a countdown operation based on the type of event. For example, the memory controller (110) may perform a countdown operation for a first number of counts when a first type of event occurs among the types of events, and perform a countdown operation for a second number of counts when a second type of event occurs. Accordingly, the memory controller (110) may perform a countdown operation for different time intervals depending on the type of event.
[0135] The memory controller (110) can prevent the performance of the storage device (100) from being degraded by unnecessary allocation of the first area (R1) by setting the first area (R1) to be unallocable during different time intervals depending on the type of event.
[0137] FIG. 10 is a drawing illustrating a second memory device (230) according to some embodiments of the present invention. Referring to FIG. 10, the second memory device (230) may include a cache memory (231). The cache memory (231) is an example in which the first and second cache memories (131, 132) of FIG. 2 are exemplarily implemented as a single cache memory, and a redundant description thereof will be omitted.
[0138] The cache memory (231) can store mapping information (MP) and segments (SG). For example, the cache memory (231) may include first to third regions (R1 to R3) separated by write pointers (e.g., first and second write pointers (WP1, WP2)), and may store mapping information (MP) and segments (SG) within the first to third regions (R1 to R3).
[0139] In some embodiments, the third region (R3) may be used as a cache region for storing mapping information (MP) for a write operation of the storage device (100) of FIG. 2, and the first and second regions (R1, R2) may be used as cache regions for storing segments (SG) for a read operation of the storage device (100) of FIG. 2.
[0140] In some embodiments, the memory controller (110) of FIG. 2 may use the first region (R1) among the first and second regions (R1, R2) to process the write request (WREQ) (or workload of the write request (WREQ)) of FIG. 2. For example, when the requests received from the host device (11) of FIG. 2 are mainly write requests (WREQ) or the workload of read requests is small, the memory controller (110) of FIG. 2 may allocate some of the first and second regions (R1, R2)) (e.g., the first region (R1)) for mapping information (MP), load segments corresponding to the write request (WREQ), and cache them.
[0141] In some embodiments, the sizes of regions within the cache memory (231) (e.g., first to third regions (R1 to R3)) may be varied as needed. For example, the size of the third region (R3) may increase as more mapping information (MP) is written to the first write pointer (WP1) within the cache memory (231). Additionally, the size of the first region (R1) may increase as more segments (SG) corresponding to a write request (WREQ) are written to the second write pointer (WP2) within the cache memory (231) (and as the segments (SG) stored in the second region (R2) are overwritten).
[0142] In some embodiments, when the storage device (100) of FIG. 2 performs internal operations (e.g., garbage collection operation, free-block operation, etc.) that require a significant amount of space in the second cache memory (132), the sizes of the first to third regions (R1 to R3) may be changed. For example, the sizes of the second and third regions (R2, R3) may be larger, and the size of the third region (R3) may be smaller. The sizes of the first to third regions (R1 to R3) are not limited to the scale exemplarily illustrated in FIG. 10.
[0144] FIG. 11 is a block diagram of a memory card system to which a storage device according to some embodiments of the present invention is applied. Referring to FIG. 11, the memory card system (30) may include a memory controller (310), a memory device (320), and a connector (330).
[0145] A memory controller (310) may be connected to a memory device (320). The memory controller (310) may be configured to access the memory device (320). For example, the memory controller (310) may be configured to control the read, write, erase, and background operations of the memory device (320). The memory controller (310) may be configured to provide an interface between the memory device (320) and an external host device (not shown). The memory controller (310) may be configured to run firmware for controlling the memory device (320). The memory controller (310) may be implemented similarly to the memory controller (110) described with reference to FIG. 1.
[0146] For example, the memory controller (310) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction circuit.
[0147] The memory controller (310) can communicate with an external device through a connector (330). For example, the memory controller (310) can communicate with an external device (e.g., a host device) according to a specific communication standard. For example, the memory controller (310) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (330) may be defined by at least one of the various communication standards described above.
[0148] For example, the memory device (320) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin-Transfer Torque Magnetoresistive RAM), etc. The memory device (220) may be implemented similarly to the first memory device (120) described with reference to FIG. 1.
[0149] The memory controller (310) and the memory device (320) can be integrated into a single semiconductor device to form a memory card. For example, the memory controller (310) and the memory device (320) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card, Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.
[0151] FIG. 12 is a drawing illustrating an electronic system according to some embodiments of the present invention. Referring to FIG. 12, the electronic system (40) may include a host device (41) and a storage device (400). The storage device (400) may exchange signals with the host device (41) through a signal connector (401) and receive power through a power connector (402). The storage device (400) may include a memory controller (410), a plurality of non-volatile memory devices (421 to 42n), an auxiliary power device (430), and a buffer memory device (440).
[0152] According to one embodiment of the present invention, the memory controller (410) can perform the functions of the memory controller (110) of FIG. 2.
[0153] The memory controller (410) can control a plurality of non-volatile memory devices (421–42n) in response to signals received from the host device (41). For example, the signals may be signals based on the interface between the host device (41) and the storage device (400). For example, the signals may be signals defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.
[0154] The auxiliary power supply unit (430) can be connected to the host device (41) via a power connector (402). The auxiliary power supply unit (430) can receive power voltage from the host device (41) and charge. The auxiliary power supply unit (430) can provide power voltage to the storage device (400) when power supply from the host device (41) is not smooth. For example, the auxiliary power supply unit (430) may be located inside the storage device (400) or outside the storage device (400). For example, the auxiliary power supply unit (430) may be located on the main board and provide auxiliary power to the storage device (400).
[0155] The buffer memory device (440) can operate as a buffer memory of the storage device (400). For example, the buffer memory device (440) can temporarily store data received from the host device (41) or data received from a plurality of non-volatile memory devices (421 to 42n), or temporarily store metadata (e.g., mapping information or segments) of the plurality of non-volatile memory devices (421 to 42n). The buffer memory device (440) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.
[0157] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention. Explanation of the symbols
[0158] 100: Storage device 130: Second memory device 110: Memory controller 131: 1st Cache Memory 120: First memory device 132: Second cache memory
Claims
Claim 1 A storage device comprising: a first memory device for storing data; a second memory device including a first cache memory for storing mapping information and a second cache memory for storing segments; and a memory controller configured to update the mapping information in response to a write request received from an external host device, wherein the memory controller is configured to allocate a first region among the regions of the second cache memory for the mapping information in response to determining that the size of the workload corresponding to the write request is smaller than or equal to a first threshold value. Claim 2 A storage device configured, wherein the memory controller determines whether there is a cache hit of a segment corresponding to the write request, modifies the segment in response to a cache hit of the segment, and updates the mapping information in response to a cache miss of the segment. Claim 3 In claim 2, the storage device further configured such that the memory controller loads the segment into the first area after updating the mapping information. Claim 4 A storage device according to claim 3, wherein the memory controller is configured to invalidate a portion of the mapping information corresponding to the segment in response to receiving a write request corresponding to the segment after loading the segment into the first area. Claim 5 A storage device according to claim 1, wherein the memory controller is configured to deallocate the first region in response to determining that the size of the workload corresponding to the write request is greater than the first threshold. Claim 6 In claim 5, the storage device configured such that the memory controller performs a map update operation in response to deallocating the first area. Claim 7 In claim 5, the memory controller is configured to perform a countdown operation in response to deallocating the first area, and is configured to set the first area to be unallocable during the countdown operation. Claim 8 In claim 7, the memory controller is configured to store information regarding the sizes of workloads corresponding to subsequent write requests during the countdown operation, and, based on the information, to determine whether to make the first area allocatable before the countdown operation is completed. Claim 9 A storage device according to claim 1, wherein the memory controller is configured to deallocate the first area in response to determining that the write request indicates a sequential write operation. Claim 10 In claim 1, the storage device wherein the write request refers to a random write operation. Claim 11 A storage device configured to perform a map update operation in response to the memory controller determining that the remaining space of the first region is smaller than a second threshold value in claim 1. Claim 12 A storage device configured such that, in response to receiving a read request from the external host device, the memory controller determines whether there is a cache hit of a segment corresponding to the read request, and in response to a cache hit of the segment, performs a read operation of read data corresponding to the segment. Claim 13 A storage device comprising: a first memory device for storing data; a second memory device including a first cache memory for storing mapping information and a second cache memory for storing segments; and a memory controller configured to allocate a first region among the regions of the second cache memory for the mapping information, wherein the memory controller is configured to: determine whether there is a cache hit of a segment corresponding to the write request in response to receiving a write request from an external host device, modify the segment in response to a cache hit of the segment, and update the mapping information in response to a cache miss of the segment. Claim 14 In claim 13, the memory controller is further configured to: load the segment into the first area after updating the mapping information, and, in response to receiving a write request corresponding to the segment after loading the segment into the first area, invalidate a portion of the mapping information corresponding to the segment. Claim 15 In claim 13, the memory controller is configured to: deallocate the first area and perform a countdown operation in response to determining that an event has occurred, and, during the countdown operation, set the first area to be unallocable. Claim 16 In claim 15, the type of event comprises: determining that the size of the segment is larger than a threshold size; that the write request is a sequential write operation; and receiving a power reduction request from the external host device. Claim 17 In claim 15, the storage device configured such that the memory controller determines the number of counts of the countdown operation based on the type of the event. Claim 18 In claim 15, the memory controller is configured to store information regarding the sizes of workloads corresponding to subsequent write requests during the countdown operation, and, based on the information, to determine whether to make the first area allocatable before the countdown operation is completed. Claim 19 In claim 13, the memory controller is configured to: determine whether there is a cache hit of a segment corresponding to the read request in response to receiving a read request from the external host device, and to perform a read operation of read data corresponding to the segment in response to the cache hit of the segment. Claim 20 A method of operation of a storage device comprising: a step of allocating a first region among regions of a second cache memory that stores segments for the mapping information of a first cache memory that stores mapping information; a step of receiving a write request from an external host device; a step of determining whether there is a cache hit of a segment corresponding to the write request within the first region in response to receiving the write request; a step of modifying the segment in response to a cache hit of the segment; and a step of updating the mapping information in response to a cache miss of the segment.