Two-Step single slope analog-to-digital converter

Abstract

A dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention may include a sampling hold circuit for sampling and holding an analog input signal at a certain point in time, a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal, a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a certain unit voltage interval based on information obtained in a macroscopic conversion stage, a comparator for generating an output signal by sequentially comparing the input signal and each ramp signal, a D-flip-flop for sampling the output signal of the comparator according to a clock signal, and a counter for performing a count according to the output of the D-flip-flop.

Description

Technology Field

[0001] The present invention relates to a dual-stage single gradient analog-to-digital converter, and more specifically, to a technology capable of converting an analog input signal into a high-speed and high-precision digital signal using a sampling hold circuit and a switched capacitor integrator. Background Technology

[0002] An Analog-to-Digital Converter (ADC) is a device that converts analog signals into digital signals and is essential in various electronic systems, such as digital image sensors, audio conversion, and sensor reading. In particular, ADCs are a critical component that determines the overall quality of a system, especially in image processing systems requiring high-resolution images or mobile sensor devices demanding low power consumption and high accuracy.

[0003] Analog-to-digital converters can be classified into various types based on their operating principles, with the single slope converter being a representative example. A single slope analog-to-digital converter generates a digital value by comparing a linearly changing reference voltage, known as a ramp signal, with the input analog voltage.

[0004] Single-slope converters have the advantage of simple circuitry and ease of implementation, making them easy to design within a pixel pitch. Additionally, single-slope analog-to-digital converters have been primarily used in CMOS image sensors because they offer high linearity and relatively low power consumption.

[0005] However, due to the recent surge in demand for high-definition CMOS image sensors, the number of pixels has increased rapidly, leading to an expansion of the overall chip area and consequently, a problem of degraded readout speed has begun to arise. In particular, for a single gradient converter, as the resolution increases, the number of clocks required for conversion becomes 2 n Since it increases exponentially with respect to (where n is the number of bits), it has a fatal disadvantage in that the conversion time becomes significantly longer at high resolutions.

[0006] For example, to perform a 10-bit resolution conversion, approximately 2 per signal 10 (1024) clock cycles are required, and 4096 clock cycles are required for 12-bit. In other words, as the total conversion time increases exponentially as the number of pixels increases, it causes a serious bottleneck problem in high-resolution image sensors that require high-speed operation.

[0007] Furthermore, single-gradient converters have the disadvantages of slow conversion speed and high power consumption because they must wait for the ramp signal to reach the input signal in the comparator. Additionally, when a single-gradient converter is implemented within an integrated circuit, the characteristics or linearity of the output signal may differ from the design values; in particular, signal distortion caused by parasitic capacitance occurs, making it difficult to secure the desired performance.

[0008] Meanwhile, to address the problems associated with such single gradient converters, a method using a resistor ladder converter has been proposed; however, this has the drawbacks of increased circuit complexity and significantly higher power consumption.

[0009] Furthermore, high-frequency noise included in the analog input signal or parasitic capacitance present at the input of the comparator has a direct adverse effect on conversion accuracy, and especially when performing high-resolution conversion, the error caused by these parasitic factors is large enough to be non-negligible.

[0010] Accordingly, conventional technology used a method of increasing the capacitance of the holding capacitor to reduce errors caused by parasitic capacitance; however, this caused new problems such as increased circuit area and load, which made it unsuitable for obtaining reliable high-precision conversion results. Prior art literature

[0011] Korean Public Document KR 10-2024-0119430A - Single-slope analog-to-digital converter and method of implementing the same (2024.08.06) The problem to be solved

[0012] Accordingly, the dual-stage single-slope analog-to-digital converter according to one embodiment is an invention designed to solve the aforementioned problems, and its purpose is to provide a high-speed / high-precision analog-to-digital converter while minimizing errors caused by parasitic capacitance by efficiently combining circuit configurations such as a sampling hold circuit, a ramp signal generator, a comparator, and a counter.

[0013] More specifically, a dual-stage single-gradient analog-to-digital converter according to one embodiment aims to provide an analog-to-digital converter at a faster speed through a dual-stage operation in which, when performing a conversion step, the upper bit is determined in the macroscopic conversion step and the lower bit is determined in the microscopic conversion step.

[0014] In addition, the dual-stage single gradient analog-to-digital converter according to the present invention aims to effectively reduce errors caused by parasitic capacitance without increasing the circuit area by compensating for the influence of parasitic capacitance based on a tracking input signal. means of solving the problem

[0015] A dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention may include a sampling hold circuit for sampling and holding an analog input signal at a certain point in time, a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal, a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a certain unit voltage interval based on information obtained in a macroscopic conversion stage, a comparator for generating an output signal by sequentially comparing the input signal and each ramp signal, a D-flip-flop for sampling the output signal of the comparator according to a clock signal, and a counter for performing a count according to the output of the D-flip-flop.

[0016] A tracking capacitor of the same size as the holding capacitor may be connected to the input terminal of the above comparator.

[0017] The above microscopic conversion step may include a step in which charge sharing is induced between the tracking capacitor and the parasitic capacitance of the input terminal of the comparator, and an error caused by the shared charge is offset.

[0018] The above macroscopic ramp signal generator or the above microscopic ramp signal generator may include a switched capacitor circuit.

[0019] A dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention may include a sampling hold circuit for sampling and holding an analog input signal at a certain point in time, a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal, a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a certain unit voltage interval based on information obtained in a macroscopic conversion stage, a comparator for generating an output signal by sequentially comparing the input signal and each ramp signal, a D-flip-flop for sampling the output signal of the comparator according to a clock signal, and a counter for performing a count according to the output of the D-flip-flop.

[0020] The above dual-stage single slope analog-to-digital converter may further include a tracking capacitor that samples and stores an input signal and a holding capacitor that stores the voltage of a macroscopic ramp signal.

[0021] The above macroscopic ramp signal generator and microscopic ramp signal generator include a switched capacitor integrator, and the switched capacitor integrator can generate a step ramp signal that decreases or increases linearly at each cycle set based on the difference in reference voltage.

[0022] The above counter can perform a macroscopic conversion step of calculating an upper bit based on a comparison result calculated by comparing the input voltage input to the comparator with a macroscopic ramp signal.

[0023] The above counter can perform a microscopic conversion step of calculating a lower bit based on a comparison result calculated by comparing the input voltage input to the comparator with a microscopic ramp signal.

[0024] The above counter can perform the macroscopic conversion step by performing a count equal to the number of clock cycles to calculate the upper bit.

[0025] The above counter can perform the microscopic conversion step by performing an additional count on the waveform of a microscopic ramp signal set based on the result of the above macroscopic conversion step to calculate the lower bit.

[0026] Between the above macroscopic conversion step and the above microscopic conversion step, a preset step may be performed in which the input terminal and capacitor terminal of the comparator are initialized to a reference voltage.

[0027] The above sampling maintenance circuit may include a correlated double sampling circuit that removes high-frequency noise from the input analog signal and maintains the basis signal component.

[0028] The tracking capacitor and the holding capacitor may have the same capacitance.

[0029] A dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention comprises a sampling hold circuit for sampling and holding an analog input signal at a certain point in time, a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal, a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a certain unit voltage interval based on information obtained in a macroscopic conversion stage, a comparator for generating an output signal by sequentially comparing the input signal and each ramp signal, a D-flip-flop for sampling the output signal of the comparator according to a clock signal, and a counter for performing a count according to the output of the D-flip-flop, wherein the comparator, the D-flip-flop, and the counter have a total clock cycle of 2 for conversion of a resolution of M+N bits. M + 2 N It can operate in a periodic manner.

[0030] The above dual-stage single slope analog-to-digital converter may further include a tracking capacitor that samples and stores an input signal and a holding capacitor that stores the voltage of a macroscopic ramp signal.

[0031] The above macroscopic ramp signal generator and microscopic ramp signal generator include a switched capacitor integrator, and the switched capacitor integrator can generate a step ramp signal that decreases or increases linearly at each cycle set based on the difference in reference voltage.

[0032] The above counter can perform a macroscopic conversion step of calculating an upper bit based on a comparison result calculated by comparing the input voltage input to the comparator with a macroscopic ramp signal.

[0033] The above counter can perform a microscopic conversion step of calculating a lower bit based on a comparison result calculated by comparing the input voltage input to the comparator with a microscopic ramp signal.

[0034] The above counter can perform the macroscopic conversion step by calculating the upper bit by performing a count equal to the number of clock cycles. Effects of the invention

[0035] A dual-stage single-slope analog-to-digital converter according to one embodiment is placed within the column pitch of a CMOS image sensor, thereby having the advantage of being able to respond more effectively to conversion speed requirements due to an increase in the number of pixels than a conventional single-slope analog-to-digital converter.

[0036] Furthermore, unlike conventional ramp signal generators that use resistor ladders or current source converters, the present invention utilizes a switched capacitor integrator circuit based on capacitor ratios as a ramp signal generator to improve the linearity and precision of the ramp signal, thereby offering the advantage of increased accuracy in digital conversion.

[0037] In addition, a dual-stage single-gradient analog-to-digital converter according to one embodiment effectively improved the overall conversion speed through a dual conversion process divided into a macroscopic stage and a microscopic stage. For example, when dividing the conversion of a total M+N-bit resolution into a macroscopic M-bit and a microscopic N-bit, approximately 2 M + 2 N The conversion is completed using only the conference clock signal, eliminating the 2 required in the conventional single-stage method M+N It can achieve a much faster speed compared to the conference clock.

[0038] In addition, the dual-stage single-slope analog-to-digital converter according to one embodiment is designed with a circuit capable of offsetting errors caused by parasitic capacitance during macroscopic conversion voltage transfer, thereby minimizing signal distortion that may occur during the conversion process. Therefore, through the parasitic capacitance correction function, there is an advantage in being able to implement a high-precision conversion circuit without signal distortion without increasing chip area.

[0039] In addition, since the dual-stage single gradient analog-to-digital converter according to one embodiment can be implemented with a relatively simple structure compared to conventional technology, circuit design is easy, which has the advantage of reducing manufacturing costs and improving design efficiency.

[0040] The effects of the present invention are not limited to the technical problems mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0041] A brief description of each drawing is provided to help to better understand the drawings cited in the detailed description of the invention. Figure 1 is a diagram showing a conventional single gradient analog-to-digital converter. FIG. 2 is a schematic diagram showing a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 3 is a diagram showing a column-parallel structure of an image sensor chip including a dual-stage single gradient analog-to-digital converter array according to one embodiment of the disclosed invention in a column ADC area. FIG. 4 is a diagram showing the timing diagram of a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 5 is a diagram illustrating the circuit connection in the macroscopic conversion stage in a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 6 is a diagram illustrating the circuit connection in the microscopic conversion stage in a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention. Figure 7 is a diagram illustrating the input terminal circuit connection in the microscopic conversion step according to Figure 6. Figure 8 is a diagram illustrating the circuit connection of the ramp signal terminal in the microscopic conversion stage according to Figure 6. FIG. 9 is a diagram showing a macroscopic ramp signal generator circuit in a dual-stage single slope analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 10 is a diagram showing a microscopic ramp signal generator circuit in a dual-stage single slope analog-to-digital converter according to one embodiment of the disclosed invention. Specific details for implementing the invention

[0042] The embodiments described in this specification and the configurations illustrated in the drawings are merely preferred examples of the disclosed invention, and various modifications that may replace the embodiments and drawings of this specification may exist at the time of filing this application.

[0043] Additionally, the same reference numerals or symbols presented in each figure of this specification represent parts or components that perform substantially the same function. Furthermore, the terms used in this specification are for describing embodiments and are not intended to limit or / or restrict the disclosed invention. Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0044] In this specification, terms such as “comprising” or “having” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and do not preclude the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0045] Additionally, terms including ordinal numbers, such as "first," "second," etc., used in this specification may be used to describe various components, but said components are not limited by said terms, and said terms are used solely for the purpose of distinguishing one component from another.

[0046] For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items. Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0047] Figure 1 is a diagram showing a conventional single gradient analog-to-digital converter.

[0048] Referring to FIG. 1, a single gradient analog-to-digital converter according to the prior art consists of a sampling hold circuit (CDS), an integrator-type ramp signal generator (Integrator / Ramp Generator), a comparator, and a counter.

[0049] A single gradient analog-to-digital converter according to conventional technology is designed with a relatively simple structure, resulting in high area efficiency. It possesses relatively high linearity and resolution, and low power consumption, making it suitable for column-parallel structures.

[0050] However, a single gradient analog-to-digital converter according to conventional technology has a problem in that the number of clocks required to detect an input signal increases exponentially as the resolution increases.

[0051] For example, to perform a 10-bit resolution conversion, approximately 2 per signal 10 (Approximately 1024) clock cycles are required. Therefore, as the number of pixels increases, the time required for conversion increases, so there were limitations in implementing the high-speed operation required in circuit design using only a single gradient analog-to-digital converter.

[0052] Accordingly, the dual-stage single-gradient analog-to-digital converter according to one embodiment aims to effectively solve the problems of the prior art by dividing the operation stages of a single-gradient analog-to-digital converter, which previously operated as a single-stage process, into two stages. This will be examined in detail through the drawings below.

[0053] FIG. 2 is a schematic diagram showing a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention.

[0054] As illustrated in FIG. 2, the dual-stage single-gradient analog-to-digital converter (1) receives an analog signal and includes a sampling sustain circuit (Correlated Double Sampling, CDS, 10), a macroscopic ramp signal generator (20), a microscopic ramp signal generator (30), a comparator (40), a D-flip-flop (50), a counter (60), and a tracking capacitor (C H1 ) and holding capacitor (C H2 It may include ) etc.

[0055] Specifically, the sampling maintenance circuit (10) can transmit a signal to the comparator (40) after noise removal and stabilization operations have been performed on the input analog signal. The macroscopic ramp signal generator (20) and the microscopic ramp signal generator (30) can each generate ramp signals for upper and lower bit conversions. The comparator (40) compares the input signal and the ramp signal to output a comparison value and can transmit the output result to the D-flip-flop and counter (60). The D-flip-flop (50) can control the switch by sampling the comparator output, and the tracking capacitor (C H1 ) and holding capacitor (C H2 Each stores the voltage corresponding to the input signal and the macroscopic ramp signal, and can play a key role in parasitic capacitance compensation. Below, we will examine in detail the components and operating principle of the dual-stage single-gradient analog-to-digital converter (1).

[0056] The sampling maintenance circuit (10) effectively removes high-frequency noise from the analog signal output from the image sensor and simultaneously performs the function of stably maintaining the basic signal component of the image, i.e., the low-frequency component.

[0057] Specifically, the sampling maintenance circuit (10) is a circuit that performs the function of accurately sampling an analog input signal at a certain point in time, maintaining it, and transmitting it, and has the characteristic of being able to remove high-frequency noise of the input signal and stably maintain only the ground component of the signal.

[0058] In particular, the sampling maintenance circuit (10) according to the present invention is a circuit designed based on the Correlated Double Sampling (CDS) technique, and has the advantage of removing parasitic noise and unnecessary offset components because it performs sampling of the input signal as a relative voltage relative to the reference voltage.

[0059] Accordingly, the sampling maintenance circuit (10) operates by sampling an analog input containing a pixel signal at a constant period and then subtracting the two signals based on the correlation between the reset signal and the image signal, thereby removing common mode components such as power noise or kT / C noise and extracting only the actual valid image signal at a specific time.

[0060] The sampling maintenance circuit (10) can stably secure the difference between the reset level and the actual signal level at each pixel unit by precisely controlling the sampling timing, which can play an important role in suppressing fixed pattern noise (FPN) and improving the signal-to-noise ratio (SNR) of the entire system by the dual-stage single-gradient analog-to-digital converter (1) according to the present invention.

[0061] The macroscopic signal ramp generator (20) can generate a step ramp signal that decreases linearly within a preset reference voltage range and may include a switched capacitor integrator.

[0062] Specifically, the macroscopic ramp signal generator (20) can generate a ramp signal having a waveform that differentially decreases the reference voltage supplied from a reference voltage source at regular time intervals. The macroscopic ramp signal generator (20) can stepwise decrease the output voltage in accordance with the period of the clock signal by changing the ratio between the capacitor selected in each period and the reference voltage by controlling a plurality of switches sequentially. The macroscopic signal generator (20) according to the present invention has a total voltage range of 2 M Since it is divided into equal steps, there is an advantage in that uniformity of precision can be ensured.

[0063] Additionally, the macroscopic signal generator (20) is integrated in such a way that the charge stored in the capacitor accumulates during each switching cycle, so that a stepped ramp signal with linearity can be output. The macroscopic ramp signal output in this way is then compared with the input analog signal through the comparator (40), and then finally converted into a digital value and output through a conversion sequence of a dual-stage single-gradient structure.

[0064] Since the integrator of the switched capacitor type according to the present invention has the characteristic that the voltage of the output signal decreases stably with process deviation, the step-shaped ramp signal generated by the macroscopic ramp signal generator (20) according to the analog input signal range can serve as a reference point for determining the reference point of the microscopic ramp signal in the subsequent microscopic conversion step after the macroscopic conversion step is completed.

[0065] The macroscopic ramp signal generator (20) configured in this way can improve the sampling accuracy and conversion speed of the analog-to-digital converter, and can also compensate for the problem of process mismatch between devices through capacitance ratio control based on the switched capacitor circuit.

[0066] The micro ramp signal generator (30) can generate a micro ramp signal and, like the macro ramp signal generator (20), may include a switched capacitor integrator. The micro ramp signal generator (30) can generate a micro ramp signal having a waveform in which the voltage decreases differentially at regular time intervals after a reference point set based on the macro ramp signal.

[0067] Specifically, the microscopic ramp signal generator (30) can generate a voltage that is reduced by a predetermined unit voltage (e.g., LSB level) for each switching cycle by precisely redistributing the charge of a plurality of capacitors and switches by digital control based on the end point or trigger point of the macroscopic ramp signal, and output this as a microscopic ramp signal.

[0068] The macroscopic ramp signal generated by the macroscopic ramp signal generator (20) and the microscopic ramp signal generated by the microscopic ramp signal generator (30) are linear analog signals and have the characteristic of changing at a constant slope over a certain period of time. Therefore, based on the voltage arrival time, the counter (60) can easily calculate the upper bit and lower bit values ​​to be described later.

[0069] Specifically, the counter (60) calculates the pulses based on the clock signal until the moment the voltage level of the input signal matches during the rising or falling interval of the ramp signal, and then converts the corresponding time value into a digital value. At this time, the output digital output value is output as a final digital signal by combining the upper bit determined in the macroscopic conversion step and the lower bit determined in the microscopic conversion step.

[0070] The macroscopic ramp signal generator (20) and the microscopic ramp signal generator (30) according to the present invention generate a ramp signal using a switched capacitor-based integration circuit without using a resistance ladder structure or a current source-based converter, so the overall complexity of the circuit implementation can be reduced and nonlinearity can be minimized, and the sensitivity of the process can be reduced.

[0071] In addition, the macroscopic ramp signal generator (20) and the microscopic ramp signal generator (30) according to the present invention sequentially charge or discharge charges in a capacitor by comparing a sample with a preset reference voltage according to a plurality of sample clocks in a time-division manner. Accordingly, the amount of charge charged or discharged in the capacitor is precisely controlled by a switch control signal, thereby enabling the generation of a ramp signal with excellent linearity.

[0072] In particular, the switched capacitor integrator can provide high-precision analog-to-digital conversion results by expressing analog voltage fluctuations as quantified charging data values ​​through a method that performs the transfer and charging of equal capacitance in each cycle. Since this integration method does not use resistance values ​​or current sources sensitive to manufacturing process errors, it has low dependence on temperature and process variations. Therefore, it can realize precise digital signal output in conjunction with comparators and timing circuits, while simultaneously offering the advantages of reducing chip area and power consumption.

[0073] The comparator (40) can perform the function of comparing the analog signal input through the sampling holding circuit (10) with the ramp signal output from the macroscopic ramp signal generator (20) or the microscopic ramp signal generator (30).

[0074] As shown in FIG. 2, an analog signal passing through the sampling holding circuit (10) is input to the (+) input terminal of the comparator (40), and a macroscopic ramp signal or a microscopic ramp signal is input to the (-) input terminal. The signal output from the comparator (40) is transmitted to a D-flip-flop (50) and an up / down counter (60) connected to the output terminal of the comparator (40), so that a digital value can be finally output.

[0075] The signals input to the comparator (40) undergo a macro conversion step and a micro conversion step as they pass through a D-flip-flop (50) and a counter (60). Since the conversion is performed in such a way that an approximate voltage range is determined in the macro conversion step and detailed voltage values ​​are determined in the micro conversion step, the overall conversion error can be reduced and the resolution and signal speed can be improved simultaneously.

[0076] Specifically, in the macroscopic transformation step, the comparator (40) detects the point of intersection between the macroscopic ramp signal and the sampled input signal. Then, based on the detected point of intersection, the counter (60) determines the upper bit value based on the accumulated value output by the comparator (40).

[0077] Meanwhile, a holding capacitor (C) connected to the (-) terminal of the comparator (40). H2 ) can perform the role of storing the analog voltage of the macroscopic ramp signal corresponding to the upper bit in the macroscopic conversion stage. In addition, a tracking capacitor (C) connected to the (+) terminal of the comparator (40) H1 ) can sample and store the input signal (Vin) input to the comparator (40).

[0078] When the macroscopic conversion step is completed, the microscopic conversion step follows. In the macroscopic conversion step, a comparator with a long time response or a relatively slow clock frequency is used to determine the upper bit, whereas in the microscopic conversion step, a ramp signal set based on the upper bit value set in the macroscopic conversion step is set as the signal to be compared.

[0079] Accordingly, the counter (60) in the microscopic conversion stage determines the lower bit based on the value obtained by comparing the ramp signal and the analog input signal.

[0080] To this end, the microscopic ramp signal input to the comparator (40) is the microscopic ramp signal output from the microscopic ramp signal generator (30) described above, and this signal is V REFL It has a step wave shape that increases linearly from (the lower limit of the reference voltage). Therefore, since the comparator (40) can accurately separate the upper and lower bits, it can transmit a more accurate comparison value to the counter (60).

[0081] To explain the characteristics of this comparator (40) based on an environment requiring a total M+N bit resolution, first, in the M-bit macroscopic stage, the output value of the macroscopic stage closest to the input signal is determined based on a reference voltage having M-bit resolution and a macroscopic ramp signal value. Then, based on this result, to increase the precision of the conversion, it switches to an N-bit microscopic conversion stage to specifically perform a finer unit correction.

[0082] This dual-stage structure is 2, which is the total conversion time required by the conventional single-slope method. M+N 2, significantly less than the clock cycle M + 2 N Since only clock cycles are required, there is an advantage in that high resolution can be secured at a fast speed.

[0083] Therefore, the analog-to-digital converter according to the present invention can be easily applied to microcontrollers or high-speed sensor reading systems, thus offering the advantage of reducing the number of clocks while simultaneously decreasing the complexity of circuit implementation and power consumption. In addition, since the accuracy of the conversion is improved in the microscopic conversion stage by referring to the information obtained in the macroscopic conversion stage, there is also the advantage of simultaneously achieving clock optimization.

[0084] The output signal of the comparator (40) is sampled by a D-flip-flop (50), and the sampled signal is controlled by switches of a combinational logic circuit.

[0085] Specifically, the output signal of the comparator (40) is input to a D-flip-flop (50) and sampled according to a clock signal, and this sampled output is transmitted to an up / down counter (60) to control the direction of operation of the counter.

[0086] The counter (60) operates by counting up when the input ramp signal is lower than the reference analog input signal, and counting down when the ramp signal is higher than the reference analog input signal. Therefore, the digital signal finally output by the counter (60) is converted into a digital code representing the magnitude of the input analog signal and output.

[0087] This operation is based on a single slope-based analog-to-digital conversion architecture, and since the output of the comparator can be sampled in real time during the process of comparing the ramp signal and the analog signal, it has the advantage of reducing errors in the conversion process and improving resolution, while simultaneously ensuring high speed and high precision of the circuit.

[0088] FIG. 3 is a diagram showing a column-parallel structure of an image sensor chip including a dual-stage single gradient analog-to-digital converter array according to one embodiment of the disclosed invention in a column ADC region.

[0089] A dual-stage single-slope analog-to-digital converter (1) according to one embodiment has a structure in which a plurality of analog-to-digital converters are arranged in parallel as shown in the drawing, and this parallel configuration can be implemented as a column-parallel structure.

[0090] Specifically, each column is formed with independently operating units, and, for example, four adjacent analog-to-digital converters can be designed to share a single ramp signal generator. In this case, the ramp signal generator can serve to distribute signals to the four analog-to-digital converters through a switching control signal.

[0091] This configuration enables the conversion of analog input signals into digital values ​​more precisely and quickly. Furthermore, by allowing multiple analog-to-digital converters to share the ramp signal generator, the number of ramp signal generators in the entire circuit can be reduced, offering the advantage of minimizing the overall circuit area and power consumption.

[0092] Each analog-to-digital converter processes the signal through two stages, a sampling stage and a comparison stage, as described in Fig. 2, and is designed to independently control the start and end times of each ramp signal. In particular, since the switching control signal performs the role of adjusting the timing so that the output of the ramp signal generator is accurately distributed to each analog-to-digital converter, it has the advantage of effectively solving problems related to signal distortion or timing delay that may occur during high-speed operation.

[0093] FIG. 4 is a diagram showing the timing diagram of a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention.

[0094] As illustrated in FIG. 4, a dual-stage single gradient analog-to-digital converter (1) according to one embodiment operates repeatedly in a cycle of a reset stage - a macroscopic conversion stage - a preset stage - a microscopic conversion stage.

[0095] In the reset step applied prior to the macroscopic conversion step, the operation is initialized according to the reset signal (RST), and during the reset process, the input nodes of the comparator (40) are initialized to the reference voltage (VREF). Therefore, when the comparator (40) performs a comparison operation, the parasitic capacitance in the initial state can be prevented from affecting the comparator (40).

[0096] Specifically, the reset step consists of setting the upper node and the lower node, each connected to the input terminal of the comparator (40), to a reference voltage to remove the charge state that is unbalanced or accumulated at the start of the analog-to-digital conversion. Accordingly, in the macroscopic conversion step performed after the reset step, the comparator (40) can perform a comparison operation on the input signal without error.

[0097] In addition, by applying a reference voltage, the unnecessary charge influence that may occur due to the inter-line capacitance of the input terminal of the comparator (40) or parasitic capacitance present in the wiring during the reset period is completely discharged or eliminated, so there is an advantage that the output data of the comparator (40) does not have errors.

[0098] Accordingly, the reset step according to one embodiment can stabilize the initial state in analog-to-digital conversion and effectively implement a capacitance prevention function, thereby enabling accurate timing comparison operations and reliable data output.

[0099] When the reset step is completed, the macroscopic conversion step proceeds. In the macroscopic conversion step, as previously described, a signal of the waveform is input to the comparator (40) by the macroscopic ramp signal generator (20) as shown in FIG. 4.

[0100] Specifically, the macroscopic ramp signal generator (20) has a fixed reference voltage difference V REFH and V REFL Using as the reference voltage, the difference value is 2 M After generating a dual-step ramp signal divided equally into steps, a ramp signal having a voltage form that decreases stepwise over time is output, synchronized with a clock signal.

[0101] The macroscopic ramp signal output from the macroscopic ramp signal generator (20) is designed to have a total resolution of M bits, with the voltage value decreasing by one step at a time interval equal to the number of clock signals.

[0102] Therefore, since the macroscopic ramp signal generates a ramp waveform based on a fixed reference voltage that is divided equally, it has the advantage of being able to detect the exact value of the input signal more precisely. In addition, since this ramp signal generation method is linked with digital control logic after an analog comparator, it enables precise timing detection, and consequently, has the advantage of enabling high-precision analog-to-digital conversion operations.

[0103] Once the macroscopic transformation stage is completed, the preset stage proceeds, and in the preset stage, the first parasitic capacitance (C P1 ) and secondary parasitic capacitance (C P2 The voltage of ) is V REFL It is initialized to.

[0104] The microscopic ramp signal used in the microscopic transformation step is the reference voltage V, as illustrated in the figure. REFLIt has a step wave shape that increases linearly starting from, and such a microscopic ramp signal can be generated by a switched capacitor integrator.

[0105] Specifically, the switched capacitor integrator is driven in an integral manner that performs charging or discharging operations according to an input signal during a predetermined clock cycle, and can output an incremental waveform implemented by dividing the difference between a predetermined reference voltage into multiple charging cycles according to timing control as the final output signal.

[0106] Inside the switched capacitor integrator, a fixed-capacity sampling capacitor and a charge storage capacitor are interconnected, and during the sampling stage, the reference voltage V REFL After starting from, a preset reference voltage is applied as input. Therefore, since a charge of a fixed size accumulates over time intervals, a step-shaped ramp signal can be generated and output.

[0107] These ramp signals can be periodically reset, and the slope and step interval of the ramp can be precisely controlled according to the clock period, charge magnitude, and switch timing. Consequently, analog-to-digital conversion with high resolution and high accuracy can be performed.

[0108] FIG. 5 is a diagram illustrating the circuit in the macroscopic conversion stage of a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention.

[0109] Referring to FIG. 5, in the macroscopic conversion step, a holding capacitor (C) connected to the (-) terminal of the comparator (40) H2 ) can perform the role of storing the analog voltage of the macroscopic ramp signal corresponding to the upper bit in the macroscopic conversion stage. A tracking capacitor (C) connected to the (+) terminal of the comparator (40) H1 The input signal (Vin) input to the comparator (40) can be sampled and stored in ).

[0110] Specifically, in the macroscopic transformation step, an input signal (Vin) is input to the (+) input terminal of the comparator (40), and a holding capacitor (C H2 ) contains the voltage of the macroscopic ramp signal (V RC ) and reference voltage (V REFL The difference of (V RC - V REFL ) voltage is stored, and a macroscopic ramp signal (V) is stored at the (-) input terminal of the comparator (40). RC ) is connected and input. At this time, the macroscopic ramp signal V RC can be defined as shown in [Equation 1] below.

[0111] [Mathematical Formula 1]

[0112] V RC [m] = V REFH - (m / 2 M ) Х (V REFH - V REFL )

[0113] V in mathematical formula (1) REFH and V REFL and represent the upper and lower limits of the input voltage Vin, respectively, and m is the time (cycle) index, 0, 1, 2, ..., 2 M It has the value of . M represents the number of bits allocated to the macroscopic transformation.

[0114] Over time, the macroscopic ramp signal is the initial value V REFH It gradually decreases in a step-like shape from, and V RC [m] < V in When this happens, the output polarity of the comparator (40) is reversed and the switch is opened, and at this time the holding capacitor (C H2 At both ends of ) (V RC [m] - V REFL The voltage is stored, and the counter value at that moment is determined as a digital code corresponding to the upper bit.

[0115] FIG. 6 is a diagram illustrating the circuit in the microscopic conversion stage of a dual-stage single gradient analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 7 is a diagram illustrating the input terminal circuit in the microscopic conversion stage according to FIG. 6, and FIG. 8 is a diagram illustrating the ramp signal terminal circuit in the microscopic conversion stage according to FIG. 6.

[0116] Referring to FIG. 6, according to one embodiment of the present invention, 2 M After several clock cycles, the macroscopic transformation phase ends, and the microscopic transformation phase proceeds through the preset phase.

[0117] In the microscopic transformation step, the voltage of the (+) node of the comparator (40) is the first tracking capacitor (C H1 ) and first-generation capacitance (C P1 It is determined based on the amount of charge sharing stored in ).

[0118] The voltage of the (-) node of the comparator (40) is the output voltage (V) of the microscopic ramp signal generator. RF ) and the holding capacitor (C) in the macroscopic conversion stage H2 The amount of charge due to the voltage stored in ) and the second parasitic capacitance (C P2 It is determined by the result of charge sharing with the charge amount of ), and at this time V RF It is determined as shown in the mathematical formula (2) below.

[0119] [Mathematical Formula 2]

[0120] V RF [n] = V REFL + ( ) Х (V REFH - V REFL )

[0121] In mathematical formula (2), n is the time (cycle) index, 0, 1, 2, ..., 2 NIt has the value of , where N represents the number of bits allocated to the microscopic transformation, and as time (cycle) progresses, the microscopic ramp signal as shown in Fig. 4 is the initial value V RC It operates by starting from [m] and increasing in a step-like manner.

[0122] Referring to FIGS. 7 and 8, a dual-stage single-slope analog-to-digital converter according to one embodiment of the disclosed invention comprises a tracking capacitor (C) to precisely convert an input voltage into a digital value. H1 ) and holding capacitor (C H2 It includes a tracking capacitor (C). Specifically, it includes a tracking capacitor (C H1 ) and holding capacitor (C H2 Since it is designed to have the same capacitance, voltage errors that may be induced from asymmetry in capacitance values ​​can be effectively eliminated.

[0123] That is, in the case of the present invention, the tracking capacitor (C H1 ) and holding capacitor (C H2 By designing the capacitors with the same capacitance, the charge sharing effect caused by parasitic capacitance is made to have the same effect on both capacitors. Through this, the present invention minimizes signal distortion caused by parasitic capacitance and enables more precise analog-to-digital conversion.

[0124] Meanwhile, the voltage error on the (+) side due to parasitic capacitance in the microscopic conversion stage is given by the following mathematical equation (3).

[0125] [Mathematical Formula 3]

[0126] - (C P1 / (C H1 + C P1 )) Х (V in - V REFL )

[0127] Meanwhile, the voltage error on the (-) side due to parasitic capacitance in the microscopic conversion stage is given by the following mathematical equation (4).

[0128] [Mathematical Formula 4]

[0129] - (C P2 / (C H2 + C P2 )) Х (V RC [m] - V REFL )

[0130] C H1 =C H2 , C P1 =C P2 Igo, Vin V RC Since [m], the two voltages become very similar, so the error caused by parasitic capacitance can be canceled out. That is, in the case of the present invention, signal distortion caused by parasitic capacitance is minimized through this method, and more precise analog-to-digital conversion is made possible.

[0131] FIG. 9 is a diagram showing a macroscopic ramp signal generator circuit in a dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention. FIG. 10 is a diagram showing a microscopic ramp signal generator circuit in a dual-stage single-gradient analog-to-digital converter according to one embodiment of the disclosed invention.

[0132] Referring to FIGS. 9 and 10, a dual-stage single-slope analog-to-digital converter (1) according to one embodiment of the present invention generates a precise stepped waveform by applying a ramp signal generator using a switched capacitor integrator that utilizes the ratio of capacitors.

[0133] Therefore, the converter according to the present invention has the advantage of minimizing the influence of parasitic capacitance.

[0134] For example, to obtain a resolution of about 10 bits, the signal-to-noise ratio (SNR) must be secured at a level of about 62 dB. Although the effect of parasitic capacitance can be reduced by increasing the size of the holding capacitor, if the capacitor becomes excessively large, it is difficult to place the capacitor within the column pitch. However, using the tracking technique proposed in the present invention has the advantage of effectively solving this parasitic capacitance problem without significantly increasing the size of the holding capacitor.

[0135] So far, we have examined in detail the structure and operating principle of a dual-stage single gradient analog-to-digital converter according to one embodiment of the present invention.

[0136] A dual-stage single-slope analog-to-digital converter according to one embodiment has the advantage of being able to respond more efficiently to conversion speed requirements due to an increase in the number of pixels than a conventional single-slope analog-to-digital converter by being placed within the column pitch of a CMOS image sensor.

[0137] In particular, a dual-stage single-gradient analog-to-digital converter according to one embodiment can effectively improve the overall conversion speed through a dual conversion process divided into a macroscopic stage and a microscopic stage. For example, when the conversion of a total M+N-bit resolution is divided into a macroscopic M-bit and a microscopic N-bit, approximately 2 M + 2 N The conversion is completed using only the conference clock signal, eliminating the 2 required in the conventional single-stage method M+N It can achieve a much faster speed compared to the conference clock.

[0138] In addition, since the dual-stage single-slope analog-to-digital converter according to one embodiment is designed with a circuit capable of offsetting errors caused by parasitic capacitance during macroscopic conversion voltage transfer, it has the advantage of minimizing signal distortion that may occur during the conversion process and improving precision through a parasitic capacitance correction function.

[0139] In addition, since the dual-stage single gradient analog-to-digital converter according to one embodiment can be implemented with a relatively simple structure compared to conventional technology, circuit design is easy, which has the advantage of reducing manufacturing costs and improving design efficiency.

[0140] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on the operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0141] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0142] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0143] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents. Therefore, other implementations, other embodiments, and equivalents to the claims below are also within the scope of the claims.

Claims

Claim 1 A dual-stage single gradient analog-to-digital converter comprising: a sampling holding circuit receiving an analog signal input; a macroscopic ramp signal generator generating a macroscopic ramp signal; a microscopic ramp signal generator generating a microscopic ramp signal; a holding capacitor; a comparator; and a counter accumulating a comparison result according to the progression of a clock signal; and performing dual-stage conversion of a macroscopic conversion stage and a microscopic conversion stage. Claim 2 A dual-stage single gradient analog-to-digital converter according to claim 1, wherein a tracking capacitor of the same size as the holding capacitor is connected to the input terminal of the comparator. Claim 3 In paragraph 2, the microscopic conversion step comprises a step in which charge sharing is induced between the tracking capacitor and the parasitic capacitance of the input terminal of the comparator, and an error caused by the shared charge is offset, in a dual-stage single gradient analog-to-digital converter. Claim 4 In claim 1, the macroscopic ramp signal generator or the microscopic ramp signal generator comprises a switched capacitor circuit, a dual-stage single gradient analog-to-digital converter. Claim 5 A dual-stage single gradient analog-to-digital converter comprising: a sampling hold circuit for sampling and holding an analog input signal at a certain point in time; a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal; a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a certain unit voltage interval based on information obtained in a macroscopic conversion step; a comparator for generating an output signal by sequentially comparing the input signal with each ramp signal; a D-flip-flop for sampling the output signal of the comparator according to a clock signal; and a counter for performing a count according to the output of the D-flip-flop. Claim 6 A dual-stage single slope analog-to-digital converter, further comprising: a tracking capacitor that samples and stores the input signal; and a holding capacitor that stores the voltage of the macroscopic ramp signal in claim 5. Claim 7 In claim 5, the macroscopic ramp signal generator and the microscopic ramp signal generator comprise a switched capacitor integrator, wherein the switched capacitor integrator generates a stepped ramp signal that decreases or increases linearly at each cycle set based on the difference in reference voltage, a dual-stage single-gradient analog-to-digital converter. Claim 8 In claim 5, the counter is a dual-stage single gradient analog-to-digital converter that performs a macroscopic conversion step of calculating an upper bit based on a comparison result calculated by comparing the input signal input to the comparator with the macroscopic ramp signal. Claim 9 In claim 8, the counter is a dual-stage single gradient analog-to-digital converter that performs a microscopic conversion step of calculating a lower bit based on a comparison result calculated by comparing the input voltage input to the comparator with the microscopic ramp signal. Claim 10 A dual-stage single gradient analog-to-digital converter, wherein, in claim 8, the counter performs the macroscopic conversion step by performing a count equal to the number of clock cycles to produce the upper bit. Claim 11 In claim 9, the counter performs the microscopic conversion step by performing an additional count on the waveform of the microscopic ramp signal set based on the result of the macroscopic conversion step to produce the lower bit, thereby forming a dual-stage single gradient analog-to-digital converter. Claim 12 A dual-stage single gradient analog-to-digital converter, wherein between the macroscopic conversion step and the microscopic conversion step, a preset step is performed in which the input terminal and capacitor terminal of the comparator are initialized to the reference voltage. Claim 13 In claim 5, the sampling maintenance circuit comprises a Correlated Double Sampling Circuit that removes high-frequency noise from the input analog signal and maintains the basis signal component, in a dual-stage single gradient analog-to-digital converter. Claim 14 In claim 6, a dual-stage single gradient analog-to-digital converter in which the tracking capacitor and the holding capacitor have the same capacitance. Claim 15 A sampling hold circuit for sampling and holding an analog input signal at a certain point in time; a macroscopic ramp signal generator for generating a macroscopic ramp signal comparable to the sampled input signal; a microscopic ramp signal generator for generating a microscopic ramp signal that changes at a fixed unit voltage interval based on information obtained in a macroscopic conversion step; a comparator for generating an output signal by sequentially comparing the input signal with each ramp signal; a D-flip-flop for sampling the output signal of the comparator according to a clock signal; and a counter for performing a count according to the output of the D-flip-flop; wherein the comparator, the D-flip-flop, and the counter have a total clock cycle of 2 for the conversion of a resolution of M+N bits. M + 2 N Dual-stage single-slope analog-to-digital converter operating in a single cycle. Claim 16 A dual-stage single slope analog-to-digital converter, further comprising: a tracking capacitor that samples and stores the input signal; and a holding capacitor that stores the voltage of the macroscopic ramp signal in claim 15. Claim 17 In paragraph 15, the macroscopic ramp signal generator and the microscopic ramp signal generator comprise a switched capacitor integrator, wherein the switched capacitor integrator generates a stepped ramp signal that decreases or increases linearly at each cycle set based on the difference in reference voltage, a dual-stage single-gradient analog-to-digital converter. Claim 18 In paragraph 15, the counter is a dual-stage single gradient analog-to-digital converter that performs a macroscopic conversion step of calculating an upper bit based on a comparison result calculated by comparing the input signal input to the comparator with the macroscopic ramp signal. Claim 19 In paragraph 15, the counter is a dual-stage single gradient analog-to-digital converter that performs a microscopic conversion step of calculating a lower bit based on a comparison result calculated by comparing the input signal input to the comparator with the microscopic ramp signal. Claim 20 In claim 19, the above counter performs the macroscopic digital conversion step by performing a count equal to the number of clock cycles to produce the upper bit and the lower bit, a dual-stage single gradient analog-to-digital converter.

Images