Via formation using imprint lithography and retargeting vias formed by same

Abstract

A resist layer is formed on a dielectric layer. A pattern of via openings is imprinted into the resist layer, for example, using nanoimprint lithography. After imprinting, the pattern of via openings imprinted in the resist layer is transferred to the dielectric layer by anisotropic etching to form via openings within the dielectric layer. Anisotropic etching has a low etching selectivity ratio between the resist layer and the dielectric layer. The via openings within the dielectric layer are filled with an electrically conductive material to form vias within the dielectric layer. The centerline of at least one retargeting via among the vias is not parallel to the centerline of at least one other via among the vias.

Description

Technology Field

[0001] This application claims priority to U.S. provisional application No. 63 / 762,821 filed on February 25, 2025. The entirety of U.S. provisional application No. 63 / 762,821 filed on February 25, 2025 is incorporated herein by reference. Background Technology

[0002] The following relates to integrated circuit (IC) technology, three-dimensional integrated circuit (3DIC) technology, IC manufacturing technology, back end-of-line (BEOL) processing technology, semiconductor manufacturing technology, and related technologies.

[0003] In the BEOL process step of IC manufacturing, a metallization stack is formed to electrically interconnect the electronic devices of the IC and to provide bonding pads, etc., for external electrical connections of the IC. The metallization stack comprises patterned metallization layers interconnected by vias, and the metallization layers and vias are disposed or embedded within an intermetal dielectric (IMD) material, which is also referred to in the art by similar nomenclature such as interlayer dielectric (ILD) material.

[0004] In a 3DIC design, a metallization stack may be formed on two (or more) processed wafers, and the metallization stack has aligned surface bonding pads that allow the two wafers to be bonded together, and electrical interconnection is made at these aligned surface bonding pads. means of solving the problem

[0005] Some additional embodiments are described below.

[0006] In a non-limiting exemplary embodiment, a via formation method comprises the steps of: forming a dielectric layer on a substrate; forming a resist layer on the dielectric layer; applying a patterned mask to the resist layer to transfer the pattern of the patterned mask onto the resist layer; curing the patterned resist layer; removing the patterned mask; etching via openings within the dielectric layer based on the patterned resist layer; and filling the via openings with an electrically conductive material to form vias.

[0007] In a non-limiting exemplary embodiment, a via formation method comprises the steps of: forming a resist layer on a dielectric layer; imprinting a pattern of via openings within the resist layer; after imprinting, transferring the pattern of via openings imprinted within the resist layer to the dielectric layer by anisotropic etching to form via openings within the dielectric layer; and filling the via openings within the dielectric layer with an electrically conductive material to form vias within the dielectric layer.

[0008] In a non-limiting exemplary embodiment, the electrical connection structure comprises: a first patterned metal layer; a dielectric layer disposed on the first patterned metal layer; a second patterned metal layer disposed on the dielectric layer—the dielectric layer is disposed between the first patterned metal layer and the second patterned metal layer—; and vias passing through the dielectric layer and connecting the first patterned metal layer and the second patterned metal layer. The centerline of at least one retargeting via among the vias is not parallel to the centerline of at least one other via among the vias.

[0009] In a non-limiting exemplary embodiment, a nano imprint lithography (NIL) mask comprises a mask substrate and a patterned layer disposed on the mask substrate. The patterned layer comprises at least one protrusion having a slanted sidewall corresponding to a via opening having a corresponding slanted sidewall. Brief explanation of the drawing

[0010] The embodiments of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. In accordance with standard practice in the industry, it should be noted that various features are not drawn to actual scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. Figure 1 schematically illustrates a method for manufacturing a metallized layer using vias, a photolithography method, and an imprint lithography method. Figure 2 schematically illustrates a via manufacturing method using a replication mask. Figure 3 schematically illustrates a via manufacturing method that does not use a replication mask. FIG. 4 schematically illustrates a method for manufacturing vias having a designed three-dimensional geometry using repeated electron beam recording and etching of a master mask. Figure 5 schematically illustrates a method for manufacturing a retargeting via using repeated electron beam recording and etching of a master mask. Figure 6 illustrates a flowchart of a method using a master mask and a replica mask for higher productivity in via fabrication by imprint lithography. Figure 7 illustrates a flowchart of a via manufacturing method using imprint lithography. FIGS. 8A, FIGS. 8B, FIGS. 8C, FIGS. 8D, and FIGS. 8E illustrate cross-sectional views after selected steps of the via manufacturing method of FIG. 7. Figure 9 illustrates a flowchart of a method for manufacturing patterned metal layers and vias using imprint lithography. FIGS. 10a, FIGS. 10b, FIGS. 10c, FIGS. 10d, FIGS. 10e, FIGS. 10f, FIGS. 10g, FIGS. 10h, and FIGS. 10i illustrate cross-sectional views after selected steps of the via manufacturing method of FIG. 9. FIGS. 11a, FIGS. 11b, FIGS. 11c, FIGS. 11d, and FIGS. 11e illustrate some non-limiting examples of three-dimensional via geometries obtainable using via fabrication with imprint lithography as disclosed herein. FIG. 12 illustrates a cross-sectional view of exemplary vias having labeled dimensions. FIGS. 13a, FIGS. 13b, FIGS. 13c, and FIGS. 13d illustrate the formation of a metallized stack by repeated iterations of the via manufacturing method of FIG. 7. Specific details for implementing the invention

[0011] The disclosure below provides various embodiments or examples for implementing various features of the disclosed invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on or above the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplification and clarification, and such repetition itself does not affect the relationship between the various embodiments and / or configurations disclosed.

[0012] Additionally, spatial relative terms such as "below," "bottom," "lower," "above," and "above" may be used herein for ease of explanation to describe the relationship between one element or feature and another element(s) or feature(s) shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented differently (rotated 90° or rotated to a different orientation), and accordingly, the spatial relative terms used herein may be interpreted in the same way.

[0013] The embodiments disclosed herein provide a via and a method for manufacturing the via that enable or facilitate via retargeting. As used herein, via retargeting refers to the top portion of the via (i.e., where the via intersects the upper metallized portion (Mx)) having a different shape and / or being laterally shifted with respect to the bottom portion of the via (i.e., where the via intersects the lower patterned metallized portion (Mx-1)). Such retargeting may provide improved flexibility in via routing in a metallized stack, enable the rerouting (e.g., spreading) of via connections in the patterned metallized Mx layer compared to via connections in the patterned metallized Mx-1 layer, improve the arrangement of bonding pads to which the vias are connected, and / or provide other design advantages. In some embodiments of the present invention, a combination of imprint lithography having a low etching selectivity and anisotropic etching enables the formation of these retargeted vias. In contrast, vias formed by a photolithography process are difficult or impossible to retarget.

[0014] Referring to FIG. 1, a cross-sectional view of vias (1) defined by a photolithography method passing through an intermetal dielectric (IMD) layer (2) to connect a first (e.g., lower, Mx-1) patterned metal layer and a second (e.g., upper, Mx) patterned metal layer is shown. The two metal layers (Mx-1, Mx) may be adjacent layers of a metallization stack, and the vias (1) defined by a photolithography method are connecting vias of the metallization stack. The vias (1) defined by a photolithography method are formed by a photolithography patterning process (3), and the photolithography patterning process (3) comprises: an operation (4) of forming an opening in a photoresist disposed on the IMD layer (2); and an operation (5) of etching the via opening in the IMD (2) through the opening in the photoresist. The method includes an operation (6) in which a via opening within the IMD (2) is filled with a conductive material (e.g., copper, tungsten, etc.) to form a via (1). The vias (1) defined by photolithography have mutually parallel centerlines (7). The mutually parallel centerlines (7) of the vias (1) defined by photolithography are orthogonal (i.e., perpendicular) to the surface of the IMD layer (2) corresponding to the Mx-1 layer. The mutually parallel centerlines (7) of the vias (1) defined by photolithography are orthogonal (i.e., perpendicular) to the surface of the IMD layer (2) corresponding to the Mx layer. The bottom and top of each via (1) defined by photolithography (i.e., “bottom and top” refer to the points where the via (1) defined by photolithography intersects the Mx-1 layer and the Mx layer, respectively) are aligned perpendicularly to the center axis (7) of the via (1) defined by photolithography. These geometric characteristics of the vias (1) defined by a photolithographic method are due to the nature of the formative photolithographic treatment (4) and etching (5) that etch the via openings along mutually parallel etching directions starting from each photolithographically defined opening within the patterned photoresist layer.

[0015] FIG. 1 further illustrates vias (100, 101, 102) formed within an IMD layer (12) using a different method (13) that also includes a lithography operation (14), an etching operation (15), and a via filling operation (16). In addition to a cross-sectional view of the vias (100, 101, 102) and the Mx-1 and Mx patterned metallized layers, FIG. 1 also illustrates a perspective view (20) of the vias (100, 101, 102) and the Mx-1 and Mx metallized layers. As the vias (20) are connected between the Mx-1 and the Mx patterned metallized layers, the vias (20) may also be referred to by notations such as via (Vx). Method (13) differs in part from photolithography method (3) in that the lithography operation (14) of method (13) is not a photolithography operation, but an imprint lithography operation (14) in which a pattern of via openings is imprinted onto a resist placed on an IMD layer. Imprint lithography in the context of semiconductor integrated circuit (IC) manufacturing is sometimes referred to as nano imprint lithography (NIL), and thus the operation (14) may also be referred to here as a NIL operation (14).

[0016] The photolithography operation (4) of the photolithography via formation method (3) typically etches an opening that passes through the photoresist. In contrast, the NIL operation (14) imprints a pattern of via openings.

[0017] NIL uses a stamp to mechanically imprint features onto a resist layer placed on a semiconductor wafer, such as a monomer or polymer resist. In a non-limiting descriptive NIL process for performing the NIL operation (14), the resist is spin-coated onto the semiconductor wafer. The stamp is pressed onto the resist to mechanically transfer the features of the stamp to the resist. While the stamp is pressed onto the resist, ultraviolet (UV) light is applied to cure the resist, and then the stamp is removed, leaving the mechanically transferred features on the cured resist. NIL can provide CD comparable to that obtainable by extreme ultraviolet (EUV) lithography at a lower cost. As a mechanical process, NIL may be affected by mechanical distortion, thermal expansion or shrinkage, etc., of the stamp and / or the semiconductor wafer. To provide overlay compensation in the NIL, in some embodiments, the stamp is controlled by finger actuators arranged to apply pressure to the transverse edges of the stamp. The finger actuators may be piezoelectric actuators, electrostatic actuators, microstepper motors (e.g., implemented using MEMS), etc. By adjusting the forces applied by each finger actuator, translational and rotational control of the stamp can be achieved. If all finger actuators are pressed inward with increased force, this may provide a negative magnification, whereas if all finger actuators are pressed inward with decreased force, this may provide a positive magnification. In some embodiments, to provide adjustment of the wafer to implement NIL overlay compensation, a laser or other light source illuminates a digital mirror device (DMD) to apply different levels of light to different parts of the IC die to create a thermal distribution that causes thermal expansion or contraction.These are merely some non-limiting explanatory examples of NIL.

[0018] As further described herein, the pattern of via openings generated by the NIL operation (14) differs in at least two aspects from the photolithographically formed openings generated by the operation (4), the pattern of via openings generated by the NIL operation (14) does not necessarily pass through the resist layer; the pattern of via openings generated by the NIL operation (14) constitutes a three-dimensional representation (i.e., an imprint) of the three-dimensional shape of the via openings to be formed. The imprint lithography operation (14), together with a suitable design of the subsequent etching operation (15), advantageously enables the formation of via openings within the IMD (12) having designed three-dimensional geometries, and accordingly, when the via openings are filled in the operation (16), the resulting vias (100, 101, 102) also have designed three-dimensional geometries.

[0019] Referring again to the cross-sectional and perspective views (20) of the vias (100, 101, 102), in this non-limiting illustrative example, the vias (100, 101, 102) have centerlines (17) that are not mutually parallel. This is because the two outer vias (101, 102) each include additional parts (20) that shift their respective centerlines (17) outward relative to the central via (100). This asymmetrically enlarges the tops of the two outer vias (101, 102) with respect to their respective bottoms and laterally shifts the tops of the two outer vias (101, 102) outward (i.e., away from the central via (100)) relative to their respective bottoms.

[0020] Now, referring to FIG. 2, in an additional optional embodiment, a master mask (30) may be provided, and the mask (32) used to form an imprint pattern of via openings in the resist in operation (14) of FIG. 1 may be a “replication” mask (32) created using the master mask (30) in some embodiments. FIG. 2 schematically illustrates a non-limiting example of such a process. As illustrated in the “master mask manufacturing” section on the left side of FIG. 2, the master mask (30) is manufactured by applying an electron beam (e-beam) resist (34) onto a substrate (36) (e.g., an exemplary quartz substrate (36), but other suitable rigid substrate materials are conceivable) and performing e-beam recording of a pattern on the resist. (Note that the example of FIG. 2 includes an optional adhesive layer (35) comprising, for example, a polymer and additives for hydrophilic adjustment to improve the adhesion of the resist (34) to the substrate (36). This adhesive layer may be omitted if the resist adheres sufficiently well to the substrate without the adhesive layer.) The e-beam recording pattern is removed by developing the e-beam resist using a suitable developer, subsequent etching forms a recess (38) aligned with the e-beam recording opening, and then the e-beam resist is removed using a suitable e-beam resist stripper. (Note that the left side view of FIG. 2 illustrates a side cross-sectional view of a master mask (30) having a recess (38) and also a top view of a portion of the master mask (30) showing four exemplary recesses (38).)

[0021] The middle section of FIG. 2 illustrates a “replication manufacturing”. As illustrated herein, a resist layer (40) is formed on a replication mask substrate (42) (e.g., an exemplary fused silica replication mask substrate (42), but other suitable rigid substrate materials are conceivable), and a master mask (30) is pressed onto the resist (40) to imprint a pattern (inverted) of the recesses of the master mask (30) onto the resist (40). The imprinted pattern is inverted in such a way that the recesses (38) of the master mask (30) are imprinted as protrusions within the resist (40). The resist (40) having the imprinted pattern of protrusions is cured using ultraviolet (UV) light (44), and then the master mask (30) is removed. Anisotropic etching having a low selectivity between the material of the resist (40) and the material of the substrate (42) is performed, which transfers the pattern of protrusions imprinted on the resist (40) to the replication mask substrate (42) to produce a replication mask (32) having the transferred protrusions (48). (Note that the center view of FIG. 2 illustrates a side cross-sectional view of the replication mask (32) having the protrusions (48) and also illustrates a top view of a portion of the replication mask (32) showing four exemplary protrusions (48).)

[0022] The right portion of FIG. 2 illustrates "wafer imprinting" corresponding to operations (14, 15) of the method (13) of FIG. 1. As illustrated herein, a resist layer (50) is formed on an intermetal dielectric (IMD) layer (52) disposed on a semiconductor wafer (54). A replica mask (32) is pressed onto the resist (50) to imprint a pattern (inverted) of protrusions of the replica mask (32) onto the resist (50). The imprinted pattern is inverted in such a way that the protrusions (48) of the replica mask (32) are imprinted as recesses within the resist (50). The resist (50) having the imprinted pattern of recesses is cured using UV light (56), and then the replica mask (32) is removed. Anisotropic etching having a low selectivity between the material of the resist (50) and the dielectric material of the IMD layer (52) is performed, which transfers the pattern of recesses imprinted on the resist (50) to the IMD layer (52), thereby transferring the pattern of recesses to the IMD material (52) to form via openings (58) within the IMD layer (52). (Note that the right side view of FIG. 2 illustrates a side cross-sectional view of a final wafer (54) having an IMD layer (52) having recesses (58) and also illustrates a top view of a portion of the IMD layer (52) showing four exemplary recesses (58).)

[0023] In the example of FIG. 2, the master mask (30) is used to generate a replica mask (32), and the replica mask (32) is then used in the imprint operation (14) of FIG. 1. This has certain advantages. In particular, while the manufacture of the master mask (30) can be complex (as will be described in more detail later in this invention), the manufacture of the replica mask (32) involves a relatively simple imprint operation. Advantageously, a single master mask (30) may be used to manufacture a plurality of replica masks (32).

[0024] However, referring to FIG. 3, alternatively, the direct use of the master mask (30) for the imprint operation (14) of FIG. 1 is considered. FIG. 3 illustrates such a process flow, which includes master mask fabrication corresponding to the master mask fabrication of FIG. 2, as illustrated on the upper left of FIG. 3. However, in the example of FIG. 3, this creates a modified master mask (30') in which the e-beam recording pattern includes protrusions (48). As illustrated on the right of FIG. 3, wafer imprinting uses the (modified) master mask (30') to imprint a pattern of via openings onto a resist (50) placed on an IMD layer (52), and then anisotropic and low selectivity etching transfers the imprinted pattern of via openings to the IMD layer (52) to form via openings (58). Thus, as illustrated in FIG. 3, the replication mask (32) can be optionally omitted from the process flow.

[0025] Returning to the example of FIG. 2 using a replication mask (32), the recess (38) of the master mask (30) has straight sidewalls, and thus the protrusion (48) of the replication mask (32) has straight sides and the via opening (58) has straight sides. However, by using repeated cycles of e-beam recording and etching in the manufacture of the master mask, a pattern of via openings can be formed on the surface of the master mask (30), thereby allowing the resulting via openings to have a designed three-dimensional geometry.

[0026] Referring to FIG. 4, a non-limiting illustrative example thereof is illustrated, which implements via openings having inclined sidewalls. As illustrated on the left side of FIG. 4, a substrate (36) (e.g., a quartz substrate in some non-limiting examples) undergoes a first e-beam recording and etching cycle labeled "E-beam recording #1 + etching #1," which forms shallow recesses of (relatively) large diameter within the substrate (36). This is followed by a second e-beam recording and etching cycle labeled "E-beam recording #2 + etching #2," which forms shallow recesses of slightly smaller diameter within the initial shallow recesses formed by the first "E-beam recording #1 + etching #1" cycle. This process is repeated in cycles of "E-beam recording #2 + etching #2", "E-beam recording #3 + etching #3", "E-beam recording #4 + etching #4", and the final "E-beam recording #5 + etching #5", with each successive cycle forming a smaller diameter recess within the previously formed recess. As shown in Figure 4, which illustrates the final master mask (30) after the final "E-beam recording #5 + etching #5" cycle, the resulting recess (38) has slanted sidewalls. Subsequently, the replication imprinting forms a corresponding protrusion (48) on the replication mask (32). As shown on the right side of FIG. 4, the step of “imprinting on the resist and transferring to the IMD by etching” (corresponding to operations (14, 15) of the via manufacturing method (13) of FIG. 1) forms a via opening (58) having a slanted sidewall similar to the slanted sidewall of the recess (38) of the master mask (30). FIG. 4 also illustrates the result of the final operation (16) of FIG. 1, namely “filling the vias,” where the via opening (58) is filled with an electrically conductive material (e.g., copper, tungsten, etc.) to form a via (20) passing through the IMD layer (52). The via (20) has a slanted sidewall corresponding to the slanted sidewall of the via opening (58).

[0027] In the example of FIG. 4, successive “E-beam recording + etching” cycles etch recesses that are concentric with each other but have progressively smaller diameters. This creates final recesses (38) that are conical in shape with circular upper and lower cross-sections (and circular cross-sections at all points between them). However, by shifting the successively etched recesses laterally, more complex via opening geometry can be formed.

[0028] Now, referring to FIG. 5, additional non-limiting illustrative examples are shown illustrating how the via formation method (13) of FIG. 1 can be used to form vias in which the centerlines (17) are not mutually parallel. The left side of FIG. 5 illustrates the fabrication of a master mask (30) using a 5-step etching sequence including an initial "E-beam recording #1 + etching #1" step, followed by an "E-beam recording #2 + etching #2" step, followed by an "E-beam recording #3 + etching #3" step, an "E-beam recording #4 + etching #4" step, and a final "E-beam recording #5 + etching #5" step. As further shown in the central part of FIG. 5, by shifting the successively etched recesses laterally, the centerlines of the resulting recesses (38) can be designed as centerlines that extend progressively outward toward the recesses closer to the periphery. FIG. 5 also schematically illustrates the imprinting of multiple (exemplary three) replica masks (32), each having a pattern of protrusions (48) corresponding to the recesses (38) of the master mask. The right portion of FIG. 5 illustrates the final vias (20) passing through the IMD (52) (i.e., corresponding to the result of operation (16) of FIG. 1). The centerlines (17) of the vias (20) are also shown, and it is seen that the centerlines (17) of the vias (20) are not mutually parallel, but rather the centerlines are inclined at increasingly larger angles so as to move further away from the vertical as the distance from the center of the set of vias (20) increases.

[0029] FIG. 5 also schematically illustrates a top view showing the top portion (20T) of the vias (20) and a bottom view showing the bottom portion (20B) of the vias (20). To provide an explanation of the orientation, XYZ directions are indicated. As labeled, the cross-section showing the centerlines (17) of the vias (20) is the XZ cutting plane. The top portion (20T) of the vias is shown by the XY plane, and the bottom portion (20B) of the vias is shown by the X-(-Y) plane. As can be seen in these figures, the bottom portions (20B) of the vias (20) have circular cross-sections and are uniformly spaced along the X direction. In contrast, the top portions (20T) of the vias (20) are spread out along the X direction, and the vias further away from the center of the set of vias have an increased length of the top portion (20T) of the vias. Meanwhile, the top of the via (20T) has the same length in the Y direction as the bottom of the via (20B). Thus, the top of the via (20T) is not circular, but an ellipse having a major axis along the X direction and a minor axis along the Y direction of each top of the via (20T). (Although not illustrated, in some examples the top of the via (20T) may be connected to and thus intersect with an Mx patterned metal layer.) FIG. 5 illustrates other features of the via (20) that can be designed, namely that the shape of the top of the via may be designed to be different from the shape of the bottom of the via (here, circular) (here, an elliptical shape that is non-circular). It will be understood that other via top and bottom shapes may be designed, including rectangular or square via top and / or bottom as additional non-limiting examples.

[0030] Generally, vias can be retargeted. Except for the central via, the vias (20) of FIG. 5 are retargeted vias. In some examples (such as FIG. 5), the retargeting via may have a non-circular cross-section at its intersection with the second (e.g., Mx) patterned metal layer. In some examples (such as FIG. 5), the retargeting via may have a circular cross-section at its intersection with the first (e.g., Mx-1) patterned metal layer and a non-circular cross-section at its intersection with the second (e.g., Mx) patterned metal layer. In some examples (such as FIG. 5), the retargeting via may have its intersection with the second (e.g., Mx) patterned metal layer offset laterally from its intersection with the first (e.g., Mx-1) patterned metal layer. This offset is the result that the centerlines (17) of the retargeted vias are not perpendicular to the surface of the dielectric layer (e.g., IMD layer (52)) on which the second patterned metal layer is placed.

[0031] Now, referring to FIG. 6, the entire process flow utilizing both a master mask (30) and one or more replica masks (32) is described. In operation (60), the master mask is formed by e-beam recording and anisotropic etching, as described by examples referring to FIG. 2, FIG. 4, and FIG. 5, for instance. In particular, operation (60) may be performed only once to produce a single master mask (30). Then, in operation (62-1), the replica mask may be formed by imprinting the master mask onto a replica mask blank by imprinting and subsequently by anisotropic and low selectivity etching, as described by examples referring to FIG. 2 and FIG. 4, for instance. Advantageously, this replica mask formation may be repeated, as indicated by a second instance (62-2) of replica mask formation in FIG. 6. More generally, one, two, three, four, five, or more replication masks may be formed by imprinting and appropriate etching of each replication mask substrate. After each replication mask (32) is formed, it may be used to imprint via openings (58) within the IMD layer (52) of successive wafers as shown in FIG. 6 by successive via opening imprint operations (64-1, 66-1, 68-1) using the replication mask produced in operation (62-1); and likewise successive via opening imprint operations (64-2, 66-2, 68-2) using the replication mask produced in operation (62-2). Accordingly, a single master mask (30) can be used to imprint a plurality of replica masks (32), and each of the replica masks (32) can be used to imprint a via opening (corresponding to operation (14) of FIG. 1). This advantageously enables rapid upscaling of the via formation process.

[0032] Now, with reference to the flowchart illustrated in FIG. 7 and the successive cross-sections illustrated in FIG. 8a, 8b, 8c, 8d, and 8e, another example of the via formation process (13) of FIG. 1 is described, which provides further explanation of some exemplary approaches for performing the via filling operation (16). In operation (70), a resist layer (50) is formed on an IMD layer (52) placed on a wafer (54). For example, in some embodiments, the resist layer (50) is spin-on. In some embodiments, there may be multiple resist layers, where the term imprint resist layer (50) is used to identify the top resist layer (50) on which the replication mask (32) will be imprinted. FIG. 8a illustrates a cross-section of the wafer after operation (70). In the example of FIG. 8a, an adhesive layer (71) is applied before the imprint resist layer (50) to promote adhesion.

[0033] In operation (72) (corresponding to operation (14) of FIG. 1), a copy mask (32) is pressed onto the imprint resist layer (50) to transfer a pattern of via openings (e.g., represented by protrusions (58) and recesses between protrusions) onto the resist layer (50), thereby forming an imprint on the imprint resist layer (50). Operation (72) may also optionally include a UV curing step ("wafer imprinting") as illustrated in FIG. 2, for example, and the subsequent removal of the copy mask (32). FIG. 8b illustrates a cross-sectional view after the copy mask (32) has been pressed onto the imprint resist layer (50) but before the subsequent removal of the copy mask. In operation (74) (corresponding to operation (15) in FIG. 1), anisotropic and non-selective etching is performed to transfer a pattern of via openings from the resist layer (50) to the IMD layer (52), resulting in the cross-section shown in FIG. 8c. The etching is anisotropic in that it preferentially etches downward rather than transversely, and is non-selective in that it etches the material of the resist layer (50) and the dielectric material of the IMD layer (52) at approximately the same etching rate. In some non-limiting examples, the etching used in operation (74) may be dry plasma etching using one or more etchants, such as C, O, H, Cl, or F-based etchant gases. The specific choice of etching may be optimized for a specific type of resist and a specific IMD material. (Note that the adhesive layer (71) is generally thin and is also etched in operation (74).) A transferred pattern of the via opening (58) is shown in FIG. 8C.

[0034] The via filling operation (16) of FIG. 1 corresponds to the metal deposition operation (76) of FIG. 7. Operation (76) may utilize copper electroplating to fill the via opening (58) with a conductive material (here, copper) to form the via (20), for example. In other embodiments, physical vapor deposition (PVD) may be used. Operation (76) also deposits excess copper (80) on the surface of the IMD layer (52). FIG. 8d shows a cross-sectional view after operation (76). In operation (78), chemical mechanical polishing (CMP) is performed to remove the excess conductive material (80), flatten the surface, and expose the top of the via (20), resulting in the structure shown in FIG. 8e. Subsequent processing (not shown) may, for example, deposit and pattern a metal layer to form an Mx layer in contact with the top of the via (20). In another example of subsequent processing (not shown), where the IMD layer (52) is the top layer, a bonding pad may be formed on the surface of the IMD layer (52) in contact with the via (Vx).

[0035] In some other embodiments, excess metal (80) deposited on the surface of the IMD layer (52) is utilized to form an Mx patterned metallized layer.

[0036] Now, with reference to the flowchart illustrated in FIG. 9 and the successive cross-sectional views illustrated in FIG. 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, and 10i, an example of a modified via formation process is described in which vias and an Mx metallization layer are formed simultaneously by utilizing excess metal deposited on a surface. In the initial operation (88) illustrated by the cross-sectional views ( FIG. 10a, 10b, 10c), an Mx metallization layer is defined. To this end, a layer (100) (labeled as "Membrane-A" in FIG. 10a and 10b) and a first resist layer (102) are formed on the dielectric layer (52). The result after these depositions is schematically illustrated in FIG. 10a (the first resist layer (102) is labeled as "Resist-A"). In a non-limiting illustrative example, film-A (100) is a dielectric material containing Si, C, H, O, N, etc. and is applied by chemical vapor deposition (CVD) or spin-on technology. Although a single layer is illustrated, film-A (100) may comprise two (or more) layers containing, for example, Si, O, N, etc. The first resist layer (102) may be a photoresist containing, for example, C, H, O, etc. A photolithography step patterns the first resist layer (102). For example, photolithography exposure may utilize deep ultraviolet (DUV) exposure, extreme ultraviolet (EUV) exposure, etc., followed by the development of a latent image using a developer suitable for the type of photoresist used. The result of photolithography exposure and development is illustrated in FIG. 10b, and an exemplary opening (104) in the first resist layer (102) is illustrated.Although a single opening (104) is illustrated by a schematic example, it should be noted that the opening (104) may represent a pattern of openings to ultimately define, for example, a patterned Mx metallization layer. In other words, the opening (104) represents an Mx metallization pattern. Subsequently, dry etching is performed to transfer the pattern from the developed resist-A (102) to the film-A (100) to create the structure illustrated in FIG. 10c. As shown here, the exemplary opening (104) is transferred to the film-A (100) as an opening (105) within the film-A (100). Again, although a single opening (105) is illustrated by a schematic example, the opening (105) may represent a pattern of openings to ultimately define, for example, a patterned Mx metallization layer. In other words, the opening (105) represents an Mx metallization pattern. In one non-limiting exemplary embodiment, the etching performed to transfer a pattern from the developed resist-A (102) to the film-A (100) may include dry plasma etching using an etchant based on C, O, H, Cl, F, etc., suitable for etching the material of the film-A (100).

[0037] Referring again to FIG. 9, following operation (88), operations (90, 92) similar or identical to the corresponding operations (70, 72) of FIG. 7 follow. In operation (90), an imprint resist layer (106) is formed. In this non-limiting illustrative example, the imprint resist layer (106) comprises a resist layer (50) (also labeled as "Resist-C" in FIG. 10d and FIG. 10e) corresponding to the resist layer (50) of the embodiment of FIG. 7 and FIG. 8a and FIG. 8b, and an optional adhesive layer (71) underneath, but the imprint resist layer (106) of the embodiment of FIG. 9 further comprises a resist layer (108) (also labeled as "Resist-B" in FIG. 10d and FIG. 10e) underneath. Resist-B (108) is an optional layer that may be included to improve the topography (fill plate) and may include, for example, a dielectric material containing C, H, O, etc. The adhesive layer (71) provides better adhesion between Resist-B and Resist-C. The adhesive layer (71) may contain C, H, O, etc. As in the example of FIG. 7, the Resist-C layer (50) is the layer on which the NIL is imprinted. FIG. 10d schematically illustrates the structure after the imprint resist layer (106) is formed according to operation (90). In operation (92), an imprint is formed on the imprint resist layer (50) by pressing a replication mask (32) onto the imprint resist layer (50) to transfer a pattern of via openings to the resist layer (50). Operation (92) may also optionally include a UV curing step. The replication mask (32) is then removed. FIG. 10e illustrates a cross-section after the replication mask (32) has been pressed onto the imprint resist layer (50) but before the subsequent removal of the replication mask.

[0038] In operation (94), anisotropic and non-selective etching is performed to transfer the pattern of via openings from the resist layer (50) to the IMD layer (52), resulting in the cross-section shown in FIG. 10f. As can be seen, the anisotropic and non-selective etching removes the imprint resist layer (106) (including the removal of the resist-C layer (50), the adhesive layer (71), and the resist-B layer (108)) and continues non-selective etching into the IMD (52) to create partial via openings (110). However, note that the partial via openings (110) do not extend completely through the IMD layer (52) to expose the Mx-1 patterned metallized region. Additionally, the (first) etching operation (94) does not etch the patterned film-A (100) intended to define the Mx patterned metallization layer. The etching of operation (94) is anisotropic in that it preferentially etches downward rather than laterally, and is non-selective in that it etches the material of the imprint resist layer (50) (including the resist layers (50, 108) and the adhesive layer (71)) and the dielectric material of the IMD layer (52) at approximately the same etching rate (thereby forming partial via openings (110)). However, as just mentioned, the etching of operation (94) is selective in that it does not etch the patterned film-A (100). In some non-limiting examples, the etching used in operation (94) may be dry plasma etching using one or more etchants, such as C, O, H, Cl, or F-based etchant gases. The specific choice of etching may be optimized for a specific type of resist and a specific IMD material. As labeled in FIG. 10f, since the etching operation (94) removes the imprint resist layer (106) but does not etch the patterned film-A (100), the etching operation (94) also reopens the Mx metallization pattern (105).

[0039] In operation (95), a second etching step is performed to complete the transfer of the imprinted via opening to the IMD (52) in order to form a via opening (112) that completely penetrates the IMD layer (52) to expose the Mx-1 regions. The etching in operation (95) is anisotropic in that it preferentially etches downward rather than laterally. However, because the imprint resist layer (106) was removed in the previous etching operation (94), the etching operation (95) is not necessarily non-selective between the material of the IMD (52) and the material of the imprint resist layer (106). Rather, the etching (95) is non-selective between the material of the IMD layer (52) and the material of the patterned film-A (100). In other words, the etching used in operation (95) etches both the IMD layer (52) and the patterned film-A (100) at roughly similar etching rates. The cross-sectional view of FIG. 10g illustrates the result of the second etching operation (95). As shown, in addition to completing the transfer of the imprinted via opening to the IMD (52) to expose Mx-1 regions (through the via opening (112)), the second etching operation (95) also transfers the Mx metallization pattern (105) from the patterned film-A (100) to the IMD (52) as an exemplary opening (114). Again, a single opening (114) is illustrated by schematic example, but the opening (114) may represent a pattern of openings. For example, the opening (114) can form an Mx metallization pattern (114).

[0040] In operation (96), metal deposition is performed, which deposits metal to fill via openings (112) to form vias (20) and also to fill opening(s) (114) to form an Mx metallization. This is illustrated in cross-sectional view (10h), where it can be seen that the deposited metal (116) overfills the openings (112, 114) to create excess metal (116) on the wafer surface. Operation (96) may utilize copper electroplating to fill the via openings (112, 114) with a conductive material (here, copper) to form vias (20) and an Mx patterned metallization. In other embodiments, PVD may be used. In operation (98), CMP is performed to remove the excess conductive material (116), flatten the surface, and expose the Mx metallization, resulting in the structure shown in FIG. 10i. Thus, compared to the process of FIG. 7, the process of FIG. 9 advantageously forms both the via (20) and the Mx metallization.

[0041] Now, referring to FIGS. 11a, 11b, 11c, 11d, and 11e, some non-limiting illustrative examples of three-dimensional via geometries that can be fabricated using the NIL-based via formation method of FIG. 9 are schematically illustrated. FIG. 11a illustrates a top view (i.e., plan view) of four vias, including the three vias (VA, VB, VC) discussed herein, where the top (Mx) metallization is omitted to reveal the top portions of the vias (VA, VB, VC). FIG. 11a also illustrates two cutting lines, namely the C1-C2 cut and the C3-C4 cut. FIGS. 11b and 11c illustrate via patterns (VA) intended to form the vias (VA, VB, VC), respectively. pat , VB pat , VC patFigures 11 and 11 show the C1-C2 and C3-C4 cuts, respectively, taken after imprinting a pattern of via openings on the imprint resist (resist-C) (50), including the ) and ) respectively. Figures 11b and 11c correspond to Figure 10e, but after the removal of the replication mask (32). Figures 11d and 11e show the C1-C2 and C3-C4 cuts, respectively, taken after the final CMP (98) of Figure 9, and show the vias (VA, VB, VC), respectively. Figures 11d and 11e correspond to Figure 10i.

[0042] As labeled in FIG. 11b, FIG. 11c, and FIG. 11d, respectively, the IMD layer (52) has an upper surface (120) located at an angle from the substrate (e.g., wafer) (54) and a lower surface (122) located near the substrate (54). Each of the vias (VA, VB, VC) has a circular cross-section on the lower surface (122), where the vias intersect with the lower (Mx-1) patterned metallization layer. Before being filled with metal, the via openings corresponding to the vias (VA, VB, VC) each have a circular lower aperture on the lower surface (122) of the IMD layer (52).

[0043] Each of the vias (VA, VB, VC) also has a top (or upper) labeled as TA, TB, and TC for the vias (VA, VB, VC) in FIG. 11a, respectively. (As previously mentioned, FIG. 11a omits the Mx patterned metallization to reveal the via tops (TA, TB, TC).) Before the via openings are filled with metal, the via openings corresponding to the vias (VA, VB, VC) each have a circular upper aperture corresponding to the via tops (TA, TB, TC) on the lower surface (120) of the IMD layer (52).

[0044] Consider the first via (VA), which is circular and has its own top (or uppermost) (TA) concentric with the bottom (or lower part) of the via (VA); however, the top (or uppermost) (TA) is larger than the bottom (or lower part) of the via (VA). This via is not retargeted, but having a larger top (TA) can facilitate bonding or other connections to the via (VA).

[0045] The vias (VB, VC) are retargeting vias, and each via top (TB, TC) has centers laterally offset from the centers of the via bottoms. The via (VB) is as shown in FIG. 11d (and the corresponding pattern in FIG. 11b (VB Pat As shown in ), it has a non-circular (exemplarily elliptical) top (TB) that is offset laterally from its bottom along the C1-C2 cutting line, that is, offset laterally to the right in the drawing. On the other hand, the top (TB) of the via (VB) is aligned with its bottom along the C3-C4 cutting line.

[0046] The via (VC) is as shown in FIG. 11e (and the corresponding pattern (VC) in FIG. 11e). Pat As shown in ), it has a non-circular (exemplarily elliptical) top (TC) that is offset laterally from its bottom along the C3-C4 cutting line, that is, offset laterally to the right in the drawing. On the other hand, the top (TC) of the via (VC) is aligned with its bottom along the C1-C2 cutting line.

[0047] FIGS. 11a through 11e are merely non-limiting illustrative examples, and retargeting vias may be laterally shifted in different directions and / or may have via tops having different shapes (e.g., rectangular or square as additional examples). The use of NIL enables a wide range of three-dimensional geometry for the retargeting vias. Generally, the pattern of the patterned mask (i.e., the pattern of the via openings of the replication mask (32)) may include at least one inclined surface (e.g., creating the imprinted inclined surfaces (130, 132) in the example of FIG. 11b and FIG. 11c), and the etching transfers the inclined surface to a dielectric layer (e.g., the IMD layer (52)), and thus, when the via openings transferred to the dielectric layer (52) are filled with copper or other conductive material, this creates vias having inclined surfaces (e.g., the inclined surface (140) of the via (VB) and the inclined surface (142) of the via (VC)).

[0048] Now, referring to FIG. 12, a representative retargeting via (20) is illustrated with annotations labeling the angle (θ) of the sidewall of the labeled via, along with the via depth (equal to the thickness of the IMD layer (52)), the bottom critical dimension (CD), and the top CD for one exemplary via. In some non-limiting illustrative examples, these dimensions may have values ​​within the following ranges: the top CD (at the top (120) of the IMD layer (52)) being greater than the bottom CD; in some examples, the top CD is about 1000 nm; the bottom CD (at the bottom (122) of the IMD layer (52)) being within the range of 10 nm to 1000 nm; and the thickness of the IMD layer (52) (corresponding to the depth of the via) being within the range of 10 nm to 10,000 nm. A ratio of top CD / bottom CD ratio in the range of 1 to 100; a via depth / top CD ratio in the range of 0.01 to 100; and a sidewall angle (θ) in the range of 30 to 90 degrees. These are merely some non-limiting illustrative examples, and values ​​outside these exemplary ranges are considered.

[0049] The examples described above illustrate a single layer of vias (Vx) between the lower (Mx-1) metallization layer and the upper (Mx) metallization layer. It will be understood that this can be extended to two, three, or more via layers.

[0050] Referring to FIGS. 13a, 13b, 13c, and 13d, examples of such multiple via layers are illustrated. FIG. 13a illustrates a cross-sectional view of a wafer (54) having an M0 patterned metallization layer formed thereon. FIG. 13b illustrates a cross-sectional view of the wafer (54) after the fabrication of a first layer (L1) of vias (V1) connecting the (here, lower) M0 patterned metallization layer to the (here, upper) M1 patterned metallization layer. The vias (V1) and the M1 patterned metallization layer can be fabricated, for example, according to the method of FIG. 9, and FIG. 13b, corresponding to FIG. 10i, is created after the final CMP step (98) of the method of FIG. 9.

[0051] For the fabrication of the second via layer (L2), the M1 patterned metallization layer is now the lower metallization layer. A second IMD layer (52') is formed on the M1 metallization layer, and the method of FIG. 9 is repeated, and FIG. 13c, corresponding to FIG. 10i, is created after the final CMP step (98) of the second repetition of the method of FIG. 9. This creates a layer of vias (V2) connected to the M2 patterned metallization layer, as shown in FIG. 13c. (Note that in this example, the M2 patterned metallization layer is patterned into three parts along a cutting line aligned with each V2 via.)

[0052] For the fabrication of the third via layer (L3), the M2 patterned metallization layer is now the lower metallization layer. The third IMD layer (52) is formed on the M2 metallization layer, and the method of FIG. 9 is repeated, and FIG. 13d, corresponding to FIG. 10i, is produced after the final CMP step (98) of the third repetition of the method of FIG. 9. This creates a layer of vias (V3) connected to the M3 patterned metallization layer, as shown in FIG. 13d. It will be noted that this process can be repeated for any number of via layers (N). Additionally, if the vias of consecutive layers are retargeted along the same direction, this can result in the vias being spread out, which may be useful for designing a redistribution layer (RDL) or other complex metallization stacks.

[0053] To enable those skilled in the art to better understand the aspects of the present disclosure, the features of several embodiments have been outlined above. Those skilled in the art should be aware that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present disclosure.

[0054] Examples

[0055] Example 1. In a method for forming vias,

[0056] Step of forming a dielectric layer on a substrate;

[0057] A step of forming a resist layer on the above dielectric layer;

[0058] A step of applying pressure to the resist layer using a patterned mask to transfer the pattern of the patterned mask to the resist layer;

[0059] A step of curing the patterned resist layer;

[0060] Step of removing the patterned mask;

[0061] A step of etching via openings within the dielectric layer based on the patterned resist layer; and

[0062] Step of filling the via openings with an electrically conductive material to form vias

[0063] A via formation method including

[0064] Example 2. In Example 1,

[0065] A via formation method wherein the pattern of the patterned mask comprises at least one inclined surface, and the etching transfers the inclined surface to the dielectric layer.

[0066] Example 3. In Example 1,

[0067] The centerlines of the above via openings are not parallel to each other;

[0068] A via formation method in which the centerlines of the above vias are not mutually parallel.

[0069] Example 4. In Example 1,

[0070] The dielectric layer has an upper surface located at a distance from the substrate;

[0071] At least one of the above via openings, a non-circular via opening, has an upper aperture that is non-circular on the upper surface of the dielectric layer;

[0072] A via formation method comprising at least one non-circular via formed by filling a corresponding non-circular via opening with the electrically conductive material.

[0073] Example 5. In Example 1,

[0074] The dielectric layer has an upper surface located far from the substrate and a lower surface located near the substrate;

[0075] The above via openings include at least one retargeted via opening, and each retargeted via opening has a lower aperture on the lower surface of the dielectric layer and an upper aperture offset laterally from the lower aperture on the upper surface of the dielectric layer;

[0076] A via formation method comprising at least one retargeted via formed by filling a corresponding retargeted via opening with the electrically conductive material.

[0077] Example 6. In Example 1,

[0078] The substrate comprises a first patterned metal layer, and the method comprises, after forming the dielectric layer and before forming the resist layer,

[0079] A step of forming a first resist layer on the above dielectric layer; and

[0080] A step of patterning the first resist layer to remove a portion of the first resist layer within the second patterned metal region.

[0081] Includes more,

[0082] A via formation method in which the step of filling the via openings with the electrically conductive material to form the vias also fills the second patterned metal region with the electrically conductive material to form the second patterned metal layer, and the vias electrically connect the first patterned metal layer and the second patterned metal layer.

[0083] Example 7. In Example 1,

[0084] A via formation method wherein the above etching includes plasma etching having a low selectivity ratio between the material of the resist layer and the material of the dielectric layer.

[0085] Example 8. In Example 1,

[0086] Step of removing excess electrically conductive material by performing chemical mechanical polishing after filling the above via openings with the above electrically conductive material.

[0087] A via formation method further comprising

[0088] Example 9. In a method for forming vias,

[0089] Step of forming a resist layer on a dielectric layer;

[0090] A step of imprinting a pattern of via openings within the resist layer;

[0091] After the above imprinting, a step of transferring the pattern of the via openings imprinted in the resist layer to the dielectric layer by anisotropic etching to form via openings in the dielectric layer; and

[0092] A step of forming vias within the dielectric layer by filling the via openings within the dielectric layer with an electrically conductive material.

[0093] A via formation method including

[0094] Example 10. In Example 9,

[0095] A via formation method in which the above imprinting is performed using nano imprint lithography (NIL).

[0096] Example 11. In Example 9,

[0097] A via formation method in which the above anisotropic etching has a low etching selectivity ratio between the resist layer and the dielectric layer.

[0098] Example 12. In Example 9,

[0099] At least one of the above via openings is a non-circular via opening and has a non-circular aperture on the surface of the dielectric layer;

[0100] A via formation method comprising at least one non-circular via formed by filling a corresponding non-circular via opening with the electrically conductive material.

[0101] Example 13. In Example 9,

[0102] The above dielectric layer has an upper surface and a lower surface, and

[0103] The above via openings include at least one retargeted via opening, and each retargeted via opening has a lower aperture on the lower surface of the dielectric layer and an upper aperture offset laterally from the lower aperture on the upper surface of the dielectric layer;

[0104] A via formation method comprising at least one retargeted via formed by filling a corresponding retargeted via opening with the electrically conductive material.

[0105] Example 14. In Example 9,

[0106] The dielectric layer is disposed on a substrate comprising a first patterned metal layer, and the method is, before forming the resist layer,

[0107] A step of forming a first resist layer on the above dielectric layer; and

[0108] A step of patterning the first resist layer to remove a portion of the first resist layer within the second patterned metal region.

[0109] Includes more,

[0110] A via formation method in which the step of filling the via openings with the electrically conductive material to form the vias also fills the second patterned metal region with the electrically conductive material to form the second patterned metal layer, and the vias electrically connect the first patterned metal layer and the second patterned metal layer.

[0111] Example 15. In Example 9,

[0112] Step of removing excess electrically conductive material by performing chemical mechanical polishing after filling the above via openings with the above electrically conductive material.

[0113] A via formation method further comprising

[0114] Example 16. In an electrical connection structure,

[0115] First patterned metal layer;

[0116] A dielectric layer disposed on the first patterned metal layer;

[0117] A second patterned metal layer disposed on the dielectric layer - the dielectric layer is disposed between the first patterned metal layer and the second patterned metal layer -; and

[0118] vias passing through the dielectric layer and connecting the first patterned metal layer and the second patterned metal layer

[0119] Includes;

[0120] An electrical connection structure in which the centerline of at least one retargeting via among the above vias is not parallel to the centerline of at least one other via among the above vias.

[0121] Example 17. In Example 16,

[0122] An electrical connection structure wherein the at least one retargeting via comprises at least one via having a non-circular cross-section at its intersection with the second patterned metal layer.

[0123] Example 18. In Example 16,

[0124] An electrical connection structure wherein the at least one retargeting via comprises at least one via having a circular cross-section at its intersection with the first patterned metal layer and a non-circular cross-section at its intersection with the second patterned metal layer.

[0125] Example 19. In Example 16,

[0126] An electrical connection structure wherein the at least one retargeting via comprises at least one via having its own intersection with the second patterned metal layer, which is laterally offset from its own intersection with the first patterned metal layer.

[0127] Example 20. In Example 16,

[0128] The above electrical connection structure wherein the at least one retargeting via comprises at least one via having a central axis not perpendicular to the surface of the dielectric layer on which the second patterned metal layer is disposed.

Claims

Claim 1 A method for forming vias comprising: forming a dielectric layer on a substrate; forming a resist layer on the dielectric layer; applying a patterned mask to the resist layer to transfer the pattern of the patterned mask to the resist layer; curing the patterned resist layer; removing the patterned mask; etching via openings within the dielectric layer based on the patterned resist layer; and filling the via openings with an electrically conductive material to form vias. Claim 2 A via formation method according to claim 1, wherein the pattern of the patterned mask comprises at least one inclined surface, and the etching transfers the inclined surface to the dielectric layer. Claim 3 A via formation method according to claim 1, wherein the centerlines of the via openings are not mutually parallel; and the centerlines of the vias are not mutually parallel. Claim 4 A via formation method according to claim 1, wherein the dielectric layer has an upper surface circular from the substrate; at least one non-circular via opening among the via openings has an upper aperture that is non-circular on the upper surface of the dielectric layer; and the vias include at least one non-circular via formed by filling the corresponding non-circular via opening with the electrically conductive material. Claim 5 A via formation method according to claim 1, wherein the dielectric layer has an upper surface located far from the substrate and a lower surface located near the substrate; the via openings include at least one retargeted via opening, each retargeted via opening having a lower aperture on the lower surface of the dielectric layer and an upper aperture offset laterally from the lower aperture on the upper surface of the dielectric layer; and the vias include at least one retargeted via formed by filling the corresponding retargeted via opening with the electrically conductive material. Claim 6 In claim 1, the substrate comprises a first patterned metal layer, and the method comprises, after forming the dielectric layer and before forming the resist layer, A step of forming a first resist layer on the above dielectric layer; and A via formation method further comprising the step of patterning the first resist layer to remove a portion of the first resist layer within the second patterned metal region, and the step of filling the via openings with the electrically conductive material to form the vias also comprises filling the second patterned metal region with the electrically conductive material to form the second patterned metal layer, wherein the vias electrically connect the first patterned metal layer and the second patterned metal layer. Claim 7 A via formation method according to claim 1, wherein the etching comprises plasma etching having a low selectivity ratio between the material of the resist layer and the material of the dielectric layer. Claim 8 A via formation method according to claim 1, further comprising the step of removing excess electrically conductive material by performing chemical mechanical polishing after filling the via openings with the electrically conductive material. Claim 9 A method for forming vias comprising: a step of forming a resist layer on a dielectric layer; a step of imprinting a pattern of via openings within the resist layer; a step of, after imprinting, transferring the pattern of via openings imprinted within the resist layer to the dielectric layer by anisotropic etching to form via openings within the dielectric layer; and a step of filling the via openings within the dielectric layer with an electrically conductive material to form vias within the dielectric layer. Claim 10 An electrical connection structure comprising: a first patterned metal layer; a dielectric layer disposed on the first patterned metal layer; a second patterned metal layer disposed on the dielectric layer, wherein the dielectric layer is disposed between the first patterned metal layer and the second patterned metal layer; and vias passing through the dielectric layer and connecting the first patterned metal layer and the second patterned metal layer; wherein the centerline of at least one retargeting via among the vias is not parallel to the centerline of at least one other via among the vias.

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