Display panel, method for manufacturing the same and electronic device having the same

Abstract

The present invention comprises a substrate, a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode, and a cladding layer which overlaps with at least a portion of the edge region of the semiconductor layer, is an oxide semiconductor, and has a mobility smaller than that of a portion of the semiconductor layer.

Description

Technology Field

[0001] Embodiments of the present invention relate to methods and apparatus, and more specifically to a display panel, a method for manufacturing a display panel, and an electronic device. Background Technology

[0002] Electronic devices based on mobility are being widely used. In addition to small electronic devices such as mobile phones, tablet PCs have recently become widely used as mobile electronic devices.

[0003] Such mobile electronic devices include a display panel to support various functions and to provide visual information, such as images or videos, to the user. Recently, as other components for driving the display panel have become miniaturized, the proportion of the display panel in the electronic device is gradually increasing, and structures capable of bending from a flat state to a predetermined angle are also being developed. The problem to be solved

[0004] Generally, when the thickness of the semiconductor layer of a display panel becomes thinner than the initial thickness, the current flowing through the semiconductor layer may decrease. This may result in a decrease in the brightness of the display element or prevent the display element from functioning properly. To solve this problem, embodiments of the present invention provide a display panel that provides a clear image, a method for manufacturing a display panel, and an electronic device. means of solving the problem

[0005] One embodiment of the present invention discloses a display panel comprising a substrate, a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode, and a cladding layer which overlaps with at least a portion of the edge region of the semiconductor layer, is an oxide semiconductor, and has a mobility smaller than that of a portion of the semiconductor layer.

[0006] In this embodiment, the semiconductor layer may have a crystalline or amorphous structure.

[0007] In this embodiment, the cladding layer is disposed on a part of the edge of the semiconductor layer on a flat surface and can shield a part of the edge of the semiconductor layer.

[0008] In this embodiment, the cladding layer may be positioned on a flat surface below a portion of the edge of the semiconductor layer and overlap with a portion of the edge of the semiconductor layer.

[0009] In this embodiment, the cladding layer may be arranged to protrude from the edge of the semiconductor layer on a plane.

[0010] In this embodiment, an insulating layer disposed between the semiconductor layer and the gate electrode may be further included.

[0011] In this embodiment, the insulating layer can cover the entire cladding layer and the semiconductor layer.

[0012] In this embodiment, two cladding layers may be arranged spaced apart from each other at both ends of the semiconductor layer.

[0013] In this embodiment, the gate electrodes on a plane may be placed between the cladding layers that are spaced apart from each other.

[0014] In this embodiment, the spacing between the cladding layers spaced apart in one direction may be larger than the width of the gate electrode in one direction.

[0015] In this embodiment, an additional gate electrode disposed between the semiconductor layer and the substrate may be further included.

[0016] In this embodiment, two cladding layers are arranged spaced apart from each other at both ends of the semiconductor layer, and the spacing between the cladding layers spaced apart in one direction may be larger than the width of the additional gate electrode in one direction.

[0017] In this embodiment, the width of the gate electrode in one direction may be smaller than the width of the additional gate electrode.

[0018] In this embodiment, the additional gate electrode may be electrically connected to the gate electrode.

[0019] In this embodiment, an electrode disposed on the semiconductor layer and electrically connected to the semiconductor layer may be further included.

[0020] In this embodiment, the cladding layer or the semiconductor layer may include at least one groove.

[0021] Another embodiment of the present invention discloses a method for manufacturing a display panel comprising the steps of: forming a semiconductor layer which is an oxide semiconductor on a substrate; arranging a cladding layer which is an oxide semiconductor and has a mobility smaller than that of a portion of the semiconductor layer on the substrate so as to overlap with a portion of the semiconductor layer on a planar surface; arranging a gate electrode on the semiconductor layer; arranging an upper insulating layer to shield the gate electrode, the cladding layer, and the semiconductor layer; and forming a contact hole in the upper insulating layer.

[0022] In this embodiment, the step of placing the cladding layer on the semiconductor layer to shield a portion of the edge of the semiconductor layer on a flat surface may be further included.

[0023] In this embodiment, the step of arranging the cladding layer such that a portion of the edge of the semiconductor layer is placed on the cladding layer on a plane may be further included.

[0024] In this embodiment, the cladding layer may be arranged to overlap with a portion of the edge of the semiconductor layer.

[0025] In the present embodiment, the step of forming at least one groove in the cladding layer or the semiconductor layer may be further included.

[0026] In this embodiment, the step of applying heat to the semiconductor layer or the cladding layer may be further included.

[0027] In this embodiment, the step of arranging two cladding layers spaced apart from each other at both ends of the semiconductor layer may be further included.

[0028] In this embodiment, the gate electrodes on a plane may be placed between the cladding layers that are spaced apart from each other.

[0029] In this embodiment, the step of placing an additional gate electrode disposed between the semiconductor layer and the substrate may be further included.

[0030] In this embodiment, two cladding layers are arranged spaced apart from each other at both ends of the semiconductor layer, and the spacing between the cladding layers spaced apart in one direction may be larger than the width of the additional gate electrode in one direction.

[0031] Another embodiment of the present invention discloses an electronic device comprising a display panel and a processor connected to the display panel to control the display panel, wherein the display panel comprises a substrate, a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode, and a cladding layer which overlaps with at least a portion of the edge region of the semiconductor layer, is an oxide semiconductor, and has a mobility smaller than that of a portion of the semiconductor layer.

[0032] In this embodiment, the semiconductor layer may have a crystalline or amorphous structure.

[0033] In this embodiment, the cladding layer is disposed on a part of the edge of the semiconductor layer on a flat surface and can shield a part of the edge of the semiconductor layer.

[0034] In this embodiment, the cladding layer may be positioned on a flat surface below a portion of the edge of the semiconductor layer and overlap with a portion of the edge of the semiconductor layer.

[0035] In the present embodiment, the display panel may further include an insulating layer disposed between the semiconductor layer and the gate electrode to cover the entire cladding layer and the semiconductor layer.

[0036] In this embodiment, two cladding layers are arranged spaced apart from each other at both ends of the semiconductor layer, and the spacing between the cladding layers spaced apart in one direction may be larger than the width of the gate electrode in one direction.

[0037] In the present embodiment, the display panel may further include an additional gate electrode disposed between the semiconductor layer and the substrate.

[0038] In this embodiment, two cladding layers are arranged spaced apart from each other at both ends of the semiconductor layer, and the spacing between the cladding layers spaced apart in one direction may be larger than the width of the additional gate electrode in one direction.

[0039] In this embodiment, the additional gate electrode may be electrically connected to the gate electrode.

[0040] Another embodiment of the present invention discloses a display panel comprising a substrate, a transistor disposed on the substrate and including a semiconductor layer which is an oxide semiconductor and a gate electrode, and a cladding layer which is an oxide semiconductor disposed so as to overlap with an impurity region of the semiconductor layer, wherein the edge of the impurity region of the semiconductor layer is disposed inside the semiconductor layer on a plane.

[0041] Another embodiment of the present invention discloses a display panel comprising a substrate, a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode, and two cladding layers which are oxide semiconductors and overlap at least a portion of the semiconductor layer, wherein the distance between the cladding layers is greater than the width of the gate electrode intersecting the semiconductor layer.

[0042] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention. Effects of the invention

[0043] The display panel and electronic device according to the embodiments of the present invention can provide a clear image.

[0044] The method for manufacturing a display panel according to the embodiments of the present invention can prevent the loss of the semiconductor layer when a hole is formed. Brief explanation of the drawing

[0045] FIG. 1a is a schematic perspective view of a display panel according to one embodiment of the present invention. FIG. 1b is a cross-sectional view along the line I-I' of a display panel according to one embodiment of the present invention. Figure 1c shows each part of the color-converting-transmitting layer of Figure 1b. FIG. 2 is an equivalent circuit diagram showing a light-emitting diode included in a light-emitting panel of a display panel according to one embodiment of the present invention and a pixel circuit electrically connected to the light-emitting diode. FIG. 3a is a plan view showing pixel circuits of a light-emitting panel according to one embodiment of the present invention. FIG. 3b is a plan view showing pixel electrodes connected to the pixel circuits of FIG. 3. FIGS. 3C to 3F are schematic plan views showing some layers of the pixel circuits illustrated in FIG. 3A. Figure 4 is a cross-sectional view along the VV´ line and VI-VI´ of Figure 3b. Figure 5 is a plan view schematically showing the semiconductor layers and switching gate electrodes illustrated in Figure 3d. FIGS. 6a to 6c are cross-sectional views schematically showing part of the manufacturing process of the pixel circuit of FIG. 3. FIG. 7 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIG. 8 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIG. 9 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIGS. 10a to 10d are cross-sectional views schematically showing part of the manufacturing process of the pixel circuit of the light-emitting panel shown in FIG. 9. FIG. 11 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIG. 12 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIGS. 13a to 13d are cross-sectional views schematically showing a part of a pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIG. 14 is a cross-sectional view schematically showing a switching semiconductor layer, a switching gate electrode, and a first and second cladding layer among parts of the pixel circuit of the light-emitting panel shown in FIG. 13a to 13d. FIG. 15 is a block diagram of an electronic device according to one embodiment of the present invention. FIGS. 16 to 18 are schematic diagrams of electronic devices according to various embodiments of the present invention. Specific details for implementing the invention

[0046] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0048] In the following examples, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0049] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0050] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0051] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0052] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0053] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0054] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0055] FIG. 1a is a schematic perspective view of a display panel according to one embodiment of the present invention, FIG. 1b is a cross-sectional view along the line I-I' of a display panel according to one embodiment of the present invention, and FIG. 1c shows each part of the color-conversion-transmittance layer of FIG. 1b.

[0056] Referring to FIG. 1a, the display panel (1) may include a display area (DA) and a non-display area (NDA) outside the display area (DA). The display panel (1) may provide an image through an array of multiple pixels arranged two-dimensionally in the display area (DA).

[0057] Each pixel of the display panel (1) is an area capable of emitting light of a predetermined color, and the display panel (1) can provide an image using the light emitted from the pixels. For example, each pixel can emit red, green, or blue light.

[0058] The non-display area (NDA) is an area that does not provide an image and may completely surround the display area (DA). Drivers or main power lines for providing electrical signals or power to pixel circuits may be placed in the non-display area (NDA). The non-display area (NDA) may include pads, which are areas where electronic components or printed circuit boards can be electrically connected.

[0059] The display area (DA) may have a polygonal shape including a rectangle, as shown in FIG. 1a. For example, the display area (DA) may have a rectangular shape where the width is greater than the height, a rectangular shape where the width is smaller than the height, or a square shape. Alternatively, the display area (DA) may have various shapes such as an ellipse or a circle.

[0060] In some embodiments, the display panel (1) may include a light-emitting panel (1) and a color panel (2) stacked in the thickness direction (e.g., z-direction). Referring to FIG. 1b, the light-emitting panel (1) may include first to third pixel circuits (PC1, PC2, PC3) on a first substrate (10) and first to third organic light-emitting diodes (OLED1, OLED2, OLED3) respectively connected thereto.

[0061] Light emitted from the first to third organic light-emitting diodes (OLED1, OLED2, OLED3) (e.g., blue light Lb) can be converted into or transmitted as blue light (Lb), red light (Lr), and green light (Lg) while passing through the color panel (2). The area where green light (Lg) is emitted corresponds to a green pixel (Pg), the area where red light (Lr) is emitted corresponds to a red pixel (Pr), and the area where blue light (Lb) is emitted corresponds to a blue pixel (Pb).

[0062] The color panel (2) may include a second substrate (20) and a first light-blocking layer (21) on the substrate (200). The first light-blocking layer (21) may include a plurality of holes formed by removing portions corresponding to a green pixel (Pg), a red pixel (Pr), and a blue pixel (Pb). The first light-blocking layer (21) includes a material portion located in a non-pixel area (NPA), and the material portion may include various materials capable of absorbing light.

[0063] The second light-blocking layer (22) may be disposed on the first light-blocking layer (21). The second light-blocking layer (22) may also include a material portion located in the non-pixel area (NPA). The second light-blocking layer (22) may include various materials capable of absorbing light. The second light-blocking layer (22) may include the same material as the aforementioned first light-blocking layer (21) or may include different materials.

[0064] The first light-blocking layer (21) and / or the second light-blocking layer (22) may be an opaque inorganic insulating material such as chromium oxide or molybdenum oxide, or may include an opaque organic insulating material such as black resin.

[0065] A color layer including first to third color filters (30a, 30b, 30c) may be disposed on the second substrate (20). The first color filter (30a) may include a pigment or dye of a first color (e.g., blue). The second color filter (30b) may include a pigment or dye of a second color (e.g., red). The third color filter (30c) may include a pigment or dye of a third color (e.g., green).

[0066] A color-conversion-transmitting layer including a second color-conversion part (40c), a first color-conversion part (40b), and a transmitting part (40a) may be disposed on the color layer.

[0067] The second color conversion unit (40c) is positioned to overlap with the third color filter (30c) and can convert incident blue light (Lb) into green light (Lg). As illustrated in FIG. 1c, the second color conversion unit (40c) may include a first photosensitive polymer (1161) in which first quantum dots (1162) and first scattering particles (1163) are dispersed.

[0068] The first quantum dots (1162) can be excited by blue light (Lb) and isotropically emit green light (Lg) having a wavelength longer than the wavelength of the blue light. The first photosensitive polymer (1161) may be an organic material having light transmittance.

[0069] The first scattering particles (1163) can increase color conversion efficiency by scattering blue light (Lb) that is not absorbed by the first quantum dots (1162), thereby causing more first quantum dots (1162) to be excited. The first scattering particles (1163) may be, for example, titanium oxide (TiO2) or metal particles. The first quantum dots (1162) may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0070] The first color conversion unit (40b) is positioned to overlap with the second color filter (30b) and can convert incident blue light (Lb) into red light (Lr). As shown in FIG. 1c, the first color conversion unit (40b) may include a second photosensitive polymer (1151) in which second quantum dots (1152) and second scattering particles (1153) are dispersed.

[0071] The second quantum dots (1152) can be excited by blue light (Lb) and isotropically emit red light (Lr) having a wavelength longer than that of the blue light. The second photosensitive polymer (1151) may be an organic material that is light-transmitting. The second scattering particles (1153) can increase color conversion efficiency by scattering the blue light (Lb) that is not absorbed by the second quantum dots (1152), thereby causing more second quantum dots (1152) to be excited. The second scattering particles (1153) may be, for example, titanium oxide (TiO2) or metal particles. The second quantum dots (1152) may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. The second quantum dot (1152) may be made of the same material as the first quantum dot (1162), and the size of the second quantum dot (1152) may be larger than the size of the first quantum dot (1162).

[0072] The transmitting portion (40a) can transmit blue light (Lb). As illustrated in FIG. 1c, the transmitting portion (40a) may include a third photosensitive polymer (1171) in which third scattering particles (1173) are dispersed. The third photosensitive polymer (1171) may be an organic material having light transmittance, such as silicone resin or epoxy resin, for example, and may be the same material as the first and second photosensitive polymers (1151, 1161). The third scattering particles (1173) can scatter and emit blue light (Lb) and may be the same material as the first and second scattering particles (1153, 1163).

[0073] Blue light (Lb) emitted from the light-emitting panel (1) can have its color converted or transmitted as it passes through the color conversion-transmission layer, and then its color purity can be improved as it passes through the color layer. For example, blue light emitted from the first organic light-emitting diode (OLED1) of the light-emitting panel (1) can pass through the first color region of the color panel (2). As it passes through the color panel (2), the blue light can be transmitted and filtered by the color panel (2). The first color region may include a stacked structure of a transmission portion (40a) and a first color filter (30a).

[0074] Blue light emitted from the second organic light-emitting diode (OLED2) of the light-emitting panel (1) can pass through the second color region of the color panel (2). As it passes through the color panel (2), the blue light can be converted into red light and filtered by the color panel (2). The second color region may include a stacked structure of the first color conversion unit (40b) and the second color filter (30b).

[0075] Blue light emitted from the third organic light-emitting diode (OLED3) of the light-emitting panel (1) can pass through the third color region of the color panel (2). As it passes through the color panel (2), the blue light can be converted into green light and filtered by the color panel (2). The third color region may include a stacked structure of the second color conversion unit (40c) and the third color filter (30c).

[0076] FIG. 2 is an equivalent circuit diagram showing a light-emitting diode included in a light-emitting panel of a display panel according to one embodiment of the present invention and a pixel circuit electrically connected to the light-emitting diode.

[0077] Referring to FIG. 2, the pixel electrode (e.g., anode) of a light-emitting diode, e.g., an organic light-emitting diode (OLED), is connected to a pixel circuit (PC), and the counter electrode (e.g., cathode) of the organic light-emitting diode (OLED) can be connected to a common power supply voltage (ELVSS). The organic light-emitting diode (OLED) can emit light with a brightness corresponding to the amount of current supplied from the pixel circuit (PC).

[0078] The organic light-emitting diode (OLED) of FIG. 2 corresponds to each of the first to third organic light-emitting diodes (OLED1, OLED2, OLED3) shown in FIG. 1b above, and the pixel circuit (PC) of FIG. 2 may correspond to each of the first to third pixel circuits (PC1, PC2, PC3) shown in FIG. 1b above.

[0079] The pixel circuit (PC) can control the amount of current flowing from the driving power supply voltage (ELVDD) through the organic light-emitting diode (OLED) to the common power supply voltage (ELVSS) in response to a data signal. The pixel circuit (PC) includes a first transistor (M1), a second transistor (M2), a third transistor (M3), a storage capacitor (Cst), and an auxiliary capacitor (C OLED It may include ).

[0080] Each of the first transistor (M1), the second transistor (M2), and the third transistor (M3) may be an oxide semiconductor thin-film transistor comprising a semiconductor layer composed of an oxide semiconductor. For example, the oxide semiconductor may include a metal oxide comprising at least one of the elements In, Ga, Zn, Sn, Hf, Zr, or Al. Additionally, the thickness of the semiconductor layer may have a range of about 50 Å or more and 250 Å or less. The semiconductor layer may have a crystalline or amorphous structure. Depending on the type of transistor, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of a source electrode and a drain electrode. For convenience of explanation, the following description will focus on the case where the semiconductor layer has a crystalline structure.

[0081] The first transistor (M1) may be a driving transistor. The first electrode of the first transistor (M1) may be connected to a driving voltage line (VDL) that supplies a driving power supply voltage (ELVDD), and the second electrode may be connected to a pixel electrode of an organic light-emitting diode (OLED). The gate electrode of the first transistor (M1) may be connected to a first node (N1). The first transistor (M1) can control the amount of current flowing from the driving power supply voltage (ELVDD) to the organic light-emitting diode (OLED) in correspondence with the voltage of the first node (N1).

[0082] The second transistor (M2) may be a switching transistor. The first electrode of the second transistor (M2) may be connected to the data line (DL), and the second electrode may be connected to the first node (N1). The gate electrode of the second transistor (M2) may be connected to the scan line (SL). The second transistor (M2) may be turned on when a scan signal is supplied to the scan line (SL) to electrically connect the data line (DL) and the first node (N1).

[0083] The third transistor (M3) may be an initialization transistor and / or a sensing transistor. The first electrode of the third transistor (M3) may be connected to the second node (N2), and the second electrode may be connected to the initialization sensing line (ISL). The gate electrode of the third transistor (M3) may be connected to the control line (CL).

[0084] The third transistor (M3) can be turned on when a control signal is supplied to the control line (CL) to electrically connect the initialization sensing line (ISL) and the second node (N2). In some embodiments, the third transistor (M3) can be turned on according to a signal received through the control line (CL) to initialize the pixel electrode of the organic light-emitting diode (OLED) with an initialization voltage from the initialization sensing line (ISL). In some embodiments, the third transistor (M3) can be turned on when a control signal is supplied to the control line (CL) to sense characteristic information of the organic light-emitting diode (OLED). The third transistor (M3) may have both the function of an initialization transistor and the function of a sensing transistor as described above, or may have either one of these functions. In some embodiments, if the third transistor (M3) has the function of an initialization transistor, the initialization sensing line (ISL) may be named the initialization voltage line, and if it has the function of a sensing transistor, the initialization sensing line (ISL) may be named the sensing line. The initialization operation and the sensing operation of the third transistor (M3) may proceed individually or simultaneously. For convenience of explanation, the following description assumes that the third transistor has both the functions of an initialization transistor and a sensing transistor.

[0085] A storage capacitor (Cst) can be connected between a first node (N1) and a second node (N2). For example, the first electrode of the storage capacitor (Cst) can be connected to the gate electrode of the first transistor (M1), and the second electrode of the storage capacitor (Cst) can be connected to the pixel electrode of the organic light-emitting diode (OLED).

[0086] Auxiliary capacitor (C) OLED ) can be electrically connected to the first transistor (T1), the third transistor (T3), a common voltage line providing a common power supply voltage (ELVSS), and the pixel electrode of an organic light-emitting diode (OLED). An auxiliary capacitor (C OLED By storing and maintaining a voltage corresponding to the voltage difference between the pixel electrode and the common voltage line of the organic light-emitting diode (OLED), the problem of black brightness increasing when the first transistor (T1) is turned off can be prevented.

[0087] Although three transistors are illustrated in FIG. 2, the present invention is not limited thereto. The pixel circuit (PC) may include four or more transistors.

[0088] FIG. 3a is a plan view showing pixel circuits of a light-emitting panel according to an embodiment of the present invention. FIG. 3b is a plan view showing pixel electrodes connected to the pixel circuits of FIG. 3. FIG. 3c to 3f are plan views schematically showing some layers of the pixel circuits shown in FIG. 3a. FIG. 4 is a cross-sectional view along the VV´ line and VI-VI´ of FIG. 3b. FIG. 5 is a plan view schematically showing the semiconductor layers and switching gate electrodes shown in FIG. 3d. Here, FIG. 4 is a cross-sectional view schematically showing a part of the light-emitting panel.

[0089] Referring to FIGS. 3a through 5, a scan line (SL) and a control line (CL) are extended along a first direction (e.g., x-direction), and a plurality of data lines, such as first to third data lines (DL1, DL2, DL3), may be arranged along a second direction (e.g., y-direction) that intersects the first direction. An initial sensing line (ISL), a driving voltage line (VDL), and a common voltage line (VSL) may be extended along the second direction.

[0090] In some embodiments, two adjacent common voltage lines (VSLs) are spaced apart from each other, and the first to third data lines (DL1, DL2, DL3), the initial sensing line (ISL), and the driving voltage line (VDL) may be placed between the two adjacent common voltage lines (VSLs). The initial sensing line (ISL) and the driving voltage line (VDL) may be placed adjacent to one of the common voltage lines (VSLs) while being adjacent to each other. The first to third data lines (DL1, DL2, DL3) may be placed adjacent to another common voltage line (VSL). For example, an initialization sensing line (ISL) and a driving voltage line (VDL) may be arranged on one side (e.g., left) centered around the first to third storage capacitors (Cst1, Cst2, Cst3) described later, and the first to third data lines (DL1, DL2, DL3) may be arranged on the other side (e.g., right), and through such a structure, the space of the display panel can be used efficiently.

[0091] A plurality of transistors and storage capacitors may be disposed between the intersecting scan line (SL) and the first to third data lines (DL1, DL2, DL3). The aforementioned transistors and storage capacitors may each be electrically connected to a corresponding organic light-emitting diode.

[0092] The first organic light-emitting diode is electrically connected to the first pixel circuit, and the first pixel circuit may include a first driving transistor (M11), a first switching transistor (M12), a first initialization-sensing transistor (M13), and a first storage capacitor (Cst1).

[0093] The second organic light-emitting diode is electrically connected to the second pixel circuit, and the second pixel circuit may include a second driving transistor (M21), a second switching transistor (M22), a second initialization-sensing transistor (M23), and a second storage capacitor (Cst2).

[0094] The third organic light-emitting diode is electrically connected to the third pixel circuit, and the third pixel circuit may include a third driving transistor (M31), a third switching transistor (M32), a third initialization-sensing transistor (M33), and a third storage capacitor (Cst3).

[0095] The first to third storage capacitors (Cst1, Cst2, Cst3) may be arranged along one direction, for example, the second direction. The first storage capacitor (Cst1) may be positioned closest to the scan line (SL) and the third storage capacitor (Cst3) may be positioned furthest from the scan line (SL) (or closest to the control line (CL)), and the second storage capacitor (Cst2) may be positioned between the first storage capacitor (Cst1) and the third storage capacitor (Cst3).

[0096] At least one of the plurality of transistors may include a cladding layer which is an oxide semiconductor. For convenience of explanation, the following description will focus on the case where all transistors include a cladding layer.

[0097] The cladding layer may be an oxide semiconductor comprising a metal oxide containing at least one of the elements In, Ga, Zn, Sn, Hf, Zr, and Al. Additionally, the cladding layer may have a crystalline or amorphous structure. In this case, the thickness of the cladding layer may be within a range of approximately 50 Å or more and 250 Å or less. For convenience of explanation, the cladding layer will be described in detail below, focusing on the case where it has a crystalline structure.

[0098] At least one of a plurality of driving transistors may include a first cladding layer (CLD1). At least one of a plurality of switching transistors may include a second cladding layer (CLD2). At least one of a plurality of initialization-sensing transistors may include a third cladding layer (CLD3). The first cladding layer (CLD1) may include a first-1 cladding layer (CLD11), a second-1 cladding layer (CLD21), and a third-1 cladding layer (CLD31). The second cladding layer (CLD2) may include a first-2 cladding layer (CLD12), a second-2 cladding layer (CLD22), and a third-2 cladding layer (CLD32). The third cladding layer (CLD3) may include the first-third cladding layer (CLD13), the second-third cladding layer (CLD23), and the third-third cladding layer (CLD33).

[0099] The first driving transistor (M11) may include a first driving semiconductor layer (A11), a first driving gate electrode (G11), and a first-1 cladding layer (CLD11). The first driving semiconductor layer (A11) may include a first high-concentration impurity region (B11) and a second high-concentration impurity region (C11), and a first channel region may be provided between the first high-concentration impurity region (B11) and the second high-concentration impurity region (C11). The first high-concentration impurity region (B11) and the second high-concentration impurity region (C11) may be regions doped with impurities at a higher concentration than the first channel region. The first driving gate electrode (G11) may overlap with the first channel region of the first driving semiconductor layer (A11).

[0100] One of the first high-concentration impurity region (B11) and the second high-concentration impurity region (C11) of the first driving semiconductor layer (A11) can be connected to the driving voltage line (VDL), and the other can be connected to the first storage capacitor (Cst1). For example, the first high-concentration impurity region (B11) can be connected to the first electrode of the first storage capacitor (Cst1) through the first contact hole (CT1), and the second high-concentration impurity region (C11) can be connected to the driving voltage line (VDL) through the second contact hole (CT2). A part of the first electrode of the first storage capacitor (Cst1) and a part of the driving voltage line (VDL) can correspond to the first electrode and the second electrode of the driving transistor described above with reference to FIG. 2.

[0101] The first-1 cladding layer (CLD11) may be positioned to shield a portion of the first high-concentration impurity region (B11) and at least a portion of the second high-concentration impurity region (C11). For example, on a plane, the first-1 cladding layer (CLD11) may be positioned to shield a first edge (ED11-1) of a portion of the first high-concentration impurity region (B11) and a second edge (ED11-2) of a portion of the second high-concentration impurity region (C11). In such a case, the first-1 cladding layer (CLD11) may completely cover the side of the end of the first driving semiconductor layer (A11). The first cladding layer (CLD11) can reduce the inflow of hydrogen from the lower layer of the first driving semiconductor layer (A11) into the first high-concentration impurity region (B11) and the second high-concentration impurity region (C11) by shielding the first edge (ED11-1) of a part of the first high-concentration impurity region (B11) and the second edge (ED11-2) of a part of the second high-concentration impurity region (C11).

[0102] The first distance (W1) between the first-1 cladding layers (CLD11) that are spaced apart from each other may be greater than the first width (W2) of the first driving gate electrode (G11). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11) on a plane. If the first-1 cladding layer (CLD11) overlaps with the first driving gate electrode (G11) on a plane, an E-trap may occur due to the first-1 cladding layer (CLD11), which may disrupt the operation of the first driving transistor (M11). However, as described above, by arranging the first-1 cladding layer (CLD11) so that it does not overlap with the first driving gate electrode (G11), the occurrence of an E-trap caused by the first-1 cladding layer (CLD11) can be reduced.

[0103] The first-1 cladding layer (CLD11) may include an oxide semiconductor of the same or different material as the first driving semiconductor layer (A11). In this case, the first-1 cladding layer (CLD11) may be a material with lower mobility than the first driving semiconductor layer (A11). For example, if the first-1 cladding layer (CLD11) and the first driving semiconductor layer (A11) are of the same material, the number of oxygen atoms contained in the first-1 cladding layer (CLD11) may be greater than the number of oxygen atoms contained in the first driving semiconductor layer (A11). As another embodiment, if the first-1 cladding layer (CLD11) and the first driving semiconductor layer (A11) are of the same material, the number of hydrogen atoms contained in the first-1 cladding layer (CLD11) may be smaller than the number of hydrogen atoms contained in the first driving semiconductor layer (A11). As another embodiment, when the first-1 cladding layer (CLD11) and the first driving semiconductor layer (A11) are made of different materials, a material having a relatively lower mobility than the mobility of the first driving semiconductor layer (A11) can be used as the first-1 cladding layer (CLD11). For example, if Indium Gallium Oxide (IGO) is used as the first driving semiconductor layer (A11), IGZO can be used as the first-1 cladding layer (CLD11).

[0104] The first switching transistor (M12) may include a first switching semiconductor layer (A12), a first switching gate electrode (G12), and a first-to-second cladding layer (CLD12). The first switching semiconductor layer (A12) may include a first high-concentration impurity region (B12) and a second high-concentration impurity region (C12), and a second channel region may be provided between the first high-concentration impurity region (B12) and the second high-concentration impurity region (C12). The first switching gate electrode (G12) may overlap with the second channel region of the first switching semiconductor layer (A12). The first switching gate electrode (G12) may correspond to a part of the scan line (SL).

[0105] At this time, the second distance (W3) between the first and second cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). Through this, the first and second cladding layers (CLD12) may not overlap with the first switching gate electrode (G12) on a plane.

[0106] The scan line (SL) may include the gate electrodes of the first to third switching transistors (M12, M22, M32). For example, the scan line (SL) may include a first branch (SL-B) in the second direction, and parts of the first branch (SL-B) may correspond to the gate electrodes of the first to third switching transistors (M12, M22, M32). The first branch (SL-B) may extend between the group of the first to third storage capacitors (Cst1, Cst2, Cst3) and the group of the first to third data lines (DL1, DL3, DL3).

[0107] One of the first high-concentration impurity region (B12) and the second high-concentration impurity region (C12) of the first switching semiconductor layer (A12) can be connected to the first data line (DL1), and the other can be connected to the first storage capacitor (Cst1). For example, the first high-concentration impurity region (B12) can be connected to the first connecting metal (NM1) through the third contact hole (CT3), and the first connecting metal (NM1) can be connected to the second electrode of the first storage capacitor (Cst1) through the fifth contact hole (CT5), and the first high-concentration impurity region (B12) can be connected to the first storage capacitor (Cst1) by the first connecting metal (NM1). The second high-concentration impurity region (C12) can be connected to the first data line (DL1) through the fourth contact hole (CT4).

[0108] The first-2 cladding layer (CLD12) can be disposed on the first high-concentration impurity region (B12) and the second high-concentration impurity region (C12) of the first switching semiconductor layer (A12), similar to the first-1 cladding layer (CLD11). That is, the first-2 cladding layer (CLD12) can completely shield the third edge (ED12-1) of the first high-concentration impurity region (B12) and the fourth edge (ED12-2) of the second high-concentration impurity region (C12) of the first switching semiconductor layer (A12). Additionally, a portion of the first-2 cladding layer (CLD12) may protrude in a direction away from the third edge (ED12-1) of the first high-concentration impurity region (B12) and the fourth edge (ED12-2) of the second high-concentration impurity region (C12) of the first switching semiconductor layer (A12). At this time, since the first-2 cladding layer (CLD12) is similar to the first-1 cladding layer (CLD11), a detailed description is omitted.

[0109] The first initialization-sensing transistor (M13) may include a first initialization-sensing semiconductor layer (A13), a first initialization-sensing gate electrode (G13), and a first-to-third cladding layer (CLD13). The first initialization-sensing semiconductor layer (A13) may include a first high-concentration impurity region (B13) and a second high-concentration impurity region (C13), and a third channel region may be provided between the first high-concentration impurity region (B13) and the second high-concentration impurity region (C13). The first initialization-sensing gate electrode (G13) may overlap with the third channel region of the first initialization-sensing semiconductor layer (A13).

[0110] The third distance (W5) between the first and third cladding layers (CLD13) may be greater than the third width (W6) of the first initialization-sensing gate electrode (G13). Through this, the first and third cladding layers (CLD13) may not overlap with the first initialization-sensing gate electrode (G13) on a plane.

[0111] The control line (CL) may include the gate electrodes of the first to third initialization-sensing transistors (M13, M23, M33). For example, the control line (CL) may include a second branch (CL-B) in the second direction, and portions of the second branch (CL-B) may correspond to the gate electrodes of the first to third initialization-sensing transistors (M13, M23, M33). The second branch (CL-B) may extend between the driving voltage line (VDL) and the initialization sensing line (ISL).

[0112] One of the first high-concentration impurity region (B13) and the second high-concentration impurity region (C13) of the first initialization-sensing semiconductor layer (A13) may be connected to the initialization-sensing line (ISL), and the other may be connected to the first storage capacitor (Cst1). For example, the first high-concentration impurity region (B13) may be connected to the initialization-sensing line (ISL) through the sixth contact hole (CT6), and the second high-concentration impurity region (C13) may be electrically connected to the second electrode of the first storage capacitor (Cst1) through the seventh contact hole (CT7).

[0113] The first-third cladding layer (CLD13) may be disposed on the first high-concentration impurity region (B13) and the second high-concentration impurity region (C13) of the first initialization-sensing semiconductor layer (A13), similar to the first-first cladding layer (CLD11). The first-third cladding layer (CLD13) may be disposed on the first high-concentration impurity region (B13) and the second high-concentration impurity region (C13) of the first initialization-sensing semiconductor layer (A13), similar to the first-first cladding layer (CLD11). That is, the first-3rd cladding layer (CLD13) can completely shield the fifth edge (ED13-1) of the first high-concentration impurity region (B13) of the first initialization-sensing semiconductor layer (A13) and the sixth edge (ED13-2) of the second high-concentration impurity region (C13). Additionally, a portion of the first-3rd cladding layer (CLD13) may protrude in a direction away from the fifth edge (ED13-1) of the first high-concentration impurity region (B13) of the first initialization-sensing semiconductor layer (A13) and the sixth edge (ED13-2) of the second high-concentration impurity region (C13). At this time, since the first-3rd cladding layer (CLD13) is similar to the first-1st cladding layer (CLD11), a detailed description will be omitted.

[0114] The first storage capacitor (Cst1) may include at least two electrodes. In one embodiment, the first storage capacitor (Cst1) includes a first electrode (CE1) and a second electrode (CE2), and the second electrode (CE2) may include a first sub-electrode (CE2b) disposed below the first electrode (CE1) and a second sub-electrode (CE2t) disposed above the first electrode (CE1). The first sub-electrode (CE2b) and the second sub-electrode (CE2t) may be connected through an eighth contact hole (CT8).

[0115] A first upper connecting electrode (CM1) may be disposed on the second sub-electrode (CE2t). At this time, the first upper connecting electrode (CM1) may be connected to the second sub-electrode (CE2t) through the first lower via hole (UVH1). Additionally, the first upper connecting electrode (CM1) may be connected to the first organic light-emitting diode through the first via hole (VH1).

[0116] Specifically, the first pixel electrode of the first organic light-emitting diode can be electrically connected to the first pixel circuit through the first upper connection electrode (CM1), the first lower via hole (UVH1), and the first via hole (VH1). At this time, the first pixel electrode is placed on the outer edge of the common voltage line (VSL) (for example, the left area of ​​the common voltage line (VSL) in FIG. 3a), although not shown in the drawing, and the first pixel electrode may include a first bridge electrode (211-1) placed on the first via hole (VH1) which is connected to the first pixel circuit. For example, the first pixel electrode of the first organic light-emitting diode is connected to the first upper connection electrode (CM1) through the first bridge electrode (211-1) and the first via hole (VH1), and the first upper connection electrode (CM1) can be connected to the second sub-electrode (CE2t) through the first lower via hole (UVH1).

[0117] The second driving transistor (M21), the second switching transistor (M22), and the second initialization-sensing transistor (M23) of the second pixel circuit may have the same structure as the first driving transistor (M11), the first switching transistor (M12), and the first initialization-sensing transistor (M13) described above. Likewise, the second storage capacitor (Cst2) may also have the same structure as the first storage capacitor (Cst1), and the second pixel electrode (212) of the second organic light-emitting diode may be electrically connected to the second pixel circuit through the second upper connection electrode (CM2), the second lower via hole (UVH2), and the second via hole (VH2) as shown in FIG. 3a. For example, the second pixel electrode (212) of the second organic light-emitting diode may be arranged to overlap with a part of the first driving transistor (M11) of the first driving circuit, the second driving transistor (M21) of the second driving circuit, and the third driving transistor (M31) of the third driving circuit. Additionally, the second pixel electrode (212) of the second organic light-emitting diode may be connected to the second upper connection electrode (CM2) through the second via hole (VH2) and the second bridge electrode protruding from the second pixel electrode (212) placed on the second via hole (VH2), and the second upper connection electrode (CM2) may be connected to the second upper electrode of the second storage capacitor (Cst2) through the second lower via hole (UVH2).

[0118] Each of the second driving transistor (M21), the second switching transistor (M22), and the second initialization-sensing transistor (M23) may include a second-1 cladding layer (CLD21), a second-2 cladding layer (CLD22), and a second-3 cladding layer (CLD23). In this case, the second-1 cladding layer (CLD21), the second-2 cladding layer (CLD22), and the second-3 cladding layer (CLD23) may be similar to the first-1 cladding layer (CLD11), the first-2 cladding layer (CLD12), and the first-3 cladding layer (CLD13) described above.

[0119] Similarly, the third driving transistor (M31), the third switching transistor (M32), and the third initialization-sensing transistor (M33) of the third pixel circuit may have the same structure as the first driving transistor (M11), the first switching transistor (M12), and the first initialization-sensing transistor (M13) described above. Likewise, the third storage capacitor (Cst3) may also have the same structure as the first storage capacitor (Cst1), and the third organic light-emitting diode may be electrically connected to the third pixel circuit through the third upper connection electrode (CM3), the third lower via hole (UVH3), and the third via hole (VH3) as shown in FIG. 3a. For example, the third pixel electrode (213) of the third organic light-emitting diode can be connected to the third upper connection electrode (CM3) through the third via hole (VH3), and the third upper connection electrode (CM3) can be connected to the second upper electrode of the third storage capacitor (Cst3) through the third lower via hole (UVH3).

[0120] Each of the third driving transistor (M31), the third switching transistor (M32), and the third initialization-sensing transistor (M33) may include a third-1 cladding layer (CLD31), a third-2 cladding layer (CLD32), and a third-3 cladding layer (CLD33). In this case, the third-1 cladding layer (CLD31), the third-2 cladding layer (CLD32), and the third-3 cladding layer (CLD33) may be similar to the first-1 cladding layer (CLD11), the first-2 cladding layer (CLD12), and the first-3 cladding layer (CLD13) described above.

[0121] Although not shown in the drawing, the first organic light-emitting diode, the second organic light-emitting diode (OLED2), and the third organic light-emitting diode may be arranged along the first direction (x-direction). The second organic light-emitting diode (OLED2) may be located between the first organic light-emitting diode and the third organic light-emitting diode and may overlap with parts of the first to third storage capacitors (Cst1, Cst2, Cst3). The third organic light-emitting diode may overlap with parts of the driving voltage line (VDL) and the initialization-sensing line (ISL). The first organic light-emitting diode may be placed on the outer edge of the first to third data lines (DL1, DL2, DL3). The positions of the first to third organic light-emitting diodes as described above may correspond to the positions of the first pixel electrode, the second pixel electrode (212) shown in FIG. 3, and the third pixel electrode (213) shown in FIG. 3.

[0122] The first to third pixel circuits are disposed on the first substrate (10). The first substrate (10) may include a glass material or a resin material. The glass material may include transparent glass with SiO2 as the main component. The resin material may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate and / or cellulose acetate propionate.

[0123] Referring to FIG. 3c and FIG. 4, to examine the method of forming each pixel circuit as described above, first, a layer including a first sub-electrode (CE2b) of a first storage capacitor (Cst1) is formed on a first substrate (10). The first sub-electrode (CE2b) can be formed by patterning a first conductive material layer after forming it, and a plurality of conductive layers can be formed together in the process of forming the first sub-electrode (CE2b). The plurality of conductive layers may include a first conductive layer (141) extending in a first direction, second to fourth conductive layers (151, 152, 153) extending in a second direction, a fifth conductive layer (161) extending in a second direction, and a sixth conductive layer (171) extending in a second direction.

[0124] The first sub-electrodes (CE2b) and the plurality of conductive layers may include molybdenum (Mo), copper (Cu) and / or titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned materials. The first sub-electrodes (CE2b) and the plurality of conductive layers may be covered by a first insulating layer (IL1). The first insulating layer (IL1) may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride, and / or an organic insulating material.

[0125] Referring to FIG. 3d and FIG. 4, a layer including a first driving semiconductor layer (A11) of a first driving transistor (M11) is formed on a first insulating layer (IL1). The first driving semiconductor layer (A11) can be formed by patterning a semiconductor material layer after forming it, and in the process of forming the first driving semiconductor layer (A11), the second and third driving semiconductor layers (A21, A31), the first to third switching semiconductor layers (A12, A22, A32), and the first to third initialization-sensing semiconductor layers (A13, A23, A33) can be formed together.

[0126] The first to third driving semiconductor layers (A11, A21, A31) are arranged sequentially along the second direction, and their lengths may be substantially the same. The first to third initialization-sensing semiconductor layers (A13, A23, A33) are also arranged sequentially along the second direction, and their lengths may be substantially the same.

[0127] The first to third switching semiconductor layers (A12, A22, A32) are arranged sequentially along the second direction, and their lengths may differ from one another. For example, the length of the second switching semiconductor layer (A22) located in the center may be greater than the length of the first switching semiconductor layer (A12) adjacent to the scan line (SL) and smaller than the length of the third switching semiconductor layer (A13) positioned furthest from the scan line (SL). The length of the first switching semiconductor layer (A12) may be smaller than the length of the third switching semiconductor layer (A13).

[0128] The first to third driving semiconductor layers (A11, A21, A31), the first to third switching semiconductor layers (A12, A22, A32), and the first to third initialization-sensing semiconductor layers (A13, A23, A33) may include oxide semiconductors, etc.

[0129] A cladding layer may be disposed on the upper or lower portion of at least one of the first to third driving semiconductor layers (A11, A21, A31), the first to third switching semiconductor layers (A12, A22, A32), and the first to third initialization-sensing semiconductor layers (A13, A23, A33). For convenience of explanation, the following description will explain in detail the case in which a first-1 cladding layer (CLD11) to a first-3 cladding layer (CLD13) is disposed on each of the first to third driving semiconductor layers (A11, A21, A31), the first to third switching semiconductor layers (A12, A22, A32), and the first to third initialization-sensing semiconductor layers (A13, A23, A33).

[0130] After this, a second insulating layer (IL2) may be formed. The second insulating layer (IL2) may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride, and / or an organic insulating material.

[0131] Next, a layer is formed on the second insulating layer (IL2) comprising the first driving gate electrode (G11) of the first driving transistor (M11) and the first electrode (CE1) of the first storage capacitor (Cst1). The first driving gate electrode (G11) and the first electrode (CE1) of the first storage capacitor (Cst1) can be formed integrally.

[0132] The first driving gate electrode (G11) and the first electrode (CE1) can be formed by patterning the second conductive material layer after forming it. In the process of forming and patterning the second conductive material layer, the first to third driving gate electrodes (G11, G21, G31), the first electrode (CE1) of the second and third storage capacitors (Cst2, Cst3), the scan line (SL), and the control line (CL) can be formed together.

[0133] The second driving gate electrode (G21) and the first electrode (CE1) of the second storage capacitor (Cst2) can be formed integrally, and the third driving gate electrode (G31) and the first electrode (CE1) of the third storage capacitor (Cst3) can be formed integrally.

[0134] The scan line (SL) and the control line (CL) may each include a first branch (SL-B) and a second branch (CL-B). Parts of the first branch (SL-B) may correspond to the first to third switching gate electrodes (G12, G22, G32) of the first to third switching transistors (M12, M22, M32), and parts of the second branch (CL-B) may correspond to the first to third initialization-sensing gate electrodes (G13, G23, G33) of the first to third initialization-sensing transistors (M13, M23, M33).

[0135] In some embodiments, when two conductive material layers are formed and then patterned, a seventh conductive layer (271) may be formed. The seventh conductive layer (271) may be connected to the sixth conductive layer (171) through a contact hole (CT).

[0136] The first to third driving gate electrodes (G11, G21, G31), scan line (SL), control line (CL), and first electrode (CE1) may include copper (Cu) and / or titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material. The first to third driving gate electrodes (G11, G21, G31), scan line (SL), control line (CL), and first electrode (CE1) may be covered by a third insulating layer (IL3). The third insulating layer (IL3) may include an inorganic insulating material such as silicon nitride, silicon oxide, and / or silicon oxynitride, and / or an organic insulating material.

[0137] Referring to FIG. 3e and FIG. 4, a layer including a driving voltage line (VDL) and a second sub-electrode (CE2t) of a first storage capacitor (Cst1) is formed. The driving voltage line (VDL) and the second sub-electrode (CE2t) can be formed by patterning a third conductive material layer after forming it. The second sub-electrodes (CE2t) of each of the first to third storage capacitors (Cst1, Cst2, Cst3), the first to third data lines (DL1, DL2, DL3), the initialization-sensing line (ISL), the driving voltage line (VDL), the common voltage line (VSL), and the first to fourth connecting metals (NM1, NM2, NM3, MN4) can be formed together.

[0138] The second sub-electrodes (CE2t) of each of the first to third storage capacitors (Cst1, Cst2, Cst3), the first to third data lines (DL1, DL2, DL3), the initialization-sensing line (ISL), the driving voltage line (VDL), the common voltage line (VSL), and the first to fourth connecting metals (NM1, NM2, NM3, MN4) may include copper (Cu) and / or titanium (Ti), etc., and may include a single-layer or multi-layer structure including the aforementioned material.

[0139] The driving voltage line (VDL) can be connected to the first driving semiconductor layer (A11) of the first driving transistor (M11) through the second contact hole (CT2), connected to the second driving semiconductor layer (A21) of the second driving transistor (M21) through the ninth contact hole (CT9), and connected to the third driving semiconductor layer (A31) of the third driving transistor (M31) through the tenth contact hole (CT10).

[0140] The first data line (DL1) can be connected to the first switching semiconductor layer (A12) of the first switching transistor (M12) through the fourth contact hole (CT4). The second data line (DL2) can be connected to the second switching semiconductor layer (A22) of the second switching transistor (M22) through the eleventh contact hole (CT11). The third data line (DL3) can be connected to the third switching semiconductor layer (A32) of the third switching transistor (M32) through the twelfth contact hole (CT12).

[0141] The initialization-sensing line (ISL) can be connected to the first initialization-sensing semiconductor layer (A13) of the first initialization-sensing transistor (M13) through the sixth contact hole (CT6), connected to the second initialization-sensing semiconductor layer (A23) of the second initialization-sensing transistor (M23) through the thirteenth contact hole (CT13), and connected to the third initialization-sensing semiconductor layer (A33) of the third initialization-sensing transistor (M33) through the fourteenth contact hole (CT14).

[0142] The second sub-electrode (CE2t) of the first storage capacitor (Cst1) can be connected to the first driving semiconductor layer (A11) of the first driving transistor (M11) through the first contact hole (CT1), and to the first initialization-sensing semiconductor layer (A13) of the first initialization-sensing transistor (M13) through the seventh contact hole (CT7). The second sub-electrode (CE2t) of the first storage capacitor (Cst1) can be connected to the first sub-electrode (CE2b) of the first storage capacitor (Cst1) through the eighth contact hole (CT8).

[0143] Similarly, the second sub-electrode (CE2t) of the second storage capacitor (Cst2) can be connected to the second driving semiconductor layer (A21) of the second driving transistor (M21) through the 15th contact hole (CT15) and to the second initialization-sensing semiconductor layer (A23) of the second initialization-sensing transistor (M23) through the 16th contact hole (CT16). The second sub-electrode (CE2t) of the second storage capacitor (Cst2) can be connected to the first sub-electrode (CE2b) of the second storage capacitor (Cst2) through the 17th contact hole (CT17).

[0144] The second sub-electrode (CE2t) of the third storage capacitor (Cst3) can be connected to the third driving semiconductor layer (A31) of the third driving transistor (M31) through the 18th contact hole (CT18), and to the third initialization-sensing semiconductor layer (A33) of the third initialization-sensing transistor (M33) through the 19th contact hole (CT19). The second sub-electrode (CE2t) of the third storage capacitor (Cst3) can be connected to the first sub-electrode (CE2b) of the third storage capacitor (Cst3) through the 20th contact hole (CT20).

[0145] The first connecting metal (NM1) can electrically connect the first switching semiconductor layer (A12) and the first driving gate electrode (G11) through contact holes. Similarly, the third connecting metal (NM3) and the fourth connecting metal (NM4) can each connect the second switching semiconductor layer (A22) and the second driving gate electrode (G21) or the third switching semiconductor layer (A32) and the third driving gate electrode (G31) through contact holes.

[0146] The second connecting metal (NM2) can connect the scan line (SL) and the first conductive layer (141, FIG. 6) through contact holes, and through such a connection structure, the resistance of the scan line (SL) can be reduced and the voltage drop of the scan line (SL) can be prevented.

[0147] Each of the first to third data lines (DL1, DL2, DL3), initialization-sensing line (ISL), and common voltage line (VSL) can be connected to a corresponding conductive layer among the plurality of conductive layers (e.g., second to sixth conductive layers, 151, 152, 153, 161, 171) described with reference to FIG. 6 through contact holes to reduce resistance.

[0148] Afterwards, a fourth insulating layer (IL4) is formed as shown in FIG. 4. The fourth insulating layer (IL4) may include an organic insulating material including polyimide, etc. Afterwards, a first lower via hole (UVH1), a second lower via hole (UVH2), and a third lower via hole (UVH3) are formed on the fourth insulating layer (IL4). In addition, a first upper connecting electrode (CM1), a second upper connecting electrode (CM2), and a third upper connecting electrode (CM3) may be formed on the fourth insulating layer (IL4) to correspond to each of the first lower via hole (UVH1), the second lower via hole (UVH2), and the third lower via hole (UVH3). Each of the first upper connecting electrode (CM1), the second upper connecting electrode (CM2), and the third upper connecting electrode (CM3) can be arranged to correspond to the first storage capacitor (Cst1), the second storage capacitor (Cst2), and the third storage capacitor (Cst3), respectively. Each of the first upper connecting electrode (CM1), the second upper connecting electrode (CM2), and the third upper connecting electrode (CM3) can be connected to each second sub-electrode (CE2t) through the first lower via hole (UVH1), the second lower via hole (UVH2), and the third lower via hole (UVH3), respectively.

[0149] A fifth insulating layer (IL5) may be disposed on the first upper connecting electrode (CM1), the second upper connecting electrode (CM2), and the third upper connecting electrode (CM3). The fifth insulating layer (IL5) may include an organic insulating material including polyimide. Each of the first pixel electrode, the second pixel electrode (212), and the third pixel electrode (213) may be connected to the first upper connecting electrode (CM1), the second upper connecting electrode (CM2), and the third upper connecting electrode (CM3), respectively, through the first via hole (VH1), the second via hole (VH2), and the third via hole (VH3) of the fifth insulating layer (IL5), respectively.

[0150] Referring to FIG. 4, a pixel defining film (PDL) may be formed on the second pixel electrode (212) and on the second pixel electrode (212). The pixel defining film (PDL) includes an opening that overlaps the second pixel electrode (212), although this is not shown in the drawing. A light-emitting layer (220) and a counter electrode (230) may be sequentially stacked on the second pixel electrode (212). The second pixel electrode (212), the light-emitting layer (220), and the counter electrode (230) may form a second organic light-emitting diode (OLED2).

[0151] The second organic light-emitting diode structure of FIG. 4 is identical to the first organic light-emitting diode and the third organic light-emitting diode structure. For example, the first organic light-emitting diode may have a stacked structure of a first pixel electrode, a light-emitting layer (220), and a counter electrode (230), and the third organic light-emitting diode may have a stacked structure of a third pixel electrode (213), a light-emitting layer (220), and a counter electrode (230).

[0152] The light-emitting layer (220) can be integrally formed in correspondence with a plurality of light-emitting diodes, similar to the counter electrode (230). The light-emitting layer may include a polymer or low-molecular-weight organic material that emits blue light.

[0153] Hereinafter, the method for forming the 1-1 cladding layer (CLD11) to the 1-3 cladding layer (CLD13) will be described in detail. However, since the method for forming each of the 1-1 cladding layer (CLD11) to the 1-3 cladding layer (CLD13) is similar to one another, for the sake of convenience of explanation, the method for forming the 1-1 cladding layer (CLD11) will be described in detail below.

[0154] FIGS. 6a to 6c are cross-sectional views schematically showing part of the manufacturing process of the pixel circuit of FIG. 3.

[0155] Referring to FIG. 6a, a first sub-electrode (CE2b), a first insulating layer (IL1), and a first driving semiconductor layer (A11) can be formed on a first substrate (10). At this time, when forming the first driving semiconductor layer (A11), an oxide semiconductor base layer with an amorphous structure can be formed on the front surface of the first insulating layer (IL1). The first driving semiconductor layer (A11) can be formed by wet etching after a photolithography process of the oxide semiconductor base layer. Afterward, the first driving semiconductor layer (A11) can be crystallized by heat treatment at a high temperature after removing the photoresist. At this time, if the first driving semiconductor layer (A11) is IGO, the first driving semiconductor layer (A11) can be crystallized by heat treatment at a high temperature of 350°C or higher.

[0156] When the above process is completed, a base layer (CLD-BA) can be placed on the first driving semiconductor layer (A11). At this time, the base layer (CLD-BA) may include an oxide semiconductor material with lower mobility than the first driving semiconductor layer (A11). In such a case, the base layer (CLD-BA) can be placed to completely cover the first insulating layer (IL1) and the first driving semiconductor layer (A11). Additionally, heat can be applied to the base layer (CLD-BA) to move oxygen atoms of the base layer (CLD-BA) to the first driving semiconductor layer (A11). At this time, if the base layer (CLD-BA) is IGO, the base layer (CLD-BA) can be heat-treated at a temperature of less than 350°C to prevent crystallization.

[0157] Referring to FIG. 6b, a photoresist (PR1) can be placed on a base layer (CLD-BA). At this time, the photoresist (PR1) can be placed on the portion where the first-1 cladding layer (CLD11) is to be formed. Subsequently, the base layer (CLD-BA) exposed to the outside through the photoresist (PR1) can be removed by wet etching. In this case, the first driving semiconductor layer (A11) may not be removed due to crystallization. Subsequently, heat can be applied to the first-1 cladding layer (CLD11) to cause crystallization. At this time, if the first-1 cladding layer (CLD11) is IGO, the first driving semiconductor layer (A11) can be crystallized by heat treatment at a high temperature of 350°C or higher.

[0158] Referring to FIG. 6c, after the above process is completed, a second insulating layer (IL2), a first driving gate electrode (G11), and a third insulating layer (IL3) can be formed sequentially.

[0159] After forming the second insulating layer (IL2) and the first driving gate electrode (G11), a region of the first driving semiconductor layer (A11) and the first-1 cladding layer (CLD11) can be doped in the form of N+ through boron doping. At this time, a region of the first driving semiconductor layer (A11) and the first-1 cladding layer (CLD11) may contain boron atoms.

[0160] Various contact holes can be formed on the third insulating layer (IL3). For example, as shown in FIG. 6c, a first contact hole (CT1), a second contact hole (CT2), and an eighth contact hole (CT8) can be formed. At this time, the first contact hole (CT1), the second contact hole (CT2), and the eighth contact hole (CT8) can each be formed through dry etching.

[0161] In the above case, the depths of the first contact hole (CT1) and the second contact hole (CT2) may be nearly similar. However, the depth of the eighth contact hole (CT8) is greater than the depth of the first contact hole (CT1) and / or the depth of the second contact hole (CT2), so that the material placed on the bottom surface of the first contact hole (CT1) and the second contact hole (CT2) can also be continuously etched until the eighth contact hole (CT8) is formed. If the first-1 cladding layer (CLD11) does not exist, energy is continuously applied to the surface of the first driving semiconductor layer (A11), and the portion of the first driving semiconductor layer (A11) corresponding to the first contact hole (CT1) and the second contact hole (CT2) may be lost. In such cases, an error may occur during the operation of the first driving semiconductor layer (A11), or the first driving semiconductor layer (A11) may be damaged, causing the display panel to not operate or to malfunction. However, as described above, contact resistance can be reduced by placing the first-1 cladding layer (CLD11) on the first driving semiconductor layer (A11) so as to correspond to the first contact hole (CT1) and the second contact hole (CT2). Additionally, by placing the first-1 cladding layer (CLD11) on the first driving semiconductor layer (A11) so as to correspond to the first contact hole (CT1) and the second contact hole (CT2), it is possible to form the thickness of the first driving semiconductor layer (A11) thinner than before.

[0162] Although not illustrated in the drawings, the method of forming the first-2 cladding layer, the first-3 cladding layer, the second cladding layer, and the third cladding layer may be the same or similar to the method of forming the first-1 cladding layer (CLD11) described above. Furthermore, by forming the first-2 cladding layer, the first-3 cladding layer, the second cladding layer, and the third cladding layer, it is possible to reduce the degradation of performance or damage to each semiconductor layer even when a contact hole is formed in each semiconductor layer corresponding to each cladding layer.

[0163] FIG. 7 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. The display panel shown in FIG. 7 may be the same or similar as that described in FIG. 1 to FIG. 4. Among the reference numerals in FIG. 7, the same reference numerals as those in FIG. 4 indicate the same components, and the following description will focus on the differences from FIG. 4.

[0164] Referring to FIG. 7, the pixel circuit of the light-emitting panel of the display panel may include a cladding layer disposed on each semiconductor layer. Each cladding layer may be the same or similar as described in FIG. 3a to FIG. 5.

[0165] At least one of the plurality of cladding layers may include a groove. For convenience of explanation, the following description will focus on the 1-1 cladding layer (CLD11).

[0166] A first sub-electrode (CE2b), a first insulating layer (IL1), and a first driving semiconductor layer (A11) may be disposed on a first substrate (10). Additionally, a first-1 cladding layer (CLD11), a second insulating layer (IL2), a first driving gate electrode (G11), a third insulating layer (IL3), a driving voltage line (VDL), and a second sub-electrode (CE2t) may be disposed sequentially on the first driving semiconductor layer (A11).

[0167] The first-1 cladding layer (CLD11) may include a first groove (CLD1-G). In this case, the first groove (CLD1-G) may be placed in a portion corresponding to the first contact hole (CT1) and / or the second contact hole (CT2). The thickness of the portion of the first-1 cladding layer (CLD11) where the first groove (CLD1-G) is placed may be smaller than the thickness of other portions of the first-1 cladding layer (CLD11).

[0168] Therefore, the first-1 cladding layer (CLD11) can prevent the thickness of the first driving semiconductor layer (A11) from becoming thinner than the initial state.

[0169] The first distance (W1) between the first-1 cladding layers (CLD11) may be greater than the first width (W2) of the first driving gate electrode (G11). Additionally, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11), and the first-2 cladding layer (CLD12) may not overlap with the first switching gate electrode (G12).

[0170] Therefore, the display panel can reduce e-traps that may occur by arranging the cladding layer and the gate electrode so that they overlap on a plane.

[0171] The manufacturing process of the display panel described above may be the same or similar as described in FIGS. 6a to 6c. Additionally, although FIG. 7 only shows a part of the first driving transistor (M11), when a cladding layer is placed on each semiconductor layer, the relationship between each semiconductor layer and each cladding layer may be the same or similar as described above.

[0172] FIG. 8 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. The display panel shown in FIG. 8 may be the same or similar as that described in FIG. 1 to FIG. 4. Among the reference numerals in FIG. 8, the same reference numerals as those in FIG. 4 indicate the same components, and the following description will focus on the differences from FIG. 4.

[0173] Referring to FIG. 8, the second insulating layer (IL2) of the display panel may be formed in a pattern shape similar to each gate electrode. For example, the second insulating layer (IL2) may be placed below the first driving gate electrode (G11) and may have a planar shape identical or similar to the first driving gate electrode (G11). Additionally, the second insulating layer (IL2) may be placed below the first switching gate electrode (G12) and may have a planar shape identical or similar to the first switching gate electrode (G12). Although not shown in the drawing, the second insulating layer (IL2) may be placed below the first initialization-sensing gate electrode and may have a planar shape identical or similar to the first initialization-sensing gate electrode.

[0174] At this time, the second insulating layer (IL2) can be formed simultaneously with the formation of each gate electrode. For example, a material for forming the second insulating layer (IL2) can be placed on the front surface of the first substrate (10), and a material for forming the gate electrode can be placed on the second insulating layer (IL2), and then the material for forming the second insulating layer (IL2) and the material for forming the gate electrode can be patterned through dry etching. In this case, the second insulating layer (IL2) and each gate electrode can have a shape similar to that of each semiconductor layer, excluding the one shown in FIG. 3d.

[0175] In the above case, when the third insulating layer (IL3) is formed, hydrogen atoms of the third insulating layer (IL3) move to the first-1 cladding layer (CLD11), the first-2 cladding layer (CLD12), a part of the first driving semiconductor layer (A11), and a part of the first switching semiconductor layer (A12) that are in contact with the third insulating layer (IL3), so that the first-1 cladding layer (CLD11), the first-2 cladding layer (CLD12), a part of the first driving semiconductor layer (A11), and a part of the first switching semiconductor layer (A12) can be doped in the form of N+.

[0176] The first-1 cladding layer (CLD11) may be placed on the first driving semiconductor layer (A11). Additionally, the first-2 cladding layer (CLD12) may be placed on the first switching semiconductor layer (A12). Although not shown in the drawing, each cladding layer may be placed on each semiconductor layer. Through this, when forming a contact hole on each semiconductor layer, each cladding layer can prevent a portion of each semiconductor layer from being lost.

[0177] The first distance (W1) between the first-1 cladding layers (CLD11) may be greater than the first width (W2) of the first driving gate electrode (G11). Additionally, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11), and the first-2 cladding layer (CLD12) may not overlap with the first switching gate electrode (G12).

[0178] Therefore, the display panel can reduce e-traps that may occur by arranging the cladding layer and the gate electrode so that they overlap on a plane.

[0179] Although the drawings disclose only the formation of a first-1 cladding layer (CLD11) and a first-2 cladding layer (CLD12) on each of the first driving semiconductor layer (A11) and the first switching semiconductor layer (A12), the relationship between each semiconductor layer and each cladding layer may be the same or similar as described above when a cladding layer is disposed on each semiconductor layer excluding the first driving semiconductor layer (A11) and the first switching semiconductor layer (A12).

[0180] FIG. 9 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. The display panel shown in FIG. 9 may be the same or similar as that described in FIG. 1 to FIG. 4. Among the reference numerals in FIG. 9, the same reference numerals as those in FIG. 4 indicate the same components, and the following description will focus on the differences from FIG. 4.

[0181] Referring to FIG. 9, each cladding layer may be placed below at least a portion of each semiconductor layer. For example, the first-1 cladding layer (CLD11) may be placed below at least a portion of the first driving semiconductor layer (A11). Additionally, the first-2 cladding layer (CLD12) may be placed below at least a portion of the first switching semiconductor layer (A12).

[0182] The first distance (W1) between the first-1 cladding layers (CLD11) may be greater than the first width (W2) of the first driving gate electrode (G11). Additionally, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11), and the first-2 cladding layer (CLD12) may not overlap with the first switching gate electrode (G12).

[0183] A second insulating layer (IL2) may be disposed on the first driving semiconductor layer (A11) and the first switching semiconductor layer (A12). The second insulating layer (IL2) may be disposed on the entire surface of the first substrate (10). For example, the second insulating layer (IL2) may be disposed over the entire display area shown in FIG. 1a.

[0184] Although not illustrated in the drawing, if a cladding layer is disposed on each semiconductor layer, the relationship between each semiconductor layer and each cladding layer may be the same or similar as described above.

[0185] Therefore, when forming a contact hole corresponding to a region of each semiconductor layer, the performance of each semiconductor layer may not deteriorate even if a part of the portion of each semiconductor layer corresponding to the contact hole is lost.

[0186] FIGS. 10a to 10d are cross-sectional views schematically showing a part of the manufacturing process of the pixel circuit of the light-emitting panel shown in FIG. 9. The display panel shown in FIG. 10 may be the same or similar as that described in FIGS. 1 to 4. Among the reference numerals in FIG. 10, the reference numerals identical to those in FIG. 4 represent the same components, and the following description will focus on the differences from FIG. 4.

[0187] Referring to FIG. 10a, a first sub-electrode (CE2b) can be formed on a first substrate (10), and then a first insulating layer (IL1) can be placed. Additionally, a base layer (CLD-BA) can be placed on the first insulating layer (IL1). Subsequently, oxygen atoms from the base layer (CLD-BA) can be supplied to the first insulating layer (IL1) through heat treatment. At this time, if the base layer (CLD-BA) is IGO, the heat treatment can be performed in a range of less than 350°C so that the base layer (CLD-BA) does not crystallize.

[0188] Referring to FIG. 10b, a photoresist (PR1) can be placed on a base layer (CLD-BA) and then the photoresist (PR1) can be formed into a pattern. Afterward, the base layer (CLD-BA) that is not shielded by the photoresist (PR1) can be removed by wet etching to form a first cladding layer (CLD11).

[0189] Referring to FIG. 10c, a first driving semiconductor layer (A11) can be placed on the first-1 cladding layer (CLD11). Since the method of forming the first driving semiconductor layer (A11) is the same or similar as described in FIG. 6c, a detailed description will be omitted.

[0190] After forming the first driving semiconductor layer (A11), the first driving semiconductor layer (A11) can be heat-treated at a high temperature to crystallize the first driving semiconductor layer (A11). For example, if the first driving semiconductor layer (A11) is IGO, it can be heat-treated at a temperature of 350°C or higher.

[0191] During the thermal treatment process, oxygen atoms inside the first insulating layer (IL1) diffuse into the first-1 cladding layer (CLD11) and the first driving semiconductor layer (A11), so that the first-1 cladding layer (CLD11) can also crystallize together with the first driving semiconductor layer (A11).

[0192] Referring to FIG. 10d, a second insulating layer (IL2), a first driving gate electrode (G11), and a third insulating layer (IL3) can be placed on the first driving semiconductor layer (A11). At this time, after forming the second insulating layer (IL2) and the first driving gate electrode (G11), a region of the first driving semiconductor layer (A11) and the first-1 cladding layer (CLD11) can be doped in an N+ form through boron doping. At this time, a region of the first driving semiconductor layer (A11) and the first-1 cladding layer (CLD11) may contain boron atoms.

[0193] A first contact hole (CT1), a second contact hole (CT2), and an eighth contact hole (CT8) can be formed in the second insulating layer (IL2) and the third insulating layer (IL3) through dry cutting. Subsequently, although not shown in the drawing, various layers shown in FIG. 4 can be placed on the third insulating layer (IL3).

[0194] While the above process is in progress, other transistors, although not shown in the drawing, are formed simultaneously with the formation of the first driving transistor (M11), and after forming the plurality of transistors, a plurality of organic light-emitting diodes may also be formed. Additionally, at least one of the plurality of transistors may include a cladding layer arranged to correspond to the corresponding semiconductor layer.

[0195] FIG. 11 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. The display panel shown in FIG. 11 may be the same or similar as that described in FIG. 1 to FIG. 4. Among the reference numerals in FIG. 11, the same reference numerals as those in FIG. 4 indicate the same components, and the following description will focus on the differences from FIG. 4.

[0196] Referring to FIG. 11, the pixel circuit of the light-emitting panel of the display panel may include a cladding layer disposed below at least one of the plurality of semiconductor layers. The cladding layer may be the same or similar as described in FIG. 9. For convenience of explanation, the following description will focus on the case where the cladding layer is disposed below each semiconductor layer.

[0197] At least one of the plurality of semiconductor layers may include a groove. For convenience of explanation, the following description will focus on the first driving semiconductor layer (A11).

[0198] A first sub-electrode (CE2b), a first insulating layer (IL1), a first-1 cladding layer (CLD11), and a first driving semiconductor layer (A11) may be disposed on a first substrate (10). Additionally, a second insulating layer (IL2), a first driving gate electrode (G11), a third insulating layer (IL3), a driving voltage line (VDL), and a second sub-electrode (CE2t) may be disposed sequentially on the first driving semiconductor layer (A11).

[0199] The first driving semiconductor layer (A11) may include a second groove (A11-G). In this case, the second groove (A11-G) may be placed in a portion corresponding to the first contact hole (CT1) and / or the second contact hole (CT2). The thickness of the portion of the first driving semiconductor layer (A11) where the second groove (A11-G) is placed may be smaller than the thickness of other portions of the first driving semiconductor layer (A11).

[0200] Therefore, even if the thickness of the first driving semiconductor layer (A11) becomes thinner than the initial state, the increase in contact resistance of the first driving semiconductor layer (A11) can be reduced due to the first-1 cladding layer (CLD11).

[0201] The first distance (W1) between the first-1 cladding layers (CLD11) may be greater than the first width (W2) of the first driving gate electrode (G11). Additionally, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11), and the first-2 cladding layer (CLD12) may not overlap with the first switching gate electrode (G12).

[0202] Therefore, the display panel can reduce e-traps that may occur by arranging the cladding layer and the gate electrode so that they overlap on a plane.

[0203] The manufacturing process of the display panel described above may be the same or similar as described in FIGS. 10a to 10d. Additionally, although FIG. 11 only shows a part of the first driving transistor (M11), when a cladding layer is placed on each semiconductor layer, the relationship between each semiconductor layer and each cladding layer may be the same or similar as described above.

[0204] FIG. 12 is a cross-sectional view schematically showing a part of the pixel circuit of a light-emitting panel according to another embodiment of the present invention. The display panel shown in FIG. 12 may be similar to that described in FIG. 1 to FIG. 4. Among the reference numerals in FIG. 12, the same reference numerals as in FIG. 4 indicate the same components, and the following description will focus on the differences from FIG. 9.

[0205] Referring to FIG. 12, the pixel circuit of the light-emitting panel of the display panel may include a cladding layer disposed below at least one of the plurality of semiconductor layers. The cladding layer may be the same or similar as described in FIG. 9. For convenience of explanation, the following description will focus on the case where the cladding layer is disposed below each semiconductor layer.

[0206] The first distance (W1) between the first-1 cladding layers (CLD11) may be greater than the first width (W2) of the first driving gate electrode (G11). Additionally, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first switching gate electrode (G12). That is, the first-1 cladding layer (CLD11) may not overlap with the first driving gate electrode (G11), and the first-2 cladding layer (CLD12) may not overlap with the first switching gate electrode (G12).

[0207] The second insulating layer (IL2) may be arranged in a pattern shape on the first driving semiconductor layer (A11) and the first switching semiconductor layer (A12). At this time, the second insulating layer (IL2) may be arranged below the first driving gate electrode (G11) and below the first switching gate electrode (G12). Since the method of forming the second insulating layer (IL2) in a pattern shape is the same or similar as described in FIG. 8, a detailed description will be omitted.

[0208] Although not illustrated in the drawing, if a cladding layer is disposed beneath each semiconductor layer, the relationship between each semiconductor layer and each cladding layer may be the same or similar as described above.

[0209] FIGS. 13a to 13d are cross-sectional views schematically showing a portion of a pixel circuit of a light-emitting panel according to another embodiment of the present invention. FIG. 14 is a cross-sectional view schematically showing a switching semiconductor layer, a switching gate electrode, and a first-second cladding layer among a portion of the pixel circuit of a light-emitting panel shown in FIGS. 13a to 13d. The display panel shown in FIGS. 13a to 13d may be similar to that described in FIGS. 1 to 4. Among the reference numerals in FIGS. 13a to 13d, reference numerals identical to those in FIG. 4 indicate identical components.

[0210] Referring to FIGS. 13a to 14, the pixel circuit of the light-emitting panel of the display panel may include a cladding layer disposed below at least one of the plurality of semiconductor layers.

[0211] The first switching transistor (M12) may include a first-1 switching gate electrode (G12a) and a first-2 switching gate electrode (G12b), which are additional gate electrodes arranged to be spaced apart from each other. In this case, the first-1 switching gate electrode (G12a) may be formed on the same layer as the first sub-electrode (CE2b) when the first sub-electrode (CE2b) described in FIG. 4 is formed. In this case, the first driving transistor (M11) may be in the same form as shown in FIG. 4, FIG. 7, FIG. 8, FIG. 9, FIG. 11, or FIG. 12.

[0212] In the above case, although not illustrated in the drawing, the first-1 switching gate electrode (G12a) and the first-2 switching gate electrode (G12b) can be directly connected to each other. For example, after forming separate contact holes in the first insulating layer (IL1) and the second insulating layer (IL2), when forming the driving voltage line (VDL), a separate connecting electrode in the form of an island can be placed on the contact hole to connect the first-1 switching gate electrode (G12a) and the first-2 switching gate electrode (G12b) to each other as connecting electrodes.

[0213] Referring to FIG. 13a and FIG. 13b, the first-second cladding layer (CLD12) can be placed on top of the first switching transistor (M12).

[0214] Referring to FIG. 13b and FIG. 13d, the second insulating layer (IL2) does not shield the entire first switching transistor (M12) but is placed only on a part of the first switching transistor (M12) and can be formed in a pattern shape such as the first-second switching gate electrode (G12b).

[0215] Referring to FIG. 13c and FIG. 13d, the first-second cladding layer (CLD12) may be placed on the lower part of the first switching transistor (M12).

[0216] In the above case, the first-2 cladding layer (CLD12) may be the same or similar as described in FIGS. 4, 7, 8, 9, 11, or 12. Additionally, the method of forming the first-2 cladding layer (CLD12) may be the same or similar as the method of forming the first-1 cladding layer (CLD11) described in FIGS. 6a to 6c or FIGS. 10a to 10d.

[0217] At least one of the plurality of switching transistors may include a plurality of switching gate electrodes spaced apart from each other in the thickness direction of the display panel. For convenience of explanation, the following description will focus on the first switching transistor.

[0218] In the above case, the second distance (W3) between the first-2 cladding layers (CLD12) may be greater than the second width (W4) of the first-2 switching gate electrode (G12b) or the fourth width (W7) of the first-1 switching gate electrode (G12a). Additionally, the fourth width (W7) may be greater than the second width (W4). In this case, the first-1 switching gate electrode (G12a) and the first-2 switching gate electrode (G12b) may be placed between the first-2 cladding layers (CLD12) that are adjacent to each other. Furthermore, the first-1 switching gate electrode (G12a) and the first-2 switching gate electrode (G12b) may not overlap with the first-2 cladding layers (CLD12) on a plane. That is, the first-1 switching gate electrode (G12a) and the first-2 switching gate electrode (G12b) can be arranged to overlap with the first-2 cladding layer (CLD12) to avoid e-traps that may occur.

[0219] Although not illustrated in the drawing, if each switching transistor includes a cladding layer, the relationship between each switching semiconductor layer and each cladding layer may be the same or similar as described above.

[0220] FIG. 15 is a block diagram of an electronic device according to one embodiment of the present invention.

[0221] Referring to FIG. 15, an electronic device (100) according to one embodiment may include a display module (110) including the display panel described above, a processor (120), a memory (130), and a power module (140).

[0222] The processor (120) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In one embodiment, the processor (120) may be provided divided into two or more parts from a functional or structural perspective. For example, the processor (120) may include a main processor in the form of a first driving chip that includes a central processing unit, and an auxiliary process in the form of a second driving chip that includes a controller that receives an image signal from the main processor and processes the image signal to match the interface specifications of the display module (110).

[0223] The memory (130) may include at least one of non-volatile memory and volatile memory. Data information necessary for the operation of the processor (120) or the display module (110) may be stored in the memory (130). When the processor (120) executes an application stored in the memory (130), an image data signal and / or an input control signal is transmitted to the display module (110), and the display module (110) can process the received signal and output image information through a display screen.

[0224] The power module (140) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (100). Power conversion by the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0225] The electronic device (100) may further include an input module (150), a non-image output module (160), and / or a communication module (170).

[0226] The input module (150) can provide input information to the processor (120) and / or the display module (110). The input module (150) may include physical buttons, a keyboard, a microphone, as well as various sensor modules. Examples of sensor modules may include touch sensors, pressure sensors, distance sensors, position sensors, digitizers, motion recognition sensors, camera sensors, light receiving sensors, photoelectric conversion sensors, temperature sensors, as well as biosensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and heart rate sensors.

[0227] The non-video output module (160) can receive information other than the video received from the processor (120) and provide it to the user. Examples of the non-video output module (160) include an acoustic module, a haptic module, a light-emitting module, and other functional modules unique to the electronic device (e.g., a cooling module of a refrigerator).

[0228] The communication module (170) is a module responsible for transmitting and receiving information between the electronic device (100) and an external device, and may include a receiving unit and a transmitting unit. The communication module (170) may include various wireless communication modules such as a mobile communication module, a Wi-Fi module, a Bluetooth module, or various wired communication modules.

[0229] At least one of each component of the electronic device (100) described above may be included within a display panel according to the embodiments described above. Additionally, some of the individual modules functionally included within a single module may be included within the display panel, while others may be provided separately from the display panel. For example, the display panel may include a display module (110), and the processor (120), memory (130), and power module (140) may be provided in the form of other devices within the electronic device (100) other than the display panel. As another example, the power module (140) may be provided within the display panel and may supply power to the processor (120) and memory (130) provided within the electronic device (100) other than the display panel, but is not limited to the above examples.

[0230] FIGS. 16 to 18 are schematic diagrams of electronic devices according to various embodiments of the present invention. FIGS. 16 to 18 illustrate examples of various electronic devices to which a display panel according to embodiments of the present invention is applied.

[0231] FIG. 16 illustrates examples of electronic devices, including a smartphone (100_1a), a tablet PC (100_1b), a laptop (100_1c), a TV (100_1d), and a desktop monitor (100_1e).

[0232] The smartphone (100_1a) may include an input module, such as a touch sensor, and a communication module in addition to the display module (110). The smartphone (100_1a) may process information received through the communication module or other input modules and display information through the display module of the display panel.

[0233] In the case of a tablet PC (100_1b), laptop (100_1c), TV (100_1d), and desktop monitor (100_1e), it also includes a display module and an input module similar to a smartphone (100_1a), and may additionally include a communication module depending on the case.

[0234] FIG. 17 illustrates a case where an electronic device including a display module is applied to a wearable electronic device. The wearable electronic device may be smart glasses (100_2a), a head-mounted display (100_2b), a smart watch (100_2c), etc.

[0235] The smart glasses (100_2a) and the head-mounted display (100_2b) may include a display module that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing the user with a virtual reality or augmented reality screen.

[0236] The smart watch (100_2c) includes a bio-sensor as an input device and can provide bio-information recognized through the bio-sensor to the user through a display module.

[0237] FIG. 18 illustrates a case where an electronic device including a display module is applied to a vehicle. For example, the electronic device (100_3) may be applied to the instrument panel, center fascia, etc. of a vehicle, or may be applied to a Center Information Display (CID) placed on the dashboard of a vehicle or a room mirror display that replaces a side mirror.

[0238] Although not illustrated, electronic devices to which display panels according to the embodiments are applied may include not only devices primarily focused on screen display, such as billboards, electronic display boards, and game consoles, but also various home appliances that display information through display modules, such as refrigerators, washing machines, dryers, air conditioners, and robot vacuum cleaners. Additionally, if the display module has a function of transmitting light, it may be applied to electronic devices such as smart windows or transparent display panels that display both a background and a display image. The types of electronic devices according to the embodiments are not limited to those exemplified above, and application to various other electronic devices not exemplified may also be possible.

[0239] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0240] 1: Panel CLD3: Third cladding layer 10: First substrate CM1: First upper connecting electrode 100: Electronic device CM2: Second upper connecting electrode 110: Display module CM3: Third upper connecting electrode 120: Processor DL1: 1st data line 130: Memory DL2: 2nd data line 140: Power module DL3: 3rd data line 150: Input Module ED11-1: 1st Border 160: Non-video output module ED11-2: Second Border 170: Communication module ED12-1: Third Border 2: Color Panel ED12-2: 4th Border A11: First driving semiconductor layer ED13-1: 5th Border A21: Second driving semiconductor layer ED13-2: 6th Border A31: Third driving semiconductor layer G11: First driving gate electrode CLD1: First cladding layer G21: Second driving gate electrode CLD2: Second cladding layer G31: Third driving gate electrode

Claims

Claim 1 A display panel comprising: a substrate; a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode; and a cladding layer which overlaps with at least a portion of the edge region of the semiconductor layer, is an oxide semiconductor, and has a mobility smaller than that of a portion of the semiconductor layer. Claim 2 In claim 1, the semiconductor layer is a display panel having a crystalline or amorphous structure. Claim 3 In claim 1, the cladding layer is disposed on a part of the edge of the semiconductor layer on a flat surface and shields a part of the edge of the semiconductor layer, forming a display panel. Claim 4 In claim 1, the cladding layer is disposed on a flat surface below a portion of the edge of the semiconductor layer and overlaps with a portion of the edge of the semiconductor layer, forming a display panel. Claim 5 A display panel further comprising, in claim 1, an insulating layer disposed between the semiconductor layer and the gate electrode. Claim 6 In claim 1, two cladding layers are arranged spaced apart from each other at both ends of the semiconductor layer, and the gate electrode on a plane is a display panel arranged between the spaced-apart cladding layers. Claim 7 A display panel according to claim 1, further comprising an additional gate electrode disposed between the semiconductor layer and the substrate, wherein two cladding layers are disposed spaced apart from each other at both ends of the semiconductor layer, and the gap between the cladding layers spaced apart in one direction is greater than the width of the additional gate electrode in one direction. Claim 8 In claim 1, the cladding layer or the semiconductor layer comprises at least one groove in the display panel. Claim 9 A method for manufacturing a display panel comprising: a step of forming a semiconductor layer, which is an oxide semiconductor, on a substrate; a step of arranging a cladding layer, which is an oxide semiconductor and has a mobility smaller than that of a portion of the semiconductor layer, on the substrate in a planar manner so as to overlap with a portion of the semiconductor layer; a step of arranging a gate electrode on the semiconductor layer; a step of arranging an upper insulating layer to shield the gate electrode, the cladding layer, and the semiconductor layer; and a step of forming a contact hole in the upper insulating layer. Claim 10 A method for manufacturing a display panel according to claim 9, further comprising the step of arranging the cladding layer on the semiconductor layer to shield a portion of the edge of the semiconductor layer on a flat surface. Claim 11 A method for manufacturing a display panel according to claim 9, further comprising the step of arranging the cladding layer such that a portion of the edge of the semiconductor layer is disposed on the cladding layer in a planar plane. Claim 12 A method for manufacturing a display panel, further comprising the step of forming at least one groove in the cladding layer or the semiconductor layer in claim 9. Claim 13 A method for manufacturing a display panel, further comprising the step of applying heat to the semiconductor layer or the cladding layer in claim 9. Claim 14 A method for manufacturing a display panel according to claim 9, further comprising the step of arranging two cladding layers spaced apart from each other at both ends of the semiconductor layer, wherein the gate electrodes are arranged between the spaced-apart cladding layers on a plane. Claim 15 A method for manufacturing a display panel according to claim 9, further comprising the step of arranging an additional gate electrode disposed between the semiconductor layer and the substrate; wherein two cladding layers are disposed spaced apart from each other at both ends of the semiconductor layer, and the gap between the cladding layers spaced apart in one direction is greater than the width of the additional gate electrode in one direction. Claim 16 An electronic device comprising: a display panel; and a processor connected to the display panel to control the display panel; wherein the display panel comprises: a substrate; a transistor disposed on the substrate and comprising a semiconductor layer which is an oxide semiconductor and a gate electrode; and a cladding layer which overlaps with at least a portion of the edge region of the semiconductor layer, is an oxide semiconductor, and has a mobility smaller than that of a portion of the semiconductor layer. Claim 17 In claim 16, the electronic device wherein the semiconductor layer has a crystalline or amorphous structure. Claim 18 An electronic device according to claim 16, wherein the cladding layer is disposed on a portion of the edge of the semiconductor layer in a planar manner to shield a portion of the edge of the semiconductor layer. Claim 19 An electronic device according to claim 16, wherein the cladding layer is disposed on a plane below a portion of the edge of the semiconductor layer and overlaps with a portion of the edge of the semiconductor layer. Claim 20 An electronic device according to claim 16, wherein the display panel further comprises an additional gate electrode disposed between the semiconductor layer and the substrate, and two cladding layers disposed spaced apart from each other at both ends of the semiconductor layer, and the gap between the cladding layers spaced apart in one direction is greater than the width of the additional gate electrode in one direction.

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