Semiconductor memory devices

Abstract

A semiconductor memory device comprises a memory cell array, an on-die error correction code (hereinafter 'ECC') engine, a link ECC engine, and a control logic circuit. The control logic circuit controls the on-die ECC engine and the link ECC engine. In a write operation, the link ECC engine receives a first codeword containing first main data and first link parity data from an external memory controller, generates a first syndrome containing a plurality of syndrome bits based on a first parity check matrix based on the first ECC and the first codeword, generates a decoding status flag indicating whether an error occurred during the transmission of the first codeword is detected using the characteristics of the first syndrome based on the regularity of the first parity check matrix while decoding the first syndrome, corrects the error bits of the first codeword based on the decoded first syndrome, and provides the first main data of the corrected first codeword to the on-die ECC engine. The above-described on-die ECC engine generates parity data by performing a first ECC encoding on the first main data based on the second ECC, and stores the first main data and the parity data in the target page of the memory cell array.

Description

Technology Field

[0001] The present invention relates to the field of memory, and more specifically to a semiconductor memory device. Background Technology

[0002] Volatile memory devices such as DRAM are used to store large amounts of data, such as in system memory, due to their relatively low cost. Furthermore, process scales are being reduced in volatile semiconductor memory devices like DRAM to increase integration density. As process scales are reduced, it is expected that the bit error rate will increase sharply and yields will decrease.

[0003] Recently, DRAM includes an Error Correction Code (ECC) engine to improve data reliability. The ECC engine can correct errors in the data. DRAM can provide the decoding result of the ECC engine to an external device (e.g., a memory controller) as a decoding status flag. The problem to be solved

[0004] The objective of the present invention is to provide a semiconductor memory device capable of generating a decoding status flag while reducing decoding latency. means of solving the problem

[0005] A semiconductor memory device according to embodiments of the present invention for achieving the above-mentioned objective includes a memory cell array, an on-die error correction code (hereinafter 'ECC') engine, a link ECC engine, and a control logic circuit. The memory cell array includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The control logic circuit controls the on-die ECC engine and the link ECC engine. In a write operation, the link ECC engine receives a first codeword containing first main data and first link parity data from an external memory controller, generates a first syndrome containing a plurality of syndrome bits based on a first parity check matrix based on the first ECC and the first codeword, generates a decoding status flag indicating whether an error occurred during the transmission of the first codeword is detected by utilizing the characteristics of the first syndrome based on the regularity of the first parity check matrix while decoding the first syndrome, corrects the error bits of the first codeword based on the decoded first syndrome, and provides the first main data of the corrected first codeword to the on-die ECC engine. The on-die ECC engine generates parity data by performing first ECC encoding on the first main data based on the second ECC, and stores the first main data and the parity data in the target page of the memory cell array.

[0006] A semiconductor memory device according to embodiments of the present invention comprises a memory cell array, an on-die error correction code (hereinafter 'ECC') engine, a link ECC engine, and a control logic circuit. The memory cell array comprises a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The control logic circuit controls the on-die ECC engine and the link ECC engine. In a write operation, the link ECC engine receives a first codeword including a first main data and a first link parity data from an external memory controller, performs a first ECC decoding on the first codeword based on the first ECC to correct an error bit that occurred during the transmission of the first codeword, and provides the first main data of the corrected first codeword to the on-die ECC engine. The on-die ECC engine generates parity data by performing a first ECC encoding on the first main data based on the second ECC, stores the first main data and the parity data in a target page of the memory cell array, and in a read operation, the on-die ECC engine generates a syndrome including a plurality of syndrome bits based on the first main data, the parity data, and a parity check matrix based on the second ECC read from the target page, generates a decoding status flag indicating whether an error in the read first main data and the parity data is detected using the characteristics of the syndrome based on the regularity of the parity check matrix while decoding the syndrome, corrects the error bits of the first main data based on the decoded syndrome to generate the second main data, and provides the second main data to the link ECC engine.

[0007] A semiconductor memory device according to embodiments of the present invention comprises a memory cell array, an error correction code (hereinafter 'ECC') engine, and a control logic circuit. The memory cell array comprises a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines. The control logic circuit controls the ECC engine. In a write operation, the ECC engine receives a first main data from an external memory controller, performs ECC encoding on the first main data based on ECC to generate parity data, and stores the main data and the parity data in a target page of the memory cell array. The ECC engine reads the first main data and the parity data from the target page during a read operation, generates a syndrome including a plurality of syndrome bits based on the read first main data, the parity data, and a parity check matrix based on the ECC, generates a decoding status flag indicating whether an error in the read first main data and the parity data is detected using the characteristics of the syndrome based on the regularity of the parity check matrix while decoding the syndrome, corrects the error bits of the first main data based on the decoded syndrome to generate the second main data, and transmits the second main data to the memory controller.

[0008] In a method of operation of a semiconductor memory device (200) comprising a memory cell array, an on-die error correction code (hereinafter 'ECC') engine, and a link ECC engine according to embodiments of the present invention, the link ECC engine receives main data and link parity data from a memory controller, and the link ECC decoder of the link ECC engine generates a syndrome based on the main data, the link parity data, and a parity check matrix, and the link ECC decoder corrects correctable error bits of the main data based on the syndrome, and generates a decoding status flag indicating whether an error is detected in the main data or the link parity data using the syndrome. The link ECC decoder provides the main data with the error bits corrected to the on-die ECC engine, and the on-die ECC engine generates parity data based on the main data and stores the main data and the parity data in a target page of the memory cell array. Effects of the invention

[0009] In a semiconductor memory device according to embodiments of the present invention, the link ECC engine can generate a syndrome, divide the syndrome bits of the syndrome into a plurality of sets in parallel with decoding the syndrome, generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generate a decoding status flag based on the counting values. Accordingly, since the decoding status flag is not generated using the result of syndrome decoding, the decoding latency can be reduced and the circuit area of ​​the ECC decoder can be reduced. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 2 is a block diagram showing a memory controller in the memory system of FIG. 1 according to embodiments of the present invention. FIG. 3 shows a data set corresponding to a plurality of burst lengths provided to or output from a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention. FIG. 4 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention. FIG. 5 shows a first bank array in the semiconductor memory device of FIG. 4 according to embodiments of the present invention. FIG. 6 is a block diagram showing a link ECC engine and an on-die ECC engine in a semiconductor memory device of FIG. 4 according to embodiments of the present invention. FIG. 7 is a block diagram showing a link ECC decoder in the link ECC engine of FIG. 6 according to embodiments of the present invention. FIG. 8 is a block diagram showing a link ECC encoder in the link ECC engine of FIG. 6 according to embodiments of the present invention. FIG. 9 shows a parity check matrix used in the link ECC engine of FIG. 6 according to embodiments of the present invention. FIG. 10 shows an example of the parity check matrix of FIG. 9 according to embodiments of the present invention. FIGS. 11a to 11l show a plurality of code groups of the parity check matrix of FIG. 10 according to embodiments of the present invention. FIG. 12a shows one of the column vectors in FIG. 11a to FIG. 11l. FIG. 12b shows one of the column vectors in FIG. 11a to FIG. 11l. FIG. 13a is a block diagram showing the configuration of the decoding status flag generator of FIG. 7 according to embodiments of the present invention. FIG. 13b is a block diagram showing the configuration of the decoding status flag generator of FIG. 7 according to embodiments of the present invention. FIG. 14 shows the encoding / decoding logic in the on-die ECC engine of FIG. 6 according to embodiments of the present invention. FIG. 15 shows the configuration of a data corrector in the on-die ECC engine of FIG. 6 according to embodiments of the present invention. FIG. 16 shows a part of the semiconductor memory device of FIG. 4 according to embodiments of the present invention. FIG. 17 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention. FIG. 18 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 19 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 18 according to embodiments of the present invention. FIG. 20 is a block diagram showing a link ECC engine and an on-die ECC engine in the semiconductor memory device of FIG. 19 according to embodiments of the present invention. FIG. 21 is a block diagram showing an ECC decoder in the on-die ECC engine of FIG. 20 according to embodiments of the present invention. FIG. 22 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention. FIG. 23 is a block diagram showing a memory system according to embodiments of the present invention. FIG. 24 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 23 according to embodiments of the present invention. FIG. 25 is a block diagram showing an ECC engine in the semiconductor memory device of FIG. 24 according to embodiments of the present invention. FIG. 26 is a block diagram showing an ECC decoder in the ECC engine of FIG. 24 according to embodiments of the present invention. FIG. 27 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention. FIG. 28 is an exemplary block diagram showing a semiconductor memory device according to embodiments of the present invention. FIG. 29 is a structural diagram showing an example of a semiconductor package including a stacked memory device according to embodiments of the present invention. Specific details for implementing the invention

[0011] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0012] FIG. 1 is a block diagram showing a memory system according to embodiments of the present invention.

[0013] Referring to FIG. 1, the memory system (20) may include a memory controller (100) and a semiconductor memory device (200).

[0014] A memory controller (100) generally controls the operation of a memory system (20) and controls the overall data exchange between an external host and a semiconductor memory device (200). For example, the memory controller (100) controls the semiconductor memory device (200) to write data or read data in response to a request from the host. Additionally, the memory controller (100) controls the operation of the semiconductor memory device (200) by applying operation commands to control the semiconductor memory device (200). The memory controller (100) may also be referred to as an external device.

[0015] According to an embodiment, the semiconductor memory device (200) may be a dynamic random access memory (DRAM) having volatile memory cells, or a low power (LP) DDR6 double data rate 6 SDRAM synchronous DRAM.

[0016] The memory controller (100) can transmit a command (CMD) and an address (ADDR) to a semiconductor memory device (200), transmit a clock signal (CK), transmit a codeword (CW) containing main data (MD) and link parity data (LPRT) to the semiconductor memory device (200), receive the codeword (CW) from the semiconductor memory device (200), and receive a decoding status flag (DSF) from the semiconductor memory device (200).

[0017] The memory controller (100) may include a central processing unit ('CPU', 110), and the central processing unit (110) may control the overall operation of the memory controller (100).

[0018] A semiconductor memory device (200) may include a memory cell array (310) in which main data (MD) is stored, an on-die ('OD') error correction code (hereinafter 'ECC') engine (400), a link ECC engine (500), and a control logic circuit (210).

[0019] The control logic circuit (210) controls access to the memory cell array (310) based on the command (CMD) and address (ADDR), and can control the on-die ECC engine (400) and the link ECC engine (500).

[0020] The link ECC engine (500) receives a codeword (CW) in a write operation based on a write command from the memory controller (100), generates a first syndrome including a plurality of syndrome bits based on the codeword (CW) and a first parity check matrix based on the first ECC, generates a decoding status flag (DSF1) indicating whether an error occurred during transmission of the first codeword is detected using the characteristics of the first syndrome based on the regularity of the first parity check matrix while decoding the first syndrome, corrects the error bits of the codeword (CW) based on the decoded first syndrome, provides the main data of the corrected codeword to the on-die ECC engine (400), and transmits the decoding status flag (DSF1) to the memory controller (100).

[0021] The on-die ECC engine (400) can generate parity data by performing a first ECC encoding on the main data based on the second ECC, and store the main data and the parity data in a target page of the memory cell array (310).

[0022] Therefore, the link ECC engine (500) generates a decoding status flag (DSF1) using only the syndrome, so the ECC decoding latency and the occupied area of ​​the related circuit can be reduced.

[0023] FIG. 2 is a block diagram showing a memory controller in the memory system of FIG. 1 according to embodiments of the present invention.

[0024] Referring to FIG. 2, the memory controller (100) may include a CPU (110), a data buffer (120), a link parity generator (130), a codeword generator (140), a system ECC decoder (150), a flag buffer (160), a command buffer (190), and an address buffer (195).

[0025] The CPU (110) receives a request (REQ) and data (DTA) from a host and provides the data (DTA) to a data buffer (120). The CPU (110) can control the data buffer (120), a link parity generator (130), a codeword generator (140), a system ECC decoder (150), a flag buffer (160), a command buffer (190), and an address buffer (195).

[0026] The data buffer (120) can buffer data (DTA) to provide main data (MD) to the codeword generator (140). The main data (MD) may include normal data (ND) and metadata (MT).

[0027] The link parity generator (130) can generate a first link parity data (LPRT11) based on the main data (MD) and provide the first link parity data (LPRT11) to the codeword generator (140). The codeword generator (140) can generate a first codeword (CW11) including the first main data (MD11) corresponding to the main data (MD) and the first link parity data (LPRT11), and transmit the first codeword (CW11) to the semiconductor memory device (200).

[0028] The system ECC decoder (150) receives a second codeword (CW12) including second main data (MD12) and second link parity data (LPRT12) from the semiconductor memory device (100) during a read operation for the semiconductor memory device (200), performs ECC decoding on the second codeword (CW12) to correct error bits of the second main data (MD12), and can provide the corrected main data (C_MD) to the CPU (110).

[0029] The flag buffer (160) receives a decoding status flag (DSF1) from the semiconductor memory device (200) and can provide the decoding status flag (DSF1) to the CPU (110). The CPU (110) can determine whether an uncorrectable error has occurred in the first codeword (CW11) transmitted to the semiconductor memory device (200) based on the logic level of the decoding status flag (DSF1).

[0030] The command buffer (190) stores a command (CMD) corresponding to a request (REQ) and transmits the command (CMD) to a semiconductor memory device (200) under the control of the CPU (110), and the address buffer (195) stores an address (ADDR) and transmits the address (ADDR) to a semiconductor memory device (200) under the control of the central processing unit (110).

[0031] FIG. 3 shows a data set corresponding to a plurality of burst lengths provided to or output from a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention.

[0032] Referring to FIG. 3, a data set (DQ_BL) corresponding to a plurality of burst lengths is input / output to / from each of the semiconductor memory devices (200). The data set (DQ_BL) may include data segments (DQ_BL_SG1 to DQ_BL_SGk, where k is a natural number greater than or equal to 4) corresponding to each of the plurality of burst lengths. That is, the data set (DQ_BL) corresponding to a plurality of burst lengths may be stored in the memory cell array (310) of the semiconductor memory device (200). The data set (DQ_BL) may include main data (MD) and rock parity data (LPRT).

[0033] FIG. 4 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 1 according to embodiments of the present invention.

[0034] Referring to FIG. 4, the semiconductor memory device (200) may include a control logic circuit (210), an address register (220), bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (310), a sense amplifier (285), an input / output gating circuit (290), an on-die ECC engine (400), a clock buffer (225), a strobe signal generator (235), and a link ECC engine (500).

[0035] The memory cell array (310) may include first to 16 bank arrays (310a to 310p). Additionally, the row decoder (260) may include first to 16 row decoders (260a to 260p) each connected to the first to 16 bank arrays (310a to 310p), the column decoder (270) may include first to 16 column decoders (270a to 270p) each connected to the first to 16 bank arrays (310a to 310p), and the sensing amplifier (285) may include first to 16 sensing amplifiers (285a to 285p) each connected to the first to 16 bank arrays (310a to 310p).

[0036] The first to 16 bank arrays (310a to 310p), the first to 16 sense amplifiers (285a to 285p), the first to 16 column decoders (270a to 270p), and the first to 16 row decoders (260a to 260p) may each constitute the first to 16 banks. Each of the first to 16 bank arrays (310a to 310p) may include a plurality of word lines (WL), a plurality of bit lines (BTL), and a plurality of memory cells (MC) formed at the intersection of the word lines (WL) and the bit lines (BTL).

[0037] The address register (220) can receive an address (ADDR) including a bank address (BANK_ADDR), a row address (ROW_ADDR), and a column address (COL_ADDR) from the memory controller (100). The address register (220) can provide the received bank address (BANK_ADDR) to the bank control logic (230), provide the received row address (ROW_ADDR) to the row address multiplexer (240), and provide the received column address (COL_ADDR) to the column address latch (250).

[0038] The bank control logic (230) can generate bank control signals in response to the bank address (BANK_ADDR). In response to the bank control signals, a row decoder corresponding to the bank address (BANK_ADDR) among the first to 16 row decoders (260a to 260p) can be activated, and a column decoder corresponding to the bank address (BANK_ADDR) among the first to 16 column decoders (270a to 270p) can be activated.

[0039] The row address multiplexer (240) can receive a row address (ROW_ADDR) from the address register (220) and a refresh row address (REF_ADDR) from the refresh counter (245). The row address multiplexer (240) can optionally output the row address (ROW_ADDR) or the refresh row address (REF_ADDR) as a row address (SRA). The row address (SRA) output from the row address multiplexer (240) can be applied to the first to sixth row decoders (260a to 260p), respectively.

[0040] The refresh counter (245) can sequentially increase or decrease the refresh row address (REF_ADDR) in control of the control logic circuit (210).

[0041] Among the first to 16th row decoders (260a to 260p), the row decoder activated by the bank control logic (230) can decode the row address (SRA) output from the row address multiplexer (240) and activate the word line corresponding to the row address (SRA). For example, the activated row decoder can apply a word line driving voltage to the word line corresponding to the row address (SRA).

[0042] The column address latch (250) receives a column address (COL_ADDR) from the address register (220) and can temporarily store the received column address (COL_ADDR). Additionally, the column address latch (250) can gradually increase the received column address (COL_ADDR) in burst mode. The column address latch (250) can apply the temporarily stored or gradually increased column address (COL_ADDR') to the first to sixth column decoders (270a to 270p), respectively.

[0043] Among the first to 16th column decoders (270a to 270p), the column decoder activated by the bank control logic (230) can activate a sensing amplifier corresponding to the bank address (BANK_ADDR) and the column address (COL_ADDR) through the corresponding input / output gating circuit (290).

[0044] The input / output gating circuit (290) may include, together with circuits for gating input / output data, input data mask logic, read-out data latches for storing codewords output from the first to 16 bank arrays (310a to 310p), and write drivers for writing data to the first to 16 bank arrays (310a to 310p).

[0045] In a read operation, a codeword (CW2) read from one of the first to 16 bank arrays (310a to 310p) is detected by a detection amplifier corresponding to the one bank array and can be stored in the read data latches. The codeword (CW2) stored in the read data latches is ECC decoded by an on-die ECC engine (400) and provided to a link ECC engine (500) as main data (MD1), and the link ECC engine (500) performs ECC encoding on the main data (MD1) to generate link parity data (LPRT1), and can transmit the codeword (CW1) containing the main data (MD1) and the link parity data (LPRT1) to a memory controller (100).

[0046] In a write operation, a codeword (CW1) containing main data (MD1) and link parity data (LPRT1) to be written to one of the first to 16 bank arrays (310a to 310p) is received by the link ECC engine (500). The link ECC engine (500) performs ECC decoding on the main data (MD1) based on the link parity data (LPRT1) to correct at least one error bit that occurred during transmission and provides the main data (MD1) to the on-die ECC engine (400). The on-die ECC engine (400) generates parity bits (or parity data) based on the main data (MD1) and can provide a codeword (CW2) containing the main data (MD1) and the parity bits to the input / output gating circuit (290). The input / output gating circuit (290) can write the codeword (CW2) to the target page of the one bank array through the write drivers.

[0047] The link ECC engine (500), in performing the ECC decoding during the write operation, generates a first syndrome including a plurality of syndrome bits based on a first parity check matrix based on the first ECC and a codeword (CW1), and while decoding the first syndrome, generates a decoding status flag (DSF1) indicating whether an error occurred during the transmission of the codeword (CW1) is detected using the characteristics of the first syndrome based on the regularity of the first parity check matrix, generates an error type signal (EKS1) indicating the type of error that occurred during the transmission, corrects the error bits of the codeword (CW1) based on the decoded first syndrome, provides the main data of the corrected codeword to the on-die ECC engine (400), transmits the decoding status flag (DSF1) to the memory controller (100) through the alert pin (201), and controls the error type signal (EKS1) to the control logic It can be provided to the circuit (210).

[0048] The on-die ECC engine (400) can perform ECC encoding for the main data (MD1) in a write operation and ECC decoding for the codeword (CW2) in a read operation based on a second control signal (CTL2) from the control logic circuit (210).

[0049] The clock buffer (225) receives a clock signal (CK), buffers the clock signal (CK) to generate an internal clock signal (ICK), and the internal clock signal (ICK) can be provided to components that process a command (CMD) and an address (ADDR).

[0050] The control logic circuit (210) can control the operation of the semiconductor memory device (200). For example, the control logic circuit (210) can generate control signals to cause the semiconductor memory device (200) to perform a write operation, a read operation, or a refresh operation. The control logic circuit (210) may include a command decoder (211) that decodes a command (CMD) received from the memory controller (100) and a mode register (212) for setting the operation mode of the semiconductor memory device (200).

[0051] For example, the command decoder (211) can decode the chip select signal and the command / address signal, etc., to generate the control signals corresponding to the command (CMD). In particular, the control logic circuit (210) can decode the command (CMD) to generate a first control signal (CTL1) for controlling the input / output gating circuit (290), a second control signal (CTL2) for controlling the on-die ECC engine (400), and a third control signal (CTL3) for controlling the link ECC engine (500).

[0052] FIG. 5 shows a first bank array in the semiconductor memory device of FIG. 4 according to embodiments of the present invention.

[0053] Referring to FIG. 5, the first bank array (310a) includes a plurality of word lines (WL0 to WLm-1, where m is an even integer greater than or equal to 2), a plurality of bit lines (BL0 to BLn-1, where n is an even integer greater than or equal to 2), and a plurality of memory cells (MCs) placed at the intersection between the word lines (WL0 to WLm-1) and the bit lines (BL0 to BLn-1).

[0054] Word lines (WL0~WLm-1) can be extended in a first direction (DR1), and bit lines (BL0~BLn-1) can be extended in a second direction (DR2).

[0055] Each memory cell (MC) has a DRAM cell structure. Additionally, it can be seen that the arrangement of memory cells (MCs) connected to each even word line (WL0) and each odd word line (WL1) is different. Each memory cell (MC) may include a cell transistor connected to each word line (WL0~WLm-1) and each bit line (BL0~BLn-1), and a cell capacitor connected to said cell transistor.

[0056] FIG. 6 is a block diagram showing a link ECC engine and an on-die ECC engine in a semiconductor memory device of FIG. 4 according to embodiments of the present invention.

[0057] Referring to FIG. 6, the link ECC engine (500) may include reordering logic (505), a link ECC decoder (520), a link ECC encoder (580), and a first memory (510). The first memory (510) may store a first ECC (ECC1).

[0058] The on-die ECC engine (400) may include a data selection circuit (410), encoding / decoding logic (440), a data corrector (470), and a buffer circuit (490).

[0059] The buffer circuit (490) may include buffers (491, 492, 493, 494). The buffers (491, 492, 493, 494) may be controlled by a buffer control signal (BCTL).

[0060] The reordering logic (505) can generate a first intermediate codeword (CW11') by reordering the data bits and link parity bits of a first codeword (CW11) including the first main data (MD11) and the first link parity data (LPRT11) in a write operation, and provide the first intermediate codeword (CW11') to a link ECC decoder (520).

[0061] A link ECC decoder (510) receives a first intermediate codeword (CW11'), generates a first syndrome including a plurality of syndrome bits based on a first parity check matrix based on the first ECC (ECC1) and the first intermediate codeword (CW11'), and while decoding the first syndrome, generates a decoding status flag (DSF1) indicating whether an error occurred during transmission of the first codeword (CW11) is detected using the characteristics of the first syndrome based on the regularity of the first parity check matrix, corrects the error bits of the first codeword (CW11) based on the decoded first syndrome, provides the main data (MD11) of the corrected codeword to an on-die ECC engine (400), and transmits the decoding status flag (DSF1) to a memory controller (100).

[0062] The link ECC decoder (510) can divide the plurality of syndrome bits into a plurality of sets, generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generate a decoding status flag (DSF1) based on the counting values.

[0063] The path selection circuit (299a) can provide the second test data (TD2) to the latch (495) in test mode in response to the first selection signal (SS1), and provide the main data (MD) to the data selection circuit (410) of the on-die ECC engine (400) and the buffer (491) of the buffer circuit (490) in normal mode.

[0064] Buffer (491) can receive main data (MD11) from the link ECC decoder (520) during a write operation and provide the main data (MD11) to the memory cell array (310). Buffer (492) can receive main data (MD11) from the memory cell array (310) during a read operation and provide the main data (MD11) to the data selection circuit (410) and the data corrector (470).

[0065] In a write operation, the encoding / decoding logic (440) receives main data (MD11) from the link ECC decoder (520), performs a first ECC encoding on the main data (MD11) to generate parity data (PRT), and provides the parity data (PRT) to the memory cell array (310) through the buffer (493). In a read operation, the encoding / decoding logic (440) receives main data (MD11) from the data selection circuit (410), receives parity data (PRT) from the buffer (494), performs a second ECC decoding on the main data (MD11) using the parity data (PRT) to generate a syndrome (SDR2), and provides the syndrome (SDR2) to the data corrector (470).

[0066] In a read operation, the data corrector (470) receives the main data (MD11) and corrects one error bit of the main data (MD11) based on the syndrome (SDR2) to provide the second main data (MD12) to the link ECC encoder (570).

[0067] The data selector (410) can provide the first main data (MD11) provided from the link ECC decoder (520) to the encoding / decoding logic (440) during a write operation based on the selection signal (SS1), and provide the first main data (MD11) provided from the buffer (492) to the encoding / decoding logic (440) during a read operation.

[0068] In a read operation, the link ECC encoder (580) can generate a second link parity data (LPRT12) by performing a second ECC encoding on the second main data (MD12) based on the first ECC (ECC1), and transmit a second codeword (CW12) containing the second main data (MD12) and the second link parity data (LPRT12) to the memory controller (100).

[0069] FIG. 7 is a block diagram showing a link ECC decoder in the link ECC engine of FIG. 6 according to embodiments of the present invention.

[0070] Referring to FIG. 7, the link ECC decoder (520) may include a syndrome generator (530), a syndrome decoder (535), a data corrector (540), and a decoding status flag (DSF) generator (550).

[0071] The syndrome generator (530) can generate a first syndrome (SDR1) based on a first intermediate codeword (CW11') in which the data bits of the first codeword (CW11) and link parity bits are rearranged, and a parity check matrix (PCM). The syndrome generator (530) can generate a first syndrome (SDR1) by performing matrix multiplication operations on the first intermediate codeword (CW11') and the parity check matrix (PCM).

[0072] The syndrome decoder (535) can decode the first syndrome (SDR1) and provide a decoding signal (DS1) to the data corrector (540) indicating the location where an error occurred in the first main data (MD11) of the first codeword (CW11).

[0073] The data corrector (540) can correct a correctable error in the first main data (MD11') of the first intermediate codeword (CW11') based on the decoding signal (DS1) and output the corrected first main data (MD11). That is, the data corrector (540) can provide the corrected first main data (MD11) to the on-die ECC engine (400).

[0074] The decoding status flag generator (550) can generate a decoding status flag (DSF1) and an error type signal (EKS1) based on the first syndrome (SDR1) in parallel with the operation of the syndrome decoder (535), transmit the decoding status flag (DSF1) to the memory controller (100), and provide the error type signal (EKS1) to the control logic circuit (210). The decoding status flag generator (550) can divide a plurality of syndrome bits of the first syndrome (SDR1) into a plurality of sets, generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generate a decoding status flag (DSF1) based on the counting values.

[0075] FIG. 8 is a block diagram showing a link ECC encoder in the link ECC engine of FIG. 6 according to embodiments of the present invention.

[0076] Referring to FIG. 8, the link ECC encoder (580) may include a link parity generator (585) and a codeword generator (590).

[0077] The link parity generator (585) receives the second main data (MD12) from the on-die ECC engine (400) of FIG. 6, generates the second link parity data (LPRT12) based on the second main data (MD12) and the parity generation matrix (PGM) based on the first ECC (ECC1), and can provide the second link parity data (LPRT12) to the codeword generator (590). The link parity generator (585) can generate the second link parity data (LPRT12) by performing matrix multiplication operations on the second main data (MD12) and the parity generation matrix (PGM).

[0078] The codeword generator (590) receives the second main data (MD12) and the second link parity data (LPRT12), generates a second codeword (CW12) containing the second main data (MD12) and the second link parity data (LPRT12), and can transmit the second codeword (CW12) to the memory controller (100).

[0079] FIG. 9 shows a parity check matrix used in the link ECC engine of FIG. 6 according to embodiments of the present invention.

[0080] In FIG. 9, it is assumed that the first intermediate codeword (CW11') includes a plurality of sub-data units (SUB1 to SUBx, where x is a natural number greater than or equal to 12).

[0081] Referring to FIG. 9, the parity check matrix (PCMa) based on the first ECC (ECC1) can be divided into multiple code groups (CG1~CGx) corresponding to sub-data units (SUB1~SUBx).

[0082] FIG. 10 shows an example of the parity check matrix of FIG. 9 according to embodiments of the present invention.

[0083] Referring to FIG. 10, the data bits and link parity bits of the first intermediate codeword (CW11') are divided into a plurality of sub-data units (SDU1, SDU2, SDU3, SDU4, …, SDU12), and the parity check matrix (PCM) may include a plurality of code groups (CG1, CG2, CG3, CG4, …, CG12) corresponding to the plurality of sub-data units (SDU1, SDU2, SDU3, SDU4, …, SDU12).

[0084] FIGS. 11a to 11l show a plurality of code groups of the parity check matrix of FIG. 10 according to embodiments of the present invention.

[0085] In FIGS. 11a to 11l, it is assumed that the main data (MD11) of the first intermediate codeword (CW11') includes 256-bit data bits (d0 to d255) and 16-bit data bits (M0 to M15), and the first link parity data (LPRT11) includes link parity bits (L0 to L15). In FIGS. 11a to 11l, for convenience of explanation, the syndrome bits (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15) of the first syndrome (SDR1) are shown together. Syndrome bits (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15) can be divided into multiple sets (SET1, SET2, SET3, SET4) of four each. Set (SET1) may include syndrome bits (S0, S1, S2, S3), Set (SET2) may include syndrome bits (S4, S5, S6, S7), Set (SET3) may include syndrome bits (S8, S9, S10, S11), and Set (SET4) may include syndrome bits (S12, S13, S14, S15).

[0086] Referring to FIG. 11a, the code group (CG1) of the parity check matrix (PCM) may include a plurality of column vectors (CV1_1 to CV1_24) corresponding to data bits (d0, d1, d2, d3, d48, d49, d50, d51, d96, d97, d98, d99, d128, d129, d130, d131, d176, d177, d178, d179, d224, d225, d226, d227). Each of the plurality of column vectors (CV1_1 to CV1_24) may include three elements having a logic high level. In FIG. 11a, the empty portions represent a logic low level ('0').

[0087] When the first syndrome (SDR1) matches one of the column vectors (CV1_1 to CV1_24) of the code group (CG1), there may be one set (SET1, SET2, SET3, SET4) in which the number of elements having a logic high level is 2, one set in which the number of elements having a logic high level is 1, and two sets in which the number of elements having a logic high level is 0 (sets containing elements having only a logic low level).

[0088] Referring to FIG. 11b, the code group (CG2) of the parity check matrix (PCM) may include a plurality of column vectors (CV2_1 to CV2_24) corresponding to data bits (d4, d5, d6, d7, d52, d53, d54, d55, d100, d101, d102, d103, d132, d133, d134, d135, d180, d181, d182, d183, d228, d229, d230, d231). Each of the plurality of column vectors (CV2_1 to CV2_24) may include three elements having a logic high level. In FIG. 11b, the empty portions represent a logic low level ('0').

[0089] When the first syndrome (SDR1) matches one of the column vectors (CV2_1 to CV2_24) of the code group (CG2), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0090] Referring to FIG. 11c, the code group (CG3) of the parity check matrix (PCM) may include a plurality of column vectors (CV3_1 to CV3_24) corresponding to data bits (d8, d9, d10, d11, d56, d57, d58, d59, d104, d105, d106, d107, d136, d137, d138, d139, d184, d185, d186, d187, d232, d233, d234, d235). Each of the plurality of column vectors (CV31 to CV324) may each contain three elements having a logic high level. In FIG. 11c, the empty portions represent a logic low level ('0').

[0091] When the first syndrome (SDR1) matches one of the column vectors (CV3_1~CV3_24) of the code group (CG3), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0092] Referring to FIG. 11c, the code group (CG3) of the parity check matrix (PCM) may include a plurality of column vectors (CV3_1 to CV3_24) corresponding to data bits (d8, d9, d10, d11, d56, d57, d58, d59, d104, d105, d106, d107, d136, d137, d138, d139, d184, d185, d186, d187, d232, d233, d234, d235). Each of the plurality of column vectors (CV3_1 to CV3_24) may include three elements having a logic high level. In FIG. 11c, the empty portions represent a logic low level ('0').

[0093] When the first syndrome (SDR1) matches one of the column vectors (CV3_1~CV3_24) of the code group (CG3), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0094] Referring to FIG. 11d, the code group (CG4) of the parity check matrix (PCM) may include a plurality of column vectors (CV4_1 to CV4_24) corresponding to data bits (d12, d13, d14, d15, d60, d61, d62, d63, d108, d109, d110, d111, d140, d141, d142, d143, d188, d189, d190, d191, d236, d237, d238, d239). Each of the plurality of column vectors (CV4_1 to CV4_24) may include three elements having a logic high level. In Fig. 11d, the empty part represents a logic low level ('0').

[0095] When the first syndrome (SDR1) matches one of the column vectors (CV4_1 to CV4_24) of the code group (CG4), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0096] Referring to FIG. 11e, the code group (CG5) of the parity check matrix (PCM) may include a plurality of column vectors (CV5_1~CV5_20) corresponding to data bits (d16, d17, d18, d19, d64, d65, d66, d67, M0, M1, M2, M3, d144, d145, d146, d147, d192, d193, d194, d195) and a plurality of column vectors (CV5_21~CV5_24) corresponding to link parity bits (L0, L1, L2, L3). Each of the multiple column vectors (CV5_1 to CV5_20) may each contain three elements having a logic high level, and each of the multiple column vectors (CV52_1 to CV5_24) may each contain one element having a logic high level. In FIG. 11e, the empty parts represent a logic low level ('0').

[0097] When the first syndrome (SDR1) matches one of the column vectors (CV5_1~CV5_20) of the code group (CG5), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level. Additionally, when the first syndrome (SDR1) matches one of the column vectors (CV5_21~CV5_24) of the code group (CG5), there may be one set (SET1, SET2, SET3, SET4) with 1 element having a logic high level, and three sets with 0 elements having a logic high level.

[0098] Referring to FIG. 11f, the code group (CG6) of the parity check matrix (PCM) may include a plurality of column vectors (CV6_1~CV6_20) corresponding to data bits (d20, d21, d22, d23, d68, d69, d70, d71, M4, M5, M6, M7, d148, d149, d150, d151, d196, d197, d198, d199) and a plurality of column vectors (CV6_21~CV6_24) corresponding to link parity bits (L4, L5, L6, L7). Each of the multiple column vectors (CV6_1 to CV6_20) may each contain three elements having a logic high level, and each of the multiple column vectors (CV6_21 to CV6_24) may each contain one element having a logic high level. In FIG. 11f, the empty parts represent a logic low level ('0').

[0099] When the first syndrome (SDR1) matches one of the column vectors (CV6_1 to CV6_20) of the code group (CG6), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level. Additionally, when the first syndrome (SDR1) matches one of the column vectors (CV6_21 to CV6_24) of the code group (CG6), there may be one set (SET1, SET2, SET3, SET4) with 1 element having a logic high level, and three sets with 0 elements having a logic high level.

[0100] Referring to FIG. 11g, the code group (CG7) of the parity check matrix (PCM) may include a plurality of column vectors (CV7_1 to CV7_24) corresponding to data bits (d24, d25, d26, d27, d72, d73, d74, d75, d112, d113, d114, d115, d152, d153, d154, d155, d200, d201, d202, d203, d240, d241, d242, d243). Each of the plurality of column vectors (CV7_1 to CV7_24) may include three elements having a logic high level. In Fig. 11g, the empty part represents a logic low level ('0').

[0101] When the first syndrome (SDR1) matches one of the column vectors (CV7_1 to CV7_24) of the code group (CG7), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0102] Referring to FIG. 11h, the code group (CG8) of the parity check matrix (PCM) may include a plurality of column vectors (CV8_1 to CV8_24) corresponding to data bits (d28, d29, d30, d31, d76, d77, d78, d79, d116, d117, d118, d119, d156, d157, d158, d159, d204, d205, d206, d207, d244, d245, d246, d247). Each of the plurality of column vectors (CV8_1 to CV8_24) may include three elements having a logic high level. In Fig. 11h, the empty part represents a logic low level ('0').

[0103] When the first syndrome (SDR1) matches one of the column vectors (CV8_1~CV8_24) of the code group (CG8), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0104] Referring to FIG. 11i, the code group (CG9) of the parity check matrix (PCM) may include a plurality of column vectors (CV9_1–CV9_24) corresponding to data bits (d32, d33, d34, d35, d80, d81, d82, d83, d120, d121, d122, d123, d160, d161, d162, d163, d208, d209, d210, d211, d248, d249, d250, d251). Each of the plurality of column vectors (CV91–CV924) may include three elements having a logic high level. In FIG. 11i, the empty portions represent a logic low level ('0').

[0105] When the first syndrome (SDR1) matches one of the column vectors (CV9_1~CV9_24) of the code group (CG9), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0106] Referring to FIG. 11j, the code group (CG10) of the parity check matrix (PCM) may include a plurality of column vectors (CV10_1 to CV10_24) corresponding to data bits (d36, d37, d38, d39, d83, d84, d85, d86, d124, d125, d126, d127, d164, d165, d166, d167, d212, d213, d214, d215, d252, d253, d254, d255). Each of the plurality of column vectors (CV10_1 to CV10_24) may include three elements having a logic high level. In Fig. 11j, the empty part represents the logic low level ('0').

[0107] When the first syndrome (SDR1) matches one of the column vectors (CV10_1 to CV10_24) of the code group (CG10), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level.

[0108] Referring to FIG. 11k, the code group (CG11) of the parity check matrix (PCM) may include a plurality of column vectors (CV11_1~CV11_20) corresponding to data bits (d40, d41, d42, d43, d88, d89, d90, d91, M8, M9, M10, M11, d168, d169, d170, d171, d216, d217, d218, d219) and a plurality of column vectors (CV11_21~CV11_24) corresponding to link parity bits (L8, L9, L10, L11). Each of the multiple column vectors (CV11_1 to CV11_20) may each contain three elements having a logic high level, and each of the multiple column vectors (CV11_21 to CV11_24) may each contain one element having a logic high level. In Fig. 11k, the empty parts represent a logic low level ('0').

[0109] When the first syndrome (SDR1) matches one of the column vectors (CV11_1~CV11_20) of the code group (CG11), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level. Additionally, when the first syndrome (SDR1) matches one of the column vectors (CV11_21~CV11_24) of the code group (CG11), there may be one set (SET1, SET2, SET3, SET4) with 1 element having a logic high level, and three sets with 0 elements having a logic high level.

[0110] Referring to FIG. 11, the code group (CG12) of the parity check matrix (PCM) may include a plurality of column vectors (CV12_1~CV12_20) corresponding to data bits (d44, d45, d46, d47, d92, d93, d94, d95, M12, M13, M14, M15, d172, d173, d174, d175, d220, d221, d222, d223) and a plurality of column vectors (CV12_21~CV12_24) corresponding to link parity bits (L12, L13, L14, L15). Each of the multiple column vectors (CV12_1 to CV12_20) may each contain three elements having a logic high level, and each of the multiple column vectors (CV12_21 to CV12_24) may each contain one element having a logic high level. In Fig. 11k, the empty parts represent a logic low level ('0').

[0111] When the first syndrome (SDR1) matches one of the column vectors (CV12_1~CV12_20) of the code group (CG12), there may be one set (SET1, SET2, SET3, SET4) with 2 elements having a logic high level, one set with 1 element having a logic high level, and two sets with 0 elements having a logic high level. Additionally, when the first syndrome (SDR1) matches one of the column vectors (CV12_21~CV12_24) of the code group (CG12), there may be one set (SET1, SET2, SET3, SET4) with 1 element having a logic high level, and three sets with 0 elements having a logic high level.

[0112] In FIGS. 11a to 11l, the column vectors corresponding to the data bits (d0 to d255, M0 to M15) may be referred to as the column vectors of the first part, and the column vectors corresponding to the link parity bits (L0 to L15) may be referred to as the column vectors of the second part. In each of the column vectors of the first part, the number of elements having a logic high level corresponds to a first value (e.g., 3), and in each of the column vectors of the second part, the number of elements having a logic high level corresponds to a second value (e.g., 1) which is smaller than the first value.

[0113] If a correctable error occurs in the first main data (MD11), the first syndrome (SDR1) may match one of the column vectors of the first part, and if an error occurs in the first link parity data (LPRT11), the first syndrome (SDR1) may match one of the column vectors of the first part, and if an uncorrectable error occurs in the first codeword (CW11), at least one of the syndrome bits of the first syndrome (SDR1) is not at a logic low level, and the first syndrome (SDR1) does not match each of the column vectors of the parity check matrix (PCM).

[0114] As described with reference to FIGS. 11a to 11i, since the arrangement of column vectors of the parity check matrix (PCM) has a certain regularity, the decoding status flag (550) of the link ECC decoder (520) can determine whether an error occurred during transmission and the type of error that occurred during transmission based on a first number of sets containing two syndrome bits having a logic high level in sets (SET1, SET2, SET3, SET4), a second number of sets containing one syndrome bit having a logic high level, and a third number of sets containing four syndrome bits having a logic low level.

[0115] For example, in response to the third number being 4, the decoding status flag generator (550) of the link ECC decoder (520) can determine that no error occurred during transmission.

[0116] For example, in response to the third number being 3, the second number being 1, and the first number being zero, the decoding status flag generator (550) of the link ECC decoder (520) can determine that an error occurred during transmission in the first link parity data (LPRT11).

[0117] For example, in response to the third number being 2, the first number being 1, and the first number being 1, the decoding status flag generator (550) of the link ECC decoder (520) can determine that a correctable error occurred during transmission in the first main data (MD11).

[0118] For example, at least one of the syndrome bits (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15) is at a logic high level, and in response to the first syndrome (SDR1) not matching each of the column vectors of the parity check matrix (PCM), the decoding status flag generator (550) determines that an uncorrectable error has occurred in the first codeword (CW11) during transmission and can output a decoding status flag (DSF1) at a logic high level.

[0119] FIG. 12a shows one of the column vectors in FIG. 11a to FIG. 11l.

[0120] Referring to FIG. 12a, when the first syndrome (SDR1) matches the column vector (CV4_1), there is one first number of set (SET1) containing two syndrome bits having a logic high level in sets (SET1, SET2, SET3, SET4), one second number of set (SET2) containing one syndrome bit having a logic high level, and two third numbers of sets (SET3, SET4) containing four syndrome bits having a logic low level, so the decoding status flag generator (550) of the link ECC decoder (520) can determine that a correctable error has occurred in the first main data (MD11) during transmission.

[0121] FIG. 12b shows one of the column vectors in FIG. 11a to FIG. 11l.

[0122] Referring to FIG. 12b, when the first syndrome (SDR1) matches the column vector (CV5_21), the first number of sets (SET1, SET2, SET3, SET4) containing two syndrome bits having a logic high level is zero, the second number of sets (SET1) containing one syndrome bit having a logic high level is one, and the third number of sets (SET2, SET3, SET4) containing four syndrome bits having a logic low level is three, so the decoding status flag generator (550) of the link ECC decoder (520) can determine that an error occurred during transmission in the first link parity data (LPRT11).

[0123] As described above, the decoding status flag generator (550) can divide a plurality of syndrome bits (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15) of the first syndrome (SDR1) into a plurality of sets (SET1, SET2, SET3, SET4) in parallel with the operation of the syndrome decoder (535), generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets (SET1, SET2, SET3, SET4), and generate a decoding status flag (DSF1) based on the counting values. Therefore, since the decoding status flag (DSF1) is not generated using the result of syndrome decoding, the decoding latency can be reduced and the circuit area of ​​the link ECC decoder (520) can be reduced.

[0124] FIG. 13a is a block diagram showing the configuration of the decoding status flag generator of FIG. 7 according to embodiments of the present invention.

[0125] Referring to FIG. 13a, the decoding status flag generator (550a) may include a plurality of summing signal generators (551a, 551b, 551c, 551d) and a signal generator (565).

[0126] A summing signal generator (551a) can generate a summing signal (SUM21) indicating whether the set (SET1) contains two elements having a logic high level, a summing signal (SUM01) indicating whether the set (SET1) contains zero elements having a logic high level, and a summing signal (SUM11) indicating whether the set (SET1) contains one element having a logic high level, based on the syndrome bits (S0, S1, S2, S3) of the set (SET1).

[0127] The summing signal generator (551a) may include a plurality of NAND gates (552, 553, 554, 555, 556, 562), a plurality of NOR gates (557, 558, 559, 560), an inverter (561), and an exclusive NOR gate (563).

[0128] The NAND gate (552) can perform NAND operations on the syndrome bits (S0, S1). The NAND gate (553) can perform NAND operations on the syndrome bits (S1, S2). The NOR gate (557) can perform NOR operations on the syndrome bits (S0, S1). The NOR gate (558) can perform NOR operations on the syndrome bits (S2, S3).

[0129] The NAND gate (554) can perform NAND operations on the outputs of the NAND gates (552, 553). The NAND gate (555) can perform NAND operations on the outputs of the NOR gates (557, 558). The NOR gate (559) can perform NOR operations on the outputs of the NOR gates (557, 558).

[0130] The NAND gate (556) can perform NAND operations on the output of the NAND gate (554) and the output of the NOR gate (559). The NOR gate (560) can perform NOR operations on the output of the NAND gate (554) and the output of the NOR gate (559).

[0131] The inverter (561) can output a sum signal (SUM01) by inverting the output of the NAND gate (555). The NAND gate (562) can output a sum signal (SUM21) by performing a NAND operation on the output of the NAND gate (556) and the output of the NOR gate (560). The exclusive NOR gate (563) can output a sum signal (SUM11) by performing an exclusive operation on the output of the NAND gate (556) and the output of the NOR gate (560).

[0132] The summing signal generator (551b) can generate a summing signal (SUM22) indicating whether the set (SET2) contains two elements having a logic high level, a summing signal (SUM02) indicating whether the set (SET2) contains zero elements having a logic high level, and a summing signal (SUM12) indicating whether the set (SET2) contains one element having a logic high level, based on the syndrome bits (S4, S5, S6, S7) of the set (SET2).

[0133] The summing signal generator (551c) can generate a summing signal (SUM23) indicating whether the set (SET3) contains two elements having a logic high level, a summing signal (SUM03) indicating whether the set (SET3) contains zero elements having a logic high level, and a summing signal (SUM13) indicating whether the set (SET3) contains one element having a logic high level, based on the syndrome bits (S8, S9, S10, S11) of the set (SET3).

[0134] The sum signal generator (551d) can generate a sum signal (SUM24) indicating whether the set (SET4) contains two elements having a logic high level, a sum signal (SUM04) indicating whether the set (SET4) contains zero elements having a logic high level, and a sum signal (SUM14) indicating whether the set (SET4) contains one element having a logic high level, based on the syndrome bits (S12, S13, S14, S15) of the set (SET4).

[0135] The signal generator (565) can generate a decoding status flag (DSF1) and an error type signal (EKS1) based on sum signals (SUMs) corresponding to sum signals (SUM21, SUM01, SUM11, SUM22, SUM02, SUM12, SUM23, SUM03, SUM13, SUM24, SUM04, SUM14).

[0136] The configuration of each of the summing signal generators (551b, 551c, 551d) may be substantially the same as the configuration of the summing signal generator (551a).

[0137] FIG. 13b is a block diagram showing the configuration of the decoding status flag generator of FIG. 7 according to embodiments of the present invention.

[0138] Referring to FIG. 13b, the decoding status flag generator (550b) may include a plurality of counters (571, 572, 573, 574) and a signal generator (575).

[0139] A counter (571) can generate a counting signal (CNT1) by counting the syndrome bits having a logic high level among the syndrome bits (S0, S1, S2, S3) of a set (SET1). A counter (572) can generate a counting signal (CNT2) by counting the syndrome bits having a logic high level among the syndrome bits (S4, S5, S6, S7) of a set (SET2). A counter (573) can generate a counting signal (CNT3) by counting the syndrome bits having a logic high level among the syndrome bits (S8, S9, S10, S11) of a set (SET3). The counter (574) can generate a counting signal (CNT4) by counting the syndrome bits (S12, S13, S14, S15) of the set (SET4) that have a logic high level.

[0140] The signal generator (575) can generate a decoding status flag (DSF1) and an error type signal (EKS1) based on counting signals (CNT1, CNT2, CNT3, CNT4).

[0141] FIG. 14 shows the encoding / decoding logic in the on-die ECC engine of FIG. 6 according to embodiments of the present invention.

[0142] Referring to FIG. 14, the encoding / decoding logic (440) may include a parity generator (441), a check bit generator (443), a syndrome generator (450), and a memory (445). The memory (445) may store a second ECC (ECC2, 447).

[0143] A parity generator (441) is connected to memory (445) and can generate parity data (PRT) based on the first main data (MD11) using an exclusive OR gate array.

[0144] The check bit generator (423) is connected to memory (445), and can generate check bits (CHB) based on the first main data (MD11) in a read operation using the second ECC (447).

[0145] The syndrome generator (450) can generate a second syndrome (SDR2) based on check bits (CHB) based on main data (MD11) in a read operation and parity data (PRT) provided from a buffer (494). The syndrome generator (450) can generate a second syndrome (SDR2) based on whether each of the check bits (CHB) and each of the bits of the parity data (PRT) are identical.

[0146] The second syndrome (SDR2) may include a plurality of syndrome bits, and each of the plurality of syndrome bits may indicate whether each of the check bits (CHB) and each of the bits of the parity data (PRT) are identical. Accordingly, the second syndrome (SDR2) may indicate the location of the error bit and the number of error bits.

[0147] FIG. 15 shows the configuration of a data corrector in the on-die ECC engine of FIG. 6 according to embodiments of the present invention.

[0148] Referring to FIG. 15, the data corrector (470) may include a syndrome decoder (471), a bit inverter (473), and a selection circuit (475) implemented as a multiplexer.

[0149] A syndrome decoder (471) can decode a second syndrome (SDR2) to generate a decoding signal (DS2) indicating the location of an error bit and a selection signal (SS2) having a logic level according to the number of error bits. A bit inverter (473) can invert the error bit in response to the decoding signal (DS2). A selection circuit (475) can provide one of the first main data (MD11) and the output of the bit inverter (473) as the second main data (MD12) in response to the selection signal (SS2).

[0150] FIG. 16 shows a part of the semiconductor memory device of FIG. 4 according to embodiments of the present invention.

[0151] In FIG. 16, a control logic circuit (210), a first bank array (310a), an input / output gating circuit (290), an on-die ECC engine (400), and a link ECC engine (500) are shown.

[0152] Referring to FIG. 16, the first bank array (310a) may include a normal cell region (NCA) and a redundancy cell region (RCA).

[0153] The normal cell area (NCA) may include a plurality of first memory blocks (MB0 to MB15, 311, 312, 313), and the redundancy cell area (RCA) may include at least one second memory block (314). The second memory block (314) may be referred to as an EDB block for ECC, data line repair, and block repair to rescue defective cells occurring in the first memory blocks (311, 312, 313). The redundancy cell area (RCA) may also be referred to as a parity cell area.

[0154] The input / output gating circuit (290) may include a plurality of switching circuits (291a to 291d) each connected to the first memory blocks (311, 312, 313) and the second memory block (294).

[0155] The on-die ECC engine (400) can be connected to the switching circuits (291a to 291d) through the corresponding first data lines (GIO) and second data lines (EDBIO), respectively. The control logic circuit (210) can decode an address (ADDR) and a command (CMD) to provide a first control signal (CTL1) to the input / output gating circuit (290) to control the switching circuits (291a to 291d), provide a second control signal (CTL2) to the on-die ECC engine (400), and provide a third control signal (CTL3) to the link ECC engine (500).

[0156] In a write operation, the link ECC engine (500) receives a codeword (CW1) containing main data (MD1) and link parity data (LPRT1), and performs ECC decoding on the main data (MD) based on the link parity data (LPRT1) to correct error bits of the main data (MD1) and provides the main data (MD1) to the on-die ECC engine (400). As described above, the link ECC engine (500) generates a first syndrome including a plurality of syndrome bits based on a parity check matrix and a codeword (CW1), and while decoding the first syndrome, generates a decoding status flag (DSF1) indicating whether an error occurred during the transmission of the codeword (CW1) is detected using the characteristics of the first syndrome based on the regularity of the parity check matrix, corrects the error bit of the codeword (CW1) based on the decoded first syndrome, and transmits the decoding status flag (DSF1) to the memory controller (100).

[0157] The on-die ECC engine (400) can perform ECC encoding on the main data (MD1) in response to the second control signal (CTL2) to generate parity data (PRT) and provide a codeword (CW2) containing the main data (MD1) and parity data (PRT) to the input / output gating circuit (290).

[0158] The control logic circuit (210) can apply a first control signal (CTL1) to the input / output gating circuit (290) so that a codeword (CW2) is stored in one subpage of the target page of the first bank array (310).

[0159] When a command (CMD) directs a read operation, the control logic circuit (210) can apply a first control signal (CTL1) to the input / output gating circuit (290) so that a codeword (CW2) stored in a subpage of a target page of the first bank array (310) is provided to the on-die ECC engine (400).

[0160] The on-die ECC engine (400) can perform ECC decoding on the parity data (PRT) and main data (MD1) included in the codeword (CW2) to correct one error bit included in the codeword (CW2) and provide the main data (MD1) to the link ECC engine (500).

[0161] The link ECC engine (500) can generate link parity data (LPRT1) by performing ECC encoding on the main data (MD1) and transmit a codeword (CW1) containing the main data (MD1) and the link parity data (LPRT1) to the memory controller (100).

[0162] FIG. 17 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention.

[0163] Referring to FIGS. 4 through 17, in a method of operation of a semiconductor memory device (200) comprising a memory cell array (310), an on-die ECC engine (400), and a link ECC engine (500), the link ECC engine (500) receives main data (MD11) and link parity data (LPRT11) from a memory controller (100) (S110). The link ECC decoder (520) of the link ECC engine (500) generates a syndrome (SDR1) based on the main data (MD11), link parity data (LPRT11), and a parity check matrix (PCM) (S120).

[0164] The link ECC decoder (520) corrects the correctable error bits of the main data (MD11) based on the syndrome (SDR1) and generates a decoding status flag (DSF1) using the syndrome (SDR1) (S130). The link ECC decoder (520) provides the main data (MD11) with the error bits corrected to the on-die ECC engine (400) (S140).

[0165] The on-die ECC engine (400) generates parity data (PRT) based on main data (MD11) (S150) and stores the main data (MD11) and parity data (PRT) in the target page of the memory cell array (310) (S160).

[0166] FIG. 18 is a block diagram showing a memory system according to embodiments of the present invention.

[0167] Descriptions in Fig. 18 that overlap with Fig. 1 are omitted.

[0168] Referring to FIG. 18, the memory system (20a) may include a memory controller (100a) and a semiconductor memory device (200a).

[0169] According to an embodiment, the semiconductor memory device (200a) may be a DRAM or LP DDR6 SDRAM having volatile memory cells.

[0170] The memory controller (100a) can transmit a command (CMD) and an address (ADDR) to the semiconductor memory device (200a), transmit a clock signal (CK), transmit a codeword (CW3) containing main data (MD3) and link parity data (LPRT3) to the semiconductor memory device (200a), receive the codeword (CW3) from the semiconductor memory device (200a), and receive a decoding status flag (DSF2) from the semiconductor memory device (200a).

[0171] The memory controller (100a) may include a CPU (110), and the CPU (110) may control the overall operation of the memory controller (100a).

[0172] A semiconductor memory device (200a) may include a memory cell array (310) in which main data (MD) is stored, an on-die ECC engine (600), a link ECC engine (295), and a control logic circuit (210a).

[0173] The link ECC engine (295) receives a codeword (CW3) in a write operation based on a write command from the memory controller (100a), and performs a first ECC decoding on the main data (MD3) based on the link parity data (LPRT3) to correct correctable errors that occurred in the main data (MD3) during transmission, and can provide the main data (MD3) to the on-die ECC engine (600).

[0174] The on-die ECC engine (600) can generate parity data by performing a first ECC encoding on the main data (MD3) and store a codeword containing the main data (MD3) and parity data in a target page of the memory cell array (310).

[0175] In a read operation based on a read command from a memory controller (100a), the on-die ECC engine (600) reads a codeword containing main data (MD3) and parity data from a target page of a memory cell array (310), and performs a second ECC decoding on the main data (MD3) based on the parity data to correct correctable error bits included in the main data (MD3). In performing the above second ECC decoding, the on-die ECC engine (600) generates a first syndrome including a plurality of syndrome bits based on a parity check matrix based on the second ECC and a codeword, and while decoding the first syndrome, generates a decoding status flag (DSF2) indicating whether an error is detected in the codeword using the characteristics of the first syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword based on the decoded first syndrome, provides the main data of the corrected codeword to the link ECC engine (295), and transmits the decoding status flag (DSF2) to the memory controller (100a).

[0176] The link ECC engine (295) can generate link parity data (LPRT2) by performing a second ECC encoding on the main data (MD2), and transmit a codeword (CW2) containing the main data (MD2) and the link parity data (LPRT2) to the memory controller (100a).

[0177] Therefore, the on-die ECC engine (600) generates a decoding status flag (DSF2) using only the syndrome, so the ECC decoding latency and the occupied area of ​​the related circuit can be reduced.

[0178] FIG. 19 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 18 according to embodiments of the present invention.

[0179] The explanation in Fig. 19 that is repeated from Fig. 4 is omitted.

[0180] Referring to FIG. 19, the semiconductor memory device (200a) may include a control logic circuit (210a), an address register (220), a bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (310), a sense amplifier (285), an input / output gating circuit (290), an on-die ECC engine (600), a clock buffer (225), a strobe signal generator (235), and a link ECC engine (295).

[0181] In a read operation, a codeword (CW4) read from one of the first to 16 bank arrays (310a to 310p) is detected by a detection amplifier corresponding to the one bank array and can be stored in the read data latches. The codeword (CW4) stored in the read data latches is ECC decoded by an on-die ECC engine (600) and provided to a link ECC engine (295) as main data (MD3), and the link ECC engine (295) performs ECC encoding on the main data (MD3) to generate link parity data (LPRT3) and can transmit the codeword (CW3) containing the main data (MD3) and the link parity data (LPRT3) to a memory controller (100a).

[0182] The on-die ECC engine (600), in performing the ECC decoding, generates a first syndrome containing multiple syndrome bits based on a parity check matrix based on the second ECC and a codeword (CW4), and while decoding the first syndrome, generates a decoding status flag (DSF2) indicating whether an error is detected in the codeword (CW4) using the characteristics of the first syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword (CW4) based on the decoded first syndrome, provides the main data (MD3) of the corrected codeword to the link ECC engine (295), and transmits the decoding status flag (DSF2) to the memory controller (100a) through the alert pin (201a). Additionally, the on-die ECC engine (600) can provide an error type signal (EKS2) to the control logic circuit (210a).

[0183] In a write operation, a codeword (CW1) containing main data (MD3) and link parity data (LPRT3) to be written to one of the first to 16 bank arrays (310a to 310p) is received by a link ECC engine (295). The link ECC engine (295) performs ECC decoding on the main data (MD3) based on the link parity data (LPRT1) to correct at least one error bit that occurred during transmission and provides the main data (MD3) to an on-die ECC engine (600). The on-die ECC engine (600) generates parity bits (or parity data) based on the main data (MD3) and can provide a codeword (CW4) containing the main data (MD3) and the parity bits to an input / output gating circuit (290). The input / output gating circuit (290) can write the codeword (CW4) to the target page of the one bank array through the write drivers.

[0184] The control logic circuit (210a) can control the operation of the semiconductor memory device (200a). For example, the control logic circuit (210a) can generate control signals to cause the semiconductor memory device (200a) to perform a write operation, a read operation, or a refresh operation. The control logic circuit (210a) may include a command decoder (211) that decodes a command (CMD) received from the memory controller (100a) and a mode register (212) for setting the operation mode of the semiconductor memory device (200a).

[0185] For example, the command decoder (211) can decode the chip select signal and the command / address signal, etc., to generate the control signals corresponding to the command (CMD). In particular, the control logic circuit (210a) can decode the command (CMD) to generate a first control signal (CTL11) for controlling the input / output gating circuit (290), a second control signal (CTL12) for controlling the on-die ECC engine (600), and a third control signal (CTL13) for controlling the link ECC engine (295).

[0186] FIG. 20 is a block diagram showing a link ECC engine and an on-die ECC engine in the semiconductor memory device of FIG. 19 according to embodiments of the present invention.

[0187] Referring to FIG. 20, the link ECC engine (295) may include a link ECC decoder (296), a link ECC encoder (297), and a first memory (298). The first memory (298) may store a first ECC (ECC11).

[0188] The on-die ECC engine (600) may include reordering logic (603), a second memory (605), an ECC encoder (610), and an ECC decoder (620). The second memory (605) may store a second ECC (ECC22).

[0189] The link ECC decoder (296) receives a first codeword (CW31) including a first main data (MD31) and a first link parity data (LPRT31) in a write operation, uses a first ECC (ECC11), performs first ECC decoding on the first main data (MD31) based on the first link parity data (LPRT31) to correct errors in the main data (MD31), and provides the corrected main data (MD3) to the reordering logic (603).

[0190] The reordering logic (603) can rearrange the data bits of the corrected main data (MD3) to generate intermediate main data (MD3') and provide the intermediate main data (MD3') to the ECC encoder (610).

[0191] The ECC encoder (610) can generate parity data (PRT) by performing a first ECC encoding on intermediate main data (MD3') using a second ECC (ECC22), and can store a codeword (CW4) containing intermediate main data (MD3') and parity data (PRT) in a target page of a memory cell array (310).

[0192] In a read operation, the ECC decoder (620) reads a codeword (CW4) containing intermediate main data (MD3') and parity data (PRT) from a target page of a memory cell array (310), performs a second ECC decoding on the codeword (CW4) using a second ECC (ECC22) to correct correctable error bits of the intermediate main data (MD3') to generate a second main data (MD32), and provides the second main data (MD32) to a link ECC encoder (297).

[0193] The ECC decoder (620), in performing the second ECC decoding, generates a syndrome containing multiple syndrome bits based on a parity check matrix based on the second ECC (ECC22) and a codeword (CW4), and while decoding the syndrome, generates a decoding status flag (DSF2) indicating whether an error is detected in the codeword (CW4) by utilizing the characteristics of the syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword (CW4) based on the decoded syndrome, provides the main data (MD32) of the corrected codeword to the link ECC encoder (297), and transmits the decoding status flag (DSF2) to the memory controller (100a). Additionally, the ECC decoder (620) can provide an error type signal (EKS2) to the control logic circuit (210a).

[0194] The link ECC encoder (297) can generate link parity data (LPRT32) by performing a second ECC encoding on the main data (MD32) using the first ECC (ECC11), and transmit a codeword (CW32) containing the main data (MD32) and the link parity data (LPRT32) to the memory controller (100a).

[0195] In an embodiment, although not illustrated, the on-die ECC engine (600) may further include a second reordering logic between the memory cell array (310) and the ECC decoder (620). The second reordering logic may rearrange the data bits of the codeword (CW4) and provide them to the ECC decoder (620).

[0196] FIG. 21 is a block diagram showing an ECC decoder in the on-die ECC engine of FIG. 20 according to embodiments of the present invention.

[0197] Referring to FIG. 21, the ECC decoder (620) may include a syndrome generator (630), a syndrome decoder (635), a data corrector (640), and a decoding status flag (DSF) generator (650).

[0198] The syndrome generator (630) can generate a syndrome (SDR3) based on the data bits and parity bits of a codeword (CW4) and a parity check matrix (PCM1). The syndrome generator (630) can generate a syndrome (SDR3) by performing matrix multiplication operations on the codeword (CW4) and the parity check matrix (PCM1).

[0199] The syndrome decoder (635) can decode the syndrome (SDR3) and provide a decoding signal (DS3) to the data corrector (640) indicating the location where an error occurred in the main data (MD3') of the codeword (CW4).

[0200] The data corrector (640) can correct correctable errors in the main data (MD3') of the codeword (CW4) based on the decoding signal (DS3) and output the corrected main data (MD32). That is, the data corrector (640) can provide the corrected main data (MD32) to the link ECC encoder (297).

[0201] The decoding status flag generator (650) can generate a decoding status flag (DSF2) and an error type signal (EKS2) based on the syndrome (SDR3) in parallel with the operation of the syndrome decoder (635), transmit the decoding status flag (DSF2) to the memory controller (100a), and provide the error type signal (EKS2) to the control logic circuit (210a). The decoding status flag generator (650) can divide a plurality of syndrome bits of the syndrome (SDR3) into a plurality of sets, generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generate the decoding status flag (DSF2) based on the counting values.

[0202] The parity check matrix (PCM1) may be similar to the parity check matrix (PCM) of FIGS. 11a to 11l. The parity check matrix (PCM1) can be obtained by replacing the link parity bits (L0 to L15) in the parity check matrix (PCM) of FIGS. 11a to 11l with the parity bits of the parity data (PRT).

[0203] As described above, the decoding status flag generator (650) divides the syndrome bits of the syndrome (SDR3) into multiple sets in parallel with the operation of the syndrome decoder (635), counts the number of syndrome bits having a logic high level in each of the sets to generate counting values, and can generate a decoding status flag (DSF2) based on the counting values. Therefore, since the decoding status flag (DSF2) is not generated using the result of syndrome decoding, the decoding latency can be reduced and the circuit area of ​​the ECC decoder (620) can be reduced.

[0204] FIG. 22 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention.

[0205] Referring to FIGS. 18 to 22, in a method of operation of a semiconductor memory device (200a) comprising a memory cell array (310), an on-die ECC engine (600), and a link ECC engine (295), the link ECC engine (295) receives a first main data (MD31) and a first link parity data (LPRT31) from a memory controller (100a) (S210). The link ECC decoder (296) of the link ECC engine (295) performs a first ECC decoding on the first main data (MD31) using the first link parity data (LPRT31) (S220), and provides the first main data (MD31) to the on-die ECC engine (600) (S230).

[0206] The ECC encoder (610) of the on-die ECC engine (600) performs a first ECC encoding on the first main data (MD31) to generate parity data (PRT) (S240), and stores the first main data (MD31) and the parity data (PRT) in the target page of the memory cell array (310) (S250).

[0207] In the read operation, the ECC decoder (620) of the on-die ECC engine (600) reads the first main data (MD31) and parity data (PRT) from the target page, generates a syndrome (SDR3) based on the parity check matrix (PCM1), the first main data (MD31), and the parity data (PRT) (S260), generates a decoding status flag (DSF2) using the syndrome (SDR3) while correcting the correctable error bits of the first main data (MD31) based on the syndrome (SDR3) (S270), and provides the corrected second main data (MD32) to the link ECC engine (295) (S280).

[0208] The link ECC encoder (297) of the link ECC engine (295) performs a second ECC encoding on the second main data (MD32) to generate the second link parity data (LPRT32) (S290), and transmits the second main data (MD32) and the second link parity data (LPRT32) to the memory controller (100a).

[0209] FIG. 23 is a block diagram showing a memory system according to embodiments of the present invention.

[0210] Descriptions in Fig. 23 that overlap with Fig. 1 are omitted.

[0211] Referring to FIG. 23, the memory system (20b) may include a memory controller (100b) and a semiconductor memory device (200b).

[0212] According to an embodiment, the semiconductor memory device (200b) may be a DRAM or LP DDR6 SDRAM having volatile memory cells.

[0213] The memory controller (100b) can transmit a command (CMD) and an address (ADDR) to the semiconductor memory device (200b), transmit a clock signal (CK), transmit main data (MD) to the semiconductor memory device (200b), receive main data (MD) from the semiconductor memory device (200b), and receive a decoding status flag (DSF3) from the semiconductor memory device (200b).

[0214] The memory controller (100b) may include a CPU (110), and the CPU (110) may control the overall operation of the memory controller (100b).

[0215] The semiconductor memory device (200b) may include a memory cell array (310) in which main data (MD) is stored, an ECC engine (700), and a control logic circuit (210b).

[0216] The ECC engine (700) receives main data (MD) in a write operation based on a write command from the memory controller (100b), performs ECC encoding on the main data (MD) to generate parity data, and can store a codeword containing the main data (MD) and parity data in a target page of the memory cell array (310).

[0217] In a read operation based on a read command from a memory controller (100a), the on-die ECC engine (700) reads a codeword containing main data (MD) and parity data from a target page of a memory cell array (310), and performs ECC decoding on the main data (MD) based on the parity data to correct correctable error bits included in the main data (MD). In performing the above ECC decoding, the on-die ECC engine (700) generates a syndrome containing multiple syndrome bits based on a parity check matrix based on ECC and a codeword, and while decoding the syndrome, generates a decoding status flag (DSF3) indicating whether an error is detected in the codeword using the characteristics of the syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword based on the decoded syndrome, and transmits the main data of the corrected codeword and the decoding status flag (DSF3) to the memory controller (100b).

[0218] Therefore, the on-die ECC engine (700) generates a decoding status flag (DSF2) using only the syndrome, so the ECC decoding latency and the area occupied by the related circuit can be reduced.

[0219] FIG. 24 is a block diagram showing the configuration of a semiconductor memory device in the memory system of FIG. 23 according to embodiments of the present invention.

[0220] The explanation in Fig. 24 that is repeated from Fig. 4 is omitted.

[0221] Referring to FIG. 24, the semiconductor memory device (200b) may include a control logic circuit (210b), an address register (220), bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (310), a sensing amplifier (285), an input / output gating circuit (290), an ECC engine (700), a clock buffer (225), a strobe signal generator (235), and a data input / output buffer (320).

[0222] In a read operation, a codeword (CW) read from one of the first to 16 bank arrays (310a to 310p) is detected by a detection amplifier corresponding to the one bank array and can be stored in the read data latches. The codeword (CW) stored in the read data latches is ECC decoded by an ECC engine (700) and provided to a data input / output buffer (320) as main data (MD), and the data input / output buffer (320) can transmit the main data (MD) to a memory controller (100b).

[0223] In performing the ECC decoding, the ECC engine (700) generates a syndrome containing multiple syndrome bits based on an ECC-based parity check matrix and a codeword (CW), and while decoding the syndrome, generates a decoding status flag (DSF3) indicating whether an error is detected in the codeword (CW) by utilizing the characteristics of the first syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword (CW) based on the decoded syndrome, provides the main data (MD) of the corrected codeword to the data input / output buffer (320), and transmits the decoding status flag (DSF3) to the memory controller (100b) through the alert pin (201b). Additionally, the ECC engine (700) can provide an error type signal (EKS3) to the control logic circuit (210b).

[0224] In a write operation, main data (MD) to be written to one of the first to 16 bank arrays (310a to 310p) is received by a data input / output buffer (320). The data input / output buffer (320) provides the main data (MD) to an ECC engine (700), and the ECC engine (700) generates parity bits (or parity data) based on the main data (MD) and can provide a codeword (CW) containing the main data (MD) and the parity bits to an input / output gating circuit (290). The input / output gating circuit (290) can write the codeword (CW) to a target page of one bank array through the write drivers.

[0225] The control logic circuit (210) can control the operation of the semiconductor memory device (200b). For example, the control logic circuit (210b) can generate control signals to cause the semiconductor memory device (200b) to perform a write operation, a read operation, or a refresh operation. The control logic circuit (210b) may include a command decoder (211) that decodes a command (CMD) received from the memory controller (100b) and a mode register (212) for setting the operation mode of the semiconductor memory device (200b).

[0226] For example, the command decoder (211) can decode the chip select signal and the command / address signal, etc., to generate the control signals corresponding to the command (CMD). In particular, the control logic circuit (210b) can decode the command (CMD) to generate a first control signal (CTL21) that controls the input / output gating circuit (290) and a second control signal (CTL22) that controls the ECC engine (700).

[0227] FIG. 25 is a block diagram showing an ECC engine in the semiconductor memory device of FIG. 24 according to embodiments of the present invention.

[0228] Referring to FIG. 25, the ECC engine (700) may include reordering logic (703), memory (705), an ECC encoder (710), and an ECC decoder (720). The memory (705) may store ECC (ECC3).

[0229] The reordering logic (703) can rearrange the data bits of the main data (MD) corrected in the write operation to generate intermediate main data (MD') and provide the intermediate main data (MD') to the ECC encoder (710).

[0230] The ECC encoder (710) can generate parity data (PRT) by performing ECC encoding on intermediate main data (MD') using ECC (ECC3), and store a codeword (CW5) containing intermediate main data (MD') and parity data (PRT) in a target page of a memory cell array (310).

[0231] In a read operation, the ECC decoder (720) reads a codeword (CW5) containing intermediate main data (MD') and parity data (PRT) from a target page of a memory cell array (310), performs ECC decoding on the codeword (CW5) using ECC (ECC3) to correct correctable error bits of the intermediate main data (MD') to generate main data (MD), and provides the main data (MD) to the data input / output buffer (320).

[0232] The ECC decoder (720), in performing the ECC decoding, generates a syndrome containing multiple syndrome bits based on a parity check matrix based on ECC (ECC3) and a codeword (CW5), and while decoding the syndrome, generates a decoding status flag (DSF3) indicating whether an error is detected in the codeword (CW5) by utilizing the characteristics of the syndrome based on the regularity of the parity check matrix, corrects the error bits of the codeword (CW5) based on the decoded syndrome, provides the main data (MD) of the corrected codeword to the data input / output buffer (320), and transmits the decoding status flag (DSF3) to the memory controller (100b). Additionally, the ECC decoder (720) can provide an error type signal (EKS3) to the control logic circuit (210b).

[0233] In the embodiment, although not illustrated, the ECC engine (700) may further include a second reordering logic between the memory cell array (310) and the ECC decoder (720). The second reordering logic may rearrange the data bits of the codeword (CW5) and provide them to the ECC decoder (720).

[0234] FIG. 26 is a block diagram showing an ECC decoder in the ECC engine of FIG. 24 according to embodiments of the present invention.

[0235] Referring to FIG. 26, the ECC decoder (720) may include a syndrome generator (730), a syndrome decoder (735), a data corrector (640), and a decoding status flag (DSF) generator (750).

[0236] The syndrome generator (730) can generate a syndrome (SDR4) based on the data bits and parity bits of a codeword (CW5) and a parity check matrix (PCM2). The syndrome generator (730) can generate a syndrome (SDR4) by performing matrix multiplication operations on the codeword (CW5) and the parity check matrix (PCM2).

[0237] The syndrome decoder (735) can decode the syndrome (SDR4) and provide a decoding signal (DS4) to the data corrector (740) indicating the location where an error occurred in the main data (MD') of the codeword (CW5).

[0238] The data corrector (740) can correct correctable errors in the main data (MD') of the codeword (CW5) based on the decoding signal (DS4) and output the corrected main data (MD). That is, the data corrector (740) can provide the corrected main data (MD) to the data input / output buffer (320).

[0239] The decoding status flag generator (750) can generate a decoding status flag (DSF3) and an error type signal (EKS3) based on the syndrome (SDR4) in parallel with the operation of the syndrome decoder (735), transmit the decoding status flag (DSF3) to the memory controller (100b), and provide the error type signal (EKS3) to the control logic circuit (210b). The decoding status flag generator (750) can divide a plurality of syndrome bits of the syndrome (SDR4) into a plurality of sets, generate counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generate a decoding status flag (DSF3) based on the counting values.

[0240] The parity check matrix (PCM2) may be similar to the parity check matrix (PCM) of FIGS. 11a to 11l. The parity check matrix (PCM2) can be obtained by replacing the link parity bits (L0 to L15) in the parity check matrix (PCM) of FIGS. 11a to 11l with the parity bits of the parity data (PRT).

[0241] As described above, the decoding status flag generator (750) divides the syndrome bits of the syndrome (SDR4) into multiple sets in parallel with the operation of the syndrome decoder (735), counts the number of syndrome bits having a logic high level in each of the sets to generate counting values, and can generate a decoding status flag (DSF2) based on the counting values. Therefore, since the decoding status flag (DSF3) is not generated using the result of syndrome decoding, the decoding latency can be reduced and the circuit area of ​​the ECC decoder (720) can be reduced.

[0242] FIG. 27 is a flowchart illustrating a method of operation of a semiconductor memory device according to embodiments of the present invention.

[0243] Referring to FIGS. 23 to 27, in a method of operation of a semiconductor memory device (200b) including a memory cell array (310) and an ECC engine (700), the ECC engine (700) receives main data (MD) from a memory controller (100b) (S310). The ECC encoder (710) of the ECC engine (700) performs ECC encoding on the main data (MD) to generate parity data (PRT) (S320), and stores the main data (MD) and the parity data (PRT) in a target page of the memory cell array (310) (S330).

[0244] In the read operation, the ECC decoder (720) of the ECC engine (700) reads the main data (MD) and parity data (PRT) from the target page (S340), generates a syndrome (SDR4) based on the parity check matrix (PCM2), the main data (MD), and the parity data (PRT) (S350), generates a decoding status flag (DSF3) using the syndrome (SDR4) while correcting the correctable error bits of the main data (MD) based on the syndrome (SDR4) (S360), and transmits the main data (MD) to the memory controller (100c) (S370).

[0245] FIG. 28 is an exemplary block diagram showing a semiconductor memory device according to embodiments of the present invention.

[0246] Referring to FIG. 28, a semiconductor memory device (800) may include at least one buffer die (810) and a plurality of memory dies (820-1, 820-2, ..., 620-q, where q is a natural number greater than or equal to 4) to provide analysis and rescue functions for soft data failure in a stacked chip structure.

[0247] Multiple memory dies (820-1, 820-2, ..., 820-q) are stacked on top of at least one buffer die (810) and can communicate data through multiple through silicon via (hereinafter TSV) lines.

[0248] Each of the above plurality of memory dies (820-1, 820-2, ..., 820-s) may include a cell core (821) having memory cells, a cell core ECC engine (824) that generates transmission parity bits using transmission data transmitted to a buffer die (810), and a control logic circuit (CLC, 823). The cell core ECC engine (824) may employ the on-die ECC engine (400) of FIG. 6.

[0249] At least one buffer die (810) may include a link ECC engine (812).

[0250] The link ECC engine (812) may include the link ECC engine (500) of FIG. 6. Accordingly, the link ECC engine (500) may generate a syndrome containing a plurality of syndrome bits based on a parity check matrix and a codeword in a write operation, and while decoding the syndrome, generate a decoding status flag indicating whether an error occurred during the transmission of the codeword is detected by utilizing the characteristics of the first syndrome based on the regularity of the parity check matrix.

[0251] The semiconductor memory device (600) may be a stacked chip type memory device or a stacked memory device that communicates the data and control signals through the TSV lines. The TSV lines may also be referred to as through-silicon electrodes.

[0252] A data TSV line group (832) formed on a single memory die (820-p) may be composed of multiple TSV lines (TH1, TH2~THq), and a parity TSV line group (834) may be composed of multiple TSV lines (TH10~THt). The TSV lines (TH1, TH2~THq) of the data TSV line group (832) and the TSV lines (TH10~THt) of the parity TSV line group (834) may be connected to microbumps (MCBs) correspondingly formed between multiple memory dies (820-1~820-q).

[0253] Each of the multiple memory dies (820-1 to 820-q) may have DRAM cells consisting of one access transistor and one storage capacitor.

[0254] The semiconductor memory device (800) may have a 3D chip structure or a 2.5D chip structure to communicate with an external memory controller via a data bus (B10). The at least one buffer die (810) may be connected to the memory controller via the data bus (B10).

[0255] FIG. 29 is a structural diagram showing an example of a semiconductor package including a stacked memory device according to embodiments of the present invention.

[0256] Referring to FIG. 29, the semiconductor package (900) may include one or more stacked memory devices (910) and a graphics processor (GPU, 920), and the graphics processor (920) may include a memory controller (925).

[0257] The stacked memory device (910) and the graphics processor (920) are mounted on an interposer (930), and the interposer (930) on which the stacked memory device (910) and the graphics processor (920) are mounted can be mounted on a package substrate (940). The memory controller (925) can perform substantially the same function as the memory controller (100) of FIG. 1.

[0258] The stacked memory device (910) can be implemented in various forms, and according to one embodiment, the stacked memory device (910) may be a memory device in the form of High Bandwidth Memory (HBM) in which a plurality of layers are stacked. Accordingly, the stacked memory device (910) includes at least one buffer die and a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array, an on-die ECC engine, and a control logic circuit. At least one buffer die may include a link ECC engine.

[0259] A plurality of stacked memory devices (910) may be mounted on the interposer (930), and a graphics processor (920) may communicate with the plurality of stacked memory devices (910). As an example, each of the stacked memory devices (910) and the graphics processor (920) may include a physical region, and communication may be performed between the stacked memory devices (910) and the graphics processor (920) through a physical (PHY) region.

[0260] As described above, in a semiconductor memory device according to embodiments of the present invention, a link ECC engine or an on-die ECC engine can generate a syndrome including a plurality of syndrome bits based on a parity check matrix based on ECC and a codeword, and while decoding the syndrome, generate a decoding status flag indicating whether an error in the codeword is detected by utilizing the characteristics of the syndrome based on the regularity of the parity check matrix. Since the decoding status flag is not generated using the result of syndrome decoding, decoding latency can be reduced and the area of ​​the circuit related to ECC decoding can be reduced. Industrial applicability

[0261] The present invention can be applied to various systems using a semiconductor memory device employing a plurality of volatile memory cells and a link ECC engine and / or an on-die ECC engine.

[0262] As described above, although the present invention has been explained with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims.

Claims

Claim 1 A memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; an on-die error correction code (hereinafter 'ECC') engine; a link ECC engine; The system includes a control logic circuit that controls the on-die ECC engine and the link ECC engine, and in a write operation, the link ECC engine receives a first codeword including first main data and first link parity data from an external memory controller, generates a first syndrome including a plurality of syndrome bits based on a first parity check matrix based on the first ECC and the first codeword, generates a decoding status flag indicating whether an error occurred during the transmission of the first codeword is detected using the characteristics of the first syndrome based on the regularity of the first parity check matrix while decoding the first syndrome, corrects the error bits of the first codeword based on the decoded first syndrome, provides the first main data of the corrected first codeword to the on-die ECC engine, and the on-die ECC engine generates parity data by performing a first ECC encoding on the first main data based on the second ECC, and the first main data and the parity data are provided to the memory cell A semiconductor memory device that stores in the target page of an array. Claim 2 A semiconductor memory device according to claim 1, wherein the link ECC engine comprises: a link ECC decoder that receives the first codeword, generates the syndrome, and generates the decoding status flag; and a memory that stores the first ECC, wherein the link ECC decoder divides the plurality of syndrome bits into a plurality of sets, generates counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, and generates the decoding status flag based on the counting values. Claim 3 A semiconductor memory device according to claim 2, wherein the first main data comprises a plurality of data bits, the first link parity data comprises a plurality of link parity bits, the first parity check matrix comprises a plurality of column vectors corresponding to the plurality of data bits and the plurality of parity bits, the plurality of column vectors comprises column vectors of a first part corresponding to the data bits and column vectors of a second part corresponding to the plurality of link parity bits, and the number of elements having a logic high level in each of the column vectors of the first part corresponds to a first value, and the number of elements having a logic high level in each of the column vectors of the second part corresponds to a second value smaller than the first value. Claim 4 A semiconductor memory device according to claim 3, wherein the plurality of sets include a first set, a second set, a third set, and a fourth set, and wherein the first value corresponds to 3 and the second value corresponds to 1. Claim 5 A semiconductor memory device according to claim 3, wherein the plurality of sets include a first set, a second set, a third set, and a fourth set, and the link ECC decoder determines the type of error that occurred during transmission based on a first number of sets including two syndrome bits having a logic high level in the first set, the second set, the third set, and the fourth set, a second number of sets including one syndrome bit having a logic high level, and a third number of sets including four syndrome bits having a logic low level. Claim 6 A semiconductor memory device according to claim 5, wherein the link ECC decoder determines that no error occurred during transmission in response to the third number being 4. Claim 7 A semiconductor memory device according to claim 5, wherein the link ECC decoder determines that an error occurred during transmission in the first link parity data in response to the third number being 3, the second number being 1, and the first number being zero. Claim 8 A semiconductor memory device according to claim 5, wherein the link ECC decoder determines that a correctable error occurred during transmission in the first main data in response to the third number being 2, the second number being 1, and the first number being 1. Claim 9 A semiconductor memory device according to claim 5, wherein the link ECC decoder determines that an uncorrectable error has occurred during transmission when at least one of the syndrome bits is at a logic high level and the syndrome does not match each of the plurality of column vectors. Claim 10 A semiconductor memory device according to claim 2, wherein the link ECC decoder comprises: a syndrome generator that generates the first syndrome by performing matrix-multiplication operations on the first intermediate codeword rearranged from the first codeword and the first parity check matrix; a syndrome decoder that generates a decoding signal by decoding the first syndrome; a data corrector that corrects an error in the first main data of the first intermediate codeword based on the decoding signal and outputs the corrected first main data; and a decoding status flag generator that generates the decoding status flag and an error type signal indicating the type of error that occurred during transmission based on the first syndrome in parallel with the syndrome decoder. Claim 11 A semiconductor memory device according to claim 2, wherein the on-die ECC engine generates parity data by performing the first ECC encoding on the first main data in the write operation, and generates a second syndrome by performing the first ECC decoding using the second ECC on the first main data and the parity data read from the target page in the read operation; an ECC decoder that generates a second main data by correcting the error bits of the read-out first main data based on the second syndrome and provides the second main data to the link ECC engine; and a second memory that stores the second ECC, wherein the link ECC engine further includes a link ECC encoder that generates second link parity data by performing the second ECC encoding on the second main data using the first ECC, and transmits a second codeword including the second main data and the second link parity data to the memory controller. Claim 12 A semiconductor memory device according to claim 1, wherein the link ECC engine transmits the decoding status flag to the memory controller through an alert pin. Claim 13 A semiconductor memory device according to claim 12, characterized in that the link ECC engine transitions the alert pin to a logic high level based on determining that an uncorrectable error occurred during transmission based on the syndrome. Claim 14 A memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; an on-die error correction code (hereinafter 'ECC') engine; a link ECC engine; The system includes a control logic circuit that controls the on-die ECC engine and the link ECC engine. In a write operation, the link ECC engine receives a first codeword containing first main data and first link parity data from an external memory controller, performs first ECC decoding on the first codeword based on the first ECC to correct error bits that occurred during transmission of the first codeword, and provides the first main data of the corrected first codeword to the on-die ECC engine. The on-die ECC engine performs first ECC encoding on the first main data based on the second ECC to generate parity data, and stores the first main data and the parity data in a target page of the memory cell array. In a read operation, the on-die ECC engine generates a syndrome containing a plurality of syndrome bits based on the first main data, the parity data, and a parity check matrix based on the second ECC read from the target page, and while decoding the syndrome, the A semiconductor memory device that generates a decoding status flag indicating whether an error in the first main data and the parity data is detected by utilizing the characteristics of the syndrome based on the regularity of the parity check matrix, generates a second main data by correcting the error bits of the first main data based on the decoded syndrome, and provides the second main data to the link ECC engine. Claim 15 A semiconductor memory device according to claim 14, wherein the on-die ECC engine comprises: an ECC encoder that generates parity data in the write operation; an ECC decoder that generates the syndrome in the read operation, generates the decoding status flag, generates the second main data, and provides the second main data to the link ECC engine; and a memory that stores the second ECC, wherein the ECC decoder divides the plurality of syndrome bits into a plurality of sets, generates counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, generates the decoding status flag based on the counting values, and the ECC decoder transmits the decoding status flag to the memory controller through an alert pin. Claim 16 A semiconductor memory device according to claim 15, wherein the first main data comprises a plurality of data bits, the parity data comprises a plurality of parity bits, the parity check matrix comprises a plurality of column vectors corresponding to the plurality of data bits and the plurality of parity bits, the plurality of column vectors comprises column vectors of a first part corresponding to the data bits and column vectors of a second part corresponding to the plurality of parity bits, the number of elements having a logic high level in each of the column vectors of the first part corresponds to a first value, and the number of elements having a logic high level in each of the column vectors of the second part corresponds to a second value smaller than the first value. Claim 17 A semiconductor memory device according to claim 16, wherein the plurality of sets include a first set, a second set, a third set, and a fourth set, wherein the first value corresponds to 4 and the second value corresponds to 1, and the ECC decoder determines the type of the detected error based on a first number of sets including two syndrome bits having a logic high level in the first set, the second set, the third set, and the fourth set, a second number of sets including one syndrome bit having a logic high level, and a third number of sets including four syndrome bits having a logic low level. Claim 18 A semiconductor memory device according to claim 17, wherein the ECC decoder determines that a correctable error has occurred in the first main data in response to the third number being 2, the second number being 1, and the first number being 1. Claim 19 A memory cell array comprising multiple memory cells connected to multiple word lines and multiple bit lines; an error correction code (hereinafter 'ECC') engine; A semiconductor memory device comprising a control logic circuit for controlling the ECC engine, wherein the ECC engine receives a first main data from an external memory controller during a write operation, performs ECC encoding on the first main data based on ECC to generate parity data, stores the main data and the parity data in a target page of the memory cell array, reads the first main data and the parity data from the target page during a read operation, generates a syndrome including a plurality of syndrome bits based on the read first main data, the parity data, and a parity check matrix based on the ECC, generates a decoding status flag indicating whether an error in the read first main data and the parity data is detected using the characteristics of the syndrome based on the regularity of the parity check matrix while decoding the syndrome, corrects the error bits of the first main data based on the decoded syndrome to generate a second main data, and transmits the second main data to the memory controller. Claim 20 A semiconductor memory device according to claim 19, wherein the ECC engine comprises: an ECC encoder that generates the parity data in the write operation; an ECC decoder that generates the syndrome in the read operation, generates the decoding status flag, and generates the second main data; and a memory that stores the ECC, wherein the ECC decoder divides the plurality of syndrome bits into a plurality of sets, generates counting values ​​by counting the number of syndrome bits having a logic high level in each of the sets, generates the decoding status flag based on the counting values, and transmits the decoding status flag to the memory controller through an alert pin.

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