Display apparatus

Abstract

A display device according to the present invention comprises a substrate including a display area in which a plurality of subpixels are arranged to display an image, a hole formed within the display area in which an optical sensor is arranged, and a blocking area formed between the display area and the hole, a thin-film transistor and a light-emitting element arranged in the subpixels, a plurality of openings formed in the blocking area, a first pattern arranged below the openings, and a second pattern arranged between the openings and the first pattern.

Description

Technology Field

[0001] The present invention relates to a display device, and more particularly to a display device capable of preventing moisture penetration. Background Technology

[0003] With the advancement of information technology, various types of small and thin display devices are being proposed, such as Liquid Crystal Display Devices, Organic Light Emitting Display Devices, Plasma Display Devices, and Micro LED Display Devices.

[0004] These display devices incorporate optical elements, such as cameras, to provide users with various functions. Through-holes are formed in the display devices to mount these optical elements. However, in this case, moisture can penetrate into the display area through these through-holes. If organic light-emitting diodes are exposed to moisture or oxygen, defects may occur, such as pixel shrinkage (where the light-emitting area shrinks) or the formation of dark spots within the light-emitting area. Furthermore, moisture can oxidize metal electrodes. Therefore, if moisture penetrates the display area, defects may occur in the light-emitting diodes and various electrodes. The problem to be solved

[0005] The present invention is made in consideration of the above-mentioned points and aims to provide a display device capable of blocking moisture penetration from a hole into a display area by forming a blocking portion around a hole where an optical sensor is placed.

[0006] Another objective of the present invention is to provide a display device capable of preventing defects in which the lower film is etched when the opening is formed by forming first and second etching stop films on the lower part of the opening. means of solving the problem

[0008] To achieve the above objective, a display device according to the present invention comprises a substrate including a display area in which a plurality of subpixels are arranged to display an image, a hole formed within the display area in which an optical sensor is arranged, and a blocking area formed between the display area and the hole, a thin-film transistor and a light-emitting element arranged in the subpixels, a plurality of openings formed in the blocking area, a first pattern arranged below the openings, and a second pattern arranged between the openings and the first pattern.

[0009] A lower blocking metal is disposed on the substrate below the thin-film transistor of the display area, and a first pattern is disposed on the blocking area on the substrate. At this time, the first pattern may be composed of the same material as the lower blocking metal.

[0010] The second pattern is placed on the buffer layer, and the second pattern may be composed of the same material as the semiconductor layer.

[0011] A metal pattern is placed on the protective layer of the blocking area, and the metal pattern protrudes toward the opening to form an overhang structure with the opening, and in this case, the metal pattern may be composed of the same material as the source electrode and the drain electrode.

[0012] An insulating pattern may be placed below the metal pattern inside the opening to cover both sides of the opening, and the insulating pattern may be composed of the same material as the first flattening layer. Effects of the invention

[0014] In the display device according to the present invention, by forming a blocking part having a plurality of openings around a hole where an optical sensor is placed, moisture can be prevented from penetrating from the hole into the display area, and as a result, oxidation of various wiring and electrodes can be prevented and deterioration of the light-emitting layer can be prevented.

[0015] In addition, in the display device according to the present invention, two etching stop films are placed below the opening to prevent defects caused by over-etching that may occur when forming the opening, such as various defects caused by the etching of the buffer layer or the penetration of moisture and oxygen.

[0016] In addition, the display device according to the present invention prevents defects caused by moisture penetration, thereby preventing the disposal of hazardous substances, etc., and thus enables the realization of an eco-friendly environment. Brief explanation of the drawing

[0018] FIG. 1 is a schematic block diagram of a display device according to the present invention. Figure 2 is a schematic block diagram of the subpixel shown in Figure 1. FIG. 3 is a circuit diagram conceptually showing a subpixel of a display device according to the present invention. FIG. 4 is an exploded perspective view schematically showing a display device according to the present invention. FIG. 5 is a plan view briefly showing a display panel of a display device according to the present invention. Figure 6 is a partially enlarged plan view of the sensor area of ​​Figure 5. Figure 7 is a cross-sectional view along line I-I' of Figure 6. Figure 8 is an enlarged cross-sectional view of area A of Figure 7. FIGS. 9a-9i are drawings illustrating a method for manufacturing a display device according to the present invention. Specific details for implementing the invention

[0019] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of this specification, and this specification is defined only by the scope of the claims.

[0020] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0022] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0023] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0024] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0025] In describing the components of this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. Where it is stated that a component is "connected," "combined," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may be "interposed" between each component, or that each component may be "connected," "combined," or "joined" through other components.

[0026] In this specification, the term "display device" may include a display device in the narrow sense, such as a display module comprising a display panel and a driving unit for driving the display panel. Additionally, it may include a set electronic device or set device or set apparatus, such as an equipment display including a complete product or final product including a display module, such as a notebook computer, television, computer monitor, automotive display, or other form of vehicle, or a mobile electronic device such as a smartphone or electronic pad.

[0027] Accordingly, the display device in this specification may include the display device itself in the narrow sense, such as a display module, and even a set device that is an application product or end-consumer device including the display module.

[0028] The present invention will be described in detail below with reference to the attached drawings.

[0029] FIG. 1 is a schematic block diagram of a display device (100) according to the present invention, and FIG. 2 is a schematic block diagram of a subpixel (SP) shown in FIG. 1.

[0030] As illustrated in FIG. 1, the display device (100) is configured to include an image processing unit (102), a timing control unit (104), a gate driving unit (106), a data driving unit (107), a power supply unit (108), and a display panel (109).

[0031] The image processing unit (102) outputs a driving signal for driving various devices along with image data supplied from the outside. For example, the driving signal output from the image processing unit (102) may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.

[0032] The timing control unit (104) receives image data and driving signals, etc., from the image processing unit (102). Based on the driving signals input from the image processing unit (102), the timing control unit (104) generates and outputs a gate timing control signal (GDC) for controlling the operation timing of the gate driving unit (106) and a data timing control signal (DDC) for controlling the operation timing of the data driving unit (107).

[0033] The gate driving unit (106) outputs a scan signal to the display panel (109) in response to a gate timing control signal (GDC) supplied from the timing control unit (104). The gate driving unit (106) outputs the scan signal through a plurality of gate lines (GL1~GLm). At this time, the gate driving unit (106) may be formed in the form of an IC (Integrated Circuit), but is not limited thereto.

[0034] The data driving unit (107) outputs a data voltage to the display panel (109) in response to a data timing control signal (DDC) input from the timing control unit (104). The data driving unit (107) samples and latches a digital data signal (DATA) supplied from the timing control unit (104) and converts it into an analog data voltage based on gamma voltage. The data driving unit (107) outputs the data voltage through a plurality of data lines (DL1~DLn). At this time, the data driving unit (107) may be formed in the form of an IC (Integrated Circuit), but is not limited thereto.

[0035] The power supply unit (108) outputs a high potential voltage (EVDD) and a low potential voltage (EVSS), etc., and supplies them to the display panel (109). The high potential voltage (EVDD) is supplied to the display panel (109) through the first power line (PL1), and the low potential voltage (EVSS) is supplied to the display panel (109) through the second power line (PL2). At this time, the voltage output from the power supply unit (108) may be output to the gate driving unit (106) or the data driving unit (107) and used for driving them.

[0036] The display panel (109) displays an image in response to the data voltage and scan signal supplied from the gate driving unit (106) and the data driving unit (108), and the power supplied from the power supply unit (108).

[0037] The display panel (109) is composed of a plurality of subpixels (SP) to display an actual image. The subpixels (SP) include a red subpixel, a green subpixel, and a blue subpixel, or a white (W) subpixel, a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. At this time, the W, R, G, and B subpixels (SP) may all be formed with the same area, but may also be formed with different areas.

[0038] As shown in FIG. 2, one subpixel (SP) can be connected to a gate line (GL1), a data line (DL1), a first power line (PL1), and a second power line (PL2). The number of transistors and capacitors, as well as the driving method of the subpixel (SP), are determined according to the configuration of the pixel circuit.

[0039] FIG. 3 is a circuit diagram conceptually showing a subpixel (SP) of a display device (100) according to the present invention. In the drawing, the pixel circuit placed in one subpixel (SP) is shown as having a circuit structure of 6T1C consisting of 6 transistors and 1 capacitor, but this is exemplary and the number of transistors and capacitors constituting the pixel circuit is not limited thereto.

[0040] As shown in FIG. 3, one subpixel (SP) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a driving transistor (DT), a storage capacitor (CST), and a light-emitting element (LED).

[0041] The light-emitting element (LED) emits light by the driving current supplied from the driving transistor (DT). The anode of the light-emitting element (LED) is connected to the fourth node (N4), and the cathode of the light-emitting element (LED) is connected to the input terminal of the low potential voltage (EVSS).

[0042] The driving transistor (DT) controls the driving current applied to the light-emitting element (LED) according to the voltage between the source electrode and the gate electrode. The source electrode of the driving transistor (DT) is connected to the input terminal of the high potential voltage (EVDD), the gate electrode is connected to the second node (N2), and the drain electrode is connected to the third node (N3).

[0043] The first transistor (T1) includes a gate electrode connected to the input terminal of the first scan signal (SCAN1), a source electrode connected to a data line supplying a data voltage (VDATA), and a drain electrode connected to the first node (N1). The first transistor (T1) can apply the data voltage (VDATA) supplied from the data line (DL) to the first node (N1) in response to the first scan signal (SCAN1).

[0044] The second transistor (T2) includes a source electrode connected to the third node (N3), a drain electrode connected to the second node (N2), and a gate electrode connected to the input terminal of the first scan signal (SCAN1). The second transistor (T2) can diode-connect the gate electrode and the drain electrode of the driving transistor (DT) in response to the first scan signal (SCAN1).

[0045] The third transistor (T3) includes a gate electrode connected to a light emission signal input terminal, a source electrode connected to a first node (N1), and a drain electrode connected to a reference voltage (VREF) input terminal. The third transistor (T3) can apply a reference voltage (VREF) to the first node (N1) in response to a light emission signal (EM).

[0046] The fourth transistor (T4) includes a source electrode connected to the third node (N3), a drain electrode connected to the fourth node (N4), and a gate electrode connected to the input terminal of the light emission signal (EM). The fourth transistor (T4) forms a current path between the third node (N3) and the fourth node (N4) in response to the light emission signal (EM).

[0047] The fifth transistor (T5) includes a drain electrode connected to the fourth node (N4), a source electrode connected to the input terminal of the reference voltage (VREF), and a gate electrode connected to the input terminal of the second scan signal (SCAN2). The fifth transistor (T5) can apply a reference voltage (Vref) to the fourth node (N4) in response to the second scan signal (SCAN2).

[0048] The storage capacitor (CST) includes a first electrode connected to a first node (N1) and a second electrode connected to a second node (N2).

[0049] Hereinafter, a display device according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0050] FIG. 4 is an exploded perspective view schematically showing a display device (100) according to one embodiment, and FIG. 5 is a plan view briefly showing a display panel (PNL) of a display device (100) according to one embodiment of the present invention.

[0051] The display device (100) of the present invention can be applied to various electronic devices. For example, the display device (100) of the present invention may be applied to mobile devices such as smartphones or wearable devices such as watches. Below, the display device (100) of the present invention applied to a watch is described as an example, but is not limited thereto.

[0052] As illustrated in FIG. 4, a display device (100) according to one embodiment of the present invention includes a display panel (PNL), a sensor module (SM), a circuit board (CB), a cover window (CW), and a frame (FRA).

[0053] The display panel (PNL) includes a display area (AA) where the actual image is displayed and a non-display area (NA) located outside the display area (AA).

[0054] A pixel area (P) comprising a plurality of subpixels (SP1, SP2, SP3) is disposed in the display area (AA). At this time, the subpixels (SP1, SP2, SP3) may each include a red (R) subpixel, a green (G) subpixel, and a blue (B) subpixel. Additionally, the pixel area (P) may further include a white (W) subpixel.

[0055] Multiple gate lines and data lines are arranged in the display area (AA), and subpixels (SP) are arranged in the intersection areas of the gate lines and data lines. In each subpixel (SP), a thin-film transistor, which is a switching element, and a display element for realizing an actual image are arranged.

[0056] The display device may include various display devices. For example, the display device may be an organic electroluminescent display device, a liquid crystal display device, a quantum dot display device, a microLED display device, or a miniLED display device.

[0057] In the non-display area (NA), a gate driver and a data driver that apply various signals to subpixels (SP1, SP2, SP3) may be disposed. The gate driver applies a scan signal to the subpixels (SP1, SP2, SP3) through a gate line, and the data driver applies an image signal to the subpixels (SP1, SP2, SP3) through a data line. At this time, the gate driver may be a GIP (Gate-In-Panel) circuit in which gate driver circuits are formed directly on the substrate.

[0058] The sensor module (SM) may be placed on the back of the display panel (PNL). The sensor module (SM) may overlap with the display area (AA) of the display panel (PNL). The sensor module (SM) may refer to any configuration that utilizes an external input received through the display panel (PNL). For example, the sensor module (SM) may be an optical sensor such as a camera, an ambient light sensor, or a fingerprint sensor.

[0059] The display device (100) according to the present invention is a display device in which a sensor module (SM) is placed below the display area (AA) of a display panel (PNL).

[0060] In conventional display devices, a notch is formed in a portion of the upper part of the display area (AA), and an optical sensor, such as a camera or an infrared sensor, is placed in this notch. However, in this case, since the notch is formed by removing a portion of the upper part of the display area (AA), there was a problem in that not only was the area of ​​the display area (AA) reduced, but the aesthetics were also poor.

[0061] In the present invention, by forming a hole in the display area (AA) and placing an optical sensor in the hole, the problem of the display area (AA) being reduced in area and having poor aesthetics can be solved.

[0062] A circuit board (CB) may be placed on the back of a display panel (PNL). The circuit board (CB) may be a printed circuit board (PCB) or a flexible printed circuit board (FPCB).

[0063] A cover window (CW) can be placed on the front of a display panel (PNL). The cover window (400) can cover the front of the display panel (PNL) to protect the display panel (PNL) from external impact.

[0064] The cover window (CW) may be made of transparent plastic, glass, or tempered glass, but is not limited thereto. For example, the cover window (CW) may have either Sapphire Glass or Gorilla Glass, or a laminated structure thereof. Additionally, the cover window (CW) may include any one of PET (polyethyleneterephthalate), PC (polycarbonate), PES (polyethersulfone), PEN (polyethylenapthanate), and PNB (polynorborneen). The cover window (CW) may be made of tempered glass to ensure scratch resistance and transparency.

[0065] The frame (FRA) accommodates the display panel (PNL) and supports the cover window (CW). The frame (FRA) accommodates the sensor module (SM) and the circuit board (CB). The frame (FRA) secures the display panel (PNL), the sensor module (SM), and the circuit board (CB) to the display device (100) and protects them from external impact.

[0066] A sensor area (SA) is formed on the display panel (PNL). The sensor area (SA) is aligned with the sensor module (SM) and transmits stimuli, such as light input from the outside, directly to the sensor module (SM).

[0067] At this time, the sensor area (SA) can be formed in various areas of the display area (AA). In the drawing, the sensor area (SA) is formed near the circumference of the circular display area (AA), but the sensor area (SA) may also be formed near the center of the display area (AA).

[0068] FIG. 6 is a partial enlarged plan view of the sensor area (SA) of FIG. 5. As shown in FIG. 6, a hole (H) is formed in the sensing area (SA). The hole (H) is formed to correspond to the sensor module (SM), so that light passing through the hole (H) reaches the sensing module (SM). As will be explained later, the hole (H) can be formed by removing various structures placed in the display area (AA). For example, the hole (H) can be formed by removing various insulating layers placed in the display area (AA).

[0069] In the drawing, the hole (H) is formed in a circular shape, but it is not limited thereto and the hole (H) can be formed in various shapes. For example, the hole (H) can be formed in an elliptical shape or a polygonal shape. In addition, the hole (H) may be formed in the same shape as the corresponding sensor module (SM).

[0070] A shielding section (STP) is formed around the hole (H). Since the hole (H) is formed by removing various insulating layers of the display area (AA), the hole (H) is directly exposed to the external environment. Consequently, moisture can penetrate into the display area (AA) through the inner surface of the hole (H). Moisture not only causes oxidation of various electrodes and wiring but also becomes a significant cause of degradation of the organic light-emitting layer.

[0071] The blocking portion (STP) is formed along the periphery of the hole (H) to block moisture penetrating into the display area (AA) through the inner surface of the hole (H), thereby preventing oxidation of various electrodes and wiring and deterioration of the organic light-emitting layer.

[0072] In the drawing, the blocking section (STP) is formed continuously along the periphery of the hole (H) in a closed curve shape, but multiple blocking sections (STP) may be formed discontinuously along the periphery of the hole (H).

[0073] FIG. 7 is a cross-sectional view along line I-I' of FIG. 6, and FIG. 8 is an enlarged cross-sectional view of area A of FIG. 7. Although the first to fifth transistors (T1-T5) and the driving transistor (DT) are arranged in the actual display panel (PNL), for convenience of explanation, only the driving transistor (DT) is shown and other transistors are omitted.

[0074] As shown in FIGS. 7 and 8, the substrate (110) shows a display area (AA), a blocking part (STP), and a hole (H).

[0075] The substrate (110) may be composed of a hard material such as glass, or may be composed of a plastic material such as polyimide, polymethylmethacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate, but is not limited thereto.

[0076] For example, if the substrate (110) is made of polyimide, it may be composed of multiple polyimides, and an inorganic layer may be further disposed between the polyimides, but is not limited thereto.

[0077] A lower blocking metal (BSM) is disposed in the display area (AA) on the substrate (110). The lower blocking metal (BSM) minimizes back channel phenomena caused by trapped charges in the substrate (110), thereby preventing afterimages or degradation of transistor performance. The lower blocking metal (BSM) may be composed of metal, but is not limited thereto.

[0078] A plurality of first patterns (172) are disposed on the blocking portion (STP) on the substrate (110). The first patterns (172) may be composed of the same material (e.g., metal) as the lower blocking metal (BSM), but may also be composed of a different material. The plurality of first patterns (172) are formed to be spaced apart from each other at a certain distance and are disposed continuously or discontinuously along the periphery of the hole (H).

[0079] A buffer layer (142) is formed on a substrate (110) on which a lower blocking metal (BSM) and a first pattern (172) are formed. The buffer layer (142) is formed over the entire substrate (110) to improve the adhesion between the layers formed thereon and the substrate (110), and to perform the role of blocking various types of defects, such as alkaline components leaking from the substrate (110). In addition, the buffer layer (142) can delay the diffusion of moisture or oxygen that has penetrated into the substrate (110).

[0080] The buffer layer (142) may be composed of a single layer of SiNx or SiOx or a multilayer thereof. If the buffer layer (142) is composed of a multilayer, SiOx and SiNx may be formed alternately. The buffer layer (142) may be omitted based on the type and material of the substrate (110), the structure and type of the thin-film transistor, etc.

[0081] A transistor (DT) is formed in the display area (AA) on the buffer layer (142). The transistor (DT) includes a semiconductor layer (114), a gate electrode (116a), a source electrode (122), and a drain electrode (124).

[0082] A semiconductor layer (114) is formed on a buffer layer (142), and a gate insulating layer (143) is formed thereon.

[0083] The semiconductor layer (114) may be made of an oxide semiconductor. For example, the semiconductor layer (114) may be made of any one of IGZO (Indium-gallium-zinc-oxide), IZO (Indium-zinc-oxide), IGTO (Indium-gallium-tin-oxide), and IGO (Indium-gallium-oxide), but is not limited thereto.

[0084] Additionally, the semiconductor layer (114) may be made of a polycrystalline semiconductor. For example, the polycrystalline semiconductor may be made of low-temperature polysilicon (LTPS) with high mobility, but is not limited thereto.

[0085] Additionally, the semiconductor layer (114) may be made of an oxide semiconductor. For example, the semiconductor layer (114) may be made of any one of IGZO (Indium-gallium-zinc-oxide), IZO (Indium-zinc-oxide), IGTO (Indium-gallium-tin-oxide), and IGO (Indium-gallium-oxide), but is not limited thereto.

[0086] The semiconductor layer (114) consists of a central channel region (114a) and two side doping layers, a source region (114b) and a drain region (114c).

[0087] A plurality of second patterns (174) are arranged on the buffer layer (142) of the blocking area (STP). The second patterns (174) are formed by being aligned with the first pattern (172) with the buffer layer (142) in between. In the drawing, the width (a1) of the first pattern (172) is the same as the width (a2) of the second pattern (174) (a1=a2), but the width (a1) of the first pattern (172) may be larger than the width (a2) of the second pattern (174) (a1>a2). In this way, by making the width (a1) of the first pattern (172) larger than the width (a2) of the second pattern (174), it is possible to prevent the first pattern (172) and the second pattern (174) from being misaligned due to process error.

[0088] Similar to the first pattern (172), a plurality of fourth patterns (174) are formed to be spaced apart from each other at a certain distance and are arranged continuously or discontinuously along the periphery of the hole (H).

[0089] A gate insulating layer (143) is formed on the semiconductor layer (114). The gate insulating layer (143) may be composed of a single layer or multiple layers made of inorganic materials such as SiOx or SiNx, but is not limited thereto.

[0090] A gate electrode (116a) is placed on top of a gate insulating layer (143). Additionally, a connecting electrode (116b) is placed on top of the gate insulating layer (143). An interlayer insulating layer (144) is formed on top of the gate electrode (116a) and the connecting electrode (116b). The gate electrode (116a) and the connecting electrode (116b) may be formed from the same metal in the same process, but are not limited thereto and may be formed from different metals by different processes.

[0091] The gate electrode (116a) and the connecting electrode (116b) are made of metal. For example, the gate electrode (116a) and the connecting electrode (116b) may be composed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but are not limited thereto.

[0092] The interlayer insulating layer (144) may be composed of a single layer or multiple layers thereof, made of an organic material such as photoacrylic or an inorganic material such as SiNx or SiOx. Additionally, the interlayer insulating layer (144) may be composed of multiple layers of an organic layer and an inorganic layer, but is not limited thereto.

[0093] The connecting electrode (116b) is electrically connected to the lower blocking metal (BSM) through a first contact hole (149a) formed in the buffer layer (142) and the gate insulating layer (143).

[0094] A storage electrode (118) is disposed in the display area (AA) on the interlayer insulation layer (144). The storage electrode (118) may be formed of metal, but is not limited thereto. The storage electrode (118) may form a gate electrode (116a) and a storage capacitor.

[0095] A protective layer (145) is formed on the interlayer insulating layer (144) on which the storage electrode (118) is formed. The protective layer (145) may be composed of an inorganic material such as SiNx or SiOx.

[0096] A first flattening layer (146) is formed on the protective layer (145), and a source electrode (122) and a drain electrode (124) are formed in the display area (AA) on the first flattening layer (146).

[0097] The first flattening layer (146) may be formed of an organic material such as photoacrylic, but may also be composed of multiple layers consisting of an inorganic layer and an organic layer.

[0098] The source electrode (122) and the drain electrode (124) may be composed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto. The source electrode (122) and the drain electrode (124) are each ohmic-contacted with the source region (114b) and the drain region (114c) of the semiconductor layer (114) through the second contact hole (149b) and the third contact hole (149c) formed in the gate insulating layer (143), the interlayer insulating layer (144), and the first planarization layer (146). Additionally, the drain electrode (124) is electrically connected to the connecting electrode (116b) through the fourth contact hole (149d).

[0099] A second planarization layer (148) is formed on a substrate (110) on which a thin-film transistor (DT) is disposed. The second planarization layer (148) may be formed from an organic material such as photoacrylic, but is not limited thereto and may be composed of multiple layers consisting of an inorganic layer and an organic layer. Additionally, the second planarization layer (148) may be composed of the same material as the first planarization layer (146), but may also be composed of a different material.

[0100] An opening (OPEN) is formed on each of the multiple second patterns (174) of the blocking section (STP). The multiple openings (OPEN) are formed at a certain distance from each other and can be formed continuously or discontinuously along the periphery of the hole (H).

[0101] Each of the multiple openings (OPEN) can be formed by removing the gate insulating layer (143) and the interlayer insulating layer (144). Since the width (a3) ​​of the opening (OPEN) is set to be smaller than the width (a2) of the second pattern (174), the second pattern (174) is exposed to the outside through the opening (OPEN).

[0102] The protective layer (145) formed in the blocking section (STP) extends into the interior of the opening (OPEN) and is disposed on the side wall of the gate insulation layer (143) and the interlayer insulation layer (144) of the opening (OPEN) and on the upper surface of the second pattern (174) that is exposed to the outside by the opening (OPEN).

[0103] A metal pattern (176) is disposed on the protective layer (145) formed on the blocking portion (STP). At this time, the metal pattern (176) extends inwardly into the opening (OPEN), so that the metal pattern (176) and the opening (OPEN) form an overhang structure. The metal pattern (176) may be composed of the same metal as the source electrode (122) and the drain electrode (124), but may also be composed of a different metal.

[0104] An insulating pattern (147) is formed within the opening (OPEN) below the metal pattern (176) that forms the opening (OPEN) and the overhang structure. The insulating pattern (147) is formed to cover the side wall of the opening (OPEN), and its width increases from the lower surface of the metal pattern (176) toward the upper surface of the protective layer (145) of the opening (OPEN). However, the width of the insulating pattern (147) placed on the upper surface of the protective layer (145) of the opening (OPEN) is smaller than the length of the metal pattern (176) protruding from the opening (OPEN). The metal pattern (176) may be composed of the same material as the first flattening layer (146), but is not limited thereto.

[0105] The gate insulating layer (143) and the interlayer insulating layer (144) are disconnected by a plurality of openings (OPEN), thereby preventing moisture from penetrating into the display area (AA) through the gate insulating layer (143) and the interlayer insulating layer (144). As a result, oxidation of various wiring and electrodes and deterioration of the light-emitting layer due to moisture can be prevented.

[0106] A light-emitting element (D) is placed in the display area (AA) on the second flattening layer (148). The light-emitting element (D) is composed of a first electrode (132), a light-emitting layer (134), and a second electrode (136).

[0107] The first electrode (132) is placed on the second flattening layer (148) and is electrically connected to the drain electrode (124) of the thin film transistor (DT) through the fifth contact hole (149e) formed in the second flattening layer (148).

[0108] The first electrode (132) may be formed from at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof. Additionally, the first electrode (132) may be formed from a transparent metal oxide layer such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0109] If the display device (100) is a top-emitting display device, the first electrode (132) may further include an opaque conductive material to function as a reflective electrode that reflects light. If the display device (100) is a bottom-emitting display device, the first electrode (132) may be disposed using a transparent conductive material that transmits light, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0110] A bank layer (152) is formed at the boundary of each subpixel on the second flattening layer (148). The bank layer (152) may be a type of partition defining the subpixel. The bank layer (152) can partition each subpixel to prevent light of a specific color output from adjacent pixels from being mixed and output.

[0111] The bank layer (152) may be made of at least one material among an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as BCB (BenzoCycloButene), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, or a photosensitive material including a black (or black) pigment, but is not limited thereto.

[0112] Although not shown in the drawing, a spacer may be placed on the bank layer (152). When forming the light-emitting layer (134) by depositing an organic light-emitting material, the spacer positions the metal mask and separates the metal mask from the deposition target by a certain distance. Therefore, if the light-emitting layer (134) is formed in a different way, the spacer may be omitted.

[0113] The light-emitting layer (134) may include an R-light-emitting layer that emits red light, a G-light-emitting layer that emits green light, and a B-light-emitting layer that emits blue light, formed in R, G, and B pixels. For example, the light-emitting layer (134) may include an organic light-emitting layer or an inorganic light-emitting layer, for example, a nano-sized material layer, a quantum dot, a micro LED light-emitting layer, or a mini LED light-emitting layer, but is not limited thereto.

[0114] In the light-emitting layer (134), not only an organic light-emitting layer but also an electron injection layer and a hole injection layer that respectively inject electrons and holes into the organic light-emitting layer, and an electron transport layer, a hole blocking layer, an electron blocking layer, and a hole transport layer that respectively transport the injected electrons and holes to the light-emitting layer may be formed, but is not limited thereto.

[0115] The second electrode (136) is placed on the light-emitting layer (134) and may be composed of a single layer or multiple layers made of metal or an alloy thereof. Additionally, the second electrode (136) may be composed of a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0116] When the display device (100) is of the top-emitting type, the second electrode (136) may be arranged using a translucent conductive material that transmits light. For example, the second electrode (136) may be formed from at least one of alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and LiF / Ca:Ag.

[0117] When the display device (100) is of the bottom-emitting type, the second electrode (136) may be formed using an opaque conductive material as a reflective electrode that reflects light. For example, the second electrode (136) may be formed from at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0118] Additionally, the light-emitting layer (134) may be configured in a tandem structure. The tandem structure may include a plurality of light-emitting layers, and a charge-generating layer may be included between the light-emitting layers. The charge-generating layer is intended to regulate the charge balance between a plurality of organic layers and may be composed of a plurality of layers including a first charge-generating layer and a second charge-generating layer. The charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer, and may be composed of a light-emitting layer doped with an alkali metal such as Li, Na, K, Cs, or an alkaline earth metal such as Mg, Sr, Ba, or Ra, but is not limited thereto.

[0119] An encapsulation layer (160) is formed in the display area (AA) and the blocking area (STP) to seal the light-emitting element (D). If the light-emitting element (D) is exposed to moisture or oxygen, a pixel shrinkage phenomenon may occur in which the light-emitting area shrinks, or a defect may occur in which a dark spot appears within the light-emitting area. In addition, moisture or oxygen oxidizes the electrodes made of metal. The encapsulation layer (160) prevents defects in the light-emitting element (D) and various electrodes by blocking the penetration of moisture and oxygen from the outside.

[0120] The bag layer (160) may be composed of a first bag layer (162), a second bag layer (164), and a third bag layer (166), but is not limited thereto and may be composed of two layers or four layers or more.

[0121] The first encapsulation layer (162) and the third encapsulation layer (166) may be composed of a single layer or a multilayer containing inorganic materials such as SiOx, SiON, SiNx, etc., and may further include organic materials between the inorganic materials such as SiOx, SiON, SiNx, etc., but are not limited thereto. The second encapsulation layer (164) may be composed of epoxy resin.

[0122] Although not shown in the drawing, a touch element may be placed. The touch element may be placed in the display area (AA) to detect touch input. The touch element may detect external touch information using a user's finger or a stylus.

[0123] The hole (H) is formed by removing the buffer layer (142), the gate insulation layer (143), the interlayer insulation layer (144), the protection layer (145), and the first and second flattening layers (146, 148), and the sealing layer (160) is formed in the hole (H).

[0124] As described above, in the display device (100) according to the present invention, by forming a blocking area (STP) including a plurality of openings (OPEN) around a hole (H), moisture penetrating along the first flattening layer (146) composed of organic material through the hole (H) is blocked, thereby preventing the oxidation of various electrodes and wiring or the deterioration of the light-emitting layer due to moisture.

[0125] Meanwhile, the first pattern (172) and the second pattern (174), which are positioned below the opening (OPEN), block the etching of the buffer layer (142), which is the lower film, when the opening (OPEN) is formed, thereby preventing defects caused by the penetration of various types of defects from the substrate (110) or defects caused by the diffusion of moisture or oxygen that has penetrated into the substrate (110). In this regard, the first pattern (172) and the second pattern (174) may be referred to as the first etching prevention pattern and the second etching prevention pattern, respectively.

[0126] Below, we will explain in detail how to block the etching of the lower film when an opening (OPEN) is formed by the first pattern (172) and the second pattern (174).

[0127] FIGS. 9a-9i are drawings illustrating a method for manufacturing a display device according to the present invention.

[0128] First, as illustrated in FIG. 9a, a metal is laminated and etched over the entire substrate (110) including a display area (AA), a blocking area (STP), and a hole (H) to form a lower blocking metal (BSM) in the display area (AA) and to form a plurality of first patterns (172) (or first etching stop patterns) in the blocking area (STP). At this time, the substrate (140) may be composed of a hard material such as glass or a plastic-based material such as polyimide, polymethylmethacrylate, polyethylene terephthalate, polyethersulfone, or polycarbonate.

[0129] After that, at least one insulating layer, such as SiOx or SiNx, is laminated over the entire substrate (110) to form a buffer layer (142).

[0130] Next, oxide semiconductors such as IGZO (Indium-gallium-zinc-oxide), IZO (Indium-zinc-oxide), IGTO (Indium-gallium-tin-oxide), and IGO (Indium-gallium-oxide) are stacked and etched on the buffer layer (142) to form a semiconductor layer (114) in the display area (AA) and a second pattern (174) (or a second etching stop pattern) in the blocking area (STP). Additionally, impurities are doped into both sides of the semiconductor layer (114) to form a channel area (112a), a source area (112b), and a drain area (112c).

[0131] Next, as illustrated in FIG. 9b, an inorganic material such as SiOx or SiNx is deposited over the entire substrate (110) to form a gate insulating layer (143), and then metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) are deposited and etched over the entire substrate (110) by sputtering to form a gate electrode (116a) and a connecting electrode (116b) in a display area (AA). At this time, the connecting electrode (116b) is connected to a lower blocking metal (BSM) through a first contact hole (149a) formed in the buffer layer (142) and the gate insulating layer (143).

[0132] Next, an intermediate insulating layer (144) is formed on the gate insulating layer (143) on which the gate electrode (116a) and the connecting electrode (116b) are formed.

[0133] After that, as shown in FIG. 9c, a photoresist is laminated and developed on the intermediate insulating layer (144) to form a first photoresist pattern (182) on the intermediate insulating layer (144).

[0134] Next, the lower film is etched using the first photoresist pattern (182) as a mask to remove the gate insulating layer (143) and the interlayer insulating layer (144) on the upper part of the second pattern (174) as shown in FIG. 9d, thereby forming a plurality of openings (OPEN) in the blocking region (STP). At this time, the gate insulating layer (143) and the interlayer insulating layer (144) of the hole (H) can be removed.

[0135] After that, as shown in FIG. 9e, a metal is stacked and etched on the interlayer insulating layer (144) to form a storage electrode (118) on the interlayer insulating layer (144) above the gate electrode (116a). At this time, the gate electrode (116a) and the storage electrode (118) are positioned with the interlayer insulating layer (144) in between to form a storage capacitor.

[0136] Next, an inorganic insulating material such as SiOx or SiNx is laminated to form a protective layer (145) on the interlayer insulating layer (144) and inside the opening (OPEN).

[0137] After that, an insulating layer (146a) is laminated over the entire substrate (110), and a photoresist is laminated thereon to form a photoresist layer (184). Then, a photomask (190) is placed over the photoresist layer, and the photoresist layer (184) is developed by irradiating it with ultraviolet light.

[0138] At this time, the photomask (190) is a halftone mask or a diffraction mask and includes a blocking portion (190a) that blocks light, a semi-transparent portion (190b) that transmits only a portion of the light, and a transmitting portion (190c) that transmits the entire light. At this time, the blocking portion (190a) of the photomask layer (190) is located in the display area (AA), the semi-transparent portion (190b) is located in the opening (OPEN), and the transmitting portion (190c) is located in the blocking area (STP) and the hole (H) excluding the opening (OPEN).

[0139] After placing the photomask (190) and irradiating it with ultraviolet light and developing it, the photomask layer (190) becomes a photoresist pattern with different thicknesses, and when the lower insulating layer (146a) is etched using this photoresist pattern, a second flattening layer (146) is formed in the display area (AA) as shown in FIG. 9f and an insulating pattern (147a) is formed inside the opening (OPEN).

[0140] At this time, the insulating layer (146a) of the display area (AA) is not removed by etching, and the second flattening layer (146) is formed. In the opening (OPEN) of the blocking area (STP), a portion of the insulating layer (146a) is removed so that an insulating pattern (147a) remains inside, and the insulating layer (146a) other than the opening (OPEN) of the blocking area (STP) is completely removed so that the protective layer (145) is exposed to the outside.

[0141] Next, as illustrated in FIG. 9g, a metal is stacked and etched to form a source electrode (122) and a drain electrode (124) on the first flattening layer (146) of the display area (AA), and a metal pattern (176) is formed in the blocking area (STP). At this time, the metal pattern (176) protrudes toward the opening (OPEN) side, so that the opening (OPEN) and the metal pattern (176) form an overhang structure.

[0142] After that, when the insulation pattern (147a) of the blocking area (STP) is ashed, only the insulating material formed in the central area of ​​the opening (OPEN) by the metal pattern (176) of the overhang structure is removed, and the insulating material on both sides of the opening (OPEN) is not removed, so as shown in FIG. 9h, an insulation pattern (147) is formed within the opening (OPEN) that covers the side walls of the opening (OPEN) and exposes the protective layer (145) of the central area.

[0143] Next, as shown in FIG. 9i, a second planarization layer (148) is formed by stacking an organic material such as photoacrylic or an inorganic material such as SiOx or SiNx, and then a transparent metal oxide such as ITO or IZO or a metal such as silver (AG), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), or chromium (Cr) is stacked and etched to form a first electrode (132) on the second planarization layer (148). At this time, the first electrode (132) is electrically connected to the drain electrode (124) of the transistor (DT) through a fifth contact hole (149e) formed in the second planarization layer (148).

[0144] After that, at least one material is laminated on the flattening layer (148) and etched by a dry etching method to form a bank layer (BNK), which is composed of an inorganic insulating material such as SiNx or SiOx, an organic insulating material such as BCB (BenzoCycloButene), an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or a photosensitive material including a black pigment.

[0145] After that, a light-emitting material is applied to the display area (AA) to form a light-emitting layer (134), and then a transparent metal oxide such as ITO or IZO or a metal such as silver (AG), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), or chromium (Cr) is laminated and etched to form a second electrode (136).

[0146] Next, an inorganic material is applied to form a first sealing layer (182), and an organic material is applied over the first sealing layer (182) to form a second sealing layer (184). Then, an inorganic material is applied over the second sealing layer (184) to form a third sealing layer (186), thereby forming a sealing layer (180) that seals the display device (100) and completing the display device (100).

[0147] In the method for manufacturing a display device (100) according to the present invention, when etching the gate insulating layer (143) and the interlayer insulating layer (144) to form an opening (OPEN) of the blocking region (STP), a first pattern (172) and a second pattern (174) are arranged to prevent the etching of the lower buffer layer (142). When etching the gate insulating layer (143) and the interlayer insulating layer (144), the etching of the buffer layer (142) can be prevented by using either the first pattern (172) or the second pattern (174). However, if only the first pattern (172) is used, the second pattern (174), which is composed of a semiconductor material, is easily etched by the etching gas (or etching liquid), so the buffer layer (142) below the second pattern (174) is also etched, and the protective layer (145) can be placed directly on the substrate (110). Additionally, if only the second pattern (174) is used, the height of the opening (OPEN) increases, causing a crack in the first sealing layer (162) formed inside the opening (OPEN), and moisture, etc., can penetrate through this crack.

[0148] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and can be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not to limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0150] 110 : Substrate 114 : Semiconductor layer 116a: Gate electrode 122 : Source electrode 124 : Drain electrode 146,148 : Leveling layer 147 : Insulation pattern 160 : Bag layer 172, 174 : Pattern 176 : Metal pattern AA : Display area STP: Blocking area H : Hole OPEN : opening SM: Sensor Module

Claims

Claim 1 A display device comprising: a substrate including a display area in which a plurality of subpixels are arranged to display an image, a hole formed within the display area in which an optical sensor is arranged, and a blocking area formed between the display area and the hole; a thin-film transistor and a light-emitting element arranged in the subpixels; a plurality of openings formed in the blocking area; a first pattern arranged below the openings; and a second pattern arranged between the openings and the first pattern. Claim 2 A display device according to claim 1, further comprising a lower blocking metal disposed on the substrate below the thin-film transistor of the display area. Claim 3 In paragraph 2, the thin-film transistor comprises: a semiconductor layer disposed on a buffer layer covering the lower blocking metal; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate electrode; a protective layer disposed on the interlayer insulating layer; a first planarization layer disposed on the protective layer; a second planarization layer disposed on the first planarization layer; and a source electrode and a drain electrode disposed on the second planarization layer and electrically connected to the semiconductor layer through a contact hole. Claim 4 In paragraph 3, the first pattern is a display device disposed in the blocking area on the substrate. Claim 5 In paragraph 4, the first pattern is a display device composed of the same material as the lower blocking metal. Claim 6 In paragraph 3, the second pattern is a display device placed on the buffer layer. Claim 7 In claim 6, the second pattern is a display device composed of the same material as the semiconductor layer. Claim 8 A display device according to paragraph 3, further comprising a metal pattern disposed on the protective layer of the blocking area and protruding toward the opening to form an overhang structure with the opening. Claim 9 In claim 8, the metal pattern is a display device composed of the same material as the source electrode and the drain electrode. Claim 10 A display device according to claim 9, further comprising an insulating pattern disposed below the metal pattern inside the opening. Claim 11 In item 10, the insulation pattern is a display device covering both sides of the opening. Claim 12 In item 10, the above insulation pattern is a display device composed of the same material as the above first flattening layer. Claim 13 In claim 1, the width of the first pattern and the width of the second pattern are the same in the display device. Claim 14 A display device according to claim 1, wherein the width of the first pattern is greater than the width of the second pattern.

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