FPGA-based Multi-functional Digital Transceiver Device and Control Method Thereof

Abstract

The present invention relates to an FPGA-based digital transceiver control device and a control method thereof, comprising a control computer that transmits a communication setting message, a plurality of test targets including a memory storing information regarding a communication method, master / slave status, and transmission speed, and an FPGA including a plurality of registers, a plurality of banks, and modules. The FPGA sets the registers based on the communication setting message received from the control computer and information read from the memory of the test targets, thereby enabling communication with a plurality of test targets in a single slot or communication with test targets in a plurality of slots through the same pin. Accordingly, the size of the test equipment can be reduced and efficiency improved.

Description

Technology Field

[0001] The present invention relates to a digital transceiver control device based on a Field Programmable Gate Array (FPGA) and a control method thereof, and more specifically, to a digital transceiver control device based on an FPGA that can communicate with multiple inspection targets in a single slot or communicate with multiple inspection targets in multiple slots through the same pin, and a control method thereof. Background Technology

[0002] Generally, test equipment for system inspection uses sub-rack slots to test multiple inspection targets. Conventional technology had the following problems:

[0003] First, tests had to be performed by allocating an individual slot to each inspection target. This required as many slots as there were inspection targets, leading to the problem of increased test equipment size and manufacturing costs.

[0004] Second, since each slot could accommodate only one circuit card assembly, a correspondingly large number of slots and circuit card assemblies were required to accommodate multiple inspection targets. This led to increased complexity of the test equipment and difficulties in maintenance.

[0005] Third, even when using an FPGA, the FPGA had to be reprogrammed to change the communication method, the master / slave state, or the clock source related to the transmission speed. This reduced the flexibility of the test configuration and caused an increase in test execution time.

[0006] Fourth, in order to communicate with inspection targets spanning multiple slots, separate pins had to be assigned to each slot. This caused problems that reduced the efficiency of pin utilization on the base plate and increased the complexity of the wiring.

[0007] Fifth, when a change in the test configuration was required, hardware reconfiguration or reprogramming of the FPGA was necessary, which resulted in reduced test continuity and longer test times.

[0008] These problems have reduced the efficiency of test equipment and required significant time and cost to conduct tests. Therefore, new technologies capable of solving these issues have been required. The problem to be solved

[0009] The present invention aims to solve the above-mentioned problems by providing an FPGA-based digital transceiver control device and a control method thereof that can accommodate multiple inspection targets in a single slot or communicate with multiple inspection targets in multiple slots through the same pin.

[0010] In addition, the present invention aims to provide an FPGA-based digital transceiver control device and a control method thereof that can easily change the communication method, master / slave status, transmission speed, etc. without FPGA reprogramming. means of solving the problem

[0011] A digital transmission and reception control device according to an embodiment of the present invention for achieving the above-described purpose comprises: a control computer that transmits a communication setting message; a plurality of inspection targets, each comprising a memory in which information regarding a communication method, a master / slave status, and a transmission speed is stored; and a Field Programmable Gate Array (FPGA), wherein the FPGA comprises: a first register for clock selection and activation; a second register for setting a communication method; a third register for setting the direction of an input / output signal; and a fourth register for setting a connection configuration. The FPGA includes a plurality of banks and a plurality of modules, and the FPGA receives a communication setting message via Ethernet from the control computer and reads the information from the memory of the inspection target, selects and activates one of a plurality of external clock sources through the first register, sets one of a plurality of communication methods and a master / slave state through the second register, sets the direction of an input / output signal according to the master / slave state through the third register, and sets the interconnection relationship between the plurality of banks and the plurality of modules through the fourth register, thereby performing communication with the plurality of inspection targets in one slot or performing communication with the inspection targets provided in each of the plurality of slots through the same pin.

[0012] In addition, the plurality of external clock sources have different frequencies, and the FPGA is characterized by setting the transmission speed according to the frequency of the selected external clock source.

[0013] In addition, it includes a clock selection register and a clock enable register, wherein the clock selection register selects one of the plurality of external clock sources and the clock enable register sets whether the selected external clock source is enabled.

[0014] And, the second register is characterized by setting one of a master or a slave mode for each of the plurality of modules.

[0015] In addition, the third register is characterized by including a Port Direction Table Register that is set as an output signal for a module set in master mode and as an input signal for a module set in slave mode.

[0016] And, the fourth register is characterized by including a module selection register that connects the plurality of banks and the plurality of modules in a matrix form and activates a specific connection among the connected matrices.

[0017] A digital transmission and reception control method using a Field Programmable Gate Array (FPGA) according to an embodiment of the present invention for achieving the above-mentioned purpose comprises: receiving a communication setting message via Ethernet from a control computer; reading information regarding a communication method, a master / slave status, and a transmission speed from a memory provided in a test target based on the communication setting message; setting a first register for clock selection and activation within the FPGA based on the read information to select a specific clock source among a plurality of external clock sources and determining whether the selected clock source is activated; setting a second register for setting a communication method within the FPGA based on the read information to select one of a plurality of communication methods and setting the master / slave status; and setting a third register for setting the direction of an input / output signal within the FPGA as an output signal in the case of master mode and as an input signal in the case of slave mode according to the set master / slave status. The method is characterized by including: a step of determining the interconnection relationship between a plurality of banks and modules by setting a fourth register for setting the connection configuration within the FPGA; and a step of performing communication with a plurality of inspection targets in one slot or performing communication with inspection targets provided in each of the plurality of slots through the same pin according to the determined interconnection relationship.

[0018] And, the clock source selection step is characterized by selecting a clock source having a frequency corresponding to the transmission speed among the plurality of external clock sources.

[0019] In addition, the first register setting step is characterized by selecting one of the plurality of external clock sources through a clock selection register and setting whether the selected external clock source is enabled through a clock enable register.

[0020] And, the second register setting step is characterized by setting one of the master or slave modes for each of the plurality of modules.

[0021] In addition, the third register setting step is characterized by setting the output signal for the module set to the master mode and the input signal for the module set to the slave mode through the Port Direction Table Register.

[0022] And, the fourth register setting step is characterized by connecting the plurality of banks and the plurality of modules in a matrix form through the Module Selection Register, and activating a specific connection among the connected matrices.

[0023] In addition, the communication execution step is characterized by simultaneously communicating with multiple inspection targets in a single slot using multiple different communication methods according to the determined interconnection relationship. Effects of the invention

[0024] According to the present invention, a plurality of inspection targets can be accommodated in a single slot or communicate with inspection targets in a plurality of slots through the same pin, thereby reducing the size of the test equipment and enabling efficient testing.

[0025] In addition, the present invention allows the communication method, master / slave status, transmission speed, etc. to be easily changed by only register settings without reprogramming the FPGA, thereby greatly improving the flexibility and efficiency of the test equipment.

[0026] Furthermore, the present invention can automate test setup and configuration by automatically reading information stored in the memory of the test target and setting FPGA registers. Brief explanation of the drawing

[0027] FIG. 1 is a diagram showing the overall configuration of a digital transmission and reception control device according to a first embodiment of the present invention. FIG. 2 is a diagram showing the overall configuration of a digital transmission and reception control device according to a second embodiment of the present invention. FIG. 3 is a diagram showing an internal block diagram of an FPGA according to the present invention. Figure 4 is a diagram showing the internal register configuration of an FPGA. Figure 5 is a diagram showing the detailed configuration of the Clock Selection Register. Figure 6 shows the configuration of the Clock Enable Register. Figure 7 shows the implementation of the Clock Selection Code. Figure 8 shows the detailed configuration of the Module A Register and Module B Register. Figure 9 shows the implementation of Module A Code and Module B Code. FIG. 10 shows in detail the matrix connection structure between modules and banks, which is one of the key features of the present invention. Figure 11 shows the detailed structure of the Module Selection Register. Figure 12 shows the configuration of the Port Direction Table Register. Figure 13 shows the detailed implementation of the Module Selection & Port Direction Code. FIG. 14 shows the operation flowchart of the entire system according to the present invention. FIG. 15 shows a specific example of a communication method switching according to the present invention. Specific details for implementing the invention

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning that is commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0029] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “have,” “may have,” “include,” or “may include” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Terms including ordinal numbers, such as second, first, etc., may be used to describe various components, but said components are not limited by said terms.

[0030] The above terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0031] In this specification, identification symbols (e.g., a, b, c, etc.) for each step are used for convenience of explanation and do not indicate the order of the steps; the steps may occur differently from the specified order unless the context clearly indicates a specific order. That is, the steps may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0032] Additionally, the term “part” as used in this specification may refer to software or hardware components such as field-programmable gate arrays (FPGAs) or ASICs, and the “part” performs certain roles. However, the “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or configured to run one or more processors. Thus, as an example, the “part” may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data structures, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.”

[0033] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0034] The present embodiment relates to a digital transceiver control device based on a Field Programmable Gate Array (FPGA) and a control method thereof, and provides a technology capable of communicating with multiple inspection targets in a single slot or communicating with multiple inspection targets in multiple slots through the same pin.

[0035] FIG. 1 is a diagram showing the overall configuration of a digital transmission and reception control device according to a first embodiment of the present invention. The first embodiment shows a configuration in which communication with a plurality of inspection targets is performed in a single slot.

[0036] The digital transmission and reception control device according to the first embodiment has a configuration including a control computer (110), an inspection circuit card assembly (120), and a plurality of inspection targets (130, 140, 150).

[0037] As shown in FIG. 1, the control computer (110) is connected to the inspection circuit card assembly (120) via Ethernet messages. The control computer (110) performs the role of transmitting settings for communication methods and characteristics of inspection targets to the inspection circuit card assembly (120) via Ethernet messages (112). At this time, the control computer (110) generates and transmits communication setting messages suitable for the characteristics of each inspection target, thereby enabling various communication methods and settings.

[0038] The inspection circuit card assembly (120) mainly comprises a central processing unit CPU (122), a field programmable gate array FPGA (124), and an I2C (Inter-Integrated Circuit) communication unit (126). The CPU (Control Processing Unit) (122) is connected to the control computer (110) via Ethernet and performs the role of setting information such as the communication method, master / slave status, and transmission speed, which is read from the memory (EEPROM: Electrically Erasable Programmable Read-Only Memory) of the inspection target, into the internal registers of the FPGA (124). The CPU (122) can also dynamically control the registers of the FPGA (124) so ​​that the communication settings can be changed in real time.

[0039] The FPGA (124) includes multiple banks (Bank1 to BankN, 142 to 148), and each bank provides an interface for communication with the inspection target. Each bank can have independent communication settings, allowing it to operate with different communication methods or settings. Each bank of the FPGA (124) has its own communication protocol processing function, so it is designed to reduce the burden on the CPU (122) and enable efficient communication.

[0040] The I2C communication unit (126) is responsible for communicating with the memory of each inspection target to read necessary information. It reads the initial setting value of each inspection target through I2C communication, and this information is used to set the registers of the FPGA (124). Through this structure, an optimized communication environment suitable for the characteristics of each inspection target can be automatically configured.

[0041] Each inspection target (130, 140, 150) includes its own memory and a respective communication interface. Inspection target 1 (130) includes an RS-232 interface and performs serial communication through the interface, transmitting and receiving data via TX (transmit) and RX (receive) signal lines. It can also perform flow control via RTS (Request to Send) and CTS (Clear to Send) signals. Inspection target 2 (140) includes an RS-422(S) interface and enables high-speed communication using differential signals. It has characteristics that are resistant to noise and suitable for long-distance communication. Inspection target 3 (150) includes an I2C(S) interface and supports 2-wire serial communication, and performs synchronous communication via SDA (Serial Data) and SCL (Serial Clock) signal lines. The memory of each inspection target stores information regarding the communication method, master / slave status, transmission speed, etc. used by the inspection target, and this information is read via I2C communication during system initialization and used for configuring the FPGA.

[0042] FIG. 2 is a diagram showing the overall configuration of a digital transmission and reception control device according to a second embodiment of the present invention. The second embodiment shows a configuration in which inspection targets mounted in a plurality of slots communicate with each other through the same pin of the main plate. This configuration has the advantage of efficiently utilizing hardware resources and increasing the scalability of the system.

[0043] In the second embodiment, multiple slots from slot 1 to slot N are configured, and each slot may be equipped with inspection targets using different communication methods. A control computer is connected to an inspection circuit card assembly via Ethernet messages and controls the communication settings for the inspection targets in each slot. In this configuration, the FPGA (124) is designed to communicate with the inspection targets in the multiple slots through fixed pins of the parent board.

[0044] FIG. 3 shows an internal block diagram of an FPGA according to the present invention in detail, and illustrates the configuration and interconnection relationships of each module.

[0045] The interior of the FPGA (300) is largely composed of the following major functional blocks:

[0046] CPU_IF (310) is a core block responsible for the interface with the external CPU. CPU_IF communicates with the CPU through the 16-bit address bus (CPU_A[15:0]) and the 16-bit data bus (CPU_D[15:0]). It also processes write signals (WR) and system clock (CLK) signals, and controls read / write operations for internal registers. CPU_IF also controls read / write operations for internal registers and performs the role of transmitting various status information to the CPU.

[0047] ADDR_DECODER (320) is a block responsible for address decoding, which interprets the address received from CPU_IF and selects the appropriate internal module. The decoded address is used to selectively activate each module from Module1 to ModuleN and the CLOCK Selection module. In particular, it transmits communication Master / Slave signals to each Module1 through ModuleN using the data received from CPU_IF to determine the operation mode of each module.

[0048] Blocks (330) from Module 1 to Module N are core modules that handle actual communication. Each module generates communication input / output signals based on data received from CPU_IF and performs interface functions. The operation mode is determined by the Master / Slave signal, and the transmission speed is set according to the clock signal received from CLOCK Selection. In particular, each module is designed to enable efficient data processing by including an independent state machine and buffer. Module 1 and Module 2 support RS-232 / 422 / 485 communication, Module 3 supports SPI communication, and Module 4 supports I2C communication. Each module has its own communication buffer and status register, enabling independent communication processing.

[0049] The CLOCK Selection (340) block manages clock signals received from multiple external oscillators (OSCILLATOR1, OSCILLATOR2, OSCILLATOR3). This block outputs a clock individually selected for each of the output clocks from Clock1 to ClockN through CPU_IF, and dynamic changes to the output clock are possible as the Data value in CPU_IF changes. Each clock signal is controlled independently to provide a transmission speed suitable for each communication module.

[0050] Module_Read_MUX (350) performs the important role of multiplexing communication data received from each Module and delivering it to CPU_IF. This block is designed to efficiently process received data that may occur simultaneously from multiple modules and deliver it to the CPU. In particular, it ensures that important data can be processed without delay through a priority-based data processing algorithm.

[0051] FIG. 4 shows the internal register configuration of the FPGA (300) in detail. Each register consists of bits for controlling specific functions and can be dynamically configured via the CPU. The Module Registers determine the operating characteristics of each communication module, and the Clock Selection Register and Clock Enable Register (342) are responsible for clock-related settings. The Module Selection Register and Port Direction Table Register (362) control the connection configuration between the module and the bank.

[0052] The registers related to clock control are shown in detail in FIGS. 5 and FIGS. 6.

[0053] Figure 5 is a diagram showing the detailed configuration of the Clock Selection Register.

[0054] The Clock Selection Register (500) of FIG. 5 is composed of a total of 16 bits by allocating 2 bits for each clock (Clock 1 to Clock 8). The lower 8 bits (510) contain selection information (530) for Clock 1 to Clock 4, and the upper 8 bits (550) contain selection information (570) for Clock 5 to Clock 8. For each clock, one of up to 4 clock sources can be selected through the ClockN Selection0 and ClockN Selection1 bits. This configuration enables independent clock source selection for each communication module. Since 2 bits are used for the selection of each clock, selection is possible from up to 4 clock sources.

[0055] Figure 6 shows the configuration of the Clock Enable Register.

[0056] The Clock Enable Register (600) of FIG. 6 is an 8-bit register that controls whether each clock is enabled. Each bit (610) determines the state value (630) of the corresponding clock, which is enabled (1) or disabled (0), thereby blocking unnecessary clock operations and optimizing power consumption. In particular, bits 7 through 0 control the Enable / Disable state of Clock 8 through Clock 1, respectively.

[0057] FIG. 7 illustrates in detail the implementation of the Clock Selection Code (700). In the Clock Selection Code (705) block, selection logic for each clock is implemented. The selection logic (710) checks the Clock_Selection value for each of Clock 1 through Clock N and selects the corresponding oscillator output. If the Clock_Selection value is '1', OSC1 is connected to the corresponding clock output (720); if it is '2', OSC2 is connected to the corresponding clock output (720); and if it is '3', OSC3 is connected to the corresponding clock output (720). This structure enables independent source selection for each clock, thereby allowing various communication speed requirements to be met simultaneously.

[0058] FIG. 8 shows the detailed configuration of the Module A Register (810) and the Module B Register (850). The Module A Register (810) is responsible for the settings for RS-232 / 422 / 485 communication, and the Module B Register (850) is responsible for the settings for SPI / I2C communication.

[0059] The ModuleA Register (810) is responsible for configuring RS-232 / 422 / 485 communication and consists of 8 bits (820). Looking at the configuration of the ModuleA Register (810), bits 7 through 2 are used to set the communication type (830) of Module1 and Module2. Three bits are allocated for each module, allowing selection of RS-232, RS-422, or RS-485. Bits 1 and 0 are used to select Slave and Master modes (830), respectively.

[0060] The ModuleB Register (850) is responsible for the settings for SPI / I2C communication and consists of 8 bits (860). The ModuleB Register (850) uses 8 bits for Master / Slave settings for 4 channels (CH1~CH4). 2 bits are allocated per channel, allowing selection of Master mode and Slave mode (870). For example, bits 7 and 6 are responsible for the Slave and Master settings of CH4, and bits 1 and 0 are responsible for the Slave and Master settings of CH1. Through this structure, the operation mode of each channel can be controlled independently.

[0061] FIG. 9 is a diagram showing the implementation of Module A Code (920) and Module B Code (970). The entire diagram (900) consists of a part (910) implementing Module A Code on the left and a part (960) implementing Module B Code on the right.

[0062] Looking at the implementation details (930) of ModuleA Code (920), it begins with a conditional statement for cases where Master / Slave is not 00. When Master / Slave[1:0] is 1, the Mode is set to Master, and the communication code is determined as follows depending on the value of Module1 Type[2:0]. If Module1 Type[2:0] is 1 or less, the RS-232 Master code is executed; if it is 2 or less, the RS-422 Master code is executed; and if it is 3 or less, the RS-485 Master code is executed. Each conditional statement ends with endif, which ensures a clear code structure.

[0063] The implementation (980) of Module B Code (970) begins with a conditional statement that checks if CH N's Master / Slave is not 00. If Master / Slave[1:0] is 1, the Mode is set to Master and the Master Mode (SPI or I2C) code is executed. If Master / Slave[1:0] is 2, the Mode is set to Slave and the Slave Mode (SPI or I2C) code is executed. All conditional statements are explicitly terminated with Endif.

[0064] Each Module A Code and Module B Code is implemented as part of the Module N (940, 990) block, and this structure enables independent communication control for each module.

[0065] FIG. 10 is a diagram showing a matrix connection structure between modules and banks, which is one of the key features of the present invention. A plurality of communication modules are configured inside the FPGA (1000), Module 1 (1011) and Module 2 (1012) handle RS-232 / 422 / 485 communication, Module 3 (1013) handles SPI communication, Module 4 (1014) handles I2C communication, and Module N (1015) represents an additional communication module. These modules are included within a module block (1010).

[0066] The communication modules are connected to the banks (1040) on the right through the central matrix area (1030). Each bank is sequentially configured from Bank 1 (1041) to Bank N (1045), and each bank is connected to eight physical pins. These pins are grouped from Pin 1 to Pin N, forming pin groups such as 1071, 1072, 1073, 1074, and 1075, respectively.

[0067] The Module Selection & Port Direction module (1060) dynamically controls these matrix connections through the Control & Selection Signal (1020). Through this structure, each module can be connected to any bank as needed, and the pins of each bank can support different communication protocols. This flexible matrix structure allows a single physical pin to support multiple communication protocols, significantly improving the scalability and reconfigurability of the system.

[0068] FIG. 11 shows the detailed structure of the Module Selection Register (1100). This register is used to establish a connection between each module and a bank. The Module Selection Register contains the Module Type (1111) and activation information for each bank (Bank1-BankN, 1112-1116).

[0069] Looking at the module types, Module1 Master (1140) and Module1 Slave (1141) each have Enable bits for Bank1 (1112) and Bank2 (1113). Similarly, bank connections can be established for each Master and Slave from Module2 (1150, 1151) to ModuleN (1180, 1181). Through this structure, it is possible for a single module to be connected to multiple banks simultaneously, or for multiple modules to share a single bank.

[0070] The top header row (1110) consists of Module Type (1111) and columns from Bank1 (1112) to BankN (1116). The Module Type column (1130) lists the Master and Slave configurations for each module, consisting of Module1 Master (1140), Module1 Slave (1141), Module2 Master (1150), Module2 Slave (1151), Module3 Master (1160), Module3 Slave (1161), Module4 Master (1170), Module4 Slave (1171), and finally ending with ModuleN Master (1180) and ModuleN Slave (1181). In each row, the 'Enable' mark indicates that the connection between the corresponding module and bank is enabled.

[0071] FIG. 12 shows the configuration of the Port Direction Table Register (1200). This register controls the input / output direction of each module in detail. Different input / output settings are possible depending on the Master and Slave modes of each module.

[0072] The first group (1210, 1215) of Module 1 Master Direction (1212) and Module 1 Slave Direction (1217), the second group (1220, 1225) of Module 2 Master Direction (1222) and Module 2 Slave Direction (1227), the third group (1230, 1235) of Module 3 Master Direction (1232) and Module 3 Slave Direction (1237), and the fourth group (1240, 1245) of Module 4 Master (1242) and Module 4 Slave Direction (1247) are configured sequentially. Finally, the last group (1250, 1255) of Module N Master Direction (1252) and Module N Slave Direction (1257) is configured. Each row defines the signal direction in the Master or Slave mode of the corresponding module and includes direction information such as Out, In, CH1-Out, CH1-In, etc.

[0073] FIG. 13 shows the implementation (1360) of the Module Selection & Port Direction Code (1300). At the top of the drawing, the title (1370) of the Module Selection & Port Direction Code (1300) is located, and the detailed implementation (1380) of this code is shown in the area indicated by the dotted line.

[0074] In the detailed implementation code (1380), processing logic according to the combination of each bank and module type is implemented sequentially. First, the case where Bank1 & Module type is not 0 is checked, and if Bank1 Module type is Module1 Master, Bank1_Direction is set to Module1 Master Direction by reading from the Module Selection Register. Then, Bank1_pin[8:1] is set to the Bank1 Direction value read from the Port Direction Register, which follows the 'Out Out Out Out In In In In' pattern.

[0075] This pattern is applied sequentially to Bank2, Bank3, etc. For Bank2, pin[16:9] is set to the 'In In In In Out Out Out Out' pattern, and for Bank3, pin[24:17] is set to the 'Out Out Out In Out Out Out In' pattern.

[0076] Finally, processing for BankN is implemented, and if the BankN Module type is ModuleN Master, BankN_Direction is set to ModuleN Master Direction, and BankN_pin[XX:YY] is set to the BankN_Direction value.

[0077] The entire Module Selection & Port Direction code is referenced as code 1390, as shown below. Through this structured code implementation, the connections and signal directions between each bank and module can be systematically controlled.

[0078] The pin settings for each bank are configured differently depending on the communication protocol of the module. For example, in the case of RS-232 communication, appropriate input / output directions are set for signals such as TX, RX, RTS, and CTS, respectively, and in the case of SPI communication, directions are set for signals such as MOSI, MISO, SCK, and SS.

[0079] FIG. 14 shows the operation flowchart of the entire system according to the present invention.

[0080] The system's operation takes the following sequence:

[0081] In the step of receiving a communication setting message from the control computer (S1405), initial setting information is received via Ethernet. This information includes the communication method and setting value of each inspection target.

[0082] In the step of reading information from the memory of the inspection target (S1410), the communication method, master / slave status, and transmission speed information stored in each inspection target are read.

[0083] In the first register setting (S1415) step, a clock source is selected and the activation state is set. During this process, an appropriate clock frequency required for each communication is selected.

[0084] In the second register setting (S1420) step, a communication method is selected and the master / slave status is set. The communication protocol and operation mode of each module are determined in this step.

[0085] In the third register setting (S1425) step, the direction of the input / output signals is set. For a module set to master mode, the necessary signals are set as outputs, and for a module set to slave mode, the corresponding signals are set as inputs.

[0086] In the fourth register setting (S1430) step, the connection configuration between the bank and the module is set. The signal path between each module and the bank is determined through the matrix connection structure, and as needed, one module may be connected to multiple banks or multiple modules may be configured to share one bank.

[0087] Finally, in the communication execution (S1435) step, actual communication is performed according to the configured settings. Multiple communications are performed in a single slot, or communication is performed through the same pin with the inspection targets in multiple slots.

[0088] FIG. 15 is a diagram (1500) showing a specific example of a communication method switching according to the present invention. It hierarchically illustrates the communication method switching process that takes place inside an FPGA (1510).

[0089] A CPU (1520) is located at the top of the FPGA (1510), and the CPU controls the lower FPGA registers (1530) through a setting signal (1525). The FPGA registers (1530) are structured to control a communication method selector (1540) through a control signal (1535).

[0090] The communication method selector (1540) can select three different communication methods: communication method A (1542), communication method B (1544), and communication method C (1546). These communication methods are connected to each inspection target within a single slot (1550). Specifically, inspection target 1 (1551) communicates via communication method A (1552), inspection target 2 (1553) communicates via communication method B (1554), and inspection target 3 (1555) communicates via communication method C (1556).

[0091] Through this structure, different communication protocols can be simultaneously supported within a single FPGA, and an optimized communication method suitable for the characteristics of each inspection target can be provided. In particular, by supporting multiple communication methods within a single slot (1550), hardware resources can be utilized efficiently and the flexibility of the system can be greatly improved.

[0092] Support for such multiple communication methods significantly improves system flexibility and enables the accommodation of various communication requirements without reprogramming the FPGA. In addition, it allows for the efficient utilization of hardware resources, thereby improving the cost efficiency of the system.

[0093] The FPGA-based digital transceiver according to the present invention provides the following major advantages.

[0094] First, the communication method can be flexibly changed. In existing systems, the FPGA had to be reprogrammed to change the communication method, but in the present invention, the communication method can be changed simply by setting registers. This significantly improves the maintainability and scalability of the system.

[0095] Second, efficient utilization of hardware resources is possible. By communicating with multiple inspection targets from a single slot or with targets in multiple slots through the same pin, hardware resources can be used in an optimized manner. This significantly contributes to reducing the size and cost of the system.

[0096] Third, it provides an automated configuration function. It can configure the FPGA by automatically reading communication-related information stored in the memory of the target being inspected, thereby minimizing configuration errors and increasing operational efficiency.

[0097] The present invention can be utilized in various fields. In particular, it can be effectively applied in the following fields:

[0098] Test Equipment System: In an environment where equipment using various communication methods must be tested, the present invention enables a flexible test configuration. Since a single test device can support multiple types of communication protocols, the utilization of the test equipment can be increased.

[0099] Industrial Control System: In industrial sites where sensors and control devices using different communication methods are mixed, the present invention can provide an integrated communication interface. This simplifies system configuration and improves maintainability.

[0100] Communication modules within the FPGA are implemented to include the following detailed functions:

[0101] Communication Speed ​​Control Mechanism: The Clock Selection module includes a clock division function to support various communication speeds required by each communication protocol. It can generate a clock suitable for the required communication speed by dividing a reference clock received from an external clock source. For example, in the case of RS-232 communication, it can support various communication speeds from 9600 bps to 115200 bps.

[0102] Data Buffering System: Each communication module includes independent receive and transmit buffers. These buffers are implemented in a FIFO (First In First Out) structure, enabling smooth mediation of data transmission between devices with different communication speeds. The buffer sizes are optimized to suit the characteristics and requirements of each communication method.

[0103] Error Detection and Handling Function: Each communication module includes error detection and handling mechanisms specialized for the corresponding protocol. For example, in the case of SPI communication, it can detect clock synchronization errors, and in the case of RS-232 communication, it can detect and handle frame errors or parity errors.

[0104] The FPGA-based digital transceiver of the present invention can provide the following extended functions:

[0105] Multi-protocol simultaneous processing: It has a structure capable of processing multiple communication protocols simultaneously within a single FPGA. This is possible because each module has an independent state machine and control logic. For example, while one module handles RS-232 communication, another module can handle SPI communication.

[0106] The present invention relates to a dynamic protocol switching system, the core feature of which lies in a real-time communication protocol switching function. This function is implemented through the following mechanism. First, each module within the FPGA monitors the current communication status in real time, and this communication status includes information on the currently active protocol, buffer usage status, and whether an error has occurred. This status information is stored in a status register so that the CPU can read it at any time. When switching protocols, the switching is performed after waiting until the currently ongoing communication is completed. To this end, the procedure follows the steps of waiting for the completion of the current communication, flushing buffer data, setting a register for the new protocol, and starting the new communication.

[0107] In addition, the present invention implements a data flow control mechanism. When data is received simultaneously from multiple communication channels, the processing order is determined according to a predefined priority, and the priority can be set based on the importance of the communication protocol, the time sensitivity of the data, buffer saturation, etc. To compensate for differences in data processing speeds, various flow control methods are supported, such as hardware flow control (RTS / CTS), software flow control (XON / XOFF), and buffer-based flow control.

[0108] The data flow control of the present invention is implemented in a systematic structure. In a priority-based data processing system, the processing order is determined by comprehensively considering the importance of the communication protocol, the time sensitivity of the data, and the saturation of the buffer. For example, control signals requiring real-time processing have a higher priority than general data, and data from a channel whose buffer has reached near saturation is processed preferentially.

[0109] The flow control mechanism integrally supports various methods. Hardware flow control controls data flow at the physical level using RTS / CTS signals. Software flow control manages data flow through XON / XOFF characters, while buffer-based flow control automatically adjusts data flow based on the state of the receive buffer.

[0110] Various techniques are applied to optimize system performance. First, latency is minimized by optimizing data processing paths. To achieve this, data transmission paths between modules are designed to be the shortest possible distances, and unnecessary intermediate steps are eliminated.

[0111] In addition, a dynamic resource allocation method is adopted to enhance resource usage efficiency. Power consumption is reduced by disabling the clocks of unused modules, and those modules are enabled only when necessary. In this way, the power efficiency of the entire system can be maximized.

[0112] The present invention implements an efficient interrupt processing system. Interrupts generated by each communication module are managed according to priority, and interrupt processing routines are implemented with optimized code to ensure a rapid response. The system supports individual interrupts for various events, such as reception completion, transmission completion, and error occurrence, thereby enabling efficient event processing.

[0113] The system of the present invention is designed with a modular structure for future expansion. Modules within the FPGA are interconnected using standardized interfaces, and this structure facilitates the addition of new communication protocols or functions. For example, if it is necessary to support a new communication protocol, a new module that processes the protocol can be easily integrated into the existing structure.

[0114] The interface between modules consists of a data bus, control signals, and status signals, all of which follow a standardized format. The data bus can optionally use an 8-bit or 16-bit width to accommodate various data processing requirements. Control signals are used to control the operation of the module, and status signals transmit the current operating status of the module to the outside.

[0115] Self-diagnostic functions have been implemented to enhance system maintainability. Each module possesses its own status monitoring capabilities, enabling rapid identification of the cause when problems occur. Status monitoring includes key performance indicators such as communication error rates, buffer usage, and processing latency.

[0116] In addition, all configuration values ​​are stored in registers, allowing the current state to be checked and modified at any time. This enables the rapid resolution of problems that occur during system operation. The value of each register is set to a default value during system initialization and can be dynamically changed during operation.

[0117] Various techniques have been applied to optimize the overall performance of the system. The data path is designed as the shortest path to minimize latency, and the internal pipelines of each module are optimized to maximize processing efficiency. When transferring data between clock domains, efficient synchronization circuits are used to ensure stable data transmission.

[0118] The system of the present invention implements various protection mechanisms for stable operation. It includes a power monitoring circuit to ensure stable operation even in situations where the power supply is unstable, and immediately switches to a safe mode if the voltage becomes unstable. In safe mode, all ongoing communications are safely terminated, and important configuration values ​​are preserved.

[0119] The stability of the system clock was also given significant consideration. A mechanism has been implemented to automatically switch to the internal backup clock if an anomaly is detected in the external clock source. This prevents system downtime caused by clock source issues.

[0120] A multi-stage verification system is implemented to ensure the integrity of communication data. Upon receiving data, the accuracy of the data is verified using error detection codes defined for each protocol. If an error is detected, a retransmission is requested, and in the event of consecutive errors, the fact is reported to the higher-level system.

[0121] Integrity checks are also performed on the transmitted data. It verifies that there is no data corruption during the transfer from the data buffer to the actual transmitter, and if necessary, adds error correction codes before transmission.

[0122] The operating status of the system is monitored in real time, and dedicated registers are implemented for this purpose. These registers store information such as the current communication status, the occurrence of errors, and buffer status, and external systems can read this data to determine the system's status.

[0123] The system of the present invention can be utilized in various industrial fields. In particular, in the field of automotive electronic systems, communication with various sensors is required, and through the system of the present invention, various automotive communication protocols such as CAN, LIN, and FlexRay can be processed in a single system.

[0124] This system is also highly applicable in the field of industrial automation. Various pieces of equipment on a production line often use different communication protocols, but the system of this invention allows for integrated control and monitoring of them. Furthermore, it can be effectively used in environments requiring real-time data collection and processing.

[0125] The system of the present invention was successfully applied to a large-scale test equipment system. This test equipment had to test devices using dozens of different communication protocols, and the configuration of the test equipment could be significantly simplified by introducing the system of the present invention.

[0126] Looking at specific application examples, a single FPGA was able to simultaneously handle various communications such as RS-232, RS-422, RS-485, SPI, and I2C, and could conduct tests while changing the speed and settings of each communication in real time. This significantly reduced the size and complexity of the system compared to the conventional method of using multiple communication modules.

[0127] Various techniques were applied to optimize performance in actual operating environments. In particular, the internal buffer size of each module was optimized to minimize data processing delays, and the CPU load was reduced by introducing the Direct Memory Access (DMA) method.

[0128] Although it is described that all components constituting the embodiments of the present invention described above are combined or operate in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all such components may be selectively combined in one or more ways to operate. Furthermore, while all such components may each be implemented as a single independent piece of hardware, they may also be implemented as a computer program having a program module that performs some or all of the combined functions in one or more pieces of hardware by selectively combining some or all of the components. Additionally, such a computer program may be stored on a computer-readable media such as a USB memory, CD disk, or flash memory, and read and executed by a computer to implement the embodiments of the present invention. Magnetic recording media, optical recording media, etc., may be included as recording media for the computer program.

[0129] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications, changes, and substitutions within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments and accompanying drawings. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

Claim 1 A digital transmission and reception control device comprises: a control computer that transmits a communication setting message; a plurality of inspection targets, each including a memory in which information regarding a communication method, a master / slave status, and a transmission speed is stored; and a Field Programmable Gate Array (FPGA), wherein the FPGA comprises: a first register for clock selection and activation; a second register for setting a communication method; a third register for setting the direction of an input / output signal; and a fourth register for setting a connection configuration. A digital transmission and reception control device comprising a plurality of banks and a plurality of modules, wherein the FPGA receives a communication setting message via Ethernet from a control computer, reads information from the memory of the inspection target, selects and activates one of a plurality of external clock sources through the first register, sets one of a plurality of communication methods and a master / slave state through the second register, sets the direction of an input / output signal according to the master / slave state through the third register, and sets the interconnection relationship between the plurality of banks and the plurality of modules through the fourth register, thereby performing communication with the plurality of inspection targets in a single slot or performing communication through the same pin as the inspection targets provided in each of the plurality of slots. Claim 2 A digital transmission and reception control device according to claim 1, wherein the plurality of external clock sources have different frequencies, and the FPGA sets the transmission speed according to the frequency of the selected external clock source. Claim 3 A digital transmission and reception control device according to claim 1, comprising a clock selection register and a clock enable register, wherein the clock selection register selects one of the plurality of external clock sources and the clock enable register sets whether the selected external clock source is enabled. Claim 4 A digital transmission and reception control device according to claim 1, wherein the second register sets one of a master or slave mode for each of the plurality of modules. Claim 5 A digital transmission and reception control device according to claim 1, wherein the third register includes a Port Direction Table Register that is set as an output signal for a module set in master mode and as an input signal for a module set in slave mode. Claim 6 A digital transmission and reception control device according to claim 1, wherein the fourth register includes a module selection register that connects the plurality of banks and the plurality of modules in a matrix form and activates a specific connection among the connected matrices. Claim 7 A digital transmission and reception control method using a Field Programmable Gate Array (FPGA), comprising: receiving a communication setting message via Ethernet from a control computer; reading information regarding a communication method, master / slave status, and transmission speed from a memory provided in a test target based on the communication setting message; setting a first register for clock selection and activation within the FPGA based on the read information to select a specific clock source among a plurality of external clock sources and determining whether the selected clock source is activated; setting a second register for communication method setting within the FPGA based on the read information to select one of a plurality of communication methods and setting the master / slave status; setting a third register for setting the direction of input / output signals within the FPGA as an output signal in the case of master mode and as an input signal in the case of slave mode according to the set master / slave status; setting a fourth register for connection configuration setting within the FPGA to [configure] between a plurality of banks and modules An FPGA-based digital transmission and reception control method characterized by comprising: a step of determining an interconnection relationship; and a step of performing communication with a plurality of inspection targets in one slot or performing communication with inspection targets provided in each of the plurality of slots through the same pin according to the determined interconnection relationship. Claim 8 In claim 7, the clock source selection step is characterized by selecting a clock source having a frequency corresponding to the transmission speed among the plurality of external clock sources. Claim 9 In claim 7, the first register setting step is characterized by selecting one of the plurality of external clock sources through a Clock Selection Register and setting whether the selected external clock source is enabled through a Clock Enable Register. Claim 10 An FPGA-based digital transmission and reception control method according to claim 7, wherein the second register setting step sets one of a master or slave mode for each of the plurality of modules. Claim 11 FPGA-based digital transmission and reception control method according to claim 7, wherein the third register setting step is set as an output signal for a module set to the master mode and as an input signal for a module set to the slave mode through the Port Direction Table Register. Claim 12 In claim 7, the FPGA-based digital transmission and reception control method is characterized in that the fourth register setting step connects the plurality of banks and the plurality of modules in a matrix form through a Module Selection Register and activates a specific connection among the connected matrices. Claim 13 In claim 7, the communication execution step is characterized by simultaneously communicating with multiple inspection targets in a single slot using multiple different communication methods according to the determined interconnection relationship, in an FPGA-based digital transmission and reception control method.

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