Display device

Abstract

A display device according to embodiments of the present disclosure may include a substrate comprising a display area in which an image is displayed and a non-display area which is an outer area of ​​the display area, a plurality of pads disposed in a first pad area included in the non-display area, a conductive layer located in the first pad area, and an organic layer disposed in the display area and extending to the first pad area. In the first pad area, the organic layer is disposed between the substrate and the conductive layer, and at least a portion of the upper surface of the organic layer may have irregularities.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a display device. Background Technology

[0002] The display device may include a display panel and a driver integrated circuit for driving the display panel. The driver integrated circuit may be connected to the display panel through a conductive layer, such as an anisotropic conductive film.

[0003] During the manufacturing process of a display device or after manufacturing is completed, delamination between the conductive layer and the display panel may occur due to various factors.

[0004] If delamination occurs between the conductive layer and the display panel, signal transmission errors may occur between the driver integrated circuit and the display panel, potentially leading to image defects.

[0005] In addition, if delamination occurs between the conductive layer and the display panel, moisture may penetrate between the conductive layer and the display panel, leading to corrosion of the metal wiring. The problem to be solved

[0006] The embodiments of the present disclosure can provide a display device capable of preventing delamination between a display panel and a conductive layer when a driver integrated circuit is connected to a pad area of ​​a display panel through a conductive layer such as an anisotropic conductive film.

[0007] Embodiments of the present disclosure can provide a display device capable of improving signal transmission characteristics between a display panel and a driver integrated circuit.

[0008] Embodiments of the present disclosure can provide a display device capable of preventing moisture from penetrating between a display panel and a conductive layer in a pad area where a driver integrated circuit is connected to a display panel through a conductive layer such as an anisotropic conductive film.

[0009] The problems of the embodiments of the present disclosure are not limited to those mentioned in this specification, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0010] A display device according to embodiments of the present disclosure may include a substrate comprising a display area in which an image is displayed and a non-display area which is an outer area of ​​the display area, a plurality of pads disposed in a first pad area included in the non-display area, a conductive layer located in the first pad area, and an organic layer disposed in the display area and extending to the first pad area. In the first pad area, the organic layer is disposed between the substrate and the conductive layer, and at least a portion of the upper surface of the organic layer may have irregularities.

[0011] According to embodiments of the present disclosure, a display panel may include a display area and a non-display area, wherein the non-display area includes a first pad area, a conductive layer located in the first pad area, and a driver integrated circuit located in the first pad area and disposed on the conductive layer. The display panel may further include a substrate, a touch sensor disposed in the display area and disposed on the substrate, an organic layer disposed in the display area and extending into the first pad area and disposed between the substrate and the conductive layer, and a pad disposed in an opening of the organic layer and electrically connected to a bump of the driver integrated circuit. The pad may include a metal (touch metal) included in the touch sensor. Effects of the invention

[0012] According to embodiments of the present disclosure, when a driver integrated circuit is connected to a pad area of ​​a display panel through a conductive layer such as an anisotropic conductive film, a display device capable of preventing delamination between the display panel and the conductive layer can be provided.

[0013] According to embodiments of the present disclosure, a display device capable of improving signal transmission characteristics between a display panel and a driver integrated circuit can be provided.

[0014] According to embodiments of the present disclosure, a display device can be provided that prevents moisture from penetrating between a display panel and a conductive layer in a pad area where a driver integrated circuit is connected to a display panel through a conductive layer such as an anisotropic conductive film.

[0015] According to an embodiment of the present disclosure, without adding a separate configuration, in a pad area where a driver integrated circuit is connected to a display panel through a conductive layer such as an anisotropic conductive film, the structure of the organic layer of the display panel is changed to prevent delamination between the display panel and the conductive layer, thereby helping to optimize the process.

[0016] The effects of the embodiments of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0017] The content of this disclosure will be more fully understood from the detailed description and accompanying drawings provided below, which are provided solely for illustrative purposes and are not intended to limit the content of this disclosure. FIG. 1 is a system configuration diagram of a display device according to embodiments of the present disclosure. FIG. 2 shows a display panel according to embodiments of the present disclosure. FIG. 3 shows a display device according to embodiments of the present disclosure. FIG. 4 is a cross-sectional view of a display panel according to embodiments of the present disclosure. FIG. 5 shows a non-display area of ​​a display panel according to embodiments of the present disclosure. FIG. 6 is a cross-sectional view of a first pad region and a second pad region of a display panel according to embodiments of the present disclosure. FIG. 7 is an enlarged cross-sectional view of a portion of a first pad area of ​​a display panel according to embodiments of the present disclosure. FIG. 8 is a cross-sectional view showing a first anti-peeling structure in a first pad area of ​​a display panel according to embodiments of the present disclosure. FIGS. 9a, FIGS. 9b, and FIGS. 9c are examples of the first anti-peeling structure. FIG. 10 is a cross-sectional view showing a second anti-peeling structure in a first pad area of ​​a display panel according to embodiments of the present disclosure. FIGS. 11a, FIGS. 11b, and FIGS. 11c are examples of a second anti-peeling structure. FIG. 12 is a plan view showing a portion of the first pad area of ​​a display panel according to embodiments of the present disclosure. FIGS. 13 to 15 are cross-sectional views taken along the DD' line, EE' line, and FF' line of FIG. 12, respectively. Specific details for implementing the invention

[0018] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0019] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0020] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0021] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0022] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0023] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0024] FIG. 1 is a system configuration diagram of a display device according to embodiments of the present disclosure.

[0025] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110) and a display driving circuit for driving the display panel (110). The display driving circuit may include a data driving circuit (120), a gate driving circuit (130), and a controller (140), etc.

[0026] The display panel (110) may include a display area (DA) where an image can be displayed and a non-display area (NDA) which is an outer area of ​​the display area (DA). The display panel (110) may include a substrate (111), a plurality of subpixels (SP) disposed on the substrate (111), and a plurality of signal wires. The substrate (111) may include a display area (DA) and a non-display area (NDA).

[0027] The display area (DA) may also be referred to as the active area and may include a plurality of subpixels (SP) for image display. The non-display area (NDA) is an area where no image is displayed and may also be referred to as the bezel (or bezel area). The non-display area (NDA) may include a pad area in which pads for electrically connecting a driving circuit are arranged.

[0028] For example, the display device (100) according to the embodiments of the present disclosure may be a display device (e.g., a liquid crystal display device, etc.) in which the display panel (110) does not emit light on its own. For another example, the display device (100) according to the embodiments of the present disclosure may be a self-emitting display device in which the display panel (110) emits light on its own. If the display device (100) according to the embodiments of the present disclosure is a self-emitting display device, each of the plurality of subpixels (SP) may include a light-emitting element.

[0029] If the display device (100) according to the embodiments of the present disclosure is a self-emissive display device, for example, the display device (100) according to the embodiments of the present disclosure may be an organic light-emitting display device in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device (100) according to the embodiments of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is implemented as an inorganic-based light-emitting diode. As another example, the display device (100) according to the embodiments of the present disclosure may be a quantum dot display device in which the light-emitting element is implemented as a quantum dot, which is a semiconductor crystal that emits light on its own. As another example, the display device (100) according to the embodiments of the present disclosure may be a micro light-emitting diode (Micro LED) display device or a mini LED display device.

[0030] Various types of signal lines for driving a plurality of subpixels (SP) may be arranged on the substrate (111) of the display panel (110). For example, the various types of signal lines may include a plurality of data lines (DL) that transmit data signals (also called data voltages or image signals) to a plurality of subpixels (SP), and a plurality of gate lines (GL) that transmit gate signals (also called scan signals) to a plurality of subpixels (SP).

[0031] For example, multiple data lines (DL) and multiple gate lines (GL) may intersect each other. Each of the multiple data lines (DL) may be arranged while extending in a first direction (e.g., column direction or row direction). Each of the multiple gate lines (GL) may be arranged while extending in a second direction different from the first direction (e.g., row direction or column direction). The angle formed by the first direction and the second direction may be vertical (or 90 degrees) or may be an angle different from vertical.

[0032] The data driving circuit (120) can output data signals to a plurality of data lines (DL). The data driving circuit (120) receives digital image data (DATA) from the controller (140), converts the received image data (DATA) into an analog data signal (or also called a data voltage), and outputs the data signal to a plurality of data lines (DL).

[0033] For example, the data driving circuit (120) may be connected to the display panel (110) by a Tape Automated Bonding (TAB) method, connected to the bonding pads of the display panel (110) by a Chip On Glass (COG) or Chip On Panel (COP) method, or implemented by a Chip On Film (COF) method and connected to the display panel (110), but is not limited thereto.

[0034] The data driving circuit (120) may be connected to one side (e.g., the upper side or the lower side) or both sides (e.g., the upper side and the lower side) of the display panel (110), or it may be connected to two or more of the four sides of the display panel (110). For example, the data driving circuit (120) may be connected to or placed in the non-display area (NDA) of the display panel (110). For another example, the data driving circuit (120) may be connected to or placed in the display area (DA) of the display panel (110).

[0035] The gate driving circuit (130) is a circuit for driving a plurality of gate lines (GL) and can output gate signals to the plurality of gate lines (GL). The gate driving circuit (130) receives a first gate voltage corresponding to a turn-on voltage (or also called a turn-on level voltage) and a second gate voltage corresponding to a turn-off voltage (or also called a turn-off level voltage) together with various gate driving control signals (GCS), generates gate signals including a section having the first gate voltage and a section having the second gate voltage for a certain period of time (e.g., one frame time), and can supply the generated gate signals to the plurality of gate lines (GL). For example, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. For another example, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage.

[0036] The gate driving circuit (130) can be embedded in the display panel (110) as a Gate In Panel (GIP) type. When the gate driving circuit (130) is of the Gate In Panel type, the gate driving circuit (130) can be formed on the substrate (111) of the display panel (110) during the manufacturing process of the display panel (110). When the gate driving circuit (130) is of the Gate In Panel type, the gate driving circuit (130) can be referred to as a Gate-in-Panel Circuit (GIPC).

[0037] For example, the gate driving circuit (130) may be placed in the non-display area (NDA) of the display panel (110). For another example, the gate driving circuit (130) may be placed in all or part of the display area (DA) of the display panel (110). When the gate driving circuit (130) is placed in the display area (DA) of the display panel (110), the gate driving circuit (130) may be vertically overlapped with the subpixels (SP) placed in the display area (DA).

[0038] The gate driving circuit (130) may include a plurality of transistors. For example, the plurality of transistors included in the gate driving circuit (130) may include a first active layer made of a first semiconductor material.

[0039] For example, a plurality of transistors included in subpixels (SP) arranged in a display area (DA) may include a first active layer made of a first semiconductor material. For another example, a plurality of transistors included in subpixels (SP) may include a second active layer made of a second semiconductor material. For yet another example, a plurality of transistors included in subpixels (SP) may include a transistor having a first active layer made of a first semiconductor material and a transistor having a second active layer made of a second semiconductor material. For example, the first semiconductor material and the second semiconductor material may be substantially the same. For yet another example, the first semiconductor material and the second semiconductor material may be different from each other.

[0040] The controller (140) receives input image data from the host system (150) and can supply image data (DATA) to the data driving circuit (120) based on the input image data.

[0041] The controller (140) can supply a data drive control signal (DCS) to the data drive circuit (120) to control the driving of the data drive circuit (120), and can supply a gate drive control signal (GCS) to the gate drive circuit (130) to control the driving of the gate drive circuit (130).

[0042] The controller (140) is mounted on a printed circuit board (e.g., a flexible printed circuit board) and can be electrically connected to a data driving circuit (120) and a gate driving circuit (130) through the printed circuit board.

[0043] The display device (100) according to the embodiments of the present disclosure may be a mobile terminal such as a smartphone or tablet, or a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display of various types and sizes capable of displaying information or images.

[0044] FIG. 2 shows a display panel (110) according to embodiments of the present disclosure.

[0045] Referring to FIG. 2, a display panel (110) according to embodiments of the present disclosure may include a substrate (111) disposed on a plurality of subpixels (SP) and an encapsulation layer (200) on the substrate (111). The encapsulation layer (200) may also be referred to as an encapsulation substrate or an encapsulation portion, etc.

[0046] In the case where the display device (100) according to the embodiments of the present disclosure is a self-emissive display device, each of the plurality of subpixels (SP) disposed on the substrate (111) may include a light-emitting element (ED) and a subpixel circuit (SPC) for driving the light-emitting element (ED). The subpixel circuit (SPC) can drive the light-emitting element (ED) by supplying a driving current to the light-emitting element (ED) at a predetermined timing. The light-emitting element (ED) can be driven by the driving current to emit light.

[0047] A subpixel circuit (SPC) may include a plurality of transistors for driving a light-emitting element (ED) and at least one capacitor. The plurality of transistors may include a driving transistor (DT) for driving the light-emitting element (ED) and a scan transistor (ST) that is turned on or turned off according to a scan signal (SC). The driving transistor (DT) may supply a driving current to the light-emitting element (ED). The scan transistor (ST) may be configured to control the electrical state of a corresponding node within the subpixel circuit (SPC) or to control the state or operation of the driving transistor (DT). At least one capacitor may include a storage capacitor (Cst) for maintaining a constant voltage during a frame.

[0048] To drive a subpixel (SP), a data signal (VDATA), which is an image signal, and a scan signal (SC), which is a type of gate signal, may be applied to the subpixel (SP). Additionally, to drive the subpixel (SP), a common voltage may be applied to the subpixel (SP). The common voltage may include a first common voltage (VSS) and a second common voltage (VDD). For example, the first common voltage (VSS) may be a low-potential power supply voltage, and the second common voltage (VDD) may be a high-potential power supply voltage.

[0049] The light-emitting element (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE). The intermediate layer (EL) may be placed between the pixel electrode (PE) and the common electrode (CE).

[0050] For example, the pixel electrode (PE) may be an electrode placed in each subpixel (SP), and the common electrode (CE) may be an electrode placed in common across multiple subpixels (SP). In one example, the pixel electrode (PE) may be an anode and the common electrode (CE) may be a cathode. In another example, the pixel electrode (PE) may be a cathode and the common electrode (CE) may be an anode.

[0051] When the light-emitting element (ED) is an organic light-emitting element, the intermediate layer (EL) may include a light-emitting layer (EML) and a common intermediate layer (EL_COM). The common intermediate layer (EL_COM) may include a first common intermediate layer (COM1) between the pixel electrode (PE) and the light-emitting layer (EML), and a second common intermediate layer (COM2) between the light-emitting layer (EML) and the common electrode (CE).

[0052] The light-emitting layer (EML) may be disposed for each subpixel (SP) or commonly disposed across multiple subpixels (SP). The common intermediate layer (EL_COM) may be commonly disposed across multiple subpixels (SP). For example, the first common intermediate layer (COM1) may include a hole injection layer (HIL), an electron blocking layer (EBL), and a hole transfer layer (HTL). The second common intermediate layer (COM2) may include an electron transfer layer (ETL), a hole blocking layer (HBL), and an electron injection layer (EIL).

[0053] For example, a common electrode (CE) may be electrically connected to a first common voltage line (VSSL). A first common voltage (VSS), which is a type of common voltage, may be applied to the common electrode (CE) through the first common voltage line (VSSL). A pixel electrode (PE) may be electrically connected directly or indirectly (through another transistor) to a first node (Na) of a driving transistor (DT) of each subpixel (SP). The first common voltage (VSS) may also be described as a low potential power supply voltage or low potential voltage, and the first common voltage line (VSSL) may also be described as a low potential power supply voltage line or low potential voltage line.

[0054] For example, the light-emitting element (ED) may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting element, a micro LED, or a mini LED. For example, if the light-emitting element (ED) is an organic light-emitting diode (OLED), the intermediate layer (EL) in the light-emitting element (ED) may include an intermediate layer (EL) containing organic material.

[0055] The driving transistor (DT) can be connected between the second common voltage line (VDDL) and the light-emitting element (ED).

[0056] The driving transistor (DT) may include a first node (Na), a second node (Nb), and a third node (Nc). The first node (Na) may be electrically connected to a light-emitting element (ED), the second node (Nb) may receive a data signal (VDATA), and the third node (Nc) may receive a second common voltage (VDD), which is another type of common voltage, from a second common voltage line (VDDL). The driving transistor (DT) may be connected to the first node (Na) and the third node (Nc). The second common voltage (VDD) may also be described as a high potential power supply voltage or a high potential voltage, and the second common voltage line (VDDL) may also be described as a high potential power supply voltage line or a high potential voltage line.

[0057] In the driving transistor (DT), the second node (Nb) may be a gate node, the first node (Na) may be a source node or a drain node, and the third node (Nc) may be a drain node or a source node.

[0058] The scan transistor (ST) may be a switching transistor for transmitting a data signal (VDATA), which is an image signal, to a second node (Nb), which is a gate node of the driving transistor (DT). The scan transistor (ST0) is turned on and off by a scan signal (SC), which is a type of gate signal applied through a scan line (SCL), which is a type of gate line (GL), thereby controlling the electrical connection between the second node (Nb) of the driving transistor (DT) and the data line (DL). The scan transistor (ST) may be connected between the data line (DL) and the second node (Nb) of the driving transistor (DT).

[0059] The storage capacitor (Cst) may be electrically connected between the first node (Na) and the second node (Nb) of the driving transistor (DT). The storage capacitor (Cst) may be an external capacitor intentionally designed outside the driving transistor (DT), rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may be located between the first node (Na) and the second node (Nb) of the driving transistor (DT).

[0060] The driving transistor (DT) and the scan transistor (ST) can each be an n-type transistor or a p-type transistor.

[0061] The display panel (110) may have a top emission structure or a bottom emission structure. If the display panel (110) has a top emission structure, at least a portion of the subpixel circuit (SPC) may overlap with at least a portion of the light-emitting element (ED) in the vertical direction. Accordingly, the area of ​​the light-emitting region may be increased and the aperture ratio may be increased. If the display panel (110) has a bottom emission structure, the subpixel circuit (SPC) may not overlap with the light-emitting element (ED) in the vertical direction.

[0062] The subpixel circuit (SPC) may have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DT, ST) and one capacitor (Cst) as shown in FIG. 2, and in some cases, may include one or more additional transistors or one or more additional capacitors.

[0063] Since the circuit elements within each subpixel (SP) (e.g., light-emitting elements (ED) implemented as organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture or oxygen, an encapsulation layer (200) can be placed on the display panel (110).

[0064] The encapsulation layer (200) can prevent external moisture or oxygen from penetrating into circuit elements (e.g., light-emitting elements (ED)). The encapsulation layer (200) can be configured in various forms so that the light-emitting elements (ED) do not come into contact with moisture or oxygen. For example, the encapsulation layer (200) can be composed of two or more layers in which an organic film and an inorganic film are alternately stacked. However, it is not limited thereto.

[0065] A display device (100) according to embodiments of the present disclosure may further include a touch sensor layer (210) in which a touch sensor is formed to provide a touch sensing function. Additionally, a display device (100) according to embodiments of the present disclosure may further include a touch sensing circuit that senses a touch sensor formed in the touch sensor layer (210) to determine whether a touch is present or a touch coordinate. For example, the touch sensing circuit may include a touch driving circuit configured to drive and sense a touch sensor formed in the touch sensor layer (210) to generate and output touch sensing data, and a touch controller configured to determine whether a touch is present or a touch coordinate using the touch sensing data.

[0066] The touch sensor layer (210) is a layer on which a touch sensor is formed, and the touch sensor may be composed of a plurality of touch electrodes. For example, each of the plurality of touch electrodes may be configured in various structures or shapes.

[0067] For example, the touch sensor layer (210) is positioned outside the display panel (110) and may be composed of a separate touch panel different from the display panel (110). In this case, the touch panel and the display panel (110) may be manufactured separately and combined during the assembly process.

[0068] As another example, the touch sensor layer (210) may be embedded in the display panel (110). When the touch sensor layer (210) is included inside the display panel (110), the touch sensor layer (210) may be formed on the substrate (111) along with signal lines and electrodes related to display driving during the manufacturing process of the display panel (110). For example, the touch sensor layer (210) may be placed on the encapsulation layer (200).

[0069] When a touch sensor layer (210) is embedded in a display panel (110), the display panel (110) may further include, in addition to a plurality of touch electrodes corresponding to touch sensors, a plurality of touch pads to which a touch driving circuit is electrically connected, and a plurality of touch routing wires to which the plurality of touch electrodes and the plurality of touch pads are electrically connected. Here, the plurality of touch routing wires may also be referred to as a plurality of touch lines. Additionally, the plurality of touch routing wires may correspond to a plurality of touch channels.

[0070] The touch driving circuit and the touch controller may be implemented as separate devices or as a single device. Additionally, the touch driving circuit and the data driving circuit may be implemented as separate devices or as a single device.

[0071] The display device (100) may further include a power supply circuit, etc., that supplies various power to a display driving circuit and / or a touch sensing circuit. The power supply circuit may supply various voltages related to display driving and power voltages to the display driving circuit or the display panel (110).

[0072] FIG. 3 shows a display device (100) according to embodiments of the present disclosure.

[0073] Referring to FIG. 3, the substrate (111) of the display panel (110) of the display device (100) according to embodiments of the present disclosure may include a display area (DA) in which a plurality of subpixels (SP) are arranged, and a non-display area (NDA) which is an outer area of ​​the display area (DA). The substrate (111) may be a flexible substrate.

[0074] A non-display area (NDA) may include a first non-display area (NDA1) which is a peripheral area of ​​a display area (DA), a second non-display area (NDA2) including pad areas (PA1, PA2), and a bending area (BA) between the first non-display area (NDA1) and the second non-display area (NDA2).

[0075] The bending area (BA) may be an area where the substrate (111) is bent. Depending on the bending of the bending area (BA), the second non-display area (NDA2) may be located on the back of the display area (DA) and the first non-display area (NDA1). Therefore, after the manufacturing of the display device (100) is completed, when the display device (100) is viewed from the front, the second non-display area (NDA2) may not be visible. The substrate edge of the substrate (111) may be the outer border of the second non-display area (NDA2). The boundary between the first non-display area (NDA1) and the bending area (BA), or the vicinity thereof, may be the panel edge of the display panel (110) in a state where manufacturing is completed.

[0076] The second non-display area (NDA2) may include a first pad area (PA1) and a second pad area (PA2). The first pad area (PA1) may be an area closer to the display area (DA) than the second pad area (PA2). The second pad area (PA2) may be an area closer to the edge of the substrate (111) than the first pad area (PA1).

[0077] A display device (100) according to embodiments of the present disclosure may include circuits (gate driving circuit, data driving circuit, controller, touch sensing circuit, etc.) for driving a display panel (110).

[0078] According to the example of FIG. 3, the gate driving circuit (130) can be implemented as a gate-in-panel (GIP) type gate-in-panel circuit (GIPC) embedded in the display panel (110). For example, the gate-in-panel circuit (GIPC) can be placed in a first non-display area (NDA1). The gate-in-panel circuit (GIPC) can be located in an outer area (i.e., the first non-display area (NDA1)) of at least one of the first and second sides of the display area (DA).

[0079] According to the example of FIG. 3, the data driving circuit (120) may be included in a Chip On Panel (COP) type driver integrated circuit (300) mounted on a display panel (110). For example, the driver integrated circuit (300) may be connected to a first pad area (PA1). For example, the driver integrated circuit (300) may include a touch driving circuit of a touch sensor circuit.

[0080] According to the example of FIG. 3, the display device (100) according to embodiments of the present disclosure may further include a printed circuit board (310) connected to a second pad area (PA2). The printed circuit board (310) may be a flexible printed circuit board (FPCB). The printed circuit board (310) may be equipped with a display controller (controller (140) of FIG. 1) related to display driving, a touch controller for touch sensing, power components, etc.

[0081] A display device (100) according to embodiments of the present disclosure may further include a first common voltage line (VSSL) disposed in a first non-display area (NDA1) and along the outer edge of a display area (DA), and a crack prevention pattern (CRP) disposed in the first non-display area (NDA1) and along the outer edge of a display area (DA). For example, the crack prevention pattern (CRP) may be disposed further outward than the first common voltage line (VSSL).

[0082] FIG. 4 is a cross-sectional view of a display panel (110) according to embodiments of the present disclosure. FIG. 4 may be a cross-sectional view taken along the line AA' of FIG. 3.

[0083] A display panel (110) according to embodiments of the present disclosure may include a substrate (111), a transistor portion, a light-emitting element portion, and an encapsulation portion.

[0084] The substrate (111) may be a single layer or a multilayer. If the substrate (111) is a multilayer, the substrate (111) may include a first substrate (401), a substrate intermediate layer (402), and a second substrate (403). For example, the first substrate (401) and the second substrate (403) may each be a polyimide (PI) layer, and the substrate intermediate layer (402) may be an inorganic insulating layer.

[0085] A substrate intermediate layer (402) may be located between the first substrate (401) and the second substrate (403). The substrate intermediate layer (402) may block charges from affecting transistors placed on the second substrate (403) through the second substrate (403), which is a polyimide layer. The substrate intermediate layer (402) may block moisture components from penetrating upward through the first substrate (401). For example, the substrate intermediate layer (402) may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, and may be formed as a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0086] The transistor section may include a transistor insulating layer stack (TFT_IOL) on a substrate (111), transistors (TFT1, TFT2), a storage capacitor (Cst), and various electrodes or signal wirings.

[0087] A transistor insulating layer stack (TFT_IOL) may include insulating layers necessary to form transistors (TFT1, TFT2). The insulating layers included in the transistor insulating layer stack (TFT_IOL) may include a first buffer layer (411), a first gate insulating layer (412), a first interlayer insulating layer (413), a second buffer layer (421), a second gate insulating layer (422), and a second interlayer insulating layer (423), etc. For example, the insulating layers included in the transistor insulating layer stack (TFT_IOL) may be inorganic layers.

[0088] The transistors (TFT1, TFT2) may include a first transistor (TFT1) and a second transistor (TFT2).

[0089] The first transistor (TFT1) may include a first active layer (ACT1), a first electrode (E1a), a second electrode (E1b), and a third electrode (E1c). The first electrode (E1a) may be a gate electrode, and the second electrode (E1b) may be a source electrode or a drain electrode. The first active layer (ACT1) may include a first semiconductor material. For example, the first semiconductor material may include an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), etc.

[0090] The second transistor (TFT2) may include a second active layer (ACT2), a fourth electrode (E2a), a fifth electrode (E2b), and a sixth electrode (E2c). The fourth electrode (E2a) may be a gate electrode, the fifth electrode (E2b) may be a source electrode or a drain electrode, and the sixth electrode (E2c) may be a drain electrode or a source electrode. The second active layer (ACT2) may include a second semiconductor material. For example, the second semiconductor material may include an oxide semiconductor, amorphous silicon, polysilicon, or low-temperature polysilicon (LTPS), etc.

[0091] Each of the first transistor (TFT1) and the second transistor (TFT2) can be implemented as a p-channel transistor or an n-channel transistor.

[0092] For example, the first active layer (ACT1) of the first transistor (TFT1) and the second active layer (ACT2) of the second transistor (TFT2) may include an oxide semiconductor material. For another example, the first active layer (ACT1) of the first transistor (TFT1) and the second active layer (ACT2) of the second transistor (TFT2) may include a low-temperature polysilicon semiconductor material. For yet another example, the first active layer (ACT1) of the first transistor (TFT1) may include a low-temperature polysilicon semiconductor material, and the second active layer (ACT2) of the second transistor (TFT2) may include an oxide semiconductor material. For yet another example, the first active layer (ACT1) of the first transistor (TFT1) may include an oxide semiconductor material, and the second active layer (ACT2) of the second transistor (TFT2) may include a low-temperature polysilicon semiconductor material.

[0093] For example, all transistors placed on the display panel (110) can be implemented as transistors including an active layer made of a first semiconductor material.

[0094] As another example, all transistors placed on the display panel (110) can be implemented as transistors including an active layer made of a second semiconductor material.

[0095] As another example, the transistors placed on the display panel (110) may include a transistor having an active layer made of a first semiconductor material and a transistor having an active layer made of a second semiconductor material.

[0096] For example, transistors within each subpixel (SP) may include a transistor having an active layer made of a first semiconductor material and a transistor having an active layer made of a second semiconductor material.

[0097] For another example, the transistors within each subpixel (SP) may be transistors having an active layer made of a second semiconductor material, and the transistors included in the gate-in-panel circuit (GIPC) may be transistors having an active layer made of a first semiconductor material. For another example, the driving transistor (DT) within each subpixel (SP) may be implemented as a second transistor (TFT2), and the switching transistor (e.g., scan transistor (ST), light-emitting control transistor, etc.) within each subpixel (SP) or the transistor within the gate-in-panel circuit (GIPC of FIG. 3) may be implemented as a first transistor (TFT1).

[0098] The second active layer (ACT2) of the second transistor (TFT2) can be located higher from the substrate (111) than the first active layer (ACT1) of the first transistor (TFT1).

[0099] For example, the storage capacitor (Cst) may be disposed within various metal layers within the display panel (110), and the storage capacitor (Cst) may include a first capacitor electrode (CAPE1) and a second capacitor (CAPE2).

[0100] The light-emitting element portion may include a plurality of light-emitting elements (ED) disposed on the planarization layer (430). Each of the plurality of light-emitting elements (ED) may include a pixel electrode (PE), an intermediate layer (EL), and a common electrode (CE).

[0101] The encapsulation portion may include an encapsulation layer (200) on a plurality of light-emitting elements (ED). The encapsulation layer (200) may be a single layer or a multilayer.

[0102] In addition to the encapsulation layer (200), the encapsulation section may further include a dam section to prevent the material constituting the encapsulation layer (200) from overflowing. For example, the dam section may include a first dam (DAM1) and a second dam (DAM2). The first dam (DAM1) may be located closer to the display area (DA) than the second dam (DAM2). Each of the first dam (DAM1) and the second dam (DAM2) may be composed of at least one of an organic insulating material forming the second flattening layer (432), an organic insulating material forming the bank (440), and an organic insulating material forming the spacer (450). For example, the first dam (DAM1) may include a first bottom dam (440a) comprising an organic insulating material forming the bank (440), and a first top dam (450a) comprising an organic insulating material forming the spacer (450). The second dam (DAM2) may include a second lower dam (432b) comprising an organic insulating material forming the second flattening layer (432), a second middle dam (440b) comprising an organic insulating material forming the bank (440), and a third upper dam (450b) comprising an organic insulating material forming the spacer (450).

[0103] Below, the structure of the display panel (110) will be described in more detail with reference to FIG. 4.

[0104] A first buffer layer (411) may be disposed on a substrate (111). The first buffer layer (411) may be a single layer or a multilayer. For example, if the first buffer layer (411) is a multilayer, the first buffer layer (411) may include a lower buffer layer (411a) and an upper buffer layer (411b). The lower buffer layer (411a) may be composed of one or two layers.

[0105] The first active layer (ACT1) of the first transistor (TFT1) may be disposed on the first buffer layer (411). The first active layer (ACT1) may include a channel region where a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0106] A first gate insulating layer (412) may be disposed on the first active layer (ACT1) of the first transistor (TFT1). A first gate electrode (E1a) of the first transistor (TFT1) may be disposed on the first gate insulating layer (412). A first interlayer insulating layer (413) may be disposed on the first gate electrode (E1a) of the first transistor (TFT1). Here, the metal layer on which the first gate electrode (E1a) of the first transistor (TFT1) is disposed may be referred to as the “first gate metal layer.”

[0107] A second buffer layer (421) can be placed on the first interlayer insulating layer (413).

[0108] A second active layer (ACT2) of a second transistor (TFT2) may be disposed on a second buffer layer (421). The second active layer (ACT2) may include a channel region where a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0109] The second gate insulating layer (422) may be placed on the second active layer (ACT2) of the second transistor (TFT2). The second gate electrode (E2a) of the second transistor (TFT2) may be placed thereon. The second interlayer insulating layer (423) may be placed on the second gate electrode (E2a) of the second transistor (TFT2). Here, the second gate electrode (E2a) of the second transistor (TFT2) may be referred to as the “second gate metal layer.”

[0110] The first source electrode (E1b) and the first drain electrode (E1c) of the first transistor (TFT1), and the second source electrode (E2b) and the second drain electrode (E2c) of the second transistor (TFT2) can be placed on the second interlayer insulating layer (423).

[0111] The first source electrode (E1b) and the first drain electrode (E1c) of the first transistor (TFT1) can be connected to the source connection region and the drain connection region of the first active layer (ACT1), respectively, through holes in the second interlayer insulating layer (423), the second gate insulating layer (422), the second buffer layer (421), the first interlayer insulating layer (413), and the first gate insulating layer (412).

[0112] The second source electrode (E2b) and the second drain electrode (E2c) of the second transistor (TFT2) can be connected to the source connection region and the drain connection region of the second active layer (ACT2), respectively, through holes in the second interlayer insulating layer (423) and the second gate insulating layer (422).

[0113] The first source electrode (E1b) and the first drain electrode (E1c) of the first transistor (TFT1), and the second source electrode (E2b) and the second drain electrode (E2c) of the second transistor (TFT2) include a “first source-drain metal” and may be disposed within the “first source-drain metal layer”.

[0114] For example, a storage capacitor (Cst) may be formed by a first capacitor electrode (CAPE1) and a second capacitor electrode (CAPE2). In some cases, the storage capacitor (Cst) may be formed by three or more capacitor electrodes, or two or more capacitors may be connected in parallel.

[0115] Each of the first capacitor electrode (CAPE1) and the second capacitor electrode (CAPE2) may be disposed on various metal layers disposed within the display panel (110). For example, the first capacitor electrode (CAPE1) may be disposed within the first gate metal layer, comprising the same first gate metal as the first gate electrode (E1a) of the first transistor (TFT1) on the first gate insulating layer (412). For example, the second capacitor electrode (CAPE2) may be disposed on the first interlayer insulating layer (413).

[0116] The second source electrode (E2b) of the second transistor (TFT2) may be electrically connected to the second capacitor electrode (CAPE2) through holes in the second interlayer insulating layer (423), the second gate insulating layer (422), and the second buffer layer (421).

[0117] The transistor portion may further include a first shield pattern (BSM1) disposed on the substrate (111). The first shield pattern (BSM1) may overlap with the first active layer (ACT1) of the first transistor (TFT1). The first shield pattern (BSM1) may be disposed below the first active layer (ACT1) of the first transistor (TFT1). For example, the first shield pattern (BSM1) may be disposed between the substrate (111) and the first buffer layer (411), or between the lower buffer layer (411a) and the upper buffer layer (411b).

[0118] The transistor portion may further include a second shield pattern (BSM2) disposed on the substrate (111). The second shield pattern (BSM2) may overlap with the second active layer (ACT2) of the second transistor (TFT2). The second shield pattern (BSM2) may be disposed below the second active layer (ACT2) of the second transistor (TFT2). For example, the second shield pattern (BSM2) may be disposed within a metal layer between the first interlayer insulating layer (413) and the second buffer layer (421). The second shield pattern (BSM2) may be disposed within the same metal layer as the second capacitor (CAPE2). As another example, the second shield pattern (BSM2) may be disposed within the same first gate metal layer as the first gate electrode (E1a) of the first transistor (TFT1).

[0119] The flattening layer (430) may be placed on the first transistor (TFT1) and the second transistor (TFT2) and may be placed below the light-emitting element (ED). The flattening layer (430) may be an organic layer (organic insulating layer) containing an organic insulating material. In one example, the flattening layer (430) may be composed of a single layer. In another example, the flattening layer (430) may include two layers. The flattening layer (430) may include a first flattening layer (431) and a second flattening layer (432). In another example, the flattening layer (430) may include three or more layers.

[0120] The first flattening layer (431) may be disposed on the first source electrode (E1b) and the first drain electrode (E1c) of the first transistor (TFT1) and the second source electrode (E2b) and the second drain electrode (E2c) of the second transistor (TFT2). For example, the first flattening layer (431) may be disposed on the first transistor (TFT1) and the second transistor (TFT2).

[0121] A connecting electrode (RE) can be placed on the first flattening layer (431). The connecting electrode (RE) can electrically connect the first source electrode (E1b) of the first transistor (TFT1) and the pixel electrode (PE). The connecting electrode (RE) can be electrically connected to the second source electrode (E2b) of the second transistor (TFT2) through a hole in the first flattening layer (431). The second source electrode (E2b) of the second transistor (TFT2) can be electrically connected to the second capacitor electrode (CAPE2) of the storage capacitor (Cst).

[0122] The connecting electrode (RE) may be disposed within the second source-drain metal layer on the first flattening layer (431) and may include the second source-drain metal.

[0123] A second flattening layer (432) may be disposed on a connecting electrode (RE). A light-emitting element may be disposed on the second flattening layer (432). A light-emitting element (ED) may be formed on the second flattening layer (432). The light-emitting region of the light-emitting element (ED) may be formed in an area where the pixel electrode (PE), the intermediate layer (EL), and the common electrode (CE) overlap and are in contact.

[0124] The pixel electrode (PE) is placed on the second flattening layer (432) and can be electrically connected to the connecting electrode (RE) through a hole in the second flattening layer (432).

[0125] A bank (440) may be placed on a pixel electrode (PE). An opening of the bank (440) may expose a portion of the pixel electrode (PE) to form a light-emitting region. An opening of the bank (440) may overlap with a portion of the pixel electrode (PE). For example, the bank (440) may be composed of a material containing black pigment, etc., or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or a photosensitive polymer. If the bank (440) is composed of a material containing black pigment or black dye, etc., it may be a black bank. If the bank (440) is composed of a material containing black pigment or black dye, it may block light from the outside or block light reflected from the outside, so the brightness of the display device (100) may be further improved.

[0126] An intermediate layer (EL) of the light-emitting element (ED) can be placed on a part of the pixel electrode (PE) and on the bank (440). A common electrode (CE) can be placed on the intermediate layer (EL).

[0127] Additional spacers (450) may be placed on the bank (440).

[0128] The encapsulation portion is disposed on the light-emitting element portion and may be located on the common electrode (CE). The encapsulation portion may include an encapsulation layer (200) formed on the common electrode (CE). The encapsulation layer (200) may be composed of a single layer or multiple layers.

[0129] For example, the bag layer (200) may include a first bag layer (461), a second bag layer (462), and a third bag layer (463). For example, the first bag layer (461) and the third bag layer (463) may include an inorganic bag layer, and the second bag layer (462) may include an organic bag layer.

[0130] A display panel (110) according to embodiments of the present disclosure may include a touch sensor layer (210) disposed on a sealing layer (200) and having a touch sensor formed thereon.

[0131] The touch sensor layer (210) may include a plurality of touch electrodes (TE) corresponding to the touch sensor, and may include at least one touch metal layer for forming the plurality of touch electrodes (TE).

[0132] For example, the touch sensor layer (210) may include a first touch metal layer in which a plurality of first touch metals (TM1) are disposed for forming a plurality of touch electrodes (TE), and a second touch metal layer in which a plurality of second touch metals (TM2) are disposed. In this case, the touch sensor layer (210) may further include an inter-touch layer insulating layer (472) disposed between the first touch metal layer and the second touch metal layer.

[0133] For example, the first touch metal layer may be a bridge metal layer, and the second touch metal layer may be a sensor metal layer. In this case, a plurality of second touch metals (TM2) disposed within the second touch metal layer may be sensor metals forming a touch sensor, and a plurality of first touch metals (TM1) disposed within the first touch metal layer may be bridge metals electrically connecting the plurality of second touch metals (TM2). For example, two or more second touch metals (TM2) and at least one first touch metal (TM1) may form a first touch electrode (TE1). In this case, two or more second touch metals (TE2) may be electrically connected by at least one first touch metal (TM1).

[0134] The touch sensor layer (210) may further include a touch buffer layer (471) disposed on the encapsulation layer (200). The touch buffer layer (471) may be disposed between the encapsulation layer (200) and the touch metal layer. For example, a first touch metal layer may be disposed on the touch buffer layer (471), and a touch layer inter-layer insulating layer (472) may be disposed on the first touch metal layer.

[0135] The touch sensor layer (210) may further include a touch protection layer (473) disposed over the touch metal layer. For example, the touch protection layer (473) may be disposed on the second touch metal layer.

[0136] For example, the touch buffer layer (471) may be an inorganic layer containing an inorganic insulating material or an organic layer containing an organic insulating material, the touch interlayer insulating layer (472) may be an inorganic layer containing an inorganic insulating material or an organic layer containing an organic insulating material, and the touch protection layer (473) may be an organic layer containing an organic insulating material.

[0137] For example, at least one of the touch buffer layer (471) and the touch layer inter-layer insulation layer (472) may be extended from the display area (DA) to the non-display area (NDA). The touch protection layer (473) may be extended from the display area (DA) to the non-display area (NDA).

[0138] The touch routing wiring (TL) can electrically connect the touch electrode (TE) and the touch pad (TP). The touch routing wiring (TL) may be composed of at least one of the first touch metal (TM1) and the second touch metal (TM2).

[0139] For example, the touch routing wiring (TL) may be composed of a first touch metal (TM1), the touch routing wiring (TL) may be composed of a second touch metal (TM2), or the first touch metal (TM1) and the second touch metal (TM2). When one touch routing wiring (TL) is composed of the first touch metal (TM1) and the second touch metal (TM2), the first touch metal (TM1) and the second touch metal (TM2) constituting one touch routing wiring (TL) may be electrically connected through a hole in the inter-touch insulating layer (472).

[0140] For example, the touch routing wiring (TL) may include a wiring section (TLa) made of a first touch metal (TM1), a wiring section (TLb) made of a second touch metal (TM2), and a wiring section (TLc) made of a second source-drain metal.

[0141] For example, a single touch routing line (TL) may include multiple line sections, and each of the multiple line sections may be a single line section or a dual line section. Here, a single line section is a line section with one signal path, and a dual line section may be a line section with two signal paths connected in parallel.

[0142] The touch routing wiring (TL) is arranged along the slope of the encapsulation layer (200) and can extend past the top of the dams (DAM1, DAM2) to the touch pad (TP).

[0143] The touch buffer layer (471) may have an opening that exposes at least a portion of the touch pad (TP). The touch routing wiring (TL) may be electrically connected to the touch pad (TP) through the opening of the touch buffer layer (471). The touch interlayer insulation layer (472) is placed on the touch routing wiring (TL) and may be extended to the area where the touch pad (TP) is placed. The touch protection layer (473) may be placed only in the display area (DA), or may be extended to the non-display area (NDA) and placed on top of the touch routing wiring (TL). In some cases, the touch protection layer (473) may be further extended to the top of the touch pad (TP).

[0144] Each of the plurality of touch electrodes (TE) may be a mesh-type electrode having a plurality of openings. In this case, each of the plurality of touch electrodes (TE) may be composed of at least one second touch metal (TM2).

[0145] A plurality of first touch metals (TM1) and a plurality of second touch metals (TM2) can be arranged so as not to overlap with the light-emitting element (ED). A plurality of first touch metals (TM1) and a plurality of second touch metals (TM2) can overlap with the bank (440). Accordingly, the light-emitting efficiency of the light-emitting element (ED) can be improved.

[0146] The display panel (110) may further include a connection pattern that electrically connects a common electrode (CE) and a first common voltage wiring (VSSL). The connection pattern may include a first connection pattern (CP1) made of the same metal as the pixel electrode (PE). The connection pattern may further include a second connection pattern (CP2) that connects the first connection pattern (CP1) and the first common voltage wiring (VSSL). For example, the second connection pattern (CP2) may be made of a second source-drain metal. The first common voltage wiring (VSSL) may be made of a first source-drain metal. At least a portion of the first connection pattern (CP1) and the second connection pattern (CP2) may be placed in a first non-display area (NDA1).

[0147] At least one of the first common voltage wiring (VSSL) and the second connection pattern (CP2) may pass under at least one of the first dam (DAM1) and the second dam (DAM2). Accordingly, at least one of the first common voltage wiring (VSSL) and the second connection pattern (CP2) may overlap with at least one of the first dam (DAM1) and the second dam (DAM2).

[0148] Various power lines (VL) other than the first common voltage line (VSSL) may be placed in the non-display area (NDA).

[0149] FIG. 5 shows a non-display area (NDA) of a display panel (110) according to embodiments of the present disclosure.

[0150] A non-display area (NDA) may include a first non-display area (NDA1) located around a display area (DA), a second non-display area (NDA2) including pad areas (PA1, PA2), and a bending area (BA) between the first non-display area (NDA1) and the second non-display area (NDA2).

[0151] The second non-display area (NDA2) may include a first pad area (PA1) to which a driver integrated circuit (300) is connected and a second pad area (PA2) to which a printed circuit board (310) is connected.

[0152] The second non-display area (NDA2) may further include a link area (LA) in which link lines are placed. The link lines may electrically connect pads placed in the first pad area (PA1) to circuits or signal wiring placed in the display area (DA) and the first non-display area (NDA1). For example, the link lines may include data link lines that connect a data pad placed in the first pad area (PA1) to a data line placed in the display area (DA). For example, the link lines may further include signal wiring that connects a pad placed in the first pad area (PA1) to a gate-in-panel circuit (GIPC) placed in the first non-display area (NDA1).

[0153] The second non-display area (NDA2) may further include an electrostatic discharge area (EDA) where electrostatic prevention patterns are placed.

[0154] Meanwhile, in the display device (100) according to the embodiments of the present disclosure, a driving circuit including a data driving circuit (120), etc., may be implemented as a driver integrated circuit in the form of an integrated circuit and connected to a first pad area (PA1) of a display panel (110). The driver integrated circuit may be connected to the display panel (110) through a conductive layer such as an anisotropic conductive film (ACF). At this time, a delamination phenomenon may occur between the conductive layer such as an anisotropic conductive film and the display panel (110). Such delamination phenomenon may cause signal transmission errors or lead to moisture penetrating between the conductive layer such as an anisotropic conductive film and the display panel (110). As a result, defects in the display device (100) or image abnormalities may occur.

[0155] Accordingly, the display device (100) according to the embodiments of the present disclosure may have a peel-prevention structure capable of preventing peeling between a conductive layer, such as an anisotropic conductive film, and a display panel (110). Hereinafter, a peel-prevention structure between a conductive layer and a display panel (110) according to the embodiments of the present disclosure will be described.

[0156] In the following description, reference is made to FIGS. 1 through 5. The laminated structure in the cross-sectional view of FIG. 4 can be applied in the same way below. Therefore, the same description may be omitted.

[0157] FIG. 6 is a cross-sectional view of a first pad area (PA1) and a second pad area (PA2) of a display panel (110) according to embodiments of the present disclosure. FIG. 7 is an enlarged cross-sectional view of a portion of the first pad area (PA1) of a display panel (110) according to embodiments of the present disclosure.

[0158] A display device (100) according to embodiments of the present disclosure may include a substrate (111) comprising a display area (DA) on which an image is displayed and a non-display area (NDA) which is an outer area of ​​the display area (DA); a plurality of pads (DP, IP, INP) disposed in a first pad area (PA1) included in the non-display area (NDA); a conductive layer (600) located in the first pad area (PA1); and an organic layer disposed in the display area (DA) and extending to the first pad area (PA1). Here, the organic layer may include at least one of a flattening layer (430) and a touch protection layer (473). For example, the flattening layer (430) may include a first flattening layer (431) and a second flattening layer (432).

[0159] For example, the conductive layer (600) may be an anisotropic conductive film (ACF) containing conductive balls (CB). For example, to connect a driver integrated circuit (300) to a display panel (110), an anisotropic conductive film is formed on a first pad area (PA1), and when the driver integrated circuit (300) is pressed onto the anisotropic conductive film, the pad placed in the first pad area (PA1) and the bump of the driver integrated circuit (300) can be electrically connected by the conductive balls (CB) included in the anisotropic conductive film.

[0160] For example, the conductive layer (600) may contain organic material.

[0161] According to the display device (100) according to embodiments of the present disclosure, in the first pad area (PA1), the organic layer may be disposed between the substrate (111) and the conductive layer (600) and may have an upper surface having an irregularity (irregularity pattern) formed thereon. Here, the irregularity (irregularity pattern) may be a regular pattern or an irregular random pattern.

[0162] When a plurality of organic layers are disposed between the substrate (111) and the conductive layer (600), irregularities may be formed on the upper surface of the uppermost organic layer among the plurality of organic layers. A structure in which irregularities are formed on the upper surface of the organic layer between the substrate (111) and the conductive layer (600) is called a peel-prevention structure.

[0163] According to the anti-peeling structure according to the embodiments of the present disclosure, the organic layer of the display panel (110) can be bonded more strongly with the conductive layer (600), thereby preventing peeling between the display panel (110) and the conductive layer (600). As a result, signal transmission characteristics between the display panel and the driver integrated circuit can be improved, and moisture penetration between the display panel (110) and the conductive layer (600) can also be prevented.

[0164] Hereinafter, a peel-prevention structure according to the embodiments of the present disclosure will be described in more detail.

[0165] A display device (100) according to embodiments of the present disclosure may further include a touch sensor disposed in a display area (DA) and a touch protection layer (473) disposed on the touch sensor and extending to a first pad area (PA1). In the first pad area (PA1), the touch protection layer (473) is an organic layer disposed between a substrate (111) and a conductive layer (600), and at least a portion of the upper surface of the touch protection layer (473) may have irregularities. Here, the touch sensor may be composed of at least one of a first touch metal (TM1) and a second touch metal (TM2) (see FIG. 4).

[0166] A display device (100) according to embodiments of the present disclosure may further include a transistor (TFT1, TFT2) disposed in a display area (DA), a light-emitting element (ED) disposed in the display area (DA), and a flattening layer (430) disposed between the transistor (TFT1, TFT2) and the light-emitting element (ED) and extended to a first pad area (PA1) (see FIG. 4). In the first pad area (PA1), the flattening layer (430) is an organic layer disposed between a substrate (111) and a conductive layer (600), and at least a portion of the upper surface of the flattening layer (430) may have irregularities. Here, the flattening layer (430) may be a second flattening layer (432).

[0167] A display device (100) according to embodiments of the present disclosure may further include an inorganic layer having irregularities corresponding to irregularities, disposed between an organic layer and a conductive layer (600) in a first pad area (PA1). Here, the inorganic layer may include at least one of a touch buffer layer (471) and an inter-touch layer insulating layer (472).

[0168] A display device (100) according to embodiments of the present disclosure may further include a transistor (TFT1, TFT2) disposed on a substrate (111) located in a display area (DA), a flattening layer (430) disposed on the transistor (TFT1, TFT2), a light-emitting element (ED) disposed on the flattening layer (430) located in the display area (DA), an encapsulation layer (200) disposed on the light-emitting element (ED), a touch sensor disposed on the encapsulation layer (200) located in the display area (DA), and a touch protection layer (473) disposed on the touch sensor. Here, the touch sensor may be composed of at least one of a first and second touch metal (TM1, TM2).

[0169] The flattening layer (430) and the touch protection layer (473) may include an organic insulating material. At least one of the flattening layer (430) and the touch protection layer (473) may be included in an organic layer that extends from the display area (DA) to the first pad area (PA1) and forms a peel-resistant structure.

[0170] Each of the touch protection layer (473) and the flattening layer (430) extends to the first pad area (PA1) and can be disposed between the substrate (111) and the conductive layer (600) in the first pad area (PA1).

[0171] Referring to FIGS. 6 and 7, the first pad area (PA1) may include an area where a touch protection layer (473) is disposed. In the area where the touch protection layer (473) is disposed, the touch protection layer (473) may be an organic layer having a peel-prevention structure formed therein, as it is the uppermost organic layer disposed between the substrate (111) and the conductive layer (600). The first pad area (PA1) may include an area where a touch protection layer (473) is disposed. In the area where the touch protection layer (473) is disposed, the touch protection layer (473) may have an upper surface (473s) that overlaps with the conductive layer (600), and the upper surface (473s) may have irregularities.

[0172] As described above, in the first pad area (PA1), the upper surface (473s) of the touch protection layer (473) may be formed with irregularities, and this structure may be referred to as the first peel-off prevention structure (610). According to the first peel-off prevention structure (610) according to the embodiments of the present disclosure, peeling between the touch protection layer (473) and the conductive layer (600) in the first pad area (PA1) can be prevented.

[0173] The first pad area (PA1) may include an area where a touch protection layer (473) is disposed. In the area where the touch protection layer (473) is disposed within the first pad area (PA1) (i.e., the area where the first anti-peeling structure (610) is formed), the flattening layer (430), which includes at least one of the first flattening layer (431) and the second flattening layer (432), may not be an organic layer with an anti-peeling structure formed therein, as it is not the uppermost organic layer disposed between the substrate (111) and the conductive layer (600). Accordingly, in the area (610) where the touch protection layer (473) is disposed within the first pad area (PA1), the second flattening layer (432) included in the flattening layer (430) has a first upper surface (432s1) disposed below the touch protection layer (473), and the first upper surface (432s1) may not have any irregularities.

[0174] Referring to FIGS. 6 and 7, the touch protection layer (473) and the flattening layer (430) each extend to a first pad area (PA1) and can be disposed between the substrate (111) and the conductive layer (600) in the first pad area (PA1).

[0175] The first pad area (PA1) may include an area where the touch protection layer (473) is not placed. In the area within the first pad area (PA1) where the touch protection layer (473) is not placed, the second flattening layer (432) included in the flattening layer (430) may be an organic layer having a peel-prevention structure formed therein, as it is the uppermost organic layer placed between the substrate (111) and the conductive layer (600). In the area within the first pad area (PA1) where the touch protection layer (473) is not placed, the second flattening layer (432) included in the flattening layer (430) has a second upper surface (432s2) that overlaps with the conductive layer (600), and the second upper surface (432s2) may have irregularities.

[0176] As described above, in the first pad area (PA1), the structure in which the second upper surface (432s2) of the second flattening layer (432) has irregularities formed thereon can be referred to as the second anti-peeling structure (620). According to the second anti-peeling structure (620) according to the embodiments of the present disclosure, peeling between the second flattening layer (432) and the conductive layer (600) in the first pad area (PA1) can be prevented.

[0177] A display device (100) according to embodiments of the present disclosure may further include a touch buffer layer (471) on an encapsulation layer (200), a first touch metal (TM1) on the touch buffer layer (471), an inter-touch layer insulating layer (472) on the first touch metal (TM1), and a second touch metal (TM2) on the inter-touch layer insulating layer (472).

[0178] The touch protection layer (473) may be placed on the second touch metal (TM2). The first touch metal (TM1) and the second touch metal (TM2) may form a touch sensor.

[0179] At least one of the touch buffer layer (471) and the touch layer inter-layer insulating layer (472) comprises an inorganic insulating material and can extend from the display area (DA) to the first pad area (PA1).

[0180] In the first pad area (PA1), at least one of the touch buffer layer (471) and the touch layer inter-layer insulating layer (472) is disposed between the second flattening layer (432) and the touch protection layer (473), and can be disposed between the second flattening layer (432) and the conductive layer (600).

[0181] In the area where the touch protection layer (473) is disposed within the first pad area (PA1), that is, in the area where the first peel-off prevention structure (610) is formed, the touch protection layer (473) has an upper surface that overlaps with the conductive layer (600), and the upper surface may have irregularities. In this case, at least one of the touch buffer layer (471) and the touch interlayer insulating layer (472) may be disposed between the flattening layer (430) and the touch protection layer (473) and may not have irregularities.

[0182] In the area where the touch protection layer (473) is not disposed within the first pad area (PA1), that is, in the area where the second peel-off prevention structure (620) is formed, the flattening layer (430) has an upper surface that overlaps with the conductive layer (600), and the upper surface may have irregularities. In this case, at least one of the touch buffer layer (471) and the touch interlayer insulating layer (472) is disposed between the flattening layer (430) and the conductive layer (600), and may have irregularities corresponding to the irregularities on the upper surface of the flattening layer (430).

[0183] The first pad area (PA1) may include a plurality of first pads corresponding to data pads (DP), a plurality of second pads corresponding to inspection pads (IP), and a third pad corresponding to input pads (INP).

[0184] Data pads (DP) may be pads for outputting data signals (data voltages) to data lines (DL). Test pads (IP) may be pads used during the inspection process in the panel manufacturing process. Input pads (INP) may be pads into which a signal output from the printed circuit board (130) is input.

[0185] Each of the plurality of first pads corresponding to the data pads (DP) can be electrically connected to the data bumps (BUMP_D) of the driver integrated circuit (300). Each of the plurality of first pads corresponding to the data pads (DP) may include at least one of three metal patterns (DPa, DPb, DPc). Here, the three metal patterns (DPa, DPb, DPc) may include a first metal pattern (DPa) composed of a first source-drain metal layer, a second metal pattern (DPb) composed of a second source-drain metal layer, and a third metal pattern (DPc) composed of a touch metal layer (including at least one of the first touch metal layer and the second touch metal layer) for forming a touch sensor.

[0186] Data link lines electrically connected to a plurality of first pads may be metal patterns (MP) placed on one of the metal layers located between the insulating layers included in the transistor insulating layer stack (TFT_IOL).

[0187] The third pads corresponding to the input pads (INP) can be electrically connected to the input bumps (BUMP_IN) of the driver integrated circuit (300). The third pad corresponding to the input pads (INP) may include at least one of three metal patterns (INPa, INPb, INPc). Here, the three metal patterns (INPa, INPb, INPc) may include a fourth metal pattern (INPa) composed of a first source-drain metal layer, a fifth metal pattern (INPb) composed of a second source-drain metal layer, and a sixth metal pattern (INPc) composed of a touch metal layer (including at least one of the first touch metal layer and the second touch metal layer) for forming a touch sensor.

[0188] The display panel (110) may include a transistor insulating layer stack (TFT_IOL) between the substrate (111) and the first planarization layer (431). For example, the transistor insulating layer stack (TFT_IOL) may include a first buffer layer (411), a first gate insulating layer (412), a first interlayer insulating layer (413), a second buffer layer (421), a second gate insulating layer (422), and a second interlayer insulating layer (423). The first buffer layer (411) may include a lower buffer layer (411a) and an upper buffer layer (411b). The lower buffer layer (411a) may include a first lower buffer layer (411a_1) and a second lower buffer layer (411a_2).

[0189] Various metal layers and semiconductor layers may exist in the transistor insulating layer stack (TFT_IOL). A first active layer (ACT1) may be placed between a first buffer layer (411) and a first gate insulating layer (412), a first gate metal layer (GAT1) may be placed between a first gate insulating layer (412) and a first interlayer insulating layer (413), an additional metal layer (TM) may be placed between a first interlayer insulating layer (413) and a second buffer layer (421), a second active layer (ACT2) may be placed between a second buffer layer (421) and a second gate insulating layer (422), and a second gate metal layer (GAT2) may be placed between a second gate insulating layer (422) and a second interlayer insulating layer (423).

[0190] A signal wiring electrically connected to at least one pad placed in the first pad region (PA1) may be composed of various metal layers present in the transistor insulation layer stack (TFT_IOL). For example, a signal wiring electrically connected to at least one pad placed in the first pad region (PA1) may be a gate metal pattern (GMP) composed of a first gate metal layer (GAT1).

[0191] FIG. 8 is a cross-sectional view showing a first anti-peeling structure (610) in a first pad area (PA1) of a display panel (110) according to embodiments of the present disclosure. FIG. 9a, FIG. 9b and FIG. 9c are cross-sectional views of a portion of FIG. 8 (800) as examples of the first anti-peeling structure (610).

[0192] In the first pad area (PA1), the first peel-off prevention structure (610) may be a structure in which irregularities are formed on the upper surface (473s) of the touch protection layer (473), which is the uppermost organic layer below the conductive layer (600).

[0193] In the touch protection layer (473), which is the uppermost organic layer below the conductive layer (600), the portion overlapping with the conductive layer (600) includes a concave portion and a convex portion, so that at least a portion of the upper surface (473s) of the touch protection layer (473) has irregularities, and the conductive layer (600) may be inserted into the concave portion.

[0194] The irregularities formed on at least a portion of the upper surface (473s) of the touch protection layer (473) may be one of a curved wave shape (Fig. 9a), a trapezoidal shape (Fig. 9b), and a square shape (Fig. 9c).

[0195] FIG. 10 is a cross-sectional view showing a second anti-peeling structure (620) in a first pad area (PA1) of a display panel (110) according to embodiments of the present disclosure. FIG. 11a, FIG. 11b and FIG. 11c are cross-sectional views of a portion of FIG. 10 (1000) as examples of the second anti-peeling structure (620).

[0196] In the first pad area (PA1), the second anti-peeling structure (620) may be a structure in which irregularities are formed on the second upper surface (432s2) of the second flattening layer (432), which is the uppermost organic layer below the conductive layer (600).

[0197] The second upper surface (432s2) of the second flattening layer (432), which is the uppermost organic layer below the conductive layer (600), has a portion that overlaps with the conductive layer (600) that includes a concave portion and a convex portion, so that at least a portion of the second upper surface (432s2) of the second flattening layer (432) has irregularities, and the conductive layer (600) may be inserted into the concave portion.

[0198] The shape of the irregularities formed on at least a portion of the second upper surface (432s2) of the second flattening layer (432) may be one of a curved wave shape (Fig. 11a), a trapezoidal shape (Fig. 11b), and a square shape (Fig. 11c).

[0199] FIG. 12 is a plan view showing a portion (500) of a first pad area (PA1) of a display panel (110) according to embodiments of the present disclosure. FIG. 13 is a cross-sectional view taken along the line DD' of FIG. 12. FIG. 14 is a cross-sectional view taken along the line EE' of FIG. 12. FIG. 15 is a cross-sectional view taken along the line FF' of FIG. 12.

[0200] Referring to FIGS. 12 to 15, a portion of the first pad area (PA1) (500) may include input pads (INP) to which signal wirings electrically connected to a second pad area (PA2) adjacent to the edge of the substrate (111) are connected, and data pads (DP1, DP2, DP3) to which data link lines (DLL1, DLL2, DLL3) electrically connected to data lines (DL) placed in the display area (DA) are connected.

[0201] Signal wires connected to input pads (INP) may include gate drive signal wires (GDSL) for transmitting gate drive related signals to a gate-in-panel circuit (GIPC). For example, gate drive related signals may include a first gate voltage (high level gate voltage) corresponding to a turn-on voltage (or also called a turn-on level voltage), a second gate voltage (low level gate voltage) corresponding to a turn-off voltage (or also called a turn-off level voltage), and clock signals.

[0202] Referring to FIGS. 12 to 15, a portion of the first pad area (PA1) (500) may include inspection pads (IP) used during the inspection process in the panel manufacturing process.

[0203] Each of the plurality of pads (DP, IP, INP) may include at least one of a first metal layer, a second metal layer, and a third metal layer. For example, the first metal layer may be a first source-drain metal layer on which the source electrode or drain electrode of a transistor (TFT1, TFT2) is disposed. The second metal layer may be a second source-drain metal layer on which a connecting electrode is disposed to electrically connect the source electrode or drain electrode of a transistor (TFT1, TFT2) and the pixel electrode of a light-emitting element (ED). The third metal layer may be a touch metal layer on which a touch sensor is formed (including at least one of the first touch metal layer and the second touch metal layer).

[0204] At least one of the plurality of pads (DP, IP, INP) may include a metal identical to the first touch metal or the second touch metal.

[0205] Referring to FIGS. 12 and 13, a plurality of pads (DP, IP, INP) may include a third pad (INP) into which a signal output from a printed circuit board (310) is input. The printed circuit board (310) is included in a non-display area (NDA) and may be connected to a second pad area (PA2) that is different from a first pad area (PA1).

[0206] The third pad (INP) may include at least one of a metal pattern (INPa) composed of a first metal layer, a metal pattern (INPb) composed of a second metal layer, and a metal pattern (INPc) composed of a third metal layer.

[0207] At least a portion of the third pad (INP) may overlap with the irregularities on the upper surface of the second flattening layer (432).

[0208] The signal line (GDSL) can electrically connect the printed circuit board (310) and the third pad (INP). For example, the signal line (GDSL) can be composed of a metal layer (e.g., a first gate metal layer (GAT1)) that is closer to the substrate (111) than the first source-drain metal layer.

[0209] Referring to FIGS. 12 and 14, a plurality of pads (DP, IP, INP) may include a second pad (IP) that overlaps with the flattening layer (430). For example, the second pad (IP) may be an inspection pad.

[0210] The second pad (IP) includes at least one of a metal pattern constituting the first metal layer and a metal pattern constituting the second metal layer, but does not include a metal pattern constituting the third metal layer.

[0211] The second pad (IP) can overlap with the irregularities on the upper surface of the flattening layer (430).

[0212] Referring to FIGS. 12 and 15, a plurality of pads (DP, IP, INP) may include a plurality of first pads (DP1, DP2, DP3) located at an opening of the planarization layer (430). Each of the plurality of first pads (DP1, DP2, DP3) may include a metal pattern (DP1a, DP2a, DP3a) composed of a first metal layer, a metal pattern (DP1b, DP2b, DP3b) composed of a second metal layer, and a metal pattern (DP1c, DP2c, DP3c) composed of a third metal layer.

[0213] Each of the multiple first pads (DP1, DP2, DP3) can receive a data voltage from the driver integrated circuit (300).

[0214] Multiple data link lines (DLL1, DLL2, DLL3) are located in a non-display area (NDA) and can electrically connect multiple data lines (DL) located in a display area (DA) and multiple first pads (DP1, DP2, DP3).

[0215] Each of the multiple data link lines (DLL1, DLL2, DLL3) may be composed of a metal layer (e.g., a first gate metal layer (GAT1)) that is closer to the substrate (111) than the first source-drain metal layer.

[0216] A display device (100) according to embodiments of the present disclosure includes a display area (DA) and a non-display area (NDA), and the non-display area (NDA) may include a display panel (110) including a first pad area (PA1), a conductive layer (600) located in the first pad area (PA1) and including conductive balls (CB), and a driver integrated circuit (300) located in the first pad area (PA1) and disposed on the conductive layer (600).

[0217] The display panel (110) may further include a substrate (111), a touch sensor disposed in a display area (DA) and on the substrate (111), an organic layer (e.g., a planarization layer) disposed in the display area (DA) and extending to a first pad area (PA1) and disposed between the substrate (111) and the conductive layer (600), and a pad (DP, INP) disposed in the first pad area (PA1), disposed at an opening of the organic layer (e.g., a planarization layer) and electrically connected to a bump (BUMP_D, BUMP_IN) of a driver integrated circuit (300) (see FIG. 6).

[0218] The pad (DP, INP) may include one of the first and second touch metals included in the touch sensor. In the first pad area (PA1), the organic layer may have an upper surface having irregularities formed thereon.

[0219] In the first pad region (PA1), the organic layer having an upper surface with irregularities formed thereon may be the uppermost organic layer among the organic layers disposed between the substrate (111) and the conductive layer (600) in the first pad region (PA1). For example, the organic layer having an upper surface with irregularities formed thereon in the first pad region (PA1) may be one of the touch protection layer (473) and the second flattening layer (432).

[0220] According to embodiments of the present disclosure, when a driver integrated circuit is connected to a pad area of ​​a display panel through a conductive layer such as an anisotropic conductive film, a display device capable of preventing delamination between the display panel and the conductive layer can be provided.

[0221] According to embodiments of the present disclosure, a display device capable of improving signal transmission characteristics between a display panel and a driver integrated circuit can be provided.

[0222] According to embodiments of the present disclosure, a display device can be provided that prevents moisture from penetrating between a display panel and a conductive layer in a pad area where a driver integrated circuit is connected to a display panel through a conductive layer such as an anisotropic conductive film.

[0223] According to an embodiment of the present disclosure, without adding a separate configuration, in a pad area where a driver integrated circuit is connected to a display panel through a conductive layer such as an anisotropic conductive film, the structure of the organic layer of the display panel is changed to prevent delamination between the display panel and the conductive layer, thereby helping to optimize the process.

[0224] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments.

Claims

Claim 1 A display device comprising: a substrate including a display area where an image is displayed and a non-display area which is an outer area of ​​the display area; a plurality of pads disposed in a first pad area included in the non-display area; a conductive layer located in the first pad area; and an organic layer disposed in the display area and extending to the first pad area, wherein in the first pad area, the organic layer is disposed between the substrate and the conductive layer, and at least a portion of the upper surface of the organic layer has irregularities. Claim 2 A display device according to claim 1, further comprising: a touch sensor disposed in the display area; and a touch protection layer disposed on the touch sensor and extending to the first pad area, wherein in the first pad area, the touch protection layer is an organic layer disposed between the substrate and the conductive layer, and at least a portion of the upper surface of the touch protection layer has irregularities. Claim 3 A display device according to claim 1, further comprising: a transistor disposed in the display area; a light-emitting element disposed in the display area; and a planarization layer disposed between the transistor and the light-emitting element and extending to the first pad area, wherein in the first pad area, the planarization layer is an organic layer disposed between the substrate and the conductive layer, and at least a portion of the upper surface of the planarization layer has irregularities. Claim 4 A display device according to claim 1, further comprising an inorganic layer disposed between the organic layer and the conductive layer in the first pad region, and having irregularities corresponding to irregularities formed on at least a portion of the upper surface of the organic layer. Claim 5 A display device according to claim 1, further comprising: a transistor located in the display area and disposed on the substrate; a planarization layer disposed on the transistor; a light-emitting element located in the display area and disposed on the planarization layer; an encapsulation layer disposed on the light-emitting element; a touch sensor located in the display area and disposed on the encapsulation layer; and a touch protection layer disposed on the touch sensor, wherein at least one of the planarization layer and the touch protection layer extends from the display area to the first pad area and has an upper surface having irregularities formed in the first pad area. Claim 6 A display device according to claim 5, wherein in the area where the touch protection layer is disposed within the first pad area, the touch protection layer has an upper surface that overlaps with the conductive layer, and the upper surface has irregularities, and the flattening layer has a first upper surface disposed below the touch protection layer, and the first upper surface does not have irregularities. Claim 7 A display device according to claim 5, wherein in the area within the first pad area where the touch protection layer is not disposed, the planarization layer has a second upper surface that overlaps with the conductive layer, and the second upper surface has irregularities. Claim 8 A display device according to claim 5, further comprising: a touch buffer layer on the encapsulation layer; a first touch metal on the touch buffer layer; an inter-touch insulating layer on the first touch metal; and a second touch metal on the inter-touch insulating layer, wherein the touch protection layer is disposed on the second touch metal, and at least one of the first touch metal and the second touch metal constitutes the touch sensor, and at least one of the touch buffer layer and the inter-touch insulating layer comprises an inorganic insulating material, and extends from the display area to the first pad area. Claim 9 A display device according to claim 8, wherein in the area where the touch protection layer is disposed within the first pad area, the touch protection layer has an upper surface that overlaps with the conductive layer, and the upper surface has irregularities, and at least one of the touch buffer layer and the touch layer inter-layer insulating layer is disposed between the flattening layer and the touch protection layer and has no irregularities. Claim 10 A display device according to claim 8, wherein in the area within the first pad region where the touch protection layer is not disposed, the flattening layer has an upper surface that overlaps with the conductive layer, and the upper surface has irregularities, and at least one of the touch buffer layer and the touch layer inter-layer insulating layer is disposed between the flattening layer and the conductive layer and has irregularities corresponding to the irregularities of the upper surface of the flattening layer. Claim 11 A display device according to claim 5, wherein at least one of the plurality of pads comprises a metal included in the touch sensor. Claim 12 A display device according to claim 5, wherein the plurality of pads includes a plurality of first pads located at the opening of the flattening layer. Claim 13 A display device according to claim 5, wherein the plurality of pads includes a second pad that overlaps with the flattening layer, and the second pad overlaps with the irregularities on the upper surface of the flattening layer. Claim 14 A display device according to claim 5, further comprising a printed circuit board included in the non-display area and connected to a second pad area different from the first pad area, wherein the plurality of pads includes a third pad into which a signal output from the printed circuit board is input, and at least a portion of the third pad overlaps with the irregularities on the upper surface of the planarization layer. Claim 15 A display device according to claim 1, wherein the shape of the irregularities formed on at least a portion of the upper surface of the organic layer is one of a curved wave shape, a square shape, and a trapezoidal shape. Claim 16 A display device comprising: a display panel including a display area and a non-display area, wherein the non-display area includes a first pad area; a conductive layer located in the first pad area; and a driver integrated circuit located in the first pad area and disposed on the conductive layer, wherein the display panel further comprises: a substrate; a touch sensor disposed in the display area and disposed on the substrate; an organic layer disposed in the display area and extending into the first pad area and disposed between the substrate and the conductive layer; and a pad disposed in the first pad area, disposed at an opening of the organic layer, electrically connected to a bump of the driver integrated circuit, and comprising a touch metal included in the touch sensor. Claim 17 In claim 16, a display device having an upper surface having irregularities formed in the organic layer in the first pad area.

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