Pixel circuit, display device including the pixel circuit, and electronic device including the display device

Abstract

The pixel circuit may include a fourth transistor and a boosting capacitor. The fourth transistor may include a gate electrode that receives a first emission signal, a first electrode that receives a first power supply voltage, a second electrode connected to a second node, and a back gate electrode connected to a fourth node. The boosting capacitor may include a first electrode connected to the fourth node and a second electrode connected to the second node.

Description

Technology Field

[0001] The present invention relates to a pixel circuit, a display device including the pixel circuit, and an electronic device including the display device. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, emission lines, and pixels. The display panel driver includes a gate driver that provides a gate signal to the gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a driving control unit that controls the gate driver, the data driver, and the emission driver.

[0003] Each of the above pixels may operate on a frame basis. For example, a frame interval may include an initialization interval, a compensation interval, a data writing interval, an emission interval, etc. The initialization interval refers to a interval for initializing the state of each of the pixels so that the pixels operate accurately and stably. The compensation interval refers to a interval for compensating the threshold voltage of the driving transistor of the pixel. The data writing interval refers to a interval for writing the data voltage to the pixel. The emission interval refers to a interval in which the light-emitting element of the pixel emits light.

[0004] The operation of the pixel may vary depending on the configuration of the pixel. For example, the compensation interval and the data writing interval may not coincide in time. In this case, generally, each of the pixels may include two capacitors. When each of the pixels includes the two capacitors, an additional mask may be required or the PPI (Pitch Per Inch) may be reduced in order to design the two capacitors. The problem to be solved

[0005] One objective of the present invention is to provide a pixel circuit comprising one capacitor per pixel circuit.

[0006] Another objective of the present invention is to provide a display device including the pixel circuit.

[0007] Another objective of the present invention is to provide an electronic device including the above-mentioned display device. means of solving the problem

[0008] A pixel circuit according to embodiments for realizing one objective of the present invention described above comprises: a first transistor including a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode including a second electrode connected to a second node; a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, and a first electrode receiving the initialization voltage It includes a seventh transistor comprising an electrode and a second electrode receiving a second electrode connected to the fourth node, a storage capacitor comprising a first electrode connected to the third node and a second electrode connected to the first node, and a light-emitting element comprising an anode electrode connected to the fourth node and a cathode electrode receiving a second power supply voltage.

[0009] In one embodiment, the first reference voltage may be greater than or equal to the maximum value of the data voltage.

[0010] In one embodiment, the pixel circuit may further include an eighth transistor comprising a gate electrode receiving a second reset gate signal, a first electrode receiving a second reference voltage different from the first reference voltage, and a second electrode connected to the third node.

[0011] In one embodiment, the second reference voltage may be less than or equal to the maximum value of the data voltage.

[0012] In one embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor may be PMOS transistors.

[0013] In one embodiment, the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors.

[0014] In one embodiment, during the initialization period, the fourth transistor may be turned on to provide the initialization voltage to the first node, and the sixth transistor may be turned on to provide the first reference voltage to the third node.

[0015] In one embodiment, in the first compensation period after the initialization period, the third transistor is turned on to diode-connect the first transistor, and the sixth transistor is turned on to provide the first reference voltage to the third node.

[0016] In one embodiment, in the second compensation / data writing section after the first compensation section, the second transistor is turned on to provide the data voltage transmitted by the data line to the third node, the third transistor is turned on to diode-connect the first transistor, and the seventh transistor is turned on to provide the initialization voltage to the fourth node.

[0017] In one embodiment, in the data transmission section after the second compensation / data writing section, the eighth transistor may be turned on to provide the second reference voltage to the third node.

[0018] In one embodiment, in the light-emitting section after the data transmission section, the first transistor is turned on based on the voltage of the first node and the first power supply voltage to generate a driving current, and the first transistor and the fifth transistor are turned on so that the driving current can be provided to the light-emitting element.

[0019] In one embodiment, the pixel circuit may further include an eighth transistor comprising a gate electrode receiving the data write gate signal, a first electrode, and a second electrode connected to the third node, and a ninth transistor comprising a gate electrode receiving the first reset gate signal, a first electrode receiving a second reference voltage different from the first reference voltage, and a second electrode connected to the first electrode of the eighth transistor.

[0020] In one embodiment, the second reference voltage may be less than or equal to the maximum value of the data voltage.

[0021] In one embodiment, the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are PMOS transistors, and the third transistor, the fourth transistor, the eighth transistor, and the ninth transistor may be NMOS transistors.

[0022] In one embodiment, during the initialization period, the fourth transistor may be turned on to provide the initialization voltage to the first node, and the sixth transistor may be turned on to provide the first reference voltage to the third node.

[0023] In one embodiment, in the first compensation period after the initialization period, the third transistor is turned on to diode-connect the first transistor, and the sixth transistor is turned on to provide the first reference voltage to the third node.

[0024] In one embodiment, in the second compensation / data writing section after the first compensation section, the second transistor is turned on to provide the data voltage transmitted by the data line to the third node, the third transistor is turned on to diode-connect the first transistor, and the seventh transistor is turned on to provide the initialization voltage to the fourth node.

[0025] In one embodiment, in the data transmission section after the second compensation / data writing section, the eighth transistor and the ninth transistor may be turned on to provide the second reference voltage to the third node.

[0026] A display device according to embodiments for realizing another objective of the present invention described above includes a display panel including a pixel circuit and a display panel driving unit for driving the display panel. The pixel circuit comprises: a first transistor including a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode including a second electrode connected to a second node; a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a sixth transistor including a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node. It includes a seventh transistor including a second electrode receiving an electrode, a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node, and a light-emitting element including an anode electrode connected to the fourth node and a cathode electrode receiving a second power supply voltage.

[0027] An electronic device according to embodiments for realizing another objective of the present invention described above includes a display panel comprising a pixel circuit, a display panel driver for driving the display panel, and a processor for controlling the display panel driver. The pixel circuit comprises: a first transistor including a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode including a second electrode connected to a second node; a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a sixth transistor including a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node. It includes a seventh transistor including a second electrode receiving an electrode, a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node, and a light-emitting element including an anode electrode connected to the fourth node and a cathode electrode receiving a second power supply voltage. Effects of the invention

[0028] According to the pixel circuit, display device, and electronic device according to embodiments of the present invention, the pixel circuit can sequentially perform a first compensation operation for a threshold voltage of a first transistor, a data writing operation for the pixel circuit, and a second compensation operation for a threshold voltage of the first transistor using a first reference voltage and a second reference voltage different from the first reference voltage. Accordingly, the pixel circuit can operate normally even if it includes only one capacitor. Brief explanation of the drawing

[0029] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing an example of a pixel circuit of the display panel of Figure 1. Figure 3 is a timing diagram showing an example of the operation of the pixel circuit of Figure 2. Figure 4 is a circuit diagram showing an example of the operation of the pixel circuit of Figure 2 in the initialization section of Figure 3. FIG. 5 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 2 in the first compensation section of FIG. 3. FIG. 6 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 2 in the second compensation / data writing section of FIG. 3. Figure 7 is a circuit diagram showing an example of the operation of the pixel circuit of Figure 2 in the data transmission section of Figure 3. Figure 8 is a circuit diagram showing an example of the operation of the pixel circuit of Figure 2 in the light-emitting section of Figure 3. Figure 9 is a circuit diagram showing an example of a pixel circuit of the display panel of Figure 1. Figure 10 is a circuit diagram showing an example of a pixel circuit of the display panel of Figure 1. Figure 11 is a timing diagram showing an example of the operation of the pixel circuit of Figure 10. FIG. 12 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 10 in the initialization section of FIG. 11. FIG. 13 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 10 in the first compensation interval of FIG. 11. FIG. 14 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 10 in the second compensation / data writing section of FIG. 11. FIG. 15 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 10 in the data transmission section of FIG. 11. FIG. 16 is a circuit diagram showing an example of the operation of the pixel circuit of FIG. 10 in the light-emitting section of FIG. 11. FIG. 17 is a block diagram showing an electronic device according to embodiments of the present invention. FIG. 18 is a diagram showing an example in which the electronic device of FIG. 17 is implemented as a smartphone. FIG. 19 is a block diagram showing an electronic device according to embodiments of the present invention. Figure 20 is a schematic diagram of the electronic device of Figure 19. Specific details for implementing the invention

[0030] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0031] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0032] Referring to FIG. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), and a data driver (500). The display panel driver may further include an emission driver (600).

[0033] For example, the drive control unit (200) and the data drive unit (500) may be formed integrally. For example, the drive control unit (200), the gamma reference voltage generation unit (400), and the data drive unit (500) may be formed integrally. For example, the drive control unit (200), the gate drive unit (300), the gamma reference voltage generation unit (400), and the data drive unit (500) may be formed integrally. For example, the drive control unit (200), the gate drive unit (300), the gamma reference voltage generation unit (400), the data drive unit (500), and the emission drive unit (600) may be formed integrally. Meanwhile, a drive module in which at least the drive control unit (200) and the data drive unit (500) are formed integrally may be named a Timing Controller Embedded Data Driver (TED).

[0034] The above display panel (100) includes a display portion for displaying an image and a peripheral portion arranged adjacent to the display portion.

[0035] For example, the display panel (100) may be an organic light-emitting diode display panel including an organic light-emitting diode. As another example, the display panel (100) may be a quantum-dot organic light-emitting diode display panel including an organic light-emitting diode and a quantum-dot color filter. As yet another example, the display panel (100) may be a quantum-dot nano light-emitting diode display panel including a nano light-emitting diode and a quantum-dot color filter. As yet another example, the display panel (100) may be a liquid crystal display panel including a liquid crystal layer.

[0036] The display panel (100) comprises a plurality of gate lines (GL), a plurality of data lines (DL), a plurality of emission lines (EL), and a plurality of pixel circuits (PC) electrically connected to each of the gate lines (GL), the data lines (DL), and the emission lines (EL). The gate lines (GL) may be extended in a first direction (D1), the data lines (DL) may be extended in a second direction (D2) that intersects the first direction (D1), and the emission lines (EL) may be extended in the first direction (D1).

[0037] The drive control unit (200) receives input image data (IMG) and an input control signal (CONT) from an external device. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0038] The above driving control unit (200) generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0039] The above drive control unit (200) generates the first control signal (CONT1) to control the operation of the gate drive unit (300) based on the input control signal (CONT) and outputs it to the gate drive unit (300). The first control signal (CONT1) may include a vertical start signal and a gate clock signal.

[0040] The above drive control unit (200) generates the second control signal (CONT2) to control the operation of the data drive unit (500) based on the input control signal (CONT) and outputs it to the data drive unit (500). The second control signal (CONT2) may include a horizontal start signal and a load signal.

[0041] The above drive control unit (200) generates a data signal (DATA) based on the input image data (IMG). The above drive control unit (200) outputs the data signal (DATA) to the data drive unit (500).

[0042] The above driving control unit (200) generates the third control signal (CONT3) to control the operation of the gamma reference voltage generation unit (400) based on the input control signal (CONT) and outputs it to the gamma reference voltage generation unit (400).

[0043] The above drive control unit (200) generates the fourth control signal (CONT4) to control the operation of the emission drive unit (600) based on the input control signal (CONT) and outputs it to the emission drive unit (600).

[0044] The gate driving unit (300) generates gate signals for driving the gate lines (GL) in response to the first control signal (CONT1) received from the driving control unit (200). The gate driving unit (300) can output the gate signals to the gate lines (GL).

[0045] In one embodiment, the gate driver (300) may be integrated into the periphery of the display panel (100). In one embodiment, the gate driver (300) may be mounted on the periphery of the display panel (100).

[0046] The gamma reference voltage generation unit (400) generates a gamma reference voltage (VGREF) in response to the third control signal (CONT3) received from the driving control unit (200). The gamma reference voltage generation unit (400) provides the gamma reference voltage (VGREF) to the data driving unit (500). The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0047] For example, the gamma reference voltage generation unit (400) may be placed within the drive control unit (200) or within the data drive unit (500).

[0048] The data driving unit (500) receives the second control signal (CONT2) and the data signal (DATA) from the driving control unit (200), and receives the gamma reference voltage (VGREF) from the gamma reference voltage generation unit (400). The data driving unit (500) converts the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The data driving unit (500) outputs the data voltage to the data line (DL).

[0049] In one embodiment, the data driving unit (500) may be integrated into the periphery of the display panel (100). In one embodiment, the data driving unit (500) may be mounted on the periphery of the display panel (100).

[0050] The emission driving unit (600) generates emission signals to drive the emission lines (EL) in response to the fourth control signal (CONT4) received from the driving control unit (200). The emission driving unit (600) can output the emission signals to the emission lines (EL).

[0051] In one embodiment, the emission driving unit (600) may be integrated into the periphery of the display panel (100). In one embodiment, the emission driving unit (600) may be mounted on the periphery of the display panel (100).

[0052] In FIG. 1, for convenience of explanation, the gate driving unit (300) is shown as being positioned on the first side of the display panel (100) and the emission driving unit (600) is shown as being positioned on the second side of the display panel (100), but the present invention is not limited thereto. For example, both the gate driving unit (300) and the emission driving unit (600) may be positioned on the first side of the display panel (100). For example, both the gate driving unit (300) and the emission driving unit (600) may be positioned on both sides of the display panel (100). For example, the gate driving unit (300) and the emission driving unit (600) may be formed integrally.

[0053] FIG. 2 is a circuit diagram showing an example (PCa) of a pixel circuit (PC) of a display panel (100) of FIG. 1.

[0054] Referring to FIGS. 1 and 2, the pixel circuit (PCa) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). In one embodiment, the pixel circuit (PCa) may further include an eighth transistor (T8).

[0055] In one embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) may be PMOS transistors.

[0056] The PMOS transistor may be turned on when the gate-source voltage of the PMOS transistor is less than or equal to the threshold voltage (e.g., a negative value) of the PMOS transistor. Conversely, the PMOS transistor may be turned off when the gate-source voltage of the PMOS transistor is greater than the threshold voltage of the PMOS transistor. For example, the PMOS transistor may be turned on when a gate signal having a low level is applied to the gate electrode of the PMOS transistor. For example, the PMOS transistor may be turned off when a gate signal having a high level is applied to the gate electrode of the PMOS transistor.

[0057] The first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode receiving a first power supply voltage (ELVDD), and a second electrode connected to a second node (N2). The first transistor (T1) may be turned on based on the voltage of the first node (N1) and the first power supply voltage (ELVDD) to generate a driving current. Specifically, the first transistor (T1) may generate the driving current based on the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD). Therefore, the greater the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD), the greater the magnitude of the driving current. For example, the first transistor (T1) may be named a driving transistor.

[0058] The second transistor (T2) may include a gate electrode that receives a data write gate signal (GW), a first electrode connected to a data line (DL) that transmits a data voltage (VDATA), and a second electrode connected to a third node (N3). The second transistor (T2) may be turned on in response to the data write gate signal (GW) having a low level to provide the data voltage (VDATA) to the third node (N3). For example, the second transistor (T2) may be named a data write transistor.

[0059] The third transistor (T3) may include a gate electrode that receives a compensation gate signal (GC), a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2). The third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a low level to connect the first node (N1) and the second node (N2) to each other. That is, the third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a low level to diode-connect the first transistor (T1). For example, the third transistor (T3) may be named a compensation transistor.

[0060] The fourth transistor (T4) may include a gate electrode that receives an initialization gate signal (GI), a first electrode that receives an initialization voltage (VINT), and a second electrode connected to the first node (N1). The fourth transistor (T4) may be turned on in response to the initialization gate signal (GI) having a low level to provide the initialization voltage (VINT) to the first node (N1). For example, the fourth transistor (T4) may be named an initialization transistor.

[0061] The fifth transistor (T5) may include a gate electrode that receives an emission signal (EM), a first electrode connected to the second node (N2), and a second electrode connected to the fourth node (N4). The fifth transistor (T5) may be turned on in response to the emission signal (EM) having a low level to connect the second node (N2) and the fourth node (N4). When the fifth transistor (T5) is turned on, the fifth transistor (T5) may provide the driving current to the light-emitting element (EE). For example, the fifth transistor (T5) may be named a light-emitting control transistor.

[0062] The sixth transistor (T6) may include a gate electrode that receives a first reset gate signal (GR1), a first electrode that receives a first reference voltage (VREF1), and a second electrode connected to the third node (N3). The sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having a low level to provide the first reference voltage (VREF1) to the third node (N3). For example, the sixth transistor (T6) may be named the first reset transistor.

[0063] The seventh transistor (T7) may include a gate electrode that receives a bias gate signal (GB), a first electrode that receives the initialization voltage (VINT), and a second electrode connected to the fourth node (N4). The seventh transistor (T7) may be turned on in response to the bias gate signal (GB) having a low level to provide the initialization voltage (VINT) to the fourth node (N4). For example, the seventh transistor (T7) may be named an anode initialization transistor.

[0064] The eighth transistor (T8) may include a gate electrode that receives a second reset gate signal (GR2), a first electrode that receives a second reference voltage (VREF2) different from the first reference voltage (VREF1), and a second electrode connected to the third node (N3). The eighth transistor (T8) may be turned on in response to the second reset gate signal (GR2) having a low level to provide the second reference voltage (VREF2) to the third node (N3). For example, the eighth transistor (T8) may be named the second reset transistor.

[0065] The storage capacitor (CST) may include a first electrode connected to the third node (N3) and a second electrode connected to the first node (N1). The storage capacitor (CST) may store the data voltage (VDATA) provided to the third node (N3) or boost the voltage of the first node (N1) based on the voltage provided to the third node (N3).

[0066] The light-emitting element (EE) may include an anode electrode connected to the fourth node (N4) and a cathode electrode receiving a second power supply voltage (ELVSS). The light-emitting element (EE) may emit light based on the driving current. The larger the magnitude of the driving current, the greater the brightness corresponding to the light intensity of the light-emitting element (EE).

[0067] Figure 3 is a timing diagram showing an example of the operation of the pixel circuit (PCa) of Figure 2.

[0068] Referring to FIGS. 1 to 3, the pixel circuit (PCa) can operate on a frame basis. The frame section (FP) of the pixel circuit (PCa) may include an initialization section (INIP), a first compensation section (CMP1), a second compensation / data writing section (CMP2 / DWP), a data transmission section (DTP), and an emission section (EP).

[0069] In the above initialization section (INIP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the low level (L), the data write gate signal (GW) may have the high level (H), the second reset gate signal (GR2) may have the high level (H), the initialization gate signal (GI) may have the low level (L), the compensation gate signal (GC) may have the high level (H), and the bias gate signal (GB) may have the high level (H).

[0070] In the first compensation interval (CMP1), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the low level (L), the data write gate signal (GW) may have the high level (H), the second reset gate signal (GR2) may have the high level (H), the initialization gate signal (GI) may have the high level (H), the compensation gate signal (GC) may have the low level (L), and the bias gate signal (GB) may have the high level (H).

[0071] In the second compensation / data write interval (CMP2 / DWP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the low level (L), the second reset gate signal (GR2) may have the high level (H), the initialization gate signal (GI) may have the high level (H), the compensation gate signal (GC) may have the low level (L), and the bias gate signal (GB) may have the low level (L).

[0072] In the above data transmission section (DTP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the high level (H), the second reset gate signal (GR2) may have the low level (L), the initialization gate signal (GI) may have the high level (H), the compensation gate signal (GC) may have the high level (H), and the bias gate signal (GB) may have the high level (H).

[0073] In the above-mentioned emission section (EP), the emission signal (EM) may have the low level (L), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the high level (H), the second reset gate signal (GR2) may have the low level (L), the initialization gate signal (GI) may have the high level (H), the compensation gate signal (GC) may have the high level (H), and the bias gate signal (GB) may have the high level (H).

[0074] Figure 4 is a circuit diagram showing an example of the operation of the pixel circuit (PCa) of Figure 2 in the initialization section (INIP) of Figure 3.

[0075] Referring to FIGS. 1 to 4, in the initialization section (INIP), an initialization operation for the gate electrode of the first transistor (T1) and an initialization operation for the storage capacitor (CST) can be performed.

[0076] In the above initialization section (INIP), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having the high level (H), the fourth transistor (T4) may be turned on in response to the initialization gate signal (GI) having the low level (L), the fifth transistor (T5) may be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having the low level (L), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may have the high level (H It can be turned off in response to the second reset gate signal (GR2) above.

[0077] The fourth transistor (T4) can be turned on to provide the initialization voltage (VINT) to the first node (N1). Therefore, the voltage of the first node (N1) can be the initialization voltage (VINT). Accordingly, the voltage of the gate electrode of the first transistor (T1) can be initialized to the initialization voltage (VINT), and the voltage of the second electrode of the storage capacitor (CST) can be initialized to the initialization voltage (VINT).

[0078] The voltage of the gate electrode (i.e., the first node (N1)) of the first transistor (T1) is the initialization voltage (VINT), and the voltage of the source electrode (i.e., the first electrode) of the first transistor (T1) is the first power supply voltage (ELVDD). In this case, the gate-source voltage of the first transistor (T1) (i.e., "VINT - ELVDD") may be less than or equal to the threshold voltage of the first transistor (T1). Therefore, the first transistor (T1) can be turned on.

[0079] The sixth transistor (T6) can be turned on to provide the first reference voltage (VREF1) to the third node (N3). Therefore, the voltage of the third node (N3) can be the first reference voltage (VREF1). Accordingly, the voltage of the first electrode of the storage capacitor (CST) can be initialized to the first reference voltage (VREF1).

[0080] In this way, in the initialization section (INIP), the initialization operation for the gate electrode of the first transistor (T1) and the initialization operation for the storage capacitor (CST) can be performed.

[0081] FIG. 5 is a circuit diagram showing an example of the operation of the pixel circuit (PCa) of FIG. 2 in the first compensation interval (CMP1) of FIG. 3.

[0082] Referring to FIGS. 1 to 5, in the first compensation interval (CMP1), a first compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed.

[0083] In the first compensation interval (CMP1), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned on in response to the compensation gate signal (GC) having the low level (L), the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having the high level (H), the fifth transistor (T5) may be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having the low level (L), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may be the high It can be turned off in response to the second reset gate signal (GR2) having a level (H).

[0084] The voltage at the gate electrode (i.e., the first node (N1)) of the first transistor (T1) is the initialization voltage (VINT), and the voltage at the source electrode (i.e., the first electrode) of the first transistor (T1) is the first power supply voltage (ELVDD). In this case, the gate-source voltage (i.e., "VINT - ELVDD") of the first transistor (T1) may be less than or equal to the threshold voltage (VTH) of the first transistor (T1). Therefore, the first transistor (T1) can be turned on.

[0085] The third transistor (T3) can be turned on to connect the first node (N1) and the third node (N3). That is, the third transistor (T3) can be turned on to diode-connect the first transistor (T1).

[0086] When the first transistor (T1) is turned on and the third transistor (T3) is turned on, the voltage of the first node (N1) can be changed from the initialization voltage (VINT) to a voltage in which the threshold voltage (VTH) of the first transistor (T1) is added to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH").

[0087] In this way, in the first compensation interval (CMP1), when the first transistor (T1) is turned on and the third transistor (T3) is turned on to diode-connect the first transistor (T1), the storage capacitor (CST) can store the threshold voltage (VTH) of the first transistor (T1). Therefore, the first compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed.

[0088] Figure 6 is a circuit diagram showing an example of the operation of the pixel circuit (PCa) of Figure 2 in the second compensation / data writing section (CMP2 / DWP) of Figure 3.

[0089] Referring to FIGS. 1 to 6, in the second compensation / data writing section (CMP2 / DWP), a second compensation operation for the threshold voltage (VTH) of the first transistor (T1) may be performed, a data writing operation for the pixel circuit (PCa) may be performed, and an anode initialization operation for the light-emitting element (EE) may be performed.

[0090] In the second compensation / data write interval (CMP2 / DWP) above, the second transistor (T2) can be turned on in response to the data write gate signal (GW) having the low level (L), the third transistor (T3) can be turned on in response to the compensation gate signal (GC) having the low level (L), the fourth transistor (T4) can be turned off in response to the initialization gate signal (GI) having the high level (H), the fifth transistor (T5) can be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) can be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) can be turned on in response to the bias gate signal (GB) having the low level (L), and the eighth The transistor (T8) can be turned off in response to the second reset gate signal (GR2) having the high level (H).

[0091] The second transistor (T2) can be turned on to provide the data voltage (VDATA) transmitted by the data line (DL) to the third node (N3). Therefore, the voltage of the third node (N3) can be changed from the first reference voltage (VREF1) to the data voltage (VDATA) by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1").

[0092] When the voltage of the third node (N3) changes, the storage capacitor (CST) can boost the voltage of the first node (N1) by the changed voltage of the third node (N3). Therefore, when the voltage of the third node (N3) changes by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1"), the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1"). Accordingly, the voltage of the first node (N1) can be boosted by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1") from the voltage obtained by adding the threshold voltage (VTH) of the first transistor (T1) to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH"), so that it becomes "ELVDD + VTH + (VDATA - VREF1)".

[0093] In this case, the gate-source voltage of the first transistor (T1) may be "ELVDD + VTH + (VDATA - VREF1) - ELVDD" (i.e., "VTH + (VDATA - VREF1)"). For the compensation operation for the threshold voltage (VTH) of the first transistor (T1) to be performed, the first transistor (T1) must be turned on. For the first transistor (T1) to be turned on, the gate-source voltage of the first transistor (T1) (i.e., "VTH + (VDATA - VREF1)") must be less than or equal to the threshold voltage (VTH) of the first transistor (T1). That is, the first reference voltage (VREF1) must be greater than or equal to the data voltage (VDATA). The data voltage (VDATA) may vary depending on the grayscale of the input image data (IMG). Therefore, the first reference voltage (VREF1) must be greater than or equal to the maximum value of the data voltage (VDATA). For example, the maximum value of the data voltage (VDATA) may correspond to the maximum grayscale of the input image data (IMG).

[0094] The third transistor (T3) can be turned on to connect the first node (N1) and the third node (N3). That is, the third transistor (T3) can be turned on to diode-connect the first transistor (T1).

[0095] When the first transistor (T1) is turned on and the third transistor (T3) is turned on, the voltage of the first node (N1) can be changed from "ELVDD + VTH + (VDATA - VREF1)" to the voltage (i.e., "ELVDD + VTH") in which the threshold voltage (VTH) of the first transistor (T1) is added to the first power supply voltage (ELVDD).

[0096] The seventh transistor (T7) can be turned on to provide the initialization voltage (VINT) to the fourth node (N4). Therefore, the voltage of the fourth node (N4) can be the initialization voltage (VINT). Accordingly, the anode electrode of the light-emitting element (EE) can be initialized to the initialization voltage (VINT).

[0097] In this way, in the second compensation / data write interval (CMP2 / DWP), when the first transistor (T1) is turned on and the third transistor (T3) is turned on to diode-connect the first transistor (T1), the storage capacitor (CST) can store the threshold voltage (VTH) of the first transistor (T1). Therefore, the second compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed. Additionally, when the second transistor (T2) is turned on to provide the data voltage (VDATA) transmitted by the data line (DL) to the third node (N3), the storage capacitor (CST) can store the data voltage (VDATA). Therefore, the data write operation for the pixel circuit (PCa) can be performed. Additionally, the anode initialization operation for the light-emitting element (EE) can be performed.

[0098] Figure 7 is a circuit diagram showing an example of the operation of the pixel circuit (PCa) of Figure 2 in the data transmission section (DTP) of Figure 3.

[0099] Referring to FIGS. 1 to 7, a data transmission operation can be performed in the data transmission section (DTP).

[0100] In the above data transmission section (DTP), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having the high level (H), the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having the high level (H), the fifth transistor (T5) may be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) may be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may have the low level (L). It can be turned on in response to the second reset gate signal (GR2) above.

[0101] The eighth transistor (T8) can be turned on to provide the second reference voltage (VREF2) to the third node (N3). Therefore, the voltage of the third node (N3) can be changed from the data voltage (VDATA) to the second reference voltage (VREF2) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA").

[0102] When the voltage of the third node (N3) changes, the storage capacitor (CST) can boost the voltage of the first node (N1) by the changed voltage of the third node (N3). Therefore, when the voltage of the third node (N3) changes by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"), the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"). Accordingly, the voltage of the first node (N1) can be boosted by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA") from the voltage obtained by adding the threshold voltage (VTH) of the first transistor (T1) to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH"), so that it becomes "ELVDD + VTH + (VREF2 - VDATA)".

[0103] In this case, the gate-source voltage of the first transistor (T1) may be "ELVDD + VTH + (VREF2 - VDATA) - ELVDD" (i.e., "VTH + (VREF2 - VDATA)"). In order for the first transistor (T1) to generate the driving current during the light emission interval (EP), the first transistor (T1) must be turned on. For the first transistor (T1) to be turned on, the gate-source voltage of the first transistor (T1) (i.e., "VTH + (VREF2 - VDATA)") must be less than or equal to the threshold voltage (VTH) of the first transistor (T1). That is, the second reference voltage (VREF2) must be less than or equal to the data voltage (VDATA). The data voltage (VDATA) may vary depending on the grayscale of the input image data (IMG). Therefore, the second reference voltage (VREF2) must be less than or equal to the maximum value of the data voltage (VDATA). For example, the maximum value of the data voltage (VDATA) may correspond to the maximum grayscale of the input image data (IMG).

[0104] In this way, during the data transmission interval (DTP), the eighth transistor (T8) can be turned on to provide the second reference voltage (VREF2) to the third node (N3), and the voltage of the third node (N3) can be changed from the data voltage (VDATA) to the second reference voltage (VREF2) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"), and the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"). Accordingly, the data voltage (VDATA) can be transmitted from the third node (N3) to the first node (N1). Therefore, the data transmission operation can be performed.

[0105] FIG. 8 is a circuit diagram showing an example of the operation of the pixel circuit (PCa) of FIG. 2 in the light-emitting section (EP) of FIG. 3.

[0106] Referring to FIGS. 1 to 8, in the light-emitting section (EP), a light-emitting operation for the light-emitting element (EE) can be performed.

[0107] In the above light emission section (EP), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having the high level (H), the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having the high level (H), the fifth transistor (T5) may be turned on in response to the emission signal (EM) having the low level (L), the sixth transistor (T6) may be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may be turned on in response to the low level (L) It can be turned on in response to the second reset gate signal (GR2).

[0108] The eighth transistor (T8) can be turned on to provide the second reference voltage (VREF2) to the third node (N3). Therefore, the voltage of the third node (N3) can be maintained at the second reference voltage (VREF2).

[0109] The first transistor (T1) can be turned on based on the voltage of the first node (N1) and the first power supply voltage (ELVDD) to generate the driving current (IDR). Specifically, the first transistor (T1) can generate the driving current (IDR) based on the difference (i.e., "VTH + (VREF2 - VDATA)") between the voltage of the first node (N1) (i.e., "ELVDD + VTH + (VREF2 - VDATA)") and the first power supply voltage (ELVDD). Since the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD) includes the data voltage (VDATA), the magnitude of the driving current (IDR) may vary depending on the data voltage (VDATA).

[0110] In addition, since the first transistor (T1) as well as the fifth transistor (T5) are turned on, a line for transmitting the driving current (IDR) can be formed between the line transmitting the first power supply voltage (ELVDD) and the line transmitting the second power supply voltage (ELVSS).

[0111] Accordingly, the driving current (IDR) can be delivered to the light-emitting element (EE) along the transmission line of the driving current (IDR). The light-emitting element (EE) can emit light based on the driving current (IDR). The larger the magnitude of the driving current (IDR), the greater the brightness corresponding to the light-emitting intensity of the light-emitting element (EE).

[0112] In this way, a light emission operation for the light-emitting element (EE) can be performed in the light emission section (EP).

[0113] In summary, the pixel circuit (PCa) can sequentially perform the first compensation operation for the threshold voltage (VTH) of the first transistor (T1), the data writing operation for the pixel circuit (PCa), and the second compensation operation for the threshold voltage (VTH) of the first transistor (T1) by using the first reference voltage (VREF1) and the second reference voltage (VREF2) which is different from the first reference voltage (VREF1). Accordingly, the pixel circuit (PCa) can operate normally even if it includes only one capacitor (CST).

[0114] FIG. 9 is a circuit diagram showing an example (PCb) of a pixel circuit (PC) of a display panel (100) of FIG. 1.

[0115] Referring to FIGS. 1 through 9, the pixel circuit (PCb) of FIG. 9 is substantially identical to the pixel circuit (PCa) of FIG. 2, except for the third transistor (T3) and the fourth transistor (T4). Specifically, the third transistor (T3) and the fourth transistor (T4) included in the pixel circuit (PCa) of FIG. 2 are PMOS transistors, whereas the third transistor (T3) and the fourth transistor (T4) included in the pixel circuit (PCb) of FIG. 9 are NMOS transistors. Therefore, the operation of the pixel circuit (PCb) of FIG. 9 is substantially identical to the operation of the pixel circuit (PCa) of FIG. 2. Accordingly, a description of the operation of the pixel circuit (PCb) of FIG. 9 is omitted.

[0116] The pixel circuit (PCb) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). In one embodiment, the pixel circuit (PCa) may further include an eighth transistor (T8).

[0117] In one embodiment, the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), and the eighth transistor (T8) may be PMOS transistors, and the third transistor (T3) and the fourth transistor (T4) may be NMOS transistors.

[0118] The PMOS transistor may be turned on when the gate-source voltage of the PMOS transistor is less than or equal to the threshold voltage (e.g., a negative value) of the PMOS transistor. Conversely, the PMOS transistor may be turned off when the gate-source voltage of the PMOS transistor is greater than the threshold voltage of the PMOS transistor. For example, the PMOS transistor may be turned on when a gate signal having a low level is applied to the gate electrode of the PMOS transistor. For example, the PMOS transistor may be turned off when a gate signal having a high level is applied to the gate electrode of the PMOS transistor.

[0119] The NMOS transistor may be turned on when the gate-source voltage of the NMOS transistor is greater than or equal to the threshold voltage (e.g., a positive value) of the NMOS transistor. Conversely, the NMOS transistor may be turned off when the gate-source voltage of the NMOS transistor is less than the threshold voltage of the NMOS transistor. For example, the PMOS transistor may be turned on when a gate signal having a high level is applied to the gate electrode of the NMOS transistor. For example, the NMOS transistor may be turned off when a gate signal having a low level is applied to the gate electrode of the PMOS transistor.

[0120] The first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode receiving a first power supply voltage (ELVDD), and a second electrode connected to a second node (N2). The first transistor (T1) may be turned on based on the voltage of the first node (N1) and the first power supply voltage (ELVDD) to generate a driving current. Specifically, the first transistor (T1) may generate the driving current based on the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD). Therefore, the greater the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD), the greater the magnitude of the driving current. For example, the first transistor (T1) may be named a driving transistor.

[0121] The second transistor (T2) may include a gate electrode that receives a data write gate signal (GW), a first electrode connected to a data line (DL) that transmits a data voltage (VDATA), and a second electrode connected to a third node (N3). The second transistor (T2) may be turned on in response to the data write gate signal (GW) having a low level to provide the data voltage (VDATA) to the third node (N3). For example, the second transistor (T2) may be named a data write transistor.

[0122] The third transistor (T3) may include a gate electrode that receives a compensation gate signal (GC), a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2). The third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a high level to connect the first node (N1) and the second node (N2) to each other. That is, the third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a high level to diode-connect the first transistor (T1). For example, the third transistor (T3) may be named a compensation transistor.

[0123] The fourth transistor (T4) may include a gate electrode that receives an initialization gate signal (GI), a first electrode that receives an initialization voltage (VINT), and a second electrode connected to the first node (N1). The fourth transistor (T4) may be turned on in response to the initialization gate signal (GI) having a high level to provide the initialization voltage (VINT) to the first node (N1). For example, the fourth transistor (T4) may be named an initialization transistor.

[0124] The fifth transistor (T5) may include a gate electrode that receives an emission signal (EM), a first electrode connected to the second node (N2), and a second electrode connected to the fourth node (N4). The fifth transistor (T5) may be turned on in response to the emission signal (EM) having a low level to connect the second node (N2) and the fourth node (N4). When the fifth transistor (T5) is turned on, the fifth transistor (T5) may provide the driving current to the light-emitting element (EE). For example, the fifth transistor (T5) may be named a light-emitting control transistor.

[0125] The sixth transistor (T6) may include a gate electrode that receives a first reset gate signal (GR1), a first electrode that receives a first reference voltage (VREF1), and a second electrode connected to the third node (N3). The sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having a low level to provide the first reference voltage (VREF1) to the third node (N3). For example, the sixth transistor (T6) may be named the first reset transistor.

[0126] The seventh transistor (T7) may include a gate electrode that receives a bias gate signal (GB), a first electrode that receives the initialization voltage (VINT), and a second electrode connected to the fourth node (N4). The seventh transistor (T7) may be turned on in response to the bias gate signal (GB) having a low level to provide the initialization voltage (VINT) to the fourth node (N4). For example, the seventh transistor (T7) may be named an anode initialization transistor.

[0127] The eighth transistor (T8) may include a gate electrode that receives a second reset gate signal (GR2), a first electrode that receives a second reference voltage (VREF2) different from the first reference voltage (VREF1), and a second electrode connected to the third node (N3). The eighth transistor (T8) may be turned on in response to the second reset gate signal (GR2) having a low level to provide the second reference voltage (VREF2) to the third node (N3). For example, the eighth transistor (T8) may be named the second reset transistor.

[0128] The storage capacitor (CST) may include a first electrode connected to the third node (N3) and a second electrode connected to the first node (N1). The storage capacitor (CST) may store the data voltage (VDATA) provided to the third node (N3) or boost the voltage of the first node (N1) based on the voltage provided to the third node (N3).

[0129] The light-emitting element (EE) may include an anode electrode connected to the fourth node (N4) and a cathode electrode receiving a second power supply voltage (ELVSS). The light-emitting element (EE) may emit light based on the driving current. The larger the magnitude of the driving current, the greater the brightness corresponding to the light intensity of the light-emitting element (EE).

[0130] In summary, the pixel circuit (PCb) can sequentially perform a first compensation operation for the threshold voltage of the first transistor (T1), a data writing operation for the pixel circuit (PCb), and a second compensation operation for the threshold voltage of the first transistor (T1) by using the first reference voltage (VREF1) and the second reference voltage (VREF2) which is different from the first reference voltage (VREF1). Accordingly, the pixel circuit (PCb) can operate normally even if it includes only one capacitor (CST).

[0131] FIG. 10 is a circuit diagram showing an example (PCc) of a pixel circuit (PC) of a display panel (100) of FIG. 1.

[0132] Referring to FIGS. 1 to 10, the pixel circuit (PCc) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7). In one embodiment, the pixel circuit (PCc) may further include an eighth transistor (T8) and a ninth transistor (T9).

[0133] In one embodiment, the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be PMOS transistors, and the third transistor (T3), the fourth transistor (T4), the eighth transistor (T8), and the ninth transistor (T9) may be NMOS transistors.

[0134] The PMOS transistor may be turned on when the gate-source voltage of the PMOS transistor is less than or equal to the threshold voltage (e.g., a negative value) of the PMOS transistor. Conversely, the PMOS transistor may be turned off when the gate-source voltage of the PMOS transistor is greater than the threshold voltage of the PMOS transistor. For example, the PMOS transistor may be turned on when a gate signal having a low level is applied to the gate electrode of the PMOS transistor. For example, the PMOS transistor may be turned off when a gate signal having a high level is applied to the gate electrode of the PMOS transistor.

[0135] The NMOS transistor may be turned on when the gate-source voltage of the NMOS transistor is greater than or equal to the threshold voltage (e.g., a positive value) of the NMOS transistor. Conversely, the NMOS transistor may be turned off when the gate-source voltage of the NMOS transistor is less than the threshold voltage of the NMOS transistor. For example, the PMOS transistor may be turned on when a gate signal having a high level is applied to the gate electrode of the NMOS transistor. For example, the NMOS transistor may be turned off when a gate signal having a low level is applied to the gate electrode of the PMOS transistor.

[0136] The first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode receiving a first power supply voltage (ELVDD), and a second electrode connected to a second node (N2). The first transistor (T1) may be turned on based on the voltage of the first node (N1) and the first power supply voltage (ELVDD) to generate a driving current. Specifically, the first transistor (T1) may generate the driving current based on the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD). Therefore, the greater the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD), the greater the magnitude of the driving current. For example, the first transistor (T1) may be named a driving transistor.

[0137] The second transistor (T2) may include a gate electrode that receives a data write gate signal (GW), a first electrode connected to a data line (DL) that transmits a data voltage (VDATA), and a second electrode connected to a third node (N3). The second transistor (T2) may be turned on in response to the data write gate signal (GW) having a low level to provide the data voltage (VDATA) to the third node (N3). For example, the second transistor (T2) may be named a data write transistor.

[0138] The third transistor (T3) may include a gate electrode that receives a compensation gate signal (GC), a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2). The third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a high level to connect the first node (N1) and the second node (N2) to each other. That is, the third transistor (T3) may be turned on in response to the compensation gate signal (GC) having a high level to diode-connect the first transistor (T1). For example, the third transistor (T3) may be named a compensation transistor.

[0139] The fourth transistor (T4) may include a gate electrode that receives an initialization gate signal (GI), a first electrode that receives an initialization voltage (VINT), and a second electrode connected to the first node (N1). The fourth transistor (T4) may be turned on in response to the initialization gate signal (GI) having a high level to provide the initialization voltage (VINT) to the first node (N1). For example, the fourth transistor (T4) may be named an initialization transistor.

[0140] The fifth transistor (T5) may include a gate electrode that receives an emission signal (EM), a first electrode connected to the second node (N2), and a second electrode connected to the fourth node (N4). The fifth transistor (T5) may be turned on in response to the emission signal (EM) having a low level to connect the second node (N2) and the fourth node (N4). When the fifth transistor (T5) is turned on, the fifth transistor (T5) may provide the driving current to the light-emitting element (EE). For example, the fifth transistor (T5) may be named a light-emitting control transistor.

[0141] The sixth transistor (T6) may include a gate electrode that receives a first reset gate signal (GR1), a first electrode that receives a first reference voltage (VREF1), and a second electrode connected to the third node (N3). The sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having a low level to provide the first reference voltage (VREF1) to the third node (N3). For example, the sixth transistor (T6) may be named the first reset transistor.

[0142] The seventh transistor (T7) may include a gate electrode that receives a bias gate signal (GB), a first electrode that receives the initialization voltage (VINT), and a second electrode connected to the fourth node (N4). The seventh transistor (T7) may be turned on in response to the bias gate signal (GB) having a low level to provide the initialization voltage (VINT) to the fourth node (N4). For example, the seventh transistor (T7) may be named an anode initialization transistor.

[0143] The eighth transistor (T8) may include a gate electrode that receives the data write gate signal (GW), a first electrode, and a second electrode connected to the third node (N3).

[0144] The ninth transistor (T9) may include a gate electrode that receives the first reset gate signal (GR1), a first electrode that receives a second reference voltage (VREF2) different from the first reference voltage (VREF), and a second electrode connected to the first electrode of the eighth transistor (T8).

[0145] When the eighth transistor (T8) is turned on in response to the data write gate signal (GW) having the high level and the ninth transistor (T9) is turned on in response to the first reset gate signal (GR1) having the high level, the eighth transistor (T8) and the ninth transistor (T9) can provide the second reference voltage (VREF2) to the third node (N3).

[0146] For example, the eighth transistor (T8) may be named the second reset transistor, and the ninth transistor (T9) may be named the third reset transistor.

[0147] The storage capacitor (CST) may include a first electrode connected to the third node (N3) and a second electrode connected to the first node (N1). The storage capacitor (CST) may store the data voltage (VDATA) provided to the third node (N3) or boost the voltage of the first node (N1) based on the voltage provided to the third node (N3).

[0148] The light-emitting element (EE) may include an anode electrode connected to the fourth node (N4) and a cathode electrode receiving a second power supply voltage (ELVSS). The light-emitting element (EE) may emit light based on the driving current. The larger the magnitude of the driving current, the greater the brightness corresponding to the light intensity of the light-emitting element (EE).

[0149] Figure 11 is a timing diagram showing an example of the operation of the pixel circuit (PCc) of Figure 10.

[0150] Referring to FIGS. 1 to 11, the pixel circuit (PCc) can operate on a frame basis. The frame section (FP) of the pixel circuit (PCc) may include an initialization section (INIP), a first compensation section (CMP1), a second compensation / data writing section (CMP2 / DWP), a data transmission section (DTP), and an emission section (EP).

[0151] In the above initialization section (INIP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the low level (L), the data write gate signal (GW) may have the high level (H), the initialization gate signal (GI) may have the high level (H), the compensation gate signal (GC) may have the low level (L), and the bias gate signal (GB) may have the high level (H).

[0152] In the first compensation interval (CMP1), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the low level (L), the data write gate signal (GW) may have the high level (H), the initialization gate signal (GI) may have the low level (L), the compensation gate signal (GC) may have the high level (H), and the bias gate signal (GB) may have the high level (H).

[0153] In the second compensation / data write interval (CMP2 / DWP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the low level (L), the initialization gate signal (GI) may have the low level (L), the compensation gate signal (GC) may have the high level (H), and the bias gate signal (GB) may have the low level (L).

[0154] In the above data transmission section (DTP), the emission signal (EM) may have the high level (H), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the high level (H), the initialization gate signal (GI) may have the low level (L), the compensation gate signal (GC) may have the low level (L), and the bias gate signal (GB) may have the high level (H).

[0155] In the above-mentioned emission section (EP), the emission signal (EM) may have the low level (L), the first reset gate signal (GR1) may have the high level (H), the data write gate signal (GW) may have the high level (H), the initialization gate signal (GI) may have the low level (L), the compensation gate signal (GC) may have the low level (L), and the bias gate signal (GB) may have the high level (H).

[0156] FIG. 12 is a circuit diagram showing an example of the operation of the pixel circuit (PCc) of FIG. 10 in the initialization section (INIP) of FIG. 11.

[0157] Referring to FIGS. 1 to 12, in the initialization section (INIP), an initialization operation for the gate electrode of the first transistor (T1) and an initialization operation for the storage capacitor (CST) can be performed.

[0158] In the above initialization section (INIP), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having the low level (L), the fourth transistor (T4) may be turned on in response to the initialization gate signal (GI) having the high level (H), the fifth transistor (T5) may be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having the low level (L), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may have the high level (H The ninth transistor (T9) can be turned on in response to the data write gate signal (GW), and the ninth transistor (T9) can be turned off in response to the first reset gate signal (GR1) having the low level (L).

[0159] The fourth transistor (T4) can be turned on to provide the initialization voltage (VINT) to the first node (N1). Therefore, the voltage of the first node (N1) can be the initialization voltage (VINT). Accordingly, the voltage of the gate electrode of the first transistor (T1) can be initialized to the initialization voltage (VINT), and the voltage of the second electrode of the storage capacitor (CST) can be initialized to the initialization voltage (VINT).

[0160] The voltage of the gate electrode (i.e., the first node (N1)) of the first transistor (T1) is the initialization voltage (VINT), and the voltage of the source electrode (i.e., the first electrode) of the first transistor (T1) is the first power supply voltage (ELVDD). In this case, the gate-source voltage of the first transistor (T1) (i.e., "VINT - ELVDD") may be less than or equal to the threshold voltage of the first transistor (T1). Therefore, the first transistor (T1) can be turned on.

[0161] The sixth transistor (T6) can be turned on to provide the first reference voltage (VREF1) to the third node (N3). Therefore, the voltage of the third node (N3) can be the first reference voltage (VREF1). Accordingly, the voltage of the first electrode of the storage capacitor (CST) can be initialized to the first reference voltage (VREF1).

[0162] In this way, in the initialization section (INIP), the initialization operation for the gate electrode of the first transistor (T1) and the initialization operation for the storage capacitor (CST) can be performed.

[0163] FIG. 13 is a circuit diagram showing an example of the operation of the pixel circuit (PCc) of FIG. 10 in the first compensation interval (CMP1) of FIG. 11.

[0164] Referring to FIGS. 1 to 13, in the first compensation interval (CMP1), a first compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed.

[0165] In the first compensation interval (CMP1), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned on in response to the compensation gate signal (GC) having the high level (H), the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having the low level (L), the fifth transistor (T5) may be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) may be turned on in response to the first reset gate signal (GR1) having the low level (L), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may be the high The ninth transistor (T9) can be turned on in response to the data write gate signal (GW) having a level (H), and the ninth transistor (T9) can be turned off in response to the first reset gate signal (GR1) having a low level (L).

[0166] The voltage at the gate electrode (i.e., the first node (N1)) of the first transistor (T1) is the initialization voltage (VINT), and the voltage at the source electrode (i.e., the first electrode) of the first transistor (T1) is the first power supply voltage (ELVDD). In this case, the gate-source voltage (i.e., "VINT - ELVDD") of the first transistor (T1) may be less than or equal to the threshold voltage (VTH) of the first transistor (T1). Therefore, the first transistor (T1) can be turned on.

[0167] The third transistor (T3) can be turned on to connect the first node (N1) and the third node (N3). That is, the third transistor (T3) can be turned on to diode-connect the first transistor (T1).

[0168] When the first transistor (T1) is turned on and the third transistor (T3) is turned on, the voltage of the first node (N1) can be changed from the initialization voltage (VINT) to a voltage in which the threshold voltage (VTH) of the first transistor (T1) is added to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH").

[0169] In this way, in the first compensation interval (CMP1), when the first transistor (T1) is turned on and the third transistor (T3) is turned on to diode-connect the first transistor (T1), the storage capacitor (CST) can store the threshold voltage (VTH) of the first transistor (T1). Therefore, the first compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed.

[0170] FIG. 14 is a circuit diagram showing an example of the operation of the pixel circuit (PCc) of FIG. 10 in the second compensation / data writing section (CMP2 / DWP) of FIG. 11.

[0171] Referring to FIGS. 1 to 6, in the second compensation / data writing section (CMP2 / DWP), a second compensation operation for the threshold voltage (VTH) of the first transistor (T1) may be performed, a data writing operation for the pixel circuit (PCc) may be performed, and an anode initialization operation for the light-emitting element (EE) may be performed.

[0172] In the second compensation / data write interval (CMP2 / DWP) above, the second transistor (T2) can be turned on in response to the data write gate signal (GW) having the low level (L), the third transistor (T3) can be turned on in response to the compensation gate signal (GC) having the high level (H), the fourth transistor (T4) can be turned off in response to the initialization gate signal (GI) having the low level (L), the fifth transistor (T5) can be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) can be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) can be turned on in response to the bias gate signal (GB) having the low level (L), and the eighth The transistor (T8) can be turned off in response to the data write gate signal (GW) having the low level (L), and the ninth transistor (T9) can be turned on in response to the first reset gate signal (GR1) having the high level (H).

[0173] The second transistor (T2) can be turned on to provide the data voltage (VDATA) transmitted by the data line (DL) to the third node (N3). Therefore, the voltage of the third node (N3) can be changed from the first reference voltage (VREF1) to the data voltage (VDATA) by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1").

[0174] When the voltage of the third node (N3) changes, the storage capacitor (CST) can boost the voltage of the first node (N1) by the changed voltage of the third node (N3). Therefore, when the voltage of the third node (N3) changes by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1"), the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1"). Accordingly, the voltage of the first node (N1) can be boosted by the difference between the data voltage (VDATA) and the first reference voltage (VREF1) (i.e., "VDATA - VREF1") from the voltage obtained by adding the threshold voltage (VTH) of the first transistor (T1) to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH"), so that it becomes "ELVDD + VTH + (VDATA - VREF1)".

[0175] In this case, the gate-source voltage of the first transistor (T1) may be "ELVDD + VTH + (VDATA - VREF1) - ELVDD" (i.e., "VTH + (VDATA - VREF1)"). For the compensation operation for the threshold voltage (VTH) of the first transistor (T1) to be performed, the first transistor (T1) must be turned on. For the first transistor (T1) to be turned on, the gate-source voltage of the first transistor (T1) (i.e., "VTH + (VDATA - VREF1)") must be less than or equal to the threshold voltage (VTH) of the first transistor (T1). That is, the first reference voltage (VREF1) must be greater than or equal to the data voltage (VDATA). The data voltage (VDATA) may vary depending on the grayscale of the input image data (IMG). Therefore, the first reference voltage (VREF1) must be greater than or equal to the maximum value of the data voltage (VDATA). For example, the maximum value of the data voltage (VDATA) may correspond to the maximum grayscale of the input image data (IMG).

[0176] The third transistor (T3) can be turned on to connect the first node (N1) and the third node (N3). That is, the third transistor (T3) can be turned on to diode-connect the first transistor (T1).

[0177] When the first transistor (T1) is turned on and the third transistor (T3) is turned on, the voltage of the first node (N1) can be changed from "ELVDD + VTH + (VDATA - VREF1)" to the voltage (i.e., "ELVDD + VTH") in which the threshold voltage (VTH) of the first transistor (T1) is added to the first power supply voltage (ELVDD).

[0178] The seventh transistor (T7) can be turned on to provide the initialization voltage (VINT) to the fourth node (N4). Therefore, the voltage of the fourth node (N4) can be the initialization voltage (VINT). Accordingly, the anode electrode of the light-emitting element (EE) can be initialized to the initialization voltage (VINT).

[0179] In this way, in the second compensation / data write interval (CMP2 / DWP), when the first transistor (T1) is turned on and the third transistor (T3) is turned on to diode-connect the first transistor (T1), the storage capacitor (CST) can store the threshold voltage (VTH) of the first transistor (T1). Therefore, the second compensation operation for the threshold voltage (VTH) of the first transistor (T1) can be performed. Additionally, when the second transistor (T2) is turned on to provide the data voltage (VDATA) transmitted by the data line (DL) to the third node (N3), the storage capacitor (CST) can store the data voltage (VDATA). Therefore, the data write operation for the pixel circuit (PCa) can be performed. Additionally, the anode initialization operation for the light-emitting element (EE) can be performed.

[0180] FIG. 15 is a circuit diagram showing an example of the operation of the pixel circuit (PCc) of FIG. 10 in the data transmission section (DTP) of FIG. 11.

[0181] Referring to FIGS. 1 to 15, a data transmission operation can be performed in the data transmission section (DTP).

[0182] In the above data transmission section (DTP), the second transistor (T2) can be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) can be turned off in response to the compensation gate signal (GC) having the low level (L), the fourth transistor (T4) can be turned off in response to the initialization gate signal (GI) having the low level (L), the fifth transistor (T5) can be turned off in response to the emission signal (EM) having the high level (H), the sixth transistor (T6) can be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) can be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) has the high level (H) The branch can be turned on in response to the data write gate signal (GW), and the ninth transistor (T9) can be turned on in response to the first reset gate signal (GR1) having the high level (H).

[0183] The eighth transistor (T8) and the ninth transistor (T9) can be turned on to provide the second reference voltage (VREF2) to the third node (N3). Therefore, the voltage of the third node (N3) can be changed from the data voltage (VDATA) to the second reference voltage (VREF2) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA").

[0184] When the voltage of the third node (N3) changes, the storage capacitor (CST) can boost the voltage of the first node (N1) by the changed voltage of the third node (N3). Therefore, when the voltage of the third node (N3) changes by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"), the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"). Accordingly, the voltage of the first node (N1) can be boosted by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA") from the voltage obtained by adding the threshold voltage (VTH) of the first transistor (T1) to the first power supply voltage (ELVDD) (i.e., "ELVDD + VTH"), so that it becomes "ELVDD + VTH + (VREF2 - VDATA)".

[0185] In this case, the gate-source voltage of the first transistor (T1) may be "ELVDD + VTH + (VREF2 - VDATA) - ELVDD" (i.e., "VTH + (VREF2 - VDATA)"). In order for the first transistor (T1) to generate the driving current during the light emission interval (EP), the first transistor (T1) must be turned on. For the first transistor (T1) to be turned on, the gate-source voltage of the first transistor (T1) (i.e., "VTH + (VREF2 - VDATA)") must be less than or equal to the threshold voltage (VTH) of the first transistor (T1). That is, the second reference voltage (VREF2) must be less than or equal to the data voltage (VDATA). The data voltage (VDATA) may vary depending on the grayscale of the input image data (IMG). Therefore, the second reference voltage (VREF2) must be less than or equal to the maximum value of the data voltage (VDATA). For example, the maximum value of the data voltage (VDATA) may correspond to the maximum grayscale of the input image data (IMG).

[0186] In this way, during the data transmission interval (DTP), the eighth transistor (T8) and the ninth transistor (T9) can be turned on to provide the second reference voltage (VREF2) to the third node (N3), and the voltage of the third node (N3) can be changed from the data voltage (VDATA) to the second reference voltage (VREF2) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"), and the storage capacitor (CST) can boost the voltage of the first node (N1) by the difference between the second reference voltage (VREF2) and the data voltage (VDATA) (i.e., "VREF2 - VDATA"). Accordingly, the data voltage (VDATA) can be transmitted from the third node (N3) to the first node (N1). Therefore, the data transmission operation can be performed.

[0187] FIG. 16 is a circuit diagram showing an example of the operation of the pixel circuit (PCc) of FIG. 10 in the light-emitting section (EP) of FIG. 11.

[0188] Referring to FIGS. 1 to 8, in the light-emitting section (EP), a light-emitting operation for the light-emitting element (EE) can be performed.

[0189] In the above light emission section (EP), the second transistor (T2) may be turned off in response to the data write gate signal (GW) having the high level (H), the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having the low level (L), the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having the low level (L), the fifth transistor (T5) may be turned on in response to the emission signal (EM) having the low level (L), the sixth transistor (T6) may be turned off in response to the first reset gate signal (GR1) having the high level (H), the seventh transistor (T7) may be turned off in response to the bias gate signal (GB) having the high level (H), and the eighth transistor (T8) may have the high level (H The ninth transistor (T9) can be turned on in response to the data write gate signal (GW), and the ninth transistor (T9) can be turned on in response to the first reset gate signal (GR1) having the high level (H).

[0190] The eighth transistor (T8) and the ninth transistor (T9) can be turned on to provide the second reference voltage (VREF2) to the third node (N3). Therefore, the voltage of the third node (N3) can be maintained at the second reference voltage (VREF2).

[0191] The first transistor (T1) can be turned on based on the voltage of the first node (N1) and the first power supply voltage (ELVDD) to generate the driving current (IDR). Specifically, the first transistor (T1) can generate the driving current (IDR) based on the difference (i.e., "VTH + (VREF2 - VDATA)") between the voltage of the first node (N1) (i.e., "ELVDD + VTH + (VREF2 - VDATA)") and the first power supply voltage (ELVDD). Since the difference between the voltage of the first node (N1) and the first power supply voltage (ELVDD) includes the data voltage (VDATA), the magnitude of the driving current (IDR) may vary depending on the data voltage (VDATA).

[0192] In addition, since the first transistor (T1) as well as the fifth transistor (T5) are turned on, a line for transmitting the driving current (IDR) can be formed between the line transmitting the first power supply voltage (ELVDD) and the line transmitting the second power supply voltage (ELVSS).

[0193] Accordingly, the driving current (IDR) can be delivered to the light-emitting element (EE) along the transmission line of the driving current (IDR). The light-emitting element (EE) can emit light based on the driving current (IDR). The larger the magnitude of the driving current (IDR), the greater the brightness corresponding to the light-emitting intensity of the light-emitting element (EE).

[0194] In this way, a light emission operation for the light-emitting element (EE) can be performed in the light emission section (EP).

[0195] In summary, the pixel circuit (PCc) can sequentially perform the first compensation operation for the threshold voltage (VTH) of the first transistor (T1), the data writing operation for the pixel circuit (PCc), and the second compensation operation for the threshold voltage (VTH) of the first transistor (T1) by using the first reference voltage (VREF1) and the second reference voltage (VREF2) which is different from the first reference voltage (VREF1). Accordingly, the pixel circuit (PCc) can operate normally even if it includes only one capacitor (CST).

[0196] FIG. 17 is a block diagram showing an electronic device (1000) according to embodiments of the present invention. FIG. 18 is a diagram showing an example in which the electronic device (1000) of FIG. 17 is implemented as a smartphone.

[0197] Referring to FIGS. 1 through 18, the electronic device (1000) may include a processor (1010), a memory device (1020), a storage device (1030), an input / output device (1040), a power supply (1050), and a display device (1060). In this case, the display device (1060) may be the display device of FIG. 1. Additionally, the electronic device (1000) may further include several ports capable of communicating with a video card, sound card, memory card, USB device, etc., or communicating with other systems.

[0198] In one embodiment, as shown in FIG. 18, the electronic device (1000) may be implemented as a smartphone. However, this is exemplary and the electronic device (1000) is not limited thereto. For example, the electronic device (1000) may be implemented as a mobile phone, video phone, smart pad, smart watch, tablet PC, vehicle navigation system, computer monitor, laptop, head-mounted display device, etc.

[0199] The processor (1010) may perform specific calculations or tasks. In one embodiment, the processor (1010) may be a microprocessor, a central processing unit, an application processor, etc. The processor (1010) may be connected to other components via an address bus, a control bus, a data bus, etc. In one embodiment, the processor (1010) may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0200] The above processor (1010) can output input image data (IMG) and input control signal (CONT) to the drive control unit (200) of FIG. 1.

[0201] The memory device (1020) can store data necessary for the operation of the electronic device (1000). For example, the memory device (1020) may include non-volatile memory devices such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM) device, a Ferroelectric Random Access Memory (FRAM) device, and / or volatile memory devices such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, etc.

[0202] The storage device (1030) may include a Solid State Drive (SSD), a Hard Disk Drive (HDD), a CD-ROM, etc. The input / output device (1040) may include input means such as a keyboard, a keypad, a touchpad, a touchscreen, a mouse, etc., and output means such as a speaker, a printer, etc. In one embodiment, the display device (1060) may be included in the input / output device (1040). The power supply (1050) may supply power necessary for the operation of the electronic device (1000). The display device (1060) may be connected to other components through the buses or other communication links.

[0203] FIG. 19 is a block diagram showing an electronic device (10) according to embodiments of the present invention. FIG. 20 is a schematic diagram of the electronic device (10) of FIG. 19.

[0204] Referring to FIG. 19, an electronic device (10) according to embodiments may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0205] The display device according to an embodiment of the present invention can be applied to various electronic devices.

[0206] In one embodiment, the electronic device (10) may include the display device of FIG. 1. That is, the operation of the display device included in the electronic device (10) may be the same as the operation of the display device described with reference to FIG. 1 to FIG. 16. In addition to the display device, it may further include a module or device having other additional functions.

[0207] The above processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0208] In one embodiment, the processor (12) may provide the input control signal (CONT) of FIG. 1 and the input image data (IMG) of FIG. 1 to the driving control unit (200) included in the display device of FIG. 1.

[0209] In one embodiment, the processor (12) may be provided divided into two or more parts from a functional or structural perspective. For example, the processor (12) may include a main processor in the form of a first driving chip that includes a central processing unit, and an auxiliary processor in the form of a second driving chip that includes a controller that receives a video signal from the main processor and processes the video signal to match the interface specifications of the display module (11). For example, the auxiliary processor may include the driving control unit (200) included in the display device of FIG. 1. Accordingly, the main processor may provide the input control signal (CONT) of FIG. 1 and the input video data (IMG) of FIG. 1 to the auxiliary processor. The auxiliary processor may process the video signal based on the input control signal (CONT) and the input video data (IMG).

[0210] The memory (13) may include at least one of non-volatile memory and volatile memory. Data information necessary for the operation of the processor (12) or the display module (11) may be stored in the memory (13). When the processor (12) executes an application stored in the memory (13), the input control signal (CONT) and / or the input image data (IMG) is transmitted to the display module (11), and the display module (11) can process the received input control signal (CONT) and / or the input image data (IMG) to output image information through a display screen.

[0211] The above power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (10).

[0212] At least one of the components of the electronic device (10) may be included within the display device according to embodiments of the present invention. Additionally, some of the individual modules functionally included within a single module may be included within the display device, while others may be provided separately from the display device. For example, the display device may include the display module (11), and the processor (12), the memory (13), and the power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0213] Referring to FIG. 20, various electronic devices to which the display device according to the embodiments is applied may include not only image display electronic devices such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a Center Information Display (CID) and a Room Mirror Display placed on the instrument panel, center fascia, and dashboard of an automobile. The electronic device (10) is not limited to image display electronic devices, wearable electronic devices, and automotive electronic devices (10_3). Industrial applicability

[0214] The present invention may be applied to a pixel circuit, a display device including the pixel circuit, and an electronic device including the display device. For example, the present invention may be applied to a mobile phone, a smartphone, a tablet computer, a TV, a digital TV, a 3D TV, a PC, a home electronic device, a laptop computer, a PDA, a PMP, a digital camera, a music player, a portable game console, a navigation system, etc.

[0215] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0216] 100: Display panel 200: Drive control unit 300: Gate drive unit 400: Gamma reference voltage generation unit 500: Data driver 600: Emission drive unit

Claims

Claim 1 A first transistor comprising a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second node; a second transistor comprising a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor comprising a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor comprising a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor comprising a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a sixth transistor comprising a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, a first electrode receiving the initialization voltage, and a second electrode connected to the fourth node A pixel circuit characterized by comprising: a seventh transistor including a second receiving electrode; a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and a light-emitting element including an anode electrode connected to the fourth node and a cathode electrode receiving a second power supply voltage. Claim 2 A pixel circuit according to claim 1, characterized in that the first reference voltage is greater than or equal to the maximum value of the data voltage. Claim 3 A pixel circuit according to claim 1, wherein the pixel circuit further comprises an eighth transistor including a gate electrode receiving a second reset gate signal, a first electrode receiving a second reference voltage different from the first reference voltage, and a second electrode connected to the third node. Claim 4 A pixel circuit according to claim 3, wherein the second reference voltage is less than or equal to the maximum value of the data voltage. Claim 5 A pixel circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors. Claim 6 A pixel circuit according to claim 3, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors. Claim 7 A pixel circuit according to claim 3, characterized in that, in the initialization period, the fourth transistor is turned on to provide the initialization voltage to the first node, and the sixth transistor is turned on to provide the first reference voltage to the third node. Claim 8 A pixel circuit according to claim 7, characterized in that, in the first compensation section after the initialization section, the third transistor is turned on to diode-connect the first transistor, and the sixth transistor is turned on to provide the first reference voltage to the third node. Claim 9 A pixel circuit according to claim 8, wherein in the second compensation / data writing section after the first compensation section, the second transistor is turned on to provide the data voltage transmitted by the data line to the third node, the third transistor is turned on to diode-connect the first transistor, and the seventh transistor is turned on to provide the initialization voltage to the fourth node. Claim 10 A pixel circuit according to claim 9, characterized in that, in the data transmission section after the second compensation / data writing section, the eighth transistor is turned on to provide the second reference voltage to the third node. Claim 11 A pixel circuit according to claim 10, wherein in the light-emitting section after the data transmission section, the first transistor is turned on based on the voltage of the first node and the first power supply voltage to generate a driving current, and the first transistor and the fifth transistor are turned on so that the driving current is provided to the light-emitting element. Claim 12 The pixel circuit according to claim 1 further comprises: an eighth transistor including a gate electrode receiving the data write gate signal, a first electrode, and a second electrode connected to the third node; and a ninth transistor including a gate electrode receiving the first reset gate signal, a first electrode receiving a second reference voltage different from the first reference voltage, and a second electrode connected to the first electrode of the eighth transistor. Claim 13 A pixel circuit according to claim 12, wherein the second reference voltage is less than or equal to the maximum value of the data voltage. Claim 14 A pixel circuit according to claim 12, wherein the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor are PMOS transistors, and the third transistor, the fourth transistor, the eighth transistor, and the ninth transistor are NMOS transistors. Claim 15 A pixel circuit according to claim 12, characterized in that, in the initialization period, the fourth transistor is turned on to provide the initialization voltage to the first node, and the sixth transistor is turned on to provide the first reference voltage to the third node. Claim 16 A pixel circuit according to claim 15, characterized in that, in the first compensation section after the initialization section, the third transistor is turned on to diode-connect the first transistor, and the sixth transistor is turned on to provide the first reference voltage to the third node. Claim 17 A pixel circuit according to claim 16, characterized in that, in the second compensation / data writing section after the first compensation section, the second transistor is turned on to provide the data voltage transmitted by the data line to the third node, the third transistor is turned on to diode-connect the first transistor, and the seventh transistor is turned on to provide the initialization voltage to the fourth node. Claim 18 A pixel circuit according to claim 17, characterized in that, in the data transmission section after the second compensation / data writing section, the eighth transistor and the ninth transistor are turned on to provide the second reference voltage to the third node. Claim 19 A display panel including pixel circuits; The display panel driver for driving the display panel described above is included, and the pixel circuit comprises: a first transistor including a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode including a second electrode connected to a second node; a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a sixth transistor including a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, and the initialization voltage A display device characterized by comprising: a seventh transistor including a first electrode that receives and a second electrode that receives a second electrode connected to the fourth node; a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and a light-emitting element including an anode electrode connected to the fourth node and a cathode electrode that receives a second power supply voltage. Claim 20 A display panel including a pixel circuit; a display panel driving unit for driving the display panel; The pixel circuit includes a processor that controls the display panel driver, and the pixel circuit comprises: a first transistor including a gate electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode including a second electrode connected to a second node; a second transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line transmitting a data voltage, and a second electrode connected to a third node; a third transistor including a gate electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode connected to the second node, and a second electrode connected to the fourth node; a sixth transistor including a gate electrode receiving a first reset gate signal, a first electrode receiving a first reference voltage, and a second electrode connected to the third node; a gate electrode receiving a bias gate signal, and the initialization voltage An electronic device characterized by comprising: a seventh transistor including a first electrode that receives and a second electrode that receives a second electrode connected to the fourth node; a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and a light-emitting element including an anode electrode connected to the fourth node and a cathode electrode that receives a second power supply voltage.

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