Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device may include: a first row line; a first column line located on the first row line; a first memory cell located between the first row line and the first column and having a first current path; a third row line; a third column line located on the third row line; a third memory cell located between the third row line and the third column line and having a third current path longer than the first current path; first contact plugs electrically connected to the first row line and the third row line, respectively; second contact plugs electrically connected to the first column line and the third column line, respectively; a first barrier pattern located between one of the first contact plugs and the first row line; and a second barrier pattern located between the first barrier pattern and the first row line.

Description

Technology Field

[0001] The present invention relates to an electronic device and a method for manufacturing an electronic device, and more specifically, to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] The integration density of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as the improvement of integration density in semiconductor devices that form memory cells as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices that stack memory cells on a substrate are being proposed. In addition, various structures and manufacturing methods are being developed to improve the operational reliability of such semiconductor devices. The problem to be solved

[0003] One embodiment of the present invention provides a semiconductor device having a stable structure and improved characteristics and a method for manufacturing a semiconductor device. means of solving the problem

[0004] According to one embodiment of the present invention, a first row line; a first column line located on the first row line; a first memory cell located between the first row line and the first column and having a first current path; a third row line; a third column line located on the third row line; a third memory cell located between the third row line and the third column line and having a third current path longer than the first current path; first contact plugs electrically connected to the first row line and the third row line, respectively; second contact plugs electrically connected to the first column line and the third column line, respectively; a first barrier pattern located between one of the first contact plugs and the first row line; and a second barrier pattern located between the first barrier pattern and the first row line.

[0005] A semiconductor device according to one embodiment of the present invention may include: a first row line having a first grain size; a first column line located on the first row line; a first memory cell located between the first row line and the first column and having a first current path; a second row line having a second grain size larger than the first grain size; a second column line located on the second row line; a second memory cell located between the second row line and the second column line and having a second current path longer than the first current path; first contact plugs electrically connected to the first row line and the second row line, respectively; and second contact plugs electrically connected to the first column line and the second column line, respectively. Effects of the invention

[0006] According to the present technology, it is possible to provide a semiconductor device having a stable structure and improved reliability. Brief explanation of the drawing

[0007] FIG. 1 is a drawing for explaining a semiconductor device according to one embodiment of the present invention. FIGS. 2a and FIGS. 2b are drawings for explaining a semiconductor device according to an embodiment of the present invention. FIGS. 3a, FIGS. 3b, FIGS. 3c, FIGS. 4a, FIGS. 4b, and FIGS. 4c are drawings for explaining a semiconductor device according to an embodiment of the present invention. FIGS. 5A and FIGS. 5B are drawings for illustrating a semiconductor device according to an embodiment of the present invention. FIGS. 6a, FIGS. 6b, FIGS. 6c, FIGS. 6d, FIGS. 7a, FIGS. 7b, FIGS. 7c, FIGS. 7d, FIGS. 8a, FIGS. 8b, FIGS. 8c, FIGS. 8d, FIGS. 9a, FIGS. 9b, FIGS. 9c, FIGS. 9d, FIGS. 10a, FIGS. 10b, FIGS. 10c, FIGS. 10d, FIGS. 10e, FIGS. 10f, and FIGS. 10g are drawings for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. Specific details for implementing the invention

[0008] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0010] FIG. 1 is a drawing for explaining a semiconductor device according to one embodiment of the present invention.

[0011] Referring to FIG. 1, the semiconductor device may include row lines (WL), column lines (BL), memory cells (MC), first contact plugs (CT1) and second contact plugs (CT2).

[0012] A memory cell array may include column lines (BL) and row lines (WL) located at different levels. For example, column lines (BL) may be located on row lines (WL). Additionally, row lines (WL) may extend in a first direction (I), and column lines (BL) may extend in a second direction (II) that intersects the first direction (I).

[0013] Low lines (WL) can each be connected to the first contact plugs (CT1). Low lines (WL) can be connected to the surrounding circuit through the first contact plugs (CT1). Column lines (BL) can each be connected to the second contact plugs (CT2). Column lines (BL) can be connected to the surrounding circuit through the second contact plugs (CT2).

[0014] Memory cells (MC) can be positioned between row lines (WL) and column lines (BL), respectively. Additionally, memory cells (MC) can be arranged in a first direction (I) and a second direction (II). Additionally, each memory cell (MC) can be a memory stack. Here, the third direction (III) can be a direction intersecting the first direction (I) and the second direction (II), and a direction perpendicular to the first direction (I) and the second direction (II).

[0015] In this drawing, the memory cell array is illustrated as having a single deck structure, but the present invention is not limited thereto, and it is also possible for memory cells (MC) to be stacked in a third direction (III). For example, the memory cell array may have a multi-deck structure in which row lines (WL) and column lines (BL) are alternately stacked in a third direction (III). In this case, memory cells may be positioned between the alternately stacked row lines (WL) and column lines (BL).

[0016] According to the structure described above, the integration density of the memory device can be improved by arranging memory cells (MC) in a cross-point array structure. In addition, the integration density of the memory device can be further improved by stacking memory cells (MC) in a multi-deck structure.

[0018] FIGS. 2a and 2b are drawings for explaining a semiconductor device according to an embodiment of the present invention. Hereinafter, content that overlaps with the previously described content will be omitted.

[0019] Referring to FIGS. 2a and 2b, a semiconductor device may include a plurality of mats (MAT). Here, a mat (MAT) may be a driving unit in which a write, read, or erase operation is performed. For example, each of the mats (MAT) may independently perform a write, read, or erase operation.

[0020] The first and second contact plugs (CT1, CT2) may be located around the perimeter of the mat (MAT) or between adjacent mats (MAT). The first and second contact plugs (CT1, CT2) may be located in a peripheral circuit area (PER). Here, the peripheral circuit area (PER) may be an area around the perimeter of the mat (MAT) or between adjacent mats (MAT). The first contact plugs (CT1) may be arranged in a second direction (II) between adjacent mats (MAT) in a first direction (I). The second contact plugs (CT2) may be arranged in a first direction (I) between adjacent mats (MAT) in a second direction (II).

[0021] A MAT may include memory cells (MC) arranged in a first direction (I) and a second direction (II). Additionally, the memory cells (MC) included in the MAT may be connected to first contact plugs (CT1) through row lines (WL) and connected to second contact plugs (CT2) through column lines (BL). Thus, the memory cells (MC) may have a current path through which current flows during write, read, or erase operations.

[0022] The current path may be a path through which current flows from the first contact plug (CT1) to the second contact plug (CT2) via the memory cell (MC). For example, the first memory cell (MC1) may have a first current path from the first contact plug (CT1) to the second contact plug (CT2) through the first memory cell (MC1). Here, the first current path may be the sum of the path of the first row line (WL1) from the first contact plug (CT1) to the first memory cell (MC1) and the path of the first column line (BL1) from the first memory cell (MC1) to the second contact plug (CT2).

[0023] The second memory cell (MC2) may have a second current path from the first contact plug (CT1) through the second memory cell (MC2) to the second contact plug (CT2). Here, the second current path may be the sum of the path of the second row line (WL2) from the first contact plug (CT1) to the second memory cell (MC2) and the path of the second column line (BL2) from the second memory cell (MC2) to the second contact plug (CT2).

[0024] The third memory cell (MC3) may have a third current path from the first contact plug (CT1) through the third memory cell (MC3) to the second contact plug (CT2). Here, the third current path may be the sum of the path of the third row line (WL3) from the first contact plug (CT1) to the third memory cell (MC3) and the path of the third column line (BL3) from the third memory cell (MC3) to the second contact plug (CT2).

[0025] Depending on their position within the MAT, memory cells (MC) may have different current paths. For example, the second current path of a second memory cell (MC2) may be longer than the first current path of a first memory cell (MC1). The third current path of a third memory cell (MC3) may be longer than the second current path of a second memory cell (MC2). Thus, the area of ​​the MAT can be divided according to the length of the current path.

[0026] The area of ​​the MAT can be divided according to the length of the current path. The NEAR area may be an area where memory cells with relatively short current paths are located. The FAR area may be an area where memory cells with relatively long current paths are located. The MIDDLE area may be an area of ​​the MAT excluding the NEAR area and the FAR area. For example, a first memory cell (MC1) having a first current path may be located in the NEAR area, a second memory cell (MC2) having a second current path may be located in the MIDDLE area, and a third memory cell (MC3) having a third current path may be located in the FAR area.

[0027] Memory cells (MC1, MC2, MC3) located in the NEAR region, MIDDLE region, and FAR region may have differences in current paths, and the total resistance of the current paths may vary depending on the differences in current paths. For example, a first current path may have a first resistance, a second current path may have a second resistance, and a third current path may have a third resistance. Here, the first resistance may be smaller than the second resistance, and the second resistance may be smaller than the third resistance.

[0028] In such cases, the amount of current applied to the memory cells (MC1, MC2, MC3) during operation may differ. For example, in the case of the first memory cell (MC1) located in the NEAR region, a relatively large current may be applied because the first resistance is relatively small. Consequently, an excessive amount of current may be applied to the first memory cell (MC1) in the NEAR region, causing an overshoot, and the first memory cell (MC1) may be damaged.

[0029] To compensate for the resistance difference along the current path, at least one barrier pattern may be added between the first contact plugs (CT1) and the row lines (WL) and / or between the second contact plugs (CT2) and the column lines (BL). For example, at least one barrier pattern may be added between the first contact plug (CT1) and the first row line (WL1). At least one barrier pattern may be added between the second contact plug (CT2) and the first column line (BL1). Here, the barrier patterns may have a higher resistivity than the row lines (WL).

[0030] In this case, the first memory cell (MC1) may have a first current path from the first contact plug to the second contact plug (CT2) through at least one barrier pattern, a first row line (WL1), the first memory cell (MC1), at least one barrier pattern, and a first column line (BL1). The first current path may have a first resistance that is increased by at least one barrier pattern. Here, the first resistance may be increased to be similar / substantially the same as the third resistance of the third current path. Therefore, since the first resistance in the first current path is larger than before, a relatively small current may be applied during driving, so that an overshoot may not occur in the first memory cell (MC1) and the first memory cell (MC1) may not be damaged.

[0031] Likewise, at least one barrier pattern can be added between the first contact plug (CT1) and the second row line (WL2). At least one barrier pattern can be added between the second contact plug (CT2) and the second column line (BL2). In this case, the second resistance of the second current path can be increased by at least one barrier pattern. Here, the second resistance can be increased similarly / substantially equal to the third resistance. Therefore, a smaller current than the existing one can be applied in the second current path as well.

[0033] FIGS. 3a, 3b, 3c, 4a, 4b, and 4c are drawings for explaining a semiconductor device according to an embodiment of the present invention. Hereinafter, content that overlaps with the previously described content will be omitted.

[0034] Referring to FIGS. 3a through 3c and FIGS. 4a through 4c, the semiconductor device may include row lines (350), column lines (390), memory cells (MC), first barrier patterns (330), second barrier patterns (340), first contact plugs (320A) and second contact plugs (320B). The semiconductor device may further include an interlayer insulating film (310), a first gap insulating film (IL1), a second gap insulating film (IL2), first liner patterns (LN1), second liner patterns (LN2), first gap fill patterns (GF1) and second gap fill patterns (GF2).

[0035] The first contact plugs (320A) may be located in a peripheral circuit area (PER). The first contact plugs (320A) may be located within an interlayer insulating film (310). The interlayer insulating film (310) may be located on a substrate. A peripheral circuit may be located on the substrate, and the first contact plugs (320A) may be connected to the peripheral circuit through an interconnection structure. The interlayer insulating film (310) may include an insulating material such as an oxide. The first contact plugs (320A) may include a conductive material such as tungsten.

[0036] Low lines (350) may be located on the first contact plugs (320A). The low lines (350) may each be electrically connected to the first contact plugs (320A). The low lines (350) may extend in a first direction (I). A low line (350) extending through the NEAR region may be a first low line (350N). A low line (350) extending through the MIDDLE region may be a second low line (350M). A low line (350) extending through the FAR region may be a third low line (350F).

[0037] The first raw line (350N) may have a first grain size and a third thickness (T3). The second raw line (350M) may have a second grain size and a fourth thickness (T4). The third raw line (350F) may have a third grain size and a fifth thickness (T5). The third thickness (T3) may be smaller than the fourth thickness (T4). The fourth thickness (T4) may be smaller than the fifth thickness (T5). Here, the raw lines (350) may be used as word lines or bit lines. The raw lines (350) may include a conductive material such as tungsten.

[0038] The grain size of the film formed on the substrate may vary depending on the material of the base. As the grain size becomes smaller, there may be more grain boundaries, and grain boundaries can hinder the movement of electrons and increase resistivity. The first grain size may be smaller than the second grain size. The second grain size may be smaller than the third grain size. In other words, the resistivity of the first low line (350N) may be greater than the resistivity of the second low line (350M). The resistivity of the second low line (350M) may be greater than the resistivity of the third low line (350F).

[0039] Column lines (390) may be located on row lines (350). Column lines (390) may extend into a second direction (II) intersecting the first direction (I). A column line (390) extending through the NEAR region may be a first column line (390N). A column line (390) extending through the MIDDLE region may be a second row line (390M). A column line (390) extending through the FAR region may be a third row line (390F).

[0040] The first column line (390N) may have a fourth grain size and an eighth thickness (T8). The second column line (390M) may have a fifth grain size and a ninth thickness (T9). The third column line (390F) may have a sixth grain size and a tenth thickness (T10). The fourth grain size may be smaller than the fifth grain size, and the fifth grain size may be smaller than the sixth grain size. The eighth thickness (T8) may be smaller than the ninth thickness (T9), and the ninth thickness (T9) may be smaller than the tenth thickness (T10). Here, the column lines (390) may be used as word lines or bit lines. The column lines (390) may include a conductive material such as tungsten.

[0041] The second contact plugs (320B) can be electrically connected to the column lines (390), respectively. The second contact plugs (320B) can be located in the peripheral circuit area (PER). The second contact plugs (320B) can be located within the first gap insulating film (IL1). The first gap insulating film (IL1) can be located on the interlayer insulating film (310). The second contact plugs (320B) can be connected to the peripheral circuit through the first contact plugs (320A) and an interconnection structure. The first gap insulating film (IL1) may include an insulating material such as an oxide. The second contact plugs (320B) may include a conductive material such as tungsten.

[0042] Memory cells (MC) can be arranged in a first direction (I) and a second direction (II). Memory cells (MC) can be positioned between row lines (350) and column lines (390), respectively. Memory cells (MC) may include a first memory cell (MC1) having a first current path through a NEAR region, a second memory cell (MC2) having a second current path through a MIDDLE region, and a third memory cell (MC3) having a third current path through a FAR region. The first memory cell (MC1) can be positioned between the first row line (350N) and the first column line (390N), the second memory cell (MC2) can be positioned between the second row line (350M) and the second column line (390M), and the third memory cell (MC3) can be positioned between the third row line (350F) and the third column line (390F).

[0043] A memory cell (MC) may include a lower electrode pattern (361), a variable resistor pattern (363), and an upper electrode pattern (365). The lower electrode pattern (361) may be located on a row line (350). The lower electrode pattern (361) may be part of the row line (350) or electrically connected to the row line (350). The upper electrode pattern (365) may be located on the lower electrode pattern (361). The upper electrode pattern (365) may be part of the column line (390) or electrically connected to the column line (390). The variable resistor pattern (363) may be located between the lower electrode pattern (361) and the upper electrode pattern (365).

[0044] The lower electrode pattern (361) and / or the upper electrode pattern (365) may include polysilicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., and may include a combination thereof.

[0045] The variable resistor pattern (363) may be positioned between the lower electrode pattern (361) and the upper electrode pattern (365). The variable resistor pattern (363) may maintain an amorphous state during programming operation and may not change to a crystalline state after programming operation. In other words, the phase of the variable resistor pattern (363) may not change after programming operation. The variable resistor pattern (363) may be used as a data storage device and simultaneously as a selection element. The variable resistor pattern (363) may include a resistive material and may have the characteristic of reversibly changing between different resistance states depending on the applied voltage or current. For example, the variable resistor pattern (363) may include a variable resistor material in which the resistance changes without a phase change and may include chalcogenide elements. The variable resistor pattern (363) may include germanium (Ge), antimony (Sb), arsenic (As), silicon (Si), indium (In), tin (Sn), gallium (Ga), etc., or may include a combination thereof.

[0046] The variable resistor pattern (363) may include a phase change material and may include a chalcogenide. The variable resistor pattern (363) may include chalcogenide glass, a chalcogenide alloy, etc. The variable resistor pattern (363) may undergo a phase change according to a program operation. For example, the variable resistor pattern (363) may have a low-resistance crystalline state by a set operation. In addition, the variable resistor pattern (363) may have a high-resistance amorphous state by a reset operation. Therefore, data can be stored in a memory cell (MC) by utilizing the resistance difference according to the phase of the variable resistor pattern (363).

[0047] The variable resistance pattern (363) may include a transition metal oxide or a metal oxide such as a perovskite material. Thus, data can be stored in the memory cell by creating or extinguishing an electrical path within the variable resistance pattern (363).

[0048] The variable resistor pattern (363) may have an MTJ structure and may include a magnetization fixed film, a magnetization free film, and a tunnel barrier film interposed between them. For example, the magnetization fixed film and the magnetization free film may include a magnetic material, and the tunnel barrier film may include an oxide of magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), etc. Here, the magnetization direction of the magnetization free film may be changed by the spin torque of electrons in the applied current. Accordingly, data can be stored in the memory cell (MC) depending on the change in the magnetization direction of the magnetization free film relative to the magnetization direction of the magnetization fixed film.

[0049] Additionally, the variable resistance pattern (363) may have a Metal Insulator Metal (MIM) structure containing a metal oxide. In this case, data can be stored in the memory cell (MC) by utilizing the change in resistance of the metal oxide that occurs when a short electric pulse is applied.

[0050] For reference, although not shown in this drawing, the semiconductor device may further include an intermediate electrode pattern and a switching pattern. For example, the semiconductor device may include a structure in which a lower electrode pattern (361), a switching pattern, an intermediate electrode pattern, a variable resistor pattern (363), and an upper electrode pattern (365) are stacked in sequence. In this case, the lower electrode pattern (361), the switching pattern, and the intermediate electrode pattern may constitute a selection element. The selection element may be a diode, a PNP diode, a transistor, a vertical transistor, a Bipolar Junction Transistor (BJT), a Metal Insulator Transition (MIT) device, a Mixed Ionic-Electronic Conduction (MIEC) device, an Ovonic Threshold Switching (OTS) device, etc. For example, the switching pattern (123) may include a chalcogenide material. Additionally, the intermediate electrode pattern, the variable resistor pattern (363), and the upper electrode pattern (365) may constitute a memory element. The memory element and the selection element may share an intermediate electrode pattern.

[0051] The first barrier pattern (330) may be positioned between the first contact plug (320A) and the row line (350). For example, the first barrier pattern (330) may be positioned between the first contact plug (320A) and the first row line (350N). The first barrier pattern (330) may have a first thickness (T1). The first barrier pattern (330) may have a resistivity greater than that of the row lines (350). The first barrier pattern (330) may include a nitride. In one example, the first barrier pattern (330) may include tungsten silicon nitride (WSiN). In another example, the first barrier pattern (330) may include titanium nitride (TiN).

[0052] The second barrier patterns (340) may be located between the first contact plugs (320A) and the row lines (350). For example, the second barrier pattern (340) may be located between the first barrier pattern (330) and the first row line (350N). For another example, the second barrier pattern (340) may be located between the first contact plug (320A) and the second row line (350M). The second barrier patterns (340) may have a second thickness (T2). The second barrier patterns (340) may have a resistivity greater than that of the row lines (350). The second barrier patterns (340) may include a nitride. For example, the second barrier patterns (340) may include tungsten silicon nitride (WSiN). As another example, the second barrier patterns (340) may include titanium nitride (TiN).

[0053] The third barrier pattern (370) may be located between the second contact plug (320B) and the first column line (390N). The third barrier pattern (370) may have a thickness similar to that of the first barrier pattern (330) and a similar material. The third barrier pattern (370) may have a sixth thickness (T6). The third barrier pattern (370) may include tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0054] The fourth barrier pattern (380) may be located between the third barrier pattern (370) and the first column line (390N). The fourth barrier pattern (380) may be located between the second contact plug (320B) and the second column line (390M). The fourth barrier pattern (380) may have a thickness similar to that of the second barrier pattern (340) and a similar material. The fourth barrier pattern (380) may have a seventh thickness (T7). The fourth barrier pattern (380) may include tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0055] The sum (TN1) of the first thickness (T1) of the first barrier pattern (330) in the NEAR region, the second thickness (T2) of the second barrier pattern (340), and the third thickness (T3) of the first row line (350N) may be substantially the same as the fifth thickness (T5, TF1) of the third row line (350F) in the FAR region. Additionally, the sum (TN1) of the first thickness (T1) of the first barrier pattern (330) in the NEAR region, the second thickness (T2) of the second barrier pattern (340), and the third thickness (T3) of the first row line (350N) may be substantially the same as the sum (TM1) of the second thickness (T2) of the second barrier pattern (340) and the fourth thickness (T4) of the second row line (350M) in the MIDDLE region. In other words, the sum of the thicknesses (TN1) of the first and second barrier patterns (330, 340) and the first row line (350N) in the NEAR region, the sum of the thicknesses (TM1) of the second barrier pattern (340) and the second row line (350M) in the MIDDLE region, and the thickness (TF1) of the third row line (350F) in the FAR region may be substantially the same.

[0056] The sum (TN2) of the sixth thickness (T6) of the third barrier pattern (370) in the NEAR region, the seventh thickness (T7) of the fourth barrier pattern (380), and the eighth thickness (T8) of the first column line (390N) may be substantially the same as the tenth thickness (T10, TF2) of the third column line (390F) in the FAR region. Additionally, the sum (TN2) of the sixth thickness (T6) of the third barrier pattern (370) in the NEAR region, the seventh thickness (T7) of the fourth barrier pattern (380), and the eighth thickness (T8) of the first column line (390N) may be substantially the same as the sum (TM2) of the seventh thickness (T2) of the fourth barrier pattern (380) and the thickness of the second column line (390M) in the MIDDLE region. In other words, the sum of the thicknesses (TN2) of the third and fourth barrier patterns (370, 380) and the first column line (390N) in the NEAR region, the sum of the thicknesses (TM2) of the fourth barrier pattern (380) and the second column line (390M) in the MIDDLE region, and the thickness (TF2) of the third column line (390F) in the FAR region may be substantially the same.

[0057] The first memory cell (MC1) may have a first current path having a first resistance. For example, the first memory cell (MC1) may have a first current path from the first contact plug (320A) to the second contact plug (320B) through the first barrier pattern (330), the second barrier pattern (340), the first row line (350N), the first memory cell (MC1), and the first column line (390N). Here, the first current path may further include a path from the first memory cell (MC1) to the first column line (390N) through the third barrier pattern (370) and the fourth barrier pattern (380). Here, the first current path may have a first resistance.

[0058] The second memory cell (MC2) may have a second current path having a second resistance. For example, the second memory cell (MC2) may have a second current path from the first contact plug (320A) to the second contact plug (320B) through the second barrier pattern (340), the second row line (350M), the second memory cell (MC2), and the second column line (390M). Here, the second current path may further include a path from the second memory cell (MC2) to the second column line (390M) through the fourth barrier pattern (380). Here, the second current path may have a second resistance.

[0059] The third memory cell (MC3) may have a third current path having a third resistance. For example, the third memory cell (MC3) may have a third current path from the first contact plug (320A) to the second contact plug (320B) through the third memory cell (MC3) and the third column line (390F).

[0060] Here, the first and second barrier patterns (330, 340) may have a higher resistivity than the row lines (350). Also, the third and fourth barrier patterns (370, 380) may have a higher resistivity than the column lines (390). The first and second row lines (350N, 350M) may have a higher resistivity than the third row line (350F). Also, the first and second column lines (390N, 390M) may have a higher resistivity than the third column line (390F). In this case, the first resistance of the first current path, the second resistance of the second current path, and the third resistance of the third current path may be substantially the same. In other words, the first resistance of the first current path, which has a relatively low resistance because it has a relatively short current path, can be compensated by the first, second, third, and fourth barrier patterns (330, 340, 370, 380), the first row line (350N), and the first column line (390N) so that it becomes substantially equal to the third resistance of the third current path. Additionally, the second resistance of the second current path can be compensated by the second and fourth barrier patterns (340, 380), the second row line (350M), and the second column line (390M) so that it becomes substantially equal to the third resistance.

[0061] When driving memory cells (MC), a smaller current may flow through the first and second memory cells (MC1, MC2) than when the first, second, third, and fourth barrier patterns (330, 340, 370, 380) are not present, and a smaller current may flow through the first and second memory cells (MC1, MC2) than when the grain size is not formed small. Therefore, overshoot may not occur in the first and second memory cells (MC1, MC2), and damage to the first and second memory cells (MC1, MC2) may be prevented.

[0062] For reference, in this drawing, the first, second, third, and fourth barrier patterns (330, 340, 370, 380) are depicted as extending from the peripheral circuit area (PER) to the NEAR and MIDDLE areas, but are not limited thereto. For example, the first, second, third, and fourth barrier patterns (330, 340, 370, 380) may be located only in the peripheral circuit area (PER).

[0063] Additionally, the present drawing illustrates a case where the first and second barrier patterns (330, 340) and the third and fourth barrier patterns (370, 380) are all present in the NEAR region, but is not limited thereto. For example, if the first and second barrier patterns (330, 340) are present in the NEAR region, the third and fourth barrier patterns (370, 380) may be omitted. For another example, if the third and fourth barrier patterns (370, 380) are present, the first and second barrier patterns (330, 340) may be omitted. In other words, if the total resistance of each of the first, second, and third current paths is substantially equal through the first and second barrier patterns (330, 340), the third and fourth barrier patterns (370, 380) may be omitted. Likewise, the same can be applied to the second barrier patterns (340) and / or fourth barrier patterns (380) in the MIDDLE region.

[0064] The first liner patterns (LN1) can wrap the sidewall of an adjacent memory cell (MC) in a second direction (II) along the profile of the memory cell (MC). The second liner patterns (LN2) can wrap the sidewall of an adjacent memory cell (MC) in a first direction (I) along the profile of the memory cell (MC). The first liner patterns (LN1) and the second liner patterns (LN2) can protect the memory cells (MC) during the process of manufacturing a semiconductor device. At least one of the first liner patterns (LN1) or the second liner patterns (LN2) may include a nitride.

[0065] The first gap-fill patterns (GF1) may be located between adjacent memory cells (MC) in the second direction (II). The second gap-fill patterns (GF2) may be located between adjacent memory cells (MC) in the first direction (I). First and second liner patterns (LN1, LN2) may be located between the first and second gap-fill patterns (GF1, GF2) and the memory cells (MC). The first and second gap-fill patterns (GF1, GF2) may include an insulating material such as an oxide.

[0066] According to the structure described above, the first and second row lines (350N, 350M) may have a relatively smaller grain size than the third row line (350F), and the first and second column lines (390N, 390M) may have a relatively smaller grain size than the third column line (390F).

[0067] Additionally, the first and second barrier patterns (330, 340) may be located between the first contact plug (320A) and the first and second row lines (350N, 350M), and the third and fourth barrier patterns (370, 380) may be located between the second contact plug (320B) and the first and second column lines (390N, 390M).

[0068] In this case, the first resistance of the first current path of the first memory cell (MC1), the second resistance of the second current path of the second memory cell (MC2), and the third resistance of the third current path of the third memory cell (MC3) may be substantially the same.

[0070] FIGS. 5a and 5b are drawings for explaining a semiconductor device according to an embodiment of the present invention. Hereinafter, content that overlaps with the previously described content will be omitted.

[0071] Referring to FIG. 5a, the current flowing during operation of the first memory cells (MC1', MC1) in the NEAR region, the second memory cells (MC2', MC2) in the MIDDLE region, and the third memory cells (MC3', MC3) in the FAR region can be compared.

[0072] If barrier patterns are not included in the first current path of the first memory cell (MC1') in the NEAR region, the first memory cell (MC1') may have a relatively short first current path, and the first current path may have a relatively small first resistance. In this case, when the first memory cell (MC1') is driven, an excessive amount of current may be applied to the first memory cell (MC1'), causing an overshoot. Consequently, the first memory cell (MC1') may be damaged, and reliability may be degraded.

[0073] On the other hand, according to one embodiment of the present invention, when barrier patterns are included in the first current path of a first memory cell (MC1) in the NEAR region, the first current path may have a first resistance compensated by the barrier patterns even if the first memory cell (MC1) has a relatively short first current path. Additionally, by forming the grain size of the first row line and the first column line included in the first current path of the first memory cell (MC1) small, the first current path may have a compensated first resistance. In other words, the first current path may have a compensated first resistance that is the same or similar to the third resistance of the third current path of the third memory cell (MC3). In this case, overshoot may not occur in the first memory cell (MC1). Therefore, the first memory cell (MC1) may not be damaged, and reliability may be improved.

[0074] Similarly, if barrier patterns are not included in the second current path of the second memory cell (MC2') in the MIDDLE region, or if the grain size of the second row line and second column line included in the second current path is not formed small, an overshoot may occur in the second memory cell (MC2') when the second memory cell (MC2') is driven. Therefore, according to one embodiment of the present invention, in order to prevent this, a barrier pattern may be included in the second current path of the second memory cell (MC2) in the MIDDLE region, and the grain size of the second row line and second column line may be formed small.

[0075] Referring to FIG. 5b, the sensing margins of the first memory cells (MC1', MC1) in the NEAR region, the second memory cells (MC2', MC2) in the MIDDLE region, and the third memory cells (MC3', MC3) in the FAR region can be compared.

[0076] To improve the operational characteristics of memory cells, a sensing margin must be secured. For example, if data exceeds the defined sensing margin range, errors may occur in the memory cells during read, write, or erase operations.

[0077] Threshold voltage (V) during SET or RESET operation in the NEAR, MIDDLE, and FAR regions t The sensing margin can be compared through the difference in dispersion. If the first and second resistances of the first and second current paths are not compensated, there is a difference in resistance between the first, second, and third current paths of the first, second, and third memory cells (MC1', MC2', MC3') in the NEAR region, MIDDLE region, and FAR region, so a difference in threshold voltage may occur between the first, second, and third memory cells (MC1', MC2', MC3') during a set operation or reset operation. In other words, a difference in the dispersion of threshold voltage may occur between the first, second, and third memory cells (MC1', MC2', MC3') during a set operation or reset operation. In this case, there may be insufficient sensing margin to sense all memory cells from the first memory cell (MC1) in the NEAR region to the third memory cell (MC3) in the FAR region during a set operation or reset operation.

[0078] On the other hand, according to one embodiment of the present invention, the first and second resistances of the first and second current paths can be compensated, and in this case, since there is almost no difference in resistance between the first, second, and third current paths, the difference in threshold voltage between the first, second, and third memory cells (MC1, MC2, MC3) during a set operation or reset operation can be reduced. In other words, the difference in the dispersion of threshold voltage between the first, second, and third memory cells (MC1, MC2, MC3) during a set operation or reset operation can be reduced. In this case, a sensing margin can be secured to sense all memory cells from the first memory cell (MC1) in the NEAR region to the third memory cell (MC3) in the FAR region during a set operation or reset operation.

[0080] FIGS. 6a, FIGS. 6b, FIGS. 6c, FIGS. 6d, FIGS. 7a, FIGS. 7b, FIGS. 7c, FIGS. 7d, FIGS. 8a, FIGS. 8b, FIGS. 8c, FIGS. 8d, FIGS. 9a, FIGS. 9b, FIGS. 9c, FIGS. 9d, FIGS. 10a, FIGS. 10b, FIGS. 10c, FIGS. 10d, FIGS. 10e, FIGS. 10f, and FIGS. 10g are drawings for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 6a, 7a, 8a, 9a, and 10a are plan views; FIGS. 6b, 7b, 8b, 9b, 10b, and 10e are cross-sectional views of the NEAR region and PER region; FIGS. 6c, 7c, 8c, 9c, 10c, and 10f are cross-sectional views of the MIDDLE region and PER region; and FIGS. 6d, 7d, 8d, 9d, 10d, and 10g are cross-sectional views of the FAR region and PER region. Hereinafter, content that overlaps with previously explained content will be omitted.

[0081] Referring to FIGS. 6a through 6d, first contact plugs (620A) can be formed in a peripheral circuit region (PER). The first contact plugs (620A) can be formed within an interlayer insulating film (610). Here, to distinguish between the first contact plug (620A) formed adjacent to the NEAR region and the first contact plug (620A) formed adjacent to the FAR region, the first contact plug (620A) formed adjacent to the NEAR region can be defined as the first contact plug (620A1), and the first contact plug (620A) formed adjacent to the FAR region can be defined as the second contact plug (620A2). The interlayer insulating film (610) may include an insulating material such as an oxide, and the first contact plugs (620A) may include a conductive material such as tungsten.

[0082] Next, a first barrier film (630A) can be formed in the NEAR region, MIDDLE region, FAR region, and peripheral circuit region (PER). A first barrier film (630A) can be formed on the interlayer insulating film (610). A first barrier film (630A) can be formed on the first contact plugs (620A). For example, a first barrier film (630A) can be formed on the first contact plug (620A1) and the second contact plug (620A2). Here, the first barrier film (630A) may comprise at least one of tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0083] Next, a first barrier film (630A) formed in the MIDDLE region, FAR region, and peripheral circuit region (PER) can be removed to form a first trench (TH1). For example, the first barrier film (630A) formed on the second contact plug (620A2) can be removed to form a first trench (TH1). Additionally, the first barrier film (630A) formed in the MIDDLE region and FAR region can be removed to form a first trench (TH1). In this case, the first barrier film (630A) formed on the first contact plug (620A1) may remain, and the remaining first barrier film (630A) may extend to the NEAR region. The remaining first barrier film (630A) can be used as a first barrier pattern (630).

[0084] Referring to FIGS. 7a through 7d, a second barrier film (640A) can be formed in the NEAR region, MIDDLE region, FAR region, and peripheral circuit region (PER). A second barrier film (640A) can be formed on the first barrier pattern (630). Additionally, a second barrier film (640A) can be formed on the second contact plug (620A2). Here, the second barrier film (640A) may comprise at least one of tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0085] Next, a second barrier film (640A) formed in the FAR region and the surrounding circuit region (PER) can be removed to form a second trench (TH2). For example, a second barrier film (640A) formed on the second contact plug (620A2) can be removed to form a second trench (TH2). Additionally, a second barrier film (640A) formed in the FAR region can be removed to form a second trench (TH2). In this case, a second barrier film (640A) may remain on the first barrier pattern (630), and the remaining second barrier film (640A) may extend to the MIDDLE region. The remaining second barrier film (640A) can be used as a second barrier pattern (640).

[0086] Referring to FIGS. 8a through 8d, a first conductive film (650) can be formed in a NEAR region, a MIDDLE region, a FAR region, and a peripheral circuit region (PER). For example, a first conductive film (650) can be formed on a second barrier pattern (640) and a second contact plug (620A2). Here, the first conductive film (650) can be formed to fill the NEAR region, the MIDDLE region, the FAR region, and the peripheral circuit region (PER). The first conductive film (650) may include a conductive material such as tungsten.

[0087] Since the first and second barrier patterns (630, 640) are formed in the NEAR and MIDDLE regions, a step difference may occur between the FAR region and the NEAR region. In this case, the first conductive film (650) can be flattened to eliminate the step difference between the regions. For example, the first conductive film (650) can be flattened such that the sum of the thickness (T1) of the first barrier pattern (630), the thickness (T2) of the second barrier pattern (640), and the thickness (TN1) of the first conductive film (650N) is substantially equal to the sum of the thicknesses (T5, TF1) of the first conductive film (650F). Additionally, the first conductive film (650) can be flattened so that the sum of the thickness (T1) of the first barrier pattern (630), the thickness (T2) of the second barrier pattern (640), and the thickness (TN1) of the first conductive film (650N) is substantially the same as the sum of the thickness (T2) of the second barrier pattern (640) and the thickness (TM1) of the first conductive film (650M). In other words, the first conductive film (650) can be flattened so that the thickness (TN1) of the material films formed on the first contact plug (620A1) in the NEAR region, the thickness (TM1) of the material films formed on the first contact plug (620A) in the MIDDLE region, and the thickness (TF1) of the material films formed on the second contact plug (620A2) are substantially the same.

[0088] The first and second barrier patterns (630, 640) may include a material having a higher resistivity than the first conductive film (650). For example, the first and second barrier patterns (630, 640) may include a nitride, and the first conductive film (650) may include tungsten. The first and second barrier patterns (630, 640) may include substantially the same material or different materials. In one example, the first and second barrier patterns (630, 640) may include substantially the same material and may include at least one of tungsten silicon nitride (WSiN) or titanium nitride (TiN). In another example, the first barrier pattern (630) may include tungsten silicon nitride (WSiN), and the second barrier pattern (640) may include titanium nitride (TiN).

[0089] The grain size of the material film formed on the substrate can vary depending on the material of the base. As the grain size decreases, the number of grain boundaries may increase, and these grain boundaries can hinder the movement of electrons, thereby increasing resistivity.

[0090] For example, when a material film formed of an oxide is used as a substrate, the grain size of the tungsten material film formed on the substrate may be large. On the other hand, when a material film formed of a nitride is used as a substrate, the grain size of the tungsten material film formed on the substrate may be relatively small. In this case, the resistivity of the tungsten material film formed of a nitride as a substrate may be higher.

[0091] According to one embodiment of the present invention, a first conductive film (650N, 650M) formed in the NEAR region and the MIDDLE region may be formed using first and second barrier patterns (630, 640) as substrates, and a first conductive film (650F) formed in the FAR region may be formed using an interlayer insulating film (610) as a substrate. In this case, the resistivity of the first conductive film (650N, 650M) formed in the NEAR region and the MIDDLE region may be greater than that of the first conductive film (650F) formed in the FAR region.

[0092] Referring to FIGS. 9a through 9d, first memory lines (ML) can be formed on a first conductive film (650). First, a memory film (MA) including a lower electrode film (661A), a variable resistor film (663A), and an upper electrode film (665A) can be formed on the first conductive film (650). Subsequently, the memory film (MA) can be etched to form memory lines (ML) extending in a first direction (I). Here, the memory lines (ML) may each include a lower electrode line (661L), a variable resistor line (663L), and an upper electrode line (665L).

[0093] Next, the first conductive film (650) can be etched to form first conductive lines. Here, the first conductive lines may extend in the same direction as the memory lines (ML). For example, the first conductive lines may extend in the first direction (I). Here, the first conductive lines may each be electrically connected to the first contact plugs (620A). The first conductive lines may be used as word lines or bit lines as row lines.

[0094] Next, first liner patterns (LN1) and first gap-fill patterns (GF1) can be formed on memory lines (ML) and first conductive lines. First, a first liner film can be formed along the profiles of memory lines (ML) and first conductive lines. Next, a first gap-fill film can be formed on the first liner film to fill the space between memory lines (ML). Next, the first gap-fill film and the first liner film can be flattened so that memory lines (ML) are exposed. In this process, the first gap-fill film can be separated into first gap-fill patterns (GF1), and the first liner film can be separated into first liner patterns (LN1). Here, the first liner patterns (LN1) may include an insulating material such as a nitride, and the first gap-fill patterns (GF1) may include an insulating material such as an oxide.

[0095] Next, memory lines (ML) formed in the peripheral circuit region (PER) can be etched and removed. For example, memory lines (ML) can be etched and removed so that the interlayer insulating film (610) is exposed. Next, a first gap insulating film (IL1) can be formed at the location where the memory lines (ML) were etched and removed. Here, the first gap insulating film (IL1) may include an insulating material such as an oxide.

[0096] Next, second contact plugs (620B) can be formed in the peripheral circuit region (PER). Third contact plugs (620B) can be formed extending through the first gap insulating film (IL1) and the interlayer insulating film (610). The second contact plugs (620B) may include a conductive material such as tungsten.

[0097] Referring to FIGS. 10a through 10g, fourth barrier patterns (670) can be formed on memory lines (ML). For example, a fourth barrier pattern (670) can be formed extending onto a third contact plug (620B) on memory lines (ML) in a NEAR region. The fourth barrier patterns (670) may include at least one of tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0098] Next, fifth barrier patterns (680) can be formed on the fourth barrier patterns (670). Additionally, fifth barrier patterns (680) can be formed on the memory lines (ML). For example, a fifth barrier pattern (680) extending onto the third contact plug (620B) on the memory lines (ML) of the MIDDLE region can be formed. The fifth barrier patterns (680) may include at least one of tungsten silicon nitride (WSiN) or titanium nitride (TiN).

[0099] Next, second conductive lines (690) can be formed on the first conductive lines. First, a second conductive film can be formed on the fifth barrier patterns (680), memory lines (ML), and third contact plugs (620B). Since a step difference may occur between the NEAR region, MIDDLE region, and FAR region during the process of forming the second conductive film, the second conductive film can be flattened to eliminate the step difference between regions. For example, the second conductive film can be flattened so that the sum (TN2) of the thickness (T6) of the fourth barrier pattern (670) in the NEAR region, the thickness (T7) of the fifth barrier pattern (680), and the thickness (T8) of the second conductive film, the sum (TM2) of the thickness (T7) of the fifth barrier pattern (680) in the MIDDLE region and the thickness (T9) of the second conductive film, and the thickness (T10, TF2) of the second conductive film in the FAR region are substantially the same.

[0100] Next, the second conductive film can be etched in a second direction (II) intersecting the first direction (I) to form second conductive lines (690) extending in the second direction (II). Here, the second conductive lines (690) can each be electrically connected to the third contact plugs (620B). The second conductive lines (690) can be used as column lines, bit lines, or word lines. The second conductive lines (690N, 690M) in the NEAR and MIDDLE regions may have a smaller grain size than the second conductive line (690F) in the FAR region. The second conductive lines (690) may include a conductive material such as tungsten.

[0101] Next, memory lines (ML) can be etched to form memory cells (MC). Here, each memory cell (MC) may include a lower electrode pattern (661), a variable resistor pattern (663), and an upper electrode pattern (665). Here, the memory cell (MC) located in the NEAR region may be a first memory cell (MC1), the memory cell (MC) located in the MIDDLE region may be a second memory cell (MC2), and the memory cell (MC) formed in the FAR region may be a third memory cell (MC3).

[0102] Next, second liner patterns (LN2) and second gap-fill patterns (GF2) can be formed on the memory cells (MC) and the second conduction lines (690). The second liner patterns (LN2) and the second gap-fill patterns (GF2) can be formed in the same manner as the first liner patterns (LN1) and the first gap-fill patterns (GF1). The second liner patterns (LN2) may include an insulating material such as a nitride, and the second gap-fill patterns (GF2) may include an insulating material such as an oxide.

[0103] Next, memory cells (MC) formed in the peripheral circuit region (PER) can be etched and removed. For example, memory cells (MC) can be etched and removed so that the first conductive line (650) is exposed. Next, a second gap insulating film (IL2) can be formed at the location where the memory cells (MC) were etched and removed. Here, the second gap insulating film (IL2) may include an insulating material such as an oxide.

[0104] Memory cells (MC) can be arranged in a first direction (I) and a second direction (II). Memory cells (MC) can be positioned between the conduction lines (650) and the conduction lines (690), respectively. Memory cells (MC) may include a first memory cell (MC1) having a first current path through the NEAR region, a second memory cell (MC2) having a second current path through the MIDDLE region, and a third memory cell (MC3) having a third current path through the FAR region.

[0105] The first memory cell (MC1) may have a first current path having a first resistance. For example, the first memory cell (MC1) may have a first current path from the first contact plug (620A1) to the third contact plug (620B) through the first barrier pattern (630), the second barrier pattern (640), the first conduction line (650N), the first memory cell (MC1), and the second conduction line (690N). Here, the first current path may further include a path from the first memory cell (MC1) to the second conduction line (690N) through the third barrier pattern (670) and the fourth barrier pattern (680). Here, the first current path may have a first resistance.

[0106] The second memory cell (MC2) may have a second current path having a second resistance. For example, the second memory cell (MC2) may have a second current path from the first contact plug (620A) to the third contact plug (620B) through the second barrier pattern (640), the first conduction line (650M), the second memory cell (MC2), and the second conduction line (690M). Here, the second current path may further include a path from the second memory cell (MC2) to the second conduction line (690M) through the fourth barrier pattern (680). Here, the second current path may have a second resistance.

[0107] The third memory cell (MC3) may have a third current path having a third resistance. For example, the third memory cell (MC3) may have a third current path from the second contact plug (620A2) to the third contact plug (620B) through the third memory cell (MC3) and the second conduction line (690F).

[0108] Here, the first, second, third, and fourth barrier patterns (630, 640, 670, 680) may have a higher resistivity than the conduction lines (650, 690). Additionally, the first and second conduction lines (650N, 650M, 690N, 690M) in the NEAR and MIDDLE regions may have a higher resistivity than the first and second conduction lines (650F, 690F) in the FAR region. In this case, the first resistance of the first current path, the second resistance of the second current path, and the third resistance of the third current path may be substantially the same. In other words, the grain size of the first and second conduction lines (650N, 650M, 690N, 690M) and the first, second, third, and fourth barrier patterns (630, 640, 670, 680) can compensate the first and second resistances to be substantially equal to the third resistance. Accordingly, according to one embodiment of the present invention, overshoot can be prevented in the first and second memory cells (MC1, MC2), and a sensing margin can be secured by reducing the difference in the dispersion of the threshold voltage between the first, second, and third memory cells (MC1, MC2, MC3).

[0109] For reference, the present drawing illustrates a case where the first and second barrier patterns (630, 640) and the third and fourth barrier patterns (670, 680) are all formed in the NEAR region, but is not limited thereto. For example, if the first and second barrier patterns (630, 640) in the NEAR region are formed, the third and fourth barrier patterns (670, 680) may not be formed. For another example, if the third and fourth barrier patterns (670, 680) are formed, the first and second barrier patterns (630, 640) may not be formed. In other words, if the total resistance of each of the first, second, and third current paths is substantially the same through the first and second barrier patterns (630, 640), the third and fourth barrier patterns (670, 680) may be omitted. Likewise, the same can be applied to the second barrier patterns (640) and / or fourth barrier patterns (680) in the MIDDLE region.

[0110] According to the manufacturing method described above, at least one barrier pattern can be formed between the contact plug and the conduction line to compensate for the resistance of the current path of memory cells in the NEAR region and MIDDLE region, where the current path is short and the total resistance of the current path is relatively small.

[0111] In addition, by using a barrier pattern as a substrate and forming a conductive line on the barrier pattern, a conductive line having a relatively small grain size can be formed. Therefore, by compensating the total resistance of the current path to a similar level regardless of the region and current path, the sensing margin of the semiconductor device can be secured and damage to the memory cells can be prevented.

[0113] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, this is merely for the purpose of explaining embodiments according to the concept of the present invention, and the present invention is not limited to the above embodiments. Within the scope of the technical concept of the present invention as described in the claims, various substitutions, modifications, and changes to the embodiments may be made by those skilled in the art to which the present invention belongs, and such are also to be considered to be within the scope of the present invention.

Claims

Claim 1 A semiconductor device comprising: a first row line; a first column line located on the first row line; a first memory cell located between the first row line and the first column and having a first current path; a third row line; a third column line located on the third row line; a third memory cell located between the third row line and the third column line and having a third current path longer than the first current path; first contact plugs electrically connected to the first row line and the third row line, respectively; second contact plugs electrically connected to the first column line and the third column line, respectively; a first barrier pattern located between one of the first contact plugs and the first row line; and a second barrier pattern located between the first barrier pattern and the first row line. Claim 2 A semiconductor device according to claim 1, wherein the first memory cell has the first current path from the first contact plug through the first barrier pattern, the second barrier pattern, the first row line, the first memory cell, and the first column line to the second contact plug, and the third memory cell has the third current path from the first contact plug through the third row line, the third memory cell, and the third column line to the second contact plug. Claim 3 A semiconductor device according to claim 1, wherein the first current path has a first resistance and the third current path has a third resistance substantially identical to the first resistance. Claim 4 A semiconductor device according to claim 1, wherein the sum of the thickness of the first barrier pattern, the thickness of the second barrier pattern, and the thickness of the first row line is substantially the same as the thickness of the third row line. Claim 5 A semiconductor device according to claim 1, wherein the resistivity of each of the first barrier pattern and the second barrier pattern is greater than the resistivity of each of the first row line and the third row line. Claim 6 A semiconductor device according to claim 5, wherein at least one of the first barrier pattern or the second barrier pattern comprises tungsten silicon nitride or titanium nitride, and at least one of the first row line or the third row line comprises tungsten. Claim 7 A semiconductor device according to claim 1, wherein the first barrier pattern and the second barrier pattern each comprise different materials. Claim 8 A semiconductor device according to claim 7, wherein the first barrier pattern comprises tungsten silicon nitride and the second barrier pattern comprises titanium nitride. Claim 9 A semiconductor device according to claim 1, wherein the grain size of the first row line is smaller than the grain size of the third row line. Claim 10 A semiconductor device according to claim 9, wherein the resistivity of the first row line is greater than the resistivity of the third row line. Claim 11 A semiconductor device according to claim 1, further comprising: a third barrier pattern positioned between one of the second contact plugs and the first column line; and a fourth barrier pattern positioned between the third barrier pattern and the first column line. Claim 12 A semiconductor device according to claim 1, wherein the first row line and the third row line are located on the first contact plugs, and the first column line and the third column line are located on the second contact plugs. Claim 13 A semiconductor device according to claim 1, further comprising: a second row line; a second column line located on the second row line; a second memory cell located between the second row line and the second column line; and a fifth barrier pattern located between one of the first contact plugs and the second row line. Claim 14 A semiconductor device according to claim 13, wherein the first memory cell has a first current path from the first contact plug to the second contact plug through the first barrier pattern, the second barrier pattern, the first row line, the first memory cell, and the first column line, the second memory cell has a second current path from the first contact plug to the second contact plug through the fifth barrier pattern, the second row line, the second memory cell, and the second column line, and the third memory cell has a third current path from the first contact plug to the second contact plug through the third row line, the third memory cell, and the third column line. Claim 15 In claim 14, the semiconductor device wherein the second current path is longer than the first current path and shorter than the third current path. Claim 16 A semiconductor device according to claim 14, wherein the first current path has a first resistance, the second current path has a second resistance substantially identical to the first resistance, and the third current path has a third resistance substantially identical to the first resistance. Claim 17 A semiconductor device according to claim 13, wherein the sum of the thickness of the fifth barrier pattern and the thickness of the second row line is substantially the same as the sum of the thickness of the first barrier pattern, the thickness of the second barrier pattern and the thickness of the first row line, and is substantially the same as the thickness of the third row line. Claim 18 A semiconductor device according to claim 13, wherein the resistivity of the fifth barrier pattern is greater than the resistivity of each of the first row line, the second row line, and the third row line. Claim 19 A semiconductor device according to claim 18, wherein at least one of the first barrier pattern, the second barrier pattern, or the fifth barrier pattern comprises tungsten silicon nitride or titanium nitride, and at least one of the first row line, the second row line, or the third row line comprises tungsten. Claim 20 A semiconductor device according to claim 13, wherein the fifth barrier pattern comprises a material different from the first barrier pattern and substantially the same material as the second barrier pattern. Claim 21 A semiconductor device according to claim 20, wherein the first barrier pattern comprises tungsten silicon nitride, and at least one of the second barrier pattern or the fifth barrier pattern comprises titanium nitride. Claim 22 A semiconductor device according to claim 13, wherein the grain size of the second row line is larger than the grain size of the first row line and smaller than the grain size of the third row line. Claim 23 A semiconductor device according to claim 13, wherein the resistivity of the second row line is smaller than the resistivity of the first row line and larger than the resistivity of the third row line. Claim 24 A semiconductor device according to claim 13, further comprising: a third barrier pattern positioned between one of the second contact plugs and the first column line; a fourth barrier pattern positioned between the third barrier pattern and the first column line; and a sixth barrier pattern positioned between one of the second contact plugs and the second column line. Claim 25 A semiconductor device according to claim 13, wherein the first row line, the second row line and the third row line are located on the first contact plugs, and the first column line, the second column line and the third column line are located on the second contact plugs. Claim 26 A semiconductor device comprising: a first row line having a first grain size; a first column line located on the first row line; a first memory cell located between the first row line and the first column and having a first current path; a second row line having a second grain size larger than the first grain size; a second column line located on the second row line; a second memory cell located between the second row line and the second column line and having a second current path longer than the first current path; first contact plugs electrically connected to the first row line and the second row line, respectively; and second contact plugs electrically connected to the first column line and the second column line, respectively. Claim 27 A semiconductor device according to claim 26, further comprising: a third row line having a third grain size larger than the second grain size; a third column line located on the third row line; and a third memory cell located between the third row line and the third column line and having a third current path larger than the second current path. Claim 28 A semiconductor device according to claim 27, further comprising: a first barrier pattern positioned between one of the first contact plugs and the first row line; a second barrier pattern positioned between the first barrier pattern and the first row line; and a fifth barrier pattern positioned between one of the first contact plugs and the second row line. Claim 29 A semiconductor device according to claim 28, wherein the first memory cell has a first current path from the first contact plug to the second contact plug through the first barrier pattern, the second barrier pattern, the first row line, the first memory cell, and the first column line, the second memory cell has a second current path from the first contact plug to the second contact plug through the fifth barrier pattern, the second row line, the second memory cell, and the second column line, and the third memory cell has a third current path from the first contact plug to the second contact plug through the third row line, the third memory cell, and the third column line. Claim 30 A semiconductor device according to claim 29, wherein the first current path has a first resistance, the second current path has a second resistance substantially identical to the first resistance, and the third current path has a third resistance substantially identical to the first resistance. Claim 31 A semiconductor device according to claim 28, wherein the sum of the thickness of the first barrier pattern, the thickness of the second barrier pattern, and the thickness of the first row line is substantially the same as the sum of the thickness of the fifth barrier pattern and the thickness of the second row line, and is substantially the same as the thickness of the third row line. Claim 32 A semiconductor device according to claim 28, wherein the resistivity of each of the first barrier pattern, the second barrier pattern, and the fifth barrier pattern is greater than the resistivity of each of the first row line, the second row line, and the third row line. Claim 33 A semiconductor device according to claim 32, wherein at least one of the first barrier pattern, the second barrier pattern, or the fifth barrier pattern comprises tungsten silicon nitride or titanium nitride, and at least one of the first row line, the second row line, or the third row line comprises tungsten. Claim 34 A semiconductor device according to claim 28, wherein the first barrier pattern comprises a material different from at least one of the second barrier pattern or the fifth barrier pattern, and the second barrier pattern and the fifth barrier pattern comprise substantially the same material. Claim 35 A semiconductor device according to claim 34, wherein the first barrier pattern comprises tungsten silicon nitride, and at least one of the second barrier pattern or the fifth barrier pattern comprises titanium nitride. Claim 36 A semiconductor device according to claim 27, wherein the resistivity of the first row line is greater than the resistivity of the second row line, and the resistivity of the second row line is greater than the resistivity of the third row line. Claim 37 A semiconductor device according to claim 28, further comprising: a third barrier pattern positioned between one of the second contact plugs and the first column line; a fourth barrier pattern positioned between the third barrier pattern and the first column line; and a sixth barrier pattern positioned between one of the second contact plugs and the second column line. Claim 38 A semiconductor device according to claim 27, wherein the first row line, the second row line and the third row line are located on the first contact plugs, and the first column line, the second column line and the third column line are located on the second contact plugs.

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