Display device
Patent Information
- Application Number
- KR1020250026578
- Authority / Receiving Office
- KR · KR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-09-04
Smart Images
Figure PAT00001_ABST
Abstract
Description
Technology Field
[0001] The embodiment relates to a display device with improved image quality. Background Technology
[0002] Various flat-panel display devices are known, such as Liquid Crystal Displays (LCDs) and Electroluminescence Displays (ELEDs). Electroluminescence displays can display input images by emitting light independently without a backlight, utilizing light-emitting elements placed in each pixel. The light-emitting elements of ELEDs can be classified into organic light-emitting diodes (OLEDs) and inorganic light-emitting diodes (OLEDs) depending on the material of the light-emitting layer. Active matrix type OLEDs utilize self-emissive Organic Light Emitting Diodes (OLEDs) placed in each pixel; they offer advantages such as fast response speed, high luminous efficiency, brightness, and viewing angle, as well as excellent contrast ratio and color reproduction because they can express black gradations as perfect black.
[0003] Multiple subpixels can emit light when a data voltage is applied by a data driver. However, since there is a resistance variation between the multiple subpixels and the data driver, the gate-source voltage of the driving transistor of each subpixel is different, and the brightness may become non-uniform. The problem to be solved
[0004] The embodiment provides a display device with improved luminance non-uniformity of a plurality of subpixels.
[0005] An embodiment provides a display device capable of sensing a resistance difference between a subpixel positioned at the center of a data driving element and a subpixel positioned at the edge.
[0006] The problems of the present embodiment are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem
[0007] A display device according to the present embodiment comprises: a display panel having a plurality of data lines, a plurality of gate lines, a plurality of reference lines, and a plurality of subpixels arranged thereon; a data driver connected to a plurality of data lines and a plurality of reference lines; a gate driver connected to a plurality of gate lines; a level shifter that outputs a gate clock signal to a gate driver; and a timing controller that controls the data driver and the gate driver, wherein the level shifter outputs a gate clock signal with a pulse width adjusted to a gate driver according to the resistance deviation of the reference lines to which a plurality of subpixels are connected.
[0008] A plurality of subpixels includes a first subpixel connected to the outermost reference line among a plurality of reference lines connected to a data driving element of a data driving unit, and a second subpixel connected to the centermost reference line among a plurality of reference lines, and the timing controller can output a control signal to a level shifter so that the pulse width of a gate clock signal is adjusted according to the resistance deviation of the reference lines to which the first subpixel and the second subpixel are connected.
[0009] The timing controller can output a control signal to the level shifter so that the timing of the rising edge of the gate clock signal is adjusted.
[0010] A subpixel may include a driving transistor comprising a first node and a second node connected to a light-emitting element, a first transistor connected between the first node of the driving transistor and a data line; a second transistor connected between the second node of the driving transistor and a reference line; a storage capacitor connected between the first node and the second node; a first reference voltage switch for applying a driving reference voltage to a reference line; and a second reference voltage switch for applying a sensing reference voltage to a reference line.
[0011] When the subpixel operates in reference line sensing mode, it may include an initialization period for charging a driving reference voltage of a first voltage level to a second node, a floating period for charging a driving reference voltage of a second voltage level lower than the first voltage level to a reference line and floating the reference line, and a sensing period for electrically connecting the second node and the reference line to sense the voltage of the reference line.
[0012] During the initialization period, the first reference voltage switch and the second transistor can be turned on to apply a driving reference voltage of the first voltage level to the second node.
[0013] During the initialization period, a sensing data voltage is applied to the first node, and the first voltage level may be higher than the sensing data voltage.
[0014] During the floating period, the second transistor can be turned off, the driving reference voltage can be changed to the second voltage level to charge the reference line, and then the first reference voltage switch can be turned off.
[0015] The second voltage level can be higher than the reference voltage for sensing.
[0016] During the sensing period, the second transistor is turned on to connect the second node and the reference line, and the sensing voltage charged in the sensing capacitor of the reference line may vary depending on the resistance of the reference line.
[0017] The power supply unit for applying a driving reference voltage to the data driving unit is further included, and the timing controller can apply a control signal to the power supply unit to change the voltage level of the driving reference voltage during the floating period.
[0018] The timing controller can increase the pulse width of the gate clock signal when the sensing voltage deviation of the reference line connecting the first subpixel and the second subpixel is greater than a predetermined deviation.
[0019] The timing controller further includes a memory in which information on the deviation threshold and the pulse width of a gate clock signal is stored, and when the sensing voltage deviation of a reference line connected to a first subpixel and a second subpixel is greater than the deviation threshold, the pulse width of the gate clock signal can be increased according to the pulse width information stored in the memory. Effects of the invention
[0020] According to the embodiment, the luminance deviation of a plurality of subpixels can be reduced to improve the visibility of vertical band shapes at equal intervals. Accordingly, luminance non-uniformity can be improved.
[0021] In addition, the charge deviation of the gate-source voltage between the subpixel placed at the center of the data driving element and the subpixel placed at the edge can be sensed, and accordingly, the width of the gate clock signal can be adjusted to reduce the charge deviation of the gate-source voltage.
[0022] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing
[0023] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a diagram showing an example of a sensing period. FIG. 3 is a drawing showing a display device according to one embodiment of the present invention. Figure 4 is a diagram showing that the lengths of multiple reference lines connected to the source driver are different. FIG. 5 is a circuit diagram showing a sensing unit electrically connected to a pixel circuit according to one embodiment of the present invention. Figures 6 to 8 are diagrams showing the process of sensing the electromotive force voltage line. FIG. 9 is a waveform diagram of a gate signal and voltage input to a pixel circuit of a first subpixel and a second subpixel according to an embodiment of the present invention. FIG. 10 is a diagram showing the connection structure between a timing controller, a level shifter, a gate driving circuit, and a display panel according to one embodiment of the present invention. Figure 11 is a diagram showing the state in which the resistance deviation of the first subpixel and the second subpixel is improved when the width of the gate clock is increased. FIG. 12 is a waveform diagram showing the waveforms of gate clock signals according to one embodiment. Specific details for implementing the invention
[0024] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below but may be implemented in various different forms; the embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.
[0025] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention.
[0026] Where terms such as “comprising,” “including,” “having,” “consisting of,” etc. are used in this specification, other parts may be added unless “~ only” is used. Where a component is expressed in the singular, it may be interpreted as plural unless specifically stated otherwise.
[0027] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.
[0028] Where positional and interconnected relationships are described between two components, such as 'on', 'above', 'below', 'next to', 'connect or couple', or 'crossing or intersecting', one or more other components may be interposed between those components unless otherwise noted, such as 'immediately' or 'directly'.
[0029] When temporal sequences are described using 'after', 'following', 'next', 'before', etc., they may not be continuous on the time axis unless 'immediately' or 'directly' is used.
[0030] First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name preceding the component.
[0031] The following embodiments may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or together in an associated relationship.
[0032] In the display device of the present invention, the pixel circuit may include a plurality of transistors. The transistor may be an Oxide TFT (Thin Film Transistor) including an oxide semiconductor or an LTPS TFT including Low Temperature Poly Silicon (LTPS).
[0033] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode from which carriers exit the transistor. In a transistor, the flow of carriers is from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage to allow electrons to flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain toward the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source toward the drain. In a p-channel transistor, current flows from the source toward the drain because holes flow from the source toward the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.
[0034] The gate signal can swing between the gate on voltage and the gate off voltage. The transistor turns on in response to the gate on voltage, while it turns off in response to the gate off voltage. In the case of an n-channel transistor, the gate on voltage can be the gate high voltage, and the gate off voltage can be the gate low voltage (VGL).
[0035] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.
[0036] Referring to FIG. 1, a display device according to an embodiment of the present invention may include a display panel (100), a display panel driving circuit (110, 120) for writing pixel data to pixels (101) of the display panel (100), a power supply unit (150) for generating power necessary for driving the pixels (101) and the display panel driving circuit (110, 120), etc.
[0037] The display panel (100) may be a rectangular panel having a width (or width) in the X-axis direction, a length in the Y-axis direction, and a thickness in the Z-axis direction, but is not limited thereto. The screen of the display panel (100) may include a display area (AA) and a non-display area (NA) outside the display area (AA). The display area (AA) of the display panel (100) may include a pixel array that displays an input image. The pixel array may include a plurality of data lines (102), a plurality of gate lines (103) that intersect the plurality of data lines (102), a plurality of reference lines (104), and pixels arranged in a matrix form. The display panel (100) may further include power lines commonly connected to the pixels. The power lines are commonly connected to the pixel circuits and can supply the voltage required for driving the pixels (101) to the pixels (101).
[0038] A plurality of data lines (102) are arranged in a long wiring form along the Y-axis direction of the display panel (100) and can be electrically connected to the data channels of the data driving unit (110). A plurality of reference lines (104) are arranged on the display panel parallel to the plurality of data lines (102) and can be connected to the pixels and the sensing channels of the data driving unit (110). A plurality of gate lines (103) are arranged in a long wiring form along the X-axis direction of the display panel (100), intersect with the plurality of data lines (102), and can be electrically connected to the output terminals of the gate driving unit (110).
[0039] Each of the pixels (101) may be divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels may further include a white subpixel. Each of the subpixels may include a pixel circuit for driving a light-emitting element. Each pixel circuit may be connected to data lines, gate lines, and power lines.
[0040] A pixel array may include multiple pixel lines (L1 to Ln). Each of the pixel lines (L1 to Ln) may include one line of pixels arranged along the X-axis direction in the pixel array of the display panel (100). Pixels arranged in one pixel line may share multiple gate lines (103). Subpixels arranged along the Y-axis direction may share the same data line (102). One horizontal period (1H) may be the time obtained by dividing one frame period by the total number of pixel lines (L1 to Ln).
[0041] The display panel (100) can be implemented as a non-transparent display panel or a transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual background is visible. The display panel (100) can be manufactured as a flexible display panel.
[0042] The power supply unit (150) can adjust the level of the DC input voltage (Vin) applied from the host system (200) to output the voltage required for driving the pixel array of the display panel (100) and the display panel driving circuit.
[0043] The power supply unit (150) may include a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc.
[0044] The power supply unit (150) can output a gamma reference voltage, a gate high voltage, a gate low voltage, a pixel driving voltage, a pixel ground voltage, a reference voltage, an IC (Integrated Circuit) driving voltage, etc. through a DC-DC converter. The voltages output from the power supply unit (150) may be constant voltages (or DC voltages). The gamma reference voltage may be supplied to the data driving unit (110). The dynamic range of the data voltage output from the data driving unit (110) may be determined according to the voltage range of the gamma reference voltage. The dynamic range of the data voltage has a voltage range between the highest grayscale voltage and the lowest grayscale voltage. The voltage level of the data voltage may be selected by the grayscale value of the pixel data.
[0045] The gate high voltage and gate low voltage can be supplied to the level shifter (140) and the gate driver (120). Voltages such as the pixel driving voltage, pixel ground voltage, and reference voltage can be supplied to the pixels (101) through power lines commonly connected to the pixels (101). The IC driving voltage may be the driving voltage of a source drive in which the circuits of the timing controller (130) and the data driver (11) are built.
[0046] The power supply unit (150) may be implemented with a power IC such as a PMIC (Power Management Integrated Circuit) or an ELIC (Electronics Integrated Circuit), but is not limited thereto. The power supply unit (150) can adjust the output voltage under the control of the timing controller (130). For example, when the power supply unit (150) is connected to the timing controller (130) via a serial interface such as I2C, the timing controller (130) can vary the voltage level of the voltage output from the power supply unit (150) by transmitting a command signal containing a register setting value to the voltage control register of the power supply unit (150). For example, the timing controller (130) can output a control signal to the power supply unit (150) so that the voltage level of the reference voltage for driving the sensing unit is varied.
[0047] The display panel driving circuit (110, 120) can write pixel data of an input image to the pixels of the display panel (100) under the control of the timing controller (130). The display panel driving circuit (110, 120) may include a data driving unit (110) and a gate driving unit (120). The display panel driving circuit (110, 120) may further include a demultiplexer (DEMUX) positioned between the data driving unit (110) and a plurality of data lines (102), but is not limited thereto. When demultiplexers are positioned between the output terminals of the data driving unit (110) and the plurality of data lines (102), the number of data channels of the data driving unit (110) may be reduced.
[0048] The display device may include a sensing unit (Fig. 5, 300) connected to subpixels. The sensing unit (300) can convert a sensing voltage obtained from the subpixels through a reference line (104) into a digital signal (hereinafter referred to as “sensing data”) (DSEN) and transmit it to a timing controller (130). The circuit of the sensing unit (300) may be placed in the sensing channel of the data driving unit (110).
[0049] Touch sensors for sensing touch input may be placed on a display panel (100). The touch sensors may be placed on the display panel (100) as an on-cell type or add-on type, or implemented as in-cell type touch sensors embedded in a pixel array.
[0050] The display panel driving circuit (110, 120) may further include a touch sensor driving unit for driving touch sensors. The touch sensor driving unit is omitted in FIG. 1. The data driving unit (110) and the touch sensor driving unit may be integrated into a single drive IC.
[0051] The data driving unit (110) can receive pixel data of an input image received as a digital signal from the timing controller (130) and output a data voltage. The data driving unit (110) may include data channels that are electrically connected to a plurality of data lines (102) to output a data voltage, and sensing channels that are electrically connected to a plurality of reference lines (104) to receive a sensing voltage.
[0052] The data channels of the data driver (110) can convert the pixel data (DATA') of the input image received from the timing controller (130) into a gamma compensation voltage using a digital-to-analog converter (hereinafter referred to as “DAC”) and output the data voltage of the pixel data. The gamma reference voltage can be divided into gamma compensation voltages for each grayscale through a voltage divider circuit. The gamma compensation voltages for each grayscale can be provided to the DAC of the data driver (110). The data voltage can be output through an output buffer at each of the channels of the data driver (110).
[0053] The sensing channels of the data driving unit (110) may include an Analog to Digital Converter (hereinafter referred to as “ADC”). The sensing channels may use the ADC to convert a sensing voltage received through a plurality of reference lines (104) into digital data and output sensing data (Dsen). The sensing data (Dsen) may be transmitted to a timing controller (130).
[0054] The gate driving unit (120) may be positioned on at least one non-display area (BZ) on the left and right sides outside the display area (AA) of the display panel (100), or at least a portion thereof may be positioned within the display area (AA).
[0055] The gate driver (120) is positioned on both non-display areas (BZ) of the display panel (100) with the display area (AA) of the display panel in between, and can supply gate pulses in a double feeding manner from both sides of a plurality of gate lines (103). In another embodiment, the gate driver (120) is positioned on at least one side of the left and right non-display areas (AA) of the display panel (100) and can supply gate signals to a plurality of gate lines (103) in a single feeding manner. The gate driver (120) can sequentially output pulses of gate signals to a plurality of gate lines (103) under the control of a timing controller (130). The gate driver (120) can sequentially supply the signals to a plurality of gate lines (103) by shifting the pulses of the gate signals using a shift register. A plurality of gate signals can be applied to the pixel circuit. In this case, the gate driving unit (120) may include a plurality of shift registers that output pulses of gate signals.
[0056] The timing controller (130) can receive digital video data of an input image and a timing signal synchronized with the data from the host system (200). Based on the timing signal received from the host system (200), the timing controller (130) can generate a data timing control signal for controlling the operation timing of the data driver (110) and a gate timing control signal for controlling the operation timing of the gate driver (120). The timing controller (130) synchronizes the data driver (110) and the gate driver (120) by controlling the operation timing of the display panel driving circuit.
[0057] The gate timing control signal output from the timing controller (130) can be input to the shift register of the gate driver (120) through the level shifter (140). The level shifter (140) can convert the gate timing control signal received from the timing controller (130) through the clock lines (105) into a swing width between the gate high voltage and the gate low voltage and provide it to the gate driver (120).
[0058] The gate timing control signal output from the level shifter (140) may include, but is not limited to, a start signal, a clock, a line selection signal, a reset signal, etc. The gate driving unit (120) may output a gate signal pulse for writing pixel data to subpixels during a display period in response to the gate timing control signal input from the level shifter (140), and may output a gate signal pulse for sensing the electrical properties of subpixels during a sensing period.
[0059] According to an embodiment, the timing controller (130) can modulate the gate timing control signal to adjust the pulse width of the gate clock signal of the level shifter (140).
[0060] The host system (200) can convert the resolution of the video signal from the video source to match the resolution of the display panel (100) and transmit it to the timing controller (130) along with the timing signal.
[0061] The sensing unit (Fig. 5, 300) can sense the electrical characteristics of the light-emitting element and / or driving transistor in all subpixels in line units by sequentially sensing the subpixels of the display area (AA) during a preset sensing period under the control of the timing controller (130), such as the gate-source voltage deviation of each driving transistor, the resistance deviation of the reference line, mobility, threshold voltage, etc.
[0062] The timing controller (130) can determine the electrical characteristic value or resistance deviation of circuit elements, such as light-emitting elements and driving transistors, included in the corresponding subpixel based on the sensing data (Dsen) received through the sensing unit (300).
[0063] The timing controller (130) can derive a compensation value to compensate for the optical and electrical characteristics of each subpixel based on the sensing data (Dsen). For example, the timing controller (130) can derive a compensation value to compensate for the optical and electrical characteristics of the pixels based on the sensing data (Dsen) by executing a preset compensation algorithm, or it can derive a compensation value output from the look-up table by inputting the sensing data (Dsen) into a look-up table (LUT) stored in the memory (132).
[0064] In the lookup table, compensation values corresponding to the initial optical and electrical characteristic values measured for each subpixel during the aging and inspection processes of the display panel are set for each subpixel. The compensation values stored in the lookup table can be updated according to the sensing values that reflect the accumulated degradation as the driving time of the subpixels increases. The compensation circuit of the timing controller (130) can compensate for deviations and changes in the electrical characteristics of the light-emitting element and / or driving transistor in each subpixel by adding or multiplying the compensation value derived from the lookup table to the pixel data of the input image.
[0065] The memory (132) may store driving setting timing information of the display panel driving circuit (110, 120), a lookup table that derives a compensation value based on the sensing results of subpixels, and program code of a compensation algorithm for improving image quality. The memory (132) may include non-volatile memory and volatile memory. The non-volatile memory may include one or more of readable and writeable memory, such as NAND flash memory, NOR flash memory, and EEPROM (Electrically Erasable Programmable Read-Only Memory). The NAND flash memory may be of the SLC (Single Level Cell) type. The volatile memory may include one or more of DRAM (Dynamic RAM), SRAM (Static RAM), SDRAM (Synchronous Dynamic RAM), and DDR SDRAM (Double Data Rate SDRAM).
[0066] The sensing unit (300) can sense the electrical characteristics of subpixels by being driven during a sensing period set in at least one of a Power ON sequence, in which power is applied to the display device as shown in FIG. 2, and a Power OFF sequence. The sensing unit (300) can sense the electrical characteristics of subpixels during a Vertical Blank interval (VB) in which there is no pixel data within the display period. During the sensing period, sensing data (Dsen) output from the sensing channels of the data driving unit (110) can be transmitted to the timing controller (130).
[0067] In FIG. 2, 'ON RF' represents the sensing period of subpixels performed during the power-on sequence. 'OFF RS' represents the sensing period of subpixels performed during the power-off sequence. During the sensing period (ON RF) of the power-on sequence, the mobility of the driving transistor placed in each subpixel can be sensed. During the sensing period (OFF RS) of the power-off sequence, the mobility of the driving transistor placed in each subpixel can be sensed. Additionally, during the sensing period (ON RF) of the power-on sequence or the sensing period (OFF RS) of the power-off sequence, the gate-source voltage deviation of the subpixel's transistor or the resistance deviation of the reference line to which the subpixel is connected can be sensed. The sensing of the resistance deviation of the reference line described in the following embodiments may be performed after sensing the threshold voltage, but the embodiments are not limited thereto.
[0068] The power off sequence (OFF RS) may be a process in which the power is turned off in a predetermined order when a user command is received to turn on the power off switch of the display device by the user. The timing controller (130), data driver (110), gate driver (120), and sensing unit (300) may stop driving when the output of the power unit is cut off after the power off switch is turned on in the power off sequence (OFF RS) and after the power off switch is driven for a predetermined time to sense the electrical characteristics of the driving transistor and / or light-emitting element and the resistance deviation of the reference line in each of the subpixels.
[0069] Referring to FIGS. 3 and 4, the data driving unit (110) can be implemented using a Chip On Film (COF) method. In this case, a plurality of data driving elements (SDIC) functioning as the data driving unit (110) are mounted on a flexible film (SF), one end of the flexible film (SF) is bonded to a Source Printed Circuit Board (SPCB), and the other end is bonded to a display panel (100).
[0070] A timing controller (130) may be placed on the control printed circuit board (CPCB). A level shifter (140) and a power supply (150) may be further placed on the control printed circuit board (CPCB).
[0071] According to an embodiment, a plurality of data driving elements (SDICs) may include a plurality of link wires that spread radially toward a display panel. Among the plurality of link wires, the wires positioned at the edges may be spaced horizontally apart from the data driving chip by a first distance (L1). As the number of link wires increases, the first distance (L1) may increase.
[0072] The link wiring may be a reference line (104) connected to a pixel circuit. The link wiring may include a central wiring (104b) placed at the center of the data driving element (SDIC) and an edge wiring (104a) placed at the edge of the data driving element (SDIC). The second sub-pixel (P12) connected to the central wiring (104b) may have a lower resistance compared to the first sub-pixel (P11) connected to the edge wiring (104a). The first sub-pixel (P11) connected to the edge wiring (104a) may have a higher resistance because the wiring length is relatively longer.
[0073] The gate-source voltage of the driving transistor of the second subpixel (P12), which has low resistance, may be greater than the gate-source voltage of the first subpixel (P11). Therefore, when driving the pixel, the brightness of the second subpixel (P12) may be greater than the brightness of the first subpixel (P11). As a result, vertical stripes may be observed within the panel.
[0074] FIG. 5 is a circuit diagram showing a sensing unit electrically connected to a pixel circuit according to an embodiment of the present invention. The pixel circuit and the sensing unit are not limited to FIG. 5. In FIG. 5, 'SDIC' represents a data driving element in which the circuit of the data driving unit (110) is integrated.
[0075] Referring to FIG. 5, the pixel circuit may include a light-emitting element (EL), a driving transistor (DR), a storage capacitor (Cst), a first switch transistor (M1), and a second switch transistor (M1, M2).
[0076] The pixel circuit may include a data line (102), a gate line (103), a reference line (104), a first constant voltage node (106) to which a pixel driving voltage (EVDD) is applied, and a second constant voltage node (107) to which a pixel ground voltage (EVSS) is applied. The constant voltage nodes (106, 107) may be connected to power lines that are commonly connected to the pixels. The pixel driving voltage (EVDD) may be set to a voltage at which the driving transistor (DR) operates in the saturation region. The pixel driving voltage (EVDD) may be a voltage higher than the maximum voltage (or white gradation voltage) of the data voltage (Vdata). The pixel ground voltage (EVSS) may be a voltage lower than the minimum voltage (or black gradation voltage) of the data voltage (Vdata).
[0077] The reference voltage (VpreR, VpreS) may include a driving reference voltage (VpreR) and a sensing reference voltage (VpreS). The driving reference voltage (VpreR) may be set to a higher voltage than the sensing reference voltage (VpreS). For example, the driving reference voltage (VpreR) may be 2[V], and the sensing reference voltage (VpreS) may be ground voltage (GND) or 0[V], but is not limited thereto. The driving reference voltage (VpreR) according to the embodiment may have a variable voltage level.
[0078] The light-emitting element (EL) may be an OLED, but is not limited thereto. The light-emitting element may include an anode electrode, a cathode electrode, and a light-emitting layer disposed between these electrodes.
[0079] The driving transistor (DR) can drive the light-emitting element (EL) by generating current according to the gate-source voltage (Vgs). The gate-source voltage (Vgs) of the driving transistor (DR) is equal to the voltage between the first node (n1) and the second node (n2). The driving transistor (DR) may include a gate electrode connected to the first node (n1), a first electrode connected to the first constant voltage node (106), and a second electrode connected to the second node (n2). A pixel driving voltage (EVDD) may be applied to the first constant voltage node (106). A storage capacitor (Cst) may be connected between the first node (n1) and the second node (n2) to charge the gate-source voltage of the driving transistor (DR).
[0080] The first transistor (M1) is connected between the data line (102) and the first node (n1) and can be turned on in response to the gate-on voltage of the gate signal (SCAN). When the first transistor (M1) is turned on, the data line (102) can be electrically connected to the first node (n1). The first transistor (M1) may include a gate electrode connected to the gate line (103) to which the gate signal (SCAN) is applied, a first electrode connected to the data line (102), and a second electrode connected to the first node (n1).
[0081] The second transistor (M2) is connected between the second node (n2) and the reference line (104) and can be turned on in response to the gate-on voltage of the gate signal (SCAN). According to an embodiment, the first transistor (M1) and the second transistor (M2) may be connected to the same gate line (103). Thus, the first transistor (M1) and the second transistor (M2) may be turned on simultaneously in response to the gate-on voltage. However, the embodiments are not limited thereto. For example, the first transistor (M1) and the second transistor (M2) may be connected to different gate lines.
[0082] When the second transistor (M2) is turned on, the reference line (104) can be electrically connected to the second node (n2). The second transistor (M2) may include a gate electrode connected to the gate line (103) to which a gate signal (SCAN) is applied, a first electrode connected to the second node (n2), and a second electrode connected to the reference line (104).
[0083] The data driving unit (110) may include a plurality of data channels and a plurality of sensing channels. The data channels may input pixel data of an input image received from the timing controller (130) during the display period into the DAC of the data channel (112) to output the data voltage (Vdata) of the pixel data. The sensing channels may include a sensing unit (300). The sensing unit (300) may be electrically connected to the pixel circuit through a reference line (104).
[0084] The sensing unit (300) may include a sampling switch (SAMP), a first reference voltage switch (RPRE), a second reference voltage switch (SPRE), and an ADC. The switches (SAMP, RPRE, SPRE) of the sensing unit (300) may be implemented as transistors that are turned on / off under the control of a logic circuit or a timing controller (130) within the data driving unit (110).
[0085] When the sampling switch (SAMP) is turned on, the reference line (104) can be electrically connected to the ADC of the sensing unit (300). The first reference voltage switch (RPRE) can be turned on during the display period to supply a driving reference voltage (VpreR) to the reference line (104). The second reference voltage switch (SPRE) can be turned on during the sensing period to supply a sensing reference voltage (VpreS) to the reference line (104).
[0086] According to the embodiment, a structure in which a timing controller (130) is connected to a single pixel circuit is illustrated, but the timing controller (130) is connected to a plurality of subpixels arranged in a horizontal direction and can sense the resistance deviation of a reference line connected to a subpixel.
[0087] In the pixel circuit of the second subpixel (P12) connected to the reference line (104) with relatively low resistance, the voltage of the second node (n2) is quickly initialized from 8V to 2.5V during normal driving, but in the pixel circuit of the first subpixel (P11) connected to the reference line (104) with high resistance, even when an initialization voltage of 2.5[V] is applied to the second node (n2), it does not drop to 2.5[V] due to the resistance deviation and maintains about 3[V], so it is not completely initialized. Therefore, since the gate-source voltage (Vgs) of the driving transistor (DR) of the second subpixel (P12) is greater than the gate-source voltage (Vgs) of the first subpixel (P11), the brightness may become non-uniform.
[0088] The timing controller (130) can receive the sensing voltage of the reference line (104) connected to the first subpixel (P11) and the sensing voltage of the reference line (104) connected to the second subpixel (P12) from the sensing unit (300). The sensing voltage of the reference line (104) can be stored in the sensing capacitor (VSEN).
[0089] The timing controller (130) can output a control signal to the level shifter (140) so that the pulse width of the gate clock signal is adjusted according to the sensing voltage. The level shifter (140) can output a gate clock signal with a pulse width adjusted according to the control signal of the timing controller (130) to the gate driver (120). The gate driver (120) can apply the gate signal adjusted according to the gate clock signal to the first transistor (M1) and / or the second transistor (M2).
[0090] FIGS. 6 to 8 are drawings showing the process of sensing a reference line. FIG. 9 is a waveform diagram of a gate signal and voltage input to a pixel circuit of a first subpixel and a second subpixel according to an embodiment of the present invention.
[0091] Referring to FIG. 6, during the initialization period (T1) of the reference line sensing mode, the first transistor (M1) and the second transistor (M2) can be turned on simultaneously in response to the gate-on voltage. Accordingly, a sensing data voltage (Vdata) can be applied to the first node (n1) of the driving transistor (DR). Additionally, since the first reference voltage switch (RPRE) is turned on, a driving reference voltage (VpreR) can be applied to the second node (n2) of the driving transistor (DR).
[0092] When sensing a reference line, the driving reference voltage (VpreR) may be set lower than the OLED driving voltage. When the driving reference voltage (VpreR) is equal to the OLED driving voltage, the light-emitting element (EL) may be turned on. The driving reference voltage (VpreR) of the first voltage level may be 7[V], and the sensing data voltage (Vdata) may be 1[V]. However, the voltage levels of the driving reference voltage (VpreR) and the sensing data voltage (Vdata) are not limited to these.
[0093] According to the embodiment, the driving reference voltage (VpreR) may be greater than the sensing data voltage (Vdata). Therefore, the driving transistor (DR) may not be turned on.
[0094] A data voltage for sensing (Vdata) and a reference voltage for driving (VpreR) are applied to both ends of the storage capacitor (Cst), respectively, so that it can be charged by the difference in voltage levels.
[0095] Referring to FIG. 7, during the floating period (T2) of the reference line sensing mode, the first transistor (M1) and the second transistor (M2) can be turned off in response to the gate-off voltage. At this time, the first reference voltage switch (RPRE) can remain in the turned-on state. The driving reference voltage (VpreR) can be varied to a second voltage level lower than the first voltage level. The second voltage level of the driving reference voltage (VpreR) may be 2.5[V], but the embodiments are not limited thereto. The second voltage level may be higher than the sensing reference voltage.
[0096] The driving reference voltage (VpreR) of the second voltage level can be charged only to the reference line (104) because the second transistor (M2) is in a turned-off state. When the reference line (104) is charged to the driving reference voltage (VpreR) of the second voltage level, the first reference voltage switch (RPRE) can be turned off. Thus, the reference line (104) can be floated. The voltage charged to the reference line (104) can be stored in the sensing capacitor (VSEN) or the line capacitor.
[0097] According to an embodiment, the timing controller (130) can apply a control signal to the power supply (150) so that the power supply (150) lowers the driving reference voltage (VpreR) to a second voltage level during a floating period (T2).
[0098] However, the embodiments are not limited thereto. For example, the second reference voltage switch (SPRE) may be turned on without lowering the driving reference voltage (VpreR) to the second voltage level to charge the sensing reference voltage (VpreS) to the reference line (104). The sensing reference voltage (VpreS) may be 0[V], but the embodiments are not limited thereto.
[0099] Referring to FIG. 8, during the sensing period (T3) of the reference line sensing mode, the first transistor (M1) and the second transistor (M2) can be turned on in response to the gate-on voltage. Thus, the second node (n2) and the reference line (104) can be electrically connected. Since the reference line (104) is in a floating state, the voltage of the reference line (104) can be increased by the voltage charged in the storage capacitor (Cst).
[0100] According to the embodiment, during the initialization period (T1), the data voltage for sensing (Vdata) may not be applied, and only the driving reference voltage (VpreR) of the first voltage level may be applied to the second node (n2). In this case, the voltage of the reference line (104) may be increased by the voltage charged in the second node (n2). The increased sensing voltage of the reference line (104) may be stored in the sensing capacitor (VSEN).
[0101] During the sensing period (T3), the sampling switch (SAMP) is turned on so that the sensing unit (300) can receive the sensing voltage of the reference line (104) stored in the sensing capacitor (VSEN). The sensing unit (300) can convert the sensing voltage, which is an analog signal, into a digital signal and transmit it to the timing controller (130).
[0102] If the resistance of the reference line (104) is large, the magnitude of the voltage rise during the sensing period may be small. Conversely, if the resistance of the reference line (104) is small, the magnitude of the voltage rise may be relatively large.
[0103] Referring to FIG. 9, in the case of the second subpixel (P12) placed in the center of the data driving element (SDIC), the resistance of the reference line (104) is small, so it can be seen that the voltage is relatively higher compared to the second voltage level (VL2) (E1). At this time, the sensing voltage (VL31) of the reference line may be lower than the first voltage level (VL1).
[0104] In contrast, for the first subpixel (P11) located at the edge of the data driving element (SDIC), it can be confirmed that the sensing voltage (VL32) is not significantly different from the second voltage level (VL2) (E2). When such a resistance deviation occurs, a difference in gate-source voltage may occur during display operation, which may result in a difference in brightness.
[0105] In the embodiment, the resistance deviation between one subpixel was exemplified, but the embodiment is not limited thereto. For example, in the case of 3 colors (e.g., W / R / B), the data voltage of the green (G) color can be floated, and the resistance deviation of the reference line can be sensed by applying only the data voltages of white (W) / red (R) / blue (B). Alternatively, in the case of 4-color driving, the resistance deviation of the reference line can be sensed by applying all the data voltages of R / W / B / G.
[0106] FIG. 10 is a diagram showing the connection structure of a timing controller, a level shifter, a gate driving circuit, and a display panel according to one embodiment of the present invention.
[0107] Referring to FIG. 10, the timing controller (130) can sense the reference line (104) of the pixel circuit of the first subpixel (P11) and the second subpixel (P12) of the data driving element (SDIC) placed on the same gate line, and adjust the width of the gate clock signal of the level shifter (140) to compensate for the deviation when a deviation occurs in the reference line (104).
[0108] As the width of the gate clock signal increases, the charging time becomes longer, so the second node (n2) can be initialized even when the resistance of the reference line (104) is high. Therefore, the gate-source voltages of subpixels with resistance variations can become similar.
[0109] The timing controller (130) can control the output to maintain the existing gate clock width when the difference in sensing voltage between the reference line (104) of the first subpixel (P11) and the second subpixel (P12) is smaller than the deviation threshold stored in the memory (132).
[0110] The timing controller (130) can output a control signal to the level shifter (140) so that the pulse width of the gate clock signal increases according to the pulse width information stored in the memory (132) when the sensing voltage difference of the reference line (104) of the first subpixel (P11) and the second subpixel (P12) is greater than the deviation threshold stored in the memory (132).
[0111] The memory (132) may store deviation threshold information and pulse width information. The pulse width information may include width information of an adjustable gate clock signal. For example, the pulse width information may include 10 pulse width modulation information in which the width of the gate clock is modulated in units of several to tens of microseconds. Each pulse width information may be a pulse width that satisfies the condition that no line dim occurs during driving. The number of pulse width modulation information is not limited.
[0112] The timing controller (130) can output a control signal to the level shifter (140) so that the pulse width of the gate clock signal is adjusted according to 10 pulse width modulation information stored in the memory (132).
[0113] For example, the timing controller (130) can modulate the period of the first control clock signal (GCLK) and transmit it to the level shifter (140). If the rising edge of the first control clock signal (GCLK) is accelerated, the width of the gate clock can be increased. According to an embodiment, the output timing of the rising edge can be adjusted to accelerate in order to increase the width of the gate clock. Since adjusting the falling edge may affect the charging time in normal driving mode, it may be preferable not to modulate it.
[0114] Referring to FIG. 11, when the reference line is sensed again after adjusting the pulse width of the gate clock signal, the turn-on time of the second transistor (M2) is extended during the sensing period (T3), so the voltage of the reference line (104) connected to the first subpixel (P11) can be further increased. Therefore, when adjusted to a predetermined gate clock width, sufficient charging time is provided, and the voltages of the reference line (104) of the first subpixel (P11) and the second subpixel (P12) can become similar.
[0115] The timing controller (130) can adjust the pulse width according to information on the pulse widths of a plurality of gate clock signals stored in memory and sense deviations from the reference line. The timing controller can select the pulse width of a gate clock signal from among the pulse widths of the plurality of gate clock signals for which no voltage deviation has occurred.
[0116] However, the embodiments are not limited thereto. For example, pulse width information may be stored in a lookup table format that matches the pulse width information according to the voltage deviation of the reference line. Accordingly, the timing controller (130) may select the pulse width of the gate clock that matches the voltage deviation of the sensed reference line.
[0117] The timing controller (130) can store pulse width information of the selected gate clock signal in the memory (132). Therefore, when driving the display, it can be driven according to the pulse width of the stored gate clock signal.
[0118] Referring to FIG. 12, the level shifter can generate a plurality of gate clock signals (SCCLK1~SCCLKn) based on the first and second control clock signals (GCLK, MCLK).
[0119] The first control clock signal (GCLK) may include on-clocks (ON_CLK) that have the same amplitude and are shifted at regular intervals, and the second control clock signal (MCLK) may include off-clocks (OFF_CLK) that have the same amplitude and are shifted at regular intervals. Multiple gate clock signals (SCCLK1~SCCLKn) may be generated by logical operations of these first and second control clock signals (GCLK, MCLK).
[0120] The on-clocks (ON_CLK) supplied by the first control clock signal (GCLK) may indicate the rising timing of the gate clock signals (SCCLK1~SCCLKn), and the off-clocks (OFF_CLK) supplied by the second control clock signal (MCLK) may indicate the falling timing of the gate clock signals (SCCLK1~SCCLKn). Accordingly, gate clock signals (SCCLK1~SCCLKn) that are sequentially rising in synchronization with the on-clock (ON_CLK) of the first control clock signal (GCLK) and sequentially falling in synchronization with the off-clock (OFF_CLK) of the second control clock signal (MCLK) may be generated.
[0121] Since the pulses of the first control clock signal (GCLK) and the second control clock signal (MCLK) have the same amplitude and are shifted at a constant interval, the gate clock signals (SCCLK1~SCCLKn) generated based thereon each have the same amplitude and are shifted at a constant interval. That is, the gate clock signals (SCCLK1~SCCLKn) may be signals that have the same waveform and are phase-shifted relative to each other.
[0122] In one embodiment, the gate clock signals (SCCLK1 to SCCLKn) may be signals with a phase shifted by 1 / 4 period. For example, the second gate clock signal (SCCLK2) may be a signal with the same waveform as the first gate clock signal (SCCLK1) and with a phase shifted by 1 / 4 period.
[0123] The ON-clock (ON_CLK) of the first control clock signal (GCLK) determines the rising timing of the gate ON voltage period of the corresponding gate clock signals (SCCLK1~SCCLKn), and the OFF-clock (OFF_CLK) of the second control clock signal (MCLK) determines the falling timing of the gate ON voltage period of the corresponding gate clock signals (SCCLK1~SCCLKn). Therefore, by adjusting the pulse timing of the control clock signals (GCLK, MCLK), the length of the gate ON voltage period of the gate clock signals (SCCLK1~SCCLKn), i.e., the pulse width, can be individually controlled.
[0124] For example, the timing controller (130) can increase the pulse width of the corresponding gate clock signals (SCCLK1 to SCCLKn) by controlling the pulse timing of the first control clock signal (GCLK) to advance. For example, the pulse timing of the first control clock (GCLK) corresponding to the third gate clock signal (SCCLK3) can be advanced by Δt1.
[0125] In addition, the timing controller can advance the pulse timing of the first control clock (GCLK) corresponding to the fourth gate clock signal (SCCLK4) by Δt2.
[0126] Accordingly, the pulse widths (W3, W4) of the third and fourth gate clock signals (SCCLK3, SCCLK4) may be larger than the pulse widths (W1, W2) of the first and second gate clock signals (SCCLK1, SCCLK2). According to an embodiment, the pulse width of the gate clock signal may vary depending on the deviation of the subpixels arranged on the horizontal line.
[0127] According to an embodiment, a temperature sensor may be further provided, and the timing controller may receive the temperature sensor value. When Power OFF, the timing controller checks the ambient temperature through the temperature sensor, and pulse width modulation information for each ambient temperature may be set in the lookup table. Accordingly, the timing controller can select a suitable pulse width for each temperature.
[0128] The display device according to an embodiment of the present invention can be applied to mobile devices, video phones, smart watches, watch phones, wearable apparatuses, foldable apparatuses, rollable apparatuses, bendable apparatuses, flexible apparatuses, curved apparatuses, sliding apparatuses, variable apparatuses, electronic notebooks, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle navigation systems, vehicle display devices, vehicle devices, theater devices, theater display devices, televisions, wallpaper devices, signage devices, game devices, laptops, monitors, cameras, camcorders, home appliances, etc.
[0129] Since the contents of the specification described above regarding the problem to be solved, the means for solving the problem, and the effect do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the specification.
[0130] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols
[0131] 100: Display panel 102: Data line 103: Gate Line 104: Reference line 110: Data driver 120: Gate drive unit 130: Timing Controller 132: Memory 140: Level Shifter 150: Power supply
Claims
Claim 1 A display device comprising: a display panel having a plurality of data lines, a plurality of gate lines, a plurality of reference lines, and a plurality of subpixels arranged thereon; a data driver connected to the plurality of data lines and the plurality of reference lines; a gate driver connected to the plurality of gate lines; a level shifter that outputs a gate clock signal to the gate driver; and a timing controller that controls the data driver and the gate driver, wherein the level shifter outputs a gate clock signal with a pulse width adjusted to the gate driver according to the resistance deviation of the reference lines to which the plurality of subpixels are connected. Claim 2 A display device according to claim 1, wherein the plurality of subpixels includes a first subpixel connected to the outermost reference line among the plurality of reference lines connected to the data driving element of the data driving unit, and a second subpixel connected to the centermost reference line among the plurality of reference lines, and the timing controller outputs a control signal to the level shifter so that the pulse width of the gate clock signal is adjusted according to the resistance deviation of the reference lines to which the first subpixel and the second subpixel are connected. Claim 3 A display device according to claim 1, wherein the timing controller outputs a control signal to the level shifter so that the timing of the rising edge of the gate clock signal is adjusted. Claim 4 A display device according to claim 1, wherein the subpixel comprises: a driving transistor including a first node and a second node connected to a light-emitting element; a first transistor connected between the first node of the driving transistor and the data line; a second transistor connected between the second node of the driving transistor and the reference line; a storage capacitor connected between the first node and the second node; a first reference voltage switch for applying a driving reference voltage to the reference line; and a second reference voltage switch for applying a sensing reference voltage to the reference line. Claim 5 A display device according to claim 4, wherein the subpixel, when operating in a reference line sensing mode, includes an initialization period for charging a driving reference voltage of a first voltage level to the second node, a floating period for charging a driving reference voltage of a second voltage level lower than the first voltage level to the reference line and floating the reference line, and a sensing period for electrically connecting the second node and the reference line to sense the voltage of the reference line. Claim 6 In claim 5, the display device, wherein the initialization period turns on the first reference voltage switch and the second transistor to apply a driving reference voltage of the first voltage level to the second node. Claim 7 A display device according to claim 6, wherein a sensing data voltage is applied to the first node during the initialization period, and the first voltage level is higher than the sensing data voltage. Claim 8 In claim 5, the floating period is a display device that turns off the second transistor, changes the driving reference voltage to the second voltage level to charge the reference line, and then turns off the first reference voltage switch. Claim 9 In paragraph 8, the display device wherein the second voltage level is higher than the reference voltage for sensing. Claim 10 A display device according to claim 5, wherein the sensing period is to turn on the second transistor to connect the second node and the reference line, and the sensing voltage charged in the sensing capacitor of the reference line is different depending on the resistance magnitude of the reference line. Claim 11 A display device according to claim 8, further comprising a power supply unit that applies the driving reference voltage to the data driving unit, wherein the timing controller applies a control signal to the power supply unit to change the voltage level of the driving reference voltage during the floating period. Claim 12 In paragraph 2, the timing controller increases the pulse width of the gate clock signal when the sensing voltage deviation of the reference line connecting the first subpixel and the second subpixel is greater than a predetermined deviation. Claim 13 A display device according to claim 12, further comprising a memory in which information on the pulse width of a gate clock signal and a deviation threshold is stored, wherein the timing controller increases the pulse width of the gate clock signal according to the pulse width information stored in the memory when the sensing voltage deviation of a reference line connecting the first subpixel and the second subpixel is greater than the deviation threshold.