Semiconductor devices

Abstract

A semiconductor device according to embodiments of the present invention comprises: a bit line structure extending in a first direction; first, second, and third active patterns arranged sequentially in the first direction on the bit line structure and connected to the bit line structure; a back gate electrode structure disposed between the first active pattern and the second active pattern and including a back gate dielectric layer and a back gate electrode disposed on the back gate dielectric layer; a word line structure disposed between the second active pattern and the third active pattern; contact patterns disposed on each of the first, second, and third active patterns and connected to the first, second, and third active patterns; and an information storage structure disposed on the contact patterns, wherein the bit line structure includes a first portion vertically overlapping with the back gate electrode structure and a second portion vertically overlapping with the word line structure and disposed at a different level from the first portion, and the upper surface of the first portion and the upper surface of the second portion may be disposed at different levels.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising a vertical channel transistor. Background Technology

[0003] As demands for high performance, high speed, and / or multifunctionality in semiconductor devices increase, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration, it is required to implement patterns with fine widths or fine spacing. The problem to be solved

[0005] The technical problem to be solved by the present invention is to provide a semiconductor device comprising a memory cell array formed using a bare wafer and a structure in contact with a structure comprising a peripheral circuit.

[0006] However, the objectives of the present invention are not limited to the objectives described above and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0008] A semiconductor device according to embodiments of the present invention comprises: a bit line structure extending in a first direction; back gate structures disposed on the bit line structure and each including a back gate electrode; word line structures disposed alternately with the back gate structures in the first direction, wherein each of the word line structures includes a first word line and a second word line adjacent to each other in the first direction; active patterns disposed between the back gate structures and the word line structures and connected to the bit line structure; contact patterns disposed on each of the active patterns and connected to each of the active patterns; and an information storage structure on the contact patterns, wherein the bit line structure may include a first portion vertically overlapping with each of the back gate structures, a second portion vertically overlapping with each of the word line structures, and a third portion having an inclined surface that contacts each of the active patterns between the first portion and the second portion.

[0009] A semiconductor device according to embodiments of the present invention comprises: a bit line structure extending in a first direction; first, second, and third active patterns arranged sequentially in the first direction on the bit line structure and connected to the bit line structure; a back gate electrode structure disposed between the first active pattern and the second active pattern and including a back gate dielectric layer and a back gate electrode disposed on the back gate dielectric layer; a word line structure disposed between the second active pattern and the third active pattern; contact patterns disposed on each of the first, second, and third active patterns and connected to the first, second, and third active patterns; and an information storage structure disposed on the contact patterns, wherein the bit line structure includes a first portion vertically overlapping with the back gate electrode structure and a second portion vertically overlapping with the word line structure and disposed at a different level from the first portion, and the upper surface of the first portion and the upper surface of the second portion may be disposed at different levels.

[0010] A semiconductor device according to embodiments of the present invention comprises: a first structure including a memory cell array region; and a second structure including a peripheral circuit region that overlaps perpendicularly with the first structure. The memory cell array region includes: a bit line structure extending in a first direction; a word line structure disposed on the bit line structure and including a gate capping pattern and a first word line and a second word line adjacent to each other in the first direction on the gate capping pattern; active patterns disposed on the bit line structure and disposed on both sides of the word line structure; insulating patterns disposed between each of the word line structures and each of the active patterns; contact patterns disposed on each of the active patterns and connected to each of the active patterns; and an information storage structure on the contact patterns. The bit line structure may include a portion having an inclined surface that contacts the lower surface of the insulating patterns and has a vertical level that increases as it is adjacent to the word line structure.

[0011] A method for manufacturing a semiconductor device according to embodiments of the present invention comprises: preparing a semiconductor substrate; patterning the semiconductor substrate to form a trench structure, wherein the trench structure includes a first trench having a first width and a second trench having the first width below the first trench, and forming a first substrate insulating pattern within the second trench and a first conductive pattern on the first substrate insulating pattern; forming a back gate structure within the first trench; removing a portion of the semiconductor substrate surrounding the first trench to form a body portion of the semiconductor substrate and protrusion portions of the semiconductor substrate extending from the body portion and on both sides of the back gate structure; removing the body portion of the semiconductor substrate surrounding the second trench to expose a side of the first substrate insulating pattern and a side of the first conductive pattern, and forming a semiconductor layer of the semiconductor substrate remaining at a level lower than the second trench; and forming a second substrate insulating pattern on the side of the first substrate insulating pattern on the semiconductor layer to form a substrate insulating layer. The method may include the steps of: forming a second conductive pattern on the side of the first conductive pattern on the second substrate insulating pattern to form a bit line structure; forming a word line structure on one side of the back gate structure on the bit line structure; forming contact patterns on protruding portions of the semiconductor substrate; and forming an information storage structure on the contact patterns.

[0012] According to one embodiment, the step of forming the first trench may include: forming a first mask pattern having first openings extending in a first direction and spaced apart in a second direction intersecting the first direction on the semiconductor substrate; forming a second mask pattern having second openings extending in the second direction and spaced apart in the first direction on the first mask pattern; removing the first mask pattern and the semiconductor substrate below the first mask pattern exposed through the second openings to form the first trench; and forming an insulating liner on the sidewall of the first trench.

[0013] According to one embodiment, the method may further include the step of etching the semiconductor substrate exposed through the first openings to form auxiliary trenches; and the step of forming a first insulating material within the auxiliary trenches.

[0014] According to one embodiment, the step of forming the back gate structure may include: forming a back gate dielectric layer conformally along the sidewall and bottom surface of the first trench; forming a back gate electrode within the back gate dielectric layer; and forming a back gate capping pattern on the back gate electrode.

[0015] According to one embodiment, the step of removing a portion of the semiconductor substrate surrounding the first trench may include: forming a first spacer layer conformally covering the upper surface of the semiconductor substrate, the side of the back gate dielectric layer exposed on the upper surface of the semiconductor substrate, and the upper surface of the back gate capping pattern; and removing a first etching region of the first spacer layer covering the upper surface of the semiconductor substrate and the semiconductor substrate overlapping with the first etching region.

[0016] According to one embodiment, the step of removing the body portion of the semiconductor substrate surrounding the second trench may include: forming the upper surface of the body portion, the side of the protruding portions, the side of the first spacer layer, and a second spacer layer conformally covering the first spacer layer; and removing the body portion that overlaps with the second etching region of the second spacer layer covering the upper surface of the body portion.

[0017] According to one embodiment, the step of removing the body portion surrounding the second trench may include the step of separating the protruding portions from the body portion and forming active patterns.

[0018] According to one embodiment, the lower surface of each of the active patterns may be formed at a lower level than the upper surface of the first conductive pattern.

[0019] According to one embodiment, the first substrate insulating pattern may include the same insulating material as the second substrate insulating pattern, and the first conductive pattern may include the same conductive material as the second conductive pattern.

[0020] According to one embodiment, the upper surface of the second conductive pattern that overlaps vertically with the word line structure may be formed at a higher level than the upper surface of the first conductive pattern that overlaps vertically with the back gate structure. Effects of the invention

[0022] A semiconductor device according to embodiments of the present invention may include a memory cell array formed using a bare wafer. Accordingly, a semiconductor device with guaranteed reliability can be provided, and the manufacturing process cost of the semiconductor device can be reduced.

[0023] However, the effects of the present invention are not limited to the effects described above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0025] FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention. FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a vertical cross-sectional view showing an embodiment along the line I-I' of the semiconductor device of FIG. 2. FIG. 4a is an enlarged view according to one embodiment of region A of the semiconductor device of FIG. 3. FIGS. 4b to 4e are enlarged views according to different embodiments of region A of the semiconductor device of FIG. 3. FIG. 5 is a vertical cross-sectional view showing another embodiment along the line I-I' of the semiconductor device of FIG. 2. FIG. 6 is a schematic perspective view of a semiconductor device according to another embodiment. FIG. 7 is a vertical cross-sectional view showing one embodiment of the semiconductor device of FIG. 6. FIGS. 8a to 35 are cross-sectional views illustrating an embodiment of a method for manufacturing a semiconductor device of FIG. 1. Specific details for implementing the invention

[0026] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0027] FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention.

[0028] Referring to FIG. 1, the semiconductor device (100) may include a first structure (ST1) and a second structure (ST2) below the first structure (ST1). The first structure (ST1) may include a memory cell array region (CA) and a first peripheral circuit region (PERI1).

[0029] The memory cell array region (CA) may include a memory cell array. In one embodiment, the memory cell array may include a plurality of bit lines (BL), a plurality of word lines (WL), a plurality of back gate lines (BG), and a plurality of memory cells (MC).

[0030] Each of the memory cells (MC) may include a cell transistor (CTR) and an information storage element (DS). A memory cell (MC) may be placed between one word line (WL) and one bit line (BL). The cell array of the semiconductor device (100) may correspond to a memory cell array of a Dynamic Random Access Memory (DRAM) device.

[0031] A cell transistor (CTR) may include a gate, a source, and a drain. The gate may be connected to a word line (WL), and the source may be connected to a bit line (BL). The drain may be connected to an information storage element (DS). The information storage element (DS) may include a capacitor composed of a lower electrode, an upper electrode, and a dielectric layer.

[0032] Word lines (WL) can be extended in a second direction (Y direction) and can be spaced apart from each other in a first direction (X direction). Word lines (WL) can be placed at the same level and connected to different memory cells (MC). Each bit line (BL) can be extended in a first direction (X direction) and can be spaced apart from each other in a second direction (Y direction).

[0033] A back gate line (BG) may be placed between two adjacent word lines (WL). For example, two adjacent word lines (WL) may share a single back gate line (BG). A voltage different from the voltage applied to the word lines (WL) may be applied to the back gate line (BG). Channel regions (e.g., channel region (140a) in FIG. 4a), which are channels of the cell transistor (CTR), may be floating bodies, and the back gate line (BG) can control charges, e.g. holes, accumulated within the channel regions. Accordingly, the floating body effect can be suppressed or controlled, and the threshold voltage of the cell transistor (CTR) can be prevented from fluctuating. Thus, the back gate line (BG) can improve the electrical characteristics of the cell transistor (CTR).

[0034] The back gate lines (BG) can be controlled independently and individually by taking into account the interlayer characteristic variation of the cell transistors (CTRs) placed on each layer. Alternatively, at least some of the back gate lines (BG) can be electrically connected to each other and controlled together.

[0035] The first peripheral circuit region (PERI1) may be spaced apart from the memory cell array region (CA) in the first direction (X direction), and peripheral wiring connected to peripheral transistors placed in the second peripheral circuit region (PERI2) may be placed therein.

[0036] The second structure (ST2) may overlap the first structure (ST1) in a vertical direction (Z direction). In one example, the second structure (ST2) may be positioned below the first structure (ST1) and may include a second peripheral circuit region (PERI2). The second peripheral circuit region (PERI2) may be positioned below the memory cell array region (CA) and the first peripheral circuit region (PERI1) and may be electrically connected to the memory cell array region (CA) and the first peripheral circuit region (PERI1). The second peripheral circuit region (PERI2) may include peripheral circuit elements, for example, sub-word line drivers electrically connected to word lines (WL) and sense amplifiers electrically connected to bit lines (BL).

[0037] The first structure (ST1) can be bonded to the second structure (ST2). For example, the first structure (ST1) may include first bonding pads (BP1) on its lower surface, and the second structure (ST2) may include second bonding pads (BP2) on its upper surface. The first bonding pads (BP1) can be bonded to the second bonding pads (BP2) and can electrically connect the first structure (ST1) and the second structure (ST2). For example, the first bonding pads (BP1) and the second bonding pads (BP2) can provide a first path (P1) that electrically connects the memory cell array region (CA) and the second peripheral circuit region (PERI2), and a second path (P2) that electrically connects the first peripheral circuit region (PERI1) and the second peripheral circuit region (PERI2). The second peripheral circuit region (PERI2) may include a first region overlapping with the memory cell array region (CA) and a second region overlapping with the first peripheral circuit region (PERI1).

[0039] FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a vertical cross-sectional view showing an embodiment along the line I-I' of the semiconductor device of FIG. 2. FIG. 4a is an enlarged view according to an embodiment of region A of the semiconductor device of FIG. 3.

[0040] Referring to FIGS. 2, FIGS. 3, and FIGS. 4a, the semiconductor device (100) may include a first structure (ST1) and a second structure (ST2) disposed below the first structure (ST1). In one example, a memory cell array region (CA) and a first peripheral circuit region (PERI1) may be disposed on a second peripheral circuit region (PERI2) of the second structure (ST2).

[0041] The memory cell array region (CA) of the semiconductor device (100) may include bit line structures (110), back gate structures (120), active patterns (140), word line structures (150), contact patterns (170), and information storage structures (180).

[0042] The memory cell array region (CA) may include a vertical channel transistor composed of active patterns (140) and word lines (154) disposed on at least one side of the active patterns (140). The vertical channel transistor may correspond to the cell transistor (CTR) shown in FIG. 1.

[0043] Each of the bit line structures (110) can be extended in a first direction (X direction) and spaced apart from each other in a second direction (Y direction). In one example, each of the bit line structures (110) can be electrically connected to active patterns (140). Each of the bit line structures (110) can correspond to a bit line (BL) of FIG. 1.

[0044] The bit line structure (110) may include Dought polysilicon, metal, conductive metal nitride, metal-semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, the bit line structure (110) may be made of Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube, or a combination thereof.

[0045] Back gate structures (120) may intersect with bit line structures (110). Each of the back gate structures (120) may extend in a second direction (Y direction) and be spaced apart from each other in a first direction (X direction). Each of the back gate structures (120) may be placed on the bit line structure (110) and may include a back gate dielectric layer (122), a back gate electrode (124), and back gate capping patterns (126). In one example, each of the back gate electrodes (124) may extend in a second direction (Y direction) and be spaced apart from each other in a first direction (X direction). The back gate electrode (124) may serve to remove charges trapped within the active pattern (140). The back gate electrode (124) may be a floating body, and the back gate electrode (124) may be a structure for supplementing the floating active pattern (140) to prevent or minimize performance degradation of the semiconductor device (100) due to the floating body effect of the active pattern (140).

[0046] The back gate electrode (124) may be formed of the same material as the word lines (154), but is not limited thereto and may include other materials. For example, the back gate electrode (124) may include Doft polysilicon, metal, conductive metal nitride, metal-semiconductor compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof. The back gate electrode (124) may be formed as a single layer or multiple layers of the aforementioned materials. The back gate electrode (124) may correspond to the back gate line (BG) of FIG. 1.

[0047] The back gate dielectric layer (122) may extend in a second direction (Y direction) along both sides of the back gate electrode (124). The length of the back gate dielectric layer (122) in the vertical direction (Z direction) may be greater than the vertical length of the back gate electrode (124). For example, the upper surface of the back gate dielectric layer (122) may be located at a higher level than the upper surface of the back gate electrode (124). The lower surface of the back gate dielectric layer (122) may be in contact with the bit line structure (110). The back gate dielectric layer (122) may include at least one of silicon oxide and a high-k dielectric.

[0048] The back gate capping patterns (126) may include a lower back gate capping pattern (126a) and an upper back gate capping pattern (126b) spaced apart from the lower back gate capping pattern (126a) in a vertical direction (Z direction). The lower back gate capping pattern (126a) may be positioned between the lower surface of the back gate electrode (124) and the back gate dielectric layer (122). The upper back gate capping pattern (126b) may be positioned on the back gate electrode (124). In one example, the sides and lower surface of the lower back gate capping pattern (126a), the sides of the back gate electrode (124), and the sides of the upper back gate capping pattern (126b) may be surrounded by the back gate dielectric layer (122). The upper surface of the upper back gate capping pattern (126b) may be positioned at substantially the same level as the upper surface of the back gate dielectric layer (122). In one example, the upper surface of the upper back gate capping pattern (126b) may be co-planar with the upper surface of the active pattern (140). In one example, the back gate capping patterns (126) may include silicon nitride.

[0049] The active patterns (140) may be extended in a vertical direction (Z direction), and in a plan view, the active patterns (140) may be placed on both sides of each of the back gate structures (120). The active patterns (140) may be spaced apart from each other in a first direction (X direction) and a second direction (Y direction).

[0050] Each of the active patterns (140) may include a first source / drain region (140b) connected to a contact pattern (170), a second source / drain region (140c) in contact with a bit line structure (110), and a channel region (140a) between the first source / drain region (140b) and the second source / drain region (140c). In one example, the first source / drain region (140b) and the second source / drain region (140c) may have an N-type conductivity. The active pattern (140) may correspond to the channel region and source / drain region of the cell transistor (CTR) illustrated in FIG. 1. In this specification, the active pattern (140) may be referred to as a 'cell channel structure' or a 'semiconductor pattern'.

[0051] Each of the active patterns (140) may include a first active pattern (141), a second active pattern (142), and a third active pattern (143) spaced apart in a first direction (X direction). In one example, a back gate structure (120) may be placed between the first active pattern (141) and the second active pattern (142), and a word line structure (150) may be placed between the second active pattern (142) and the third active pattern (143). In one example, one side of the first active pattern (141) may be in contact with the back gate dielectric layer (122) of the back gate structure (120), one side of the second active pattern (142) may be in contact with the insulating pattern (135), the other side facing the one side of the second active pattern (142) may be in contact with the back gate dielectric layer (122) of the back gate structure (120), and the other side of the third active pattern (143) may be in contact with the insulating pattern (135) placed on both sides of the word line structure (150).

[0052] The upper surface of each active pattern (140) may be co-planed with the upper surface of the back gate structure (120) and the upper surface of the word line structure (150). For example, the upper surface of each active pattern (140) may be co-planed with the upper surface of the upper back gate capping pattern (126b) of the back gate structure (120) and the upper surface of the upper gate capping pattern (156b) of the word line structure (150).

[0053] The lower surface of each active pattern (140) may be positioned at a lower level than the lower surface of the back gate structure (120) and the lower surface of the word line structure (150). In one example, the vertical length from the lower surface of the bit line structure (110) to the lower surface of the active pattern (140) may be smaller than the vertical length from the lower surface of the bit line structure (110) to the lower surface of the back gate structure (120) (or the lower surface of the back gate dielectric layer (122)). In one example, the vertical length from the lower surface of the bit line structure (110) to the lower surface of the active pattern (140) may be smaller than the vertical length from the lower surface of the bit line structure (110) to the lower surface of the word line structure (150) (or the lower surface of the lower gate capping pattern (156a)).

[0054] The lower surface of each active pattern (140) may have a shape that protrudes toward the lower surface of the bit line structure (110). In one example, the lower surface of the active pattern (140) may have an inverted triangle shape that narrows toward the lower surface of the bit line structure (110).

[0055] Each side of the active patterns (140) may include one side in contact with the back gate structure (120) and the other side opposite to the one side and in contact with the insulating pattern (135) described later.

[0056] The active pattern (140) may include a single-crystal semiconductor material. The single-crystal semiconductor material may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor, and may be a single-crystal semiconductor including, for example, at least one of silicon, silicon carbide, germanium, or silicon-germanium.

[0057] The memory cell array region (CA) may further include a silicide pattern (145) disposed between the lower surface of the active pattern (140) and the upper surface of the bit line structure (110). The silicide pattern (145) may have a shape corresponding to the surface profile of the lower surface of the active pattern (140). In one example, the silicide pattern (145) may be a shape that narrows in width toward the lower surface of the bit line structure (110). The silicide pattern (145) is formed by contact between the lower surface of the active pattern (140) and the upper surface of the bit line structure (110), and the silicide pattern (145) may constitute a part of the active pattern (140). The silicide pattern (145) may include a metal nitride such as titanium nitride (TiN) or a silicide material such as titanium silicide (TiSi). In one example, the silicide pattern (145) may constitute part of the active pattern (140).

[0058] Each of the word line structures (150) may intersect the bit line structures (110), extend in a second direction (Y direction), and be spaced apart from each other in a first direction (X direction). In one example, the word line structures (150) may be arranged alternately with the back gate structures (120) in the first direction (X direction). Each of the word line structures (150) may include word lines (154) and gate capping patterns (156). The word lines (154) may include first and second word lines (154a, 154b), and the gate capping patterns (156) may include a lower gate capping pattern (156a) and an upper gate capping pattern (156b) placed on the lower gate capping pattern (156a).

[0059] Each of the first and second word lines (154a, 154b) is placed on the lower gate capping pattern (156a) and extends in the second direction (Y direction) but can be spaced apart from each other in the first direction (X direction). Each of the first and second word lines (154a, 154b) can correspond to the word line (WL) of FIG. 1.

[0060] In one embodiment, the lower surface of the word line structure (150) may be embedded within the bit line structure (110). At least a portion of the lower gate capping pattern (156a) may be embedded in the upper surface of the bit line structure (110). However, this is not limited thereto, and in this regard, it will be described later with reference to FIGS. 4b to 4e. The upper surface of the lower gate capping pattern (156a) may be positioned at a higher level than the upper surface of the bit line structure (110).

[0061] The word lines (154) may include Dought polysilicon, metal, conductive metal nitride, metal-semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or a combination thereof. For example, the word lines (154) may be composed of Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotube, or a combination thereof, but are not limited thereto. The word lines (154) may include a single layer or a multilayer of the aforementioned materials.

[0062] The upper gate capping pattern (156b) may extend in a second direction (Y direction) between the first and second word lines (154a, 154b) and may cover the upper surface of the first and second word lines (154a, 154b). The upper surface of the upper gate capping pattern (156b) may be co-plane with the upper surface of the active pattern (140) and the upper surface of the upper back gate capping pattern (126b).

[0063] The gate capping pattern (156) may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a low dielectric, or a combination thereof. In one example, the lower gate capping pattern (156a) may include silicon nitride, and the upper gate capping pattern (156b) may include silicon oxide. In some embodiments, the lower gate capping pattern (156a) and the upper gate capping pattern (156b) may include the same material.

[0064] The memory cell array region (CA) may further include insulating patterns (135) disposed on both sides of each of the word line structures (150). Each of the insulating patterns (135) may be disposed between the active pattern (140) and the word line structure (150). In one example, each side of the insulating patterns (135) may include one side in contact with the word line structure (150) and the other side opposite to said side and in contact with the active pattern (140). In this document, the insulating pattern (135) may be referred to as a 'gate spacer'.

[0065] The upper surface of each of the insulating patterns (135) can be co-surfaced with the upper surface of the active pattern (140), the upper surface of the back gate structure (120), and the upper surface of the word line structure (150).

[0066] The lower surface of each insulating pattern (135) may have a sloped surface that becomes higher in vertical level as it approaches the word line structure (150). The lower surface of the insulating pattern (135) may be positioned at a higher level than the lower surface of the active pattern (140) and the lower surface of the back gate structure (120). In one example, the lower surface of the insulating pattern (135) may be in contact with the side of the lower gate capping pattern (156a). In this specification, the insulating pattern (135) may be a tunnel dielectric layer that does not include an information storage layer. For example, the insulating pattern (135) may include at least one of silicon oxide and a high-k dielectric. The high-k dielectric may include a metal oxide or a metal oxynitride. For example, the high-k dielectric may be composed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0067] Referring to FIG. 4a, the bit line structure (110) may include a first part (110a) overlapping with the back gate structure (120), a second part (110b) overlapping with the word line structure (150), and a third part (110c) having an inclined surface (110s) between the first part (110a) and the second part (110b).

[0068] In one example, the first part (110a) may be in contact with the lower surface of the back gate structure (120). The lower surface of the back gate dielectric layer (122) of the back gate structure (120) may be in contact with the upper surface of the first part (110a). In one example, the second part (110b) may be in contact with the lower surface of the word line structure (150). The lower surface of the lower gate capping pattern (156a) of the word line structure (150) may be embedded within the second part (110b). The word lines (154) may be separated from the bit line structure (110) in a vertical direction (Z direction) through the lower gate capping pattern (156a). That is, the lower surfaces of the first and second word lines (154a, 154b) may be separated from the bit line structure (110) in a vertical direction (Z direction). In one example, the upper surface of the first part (110a) and the upper surface of the second part (110b) of the bit line structure (110) may be flat.

[0069] In one example, the lower surface of each active pattern (140) may be positioned at a lower level than the upper surface of the first part (110a) and the upper surface of the second part (110b). That is, the lower surface of the silicide pattern (145) may be positioned at a lower level than the upper surface of the first part (110a) and the upper surface of the second part (110b). In one example, the upper surface of the first part (110a) may be positioned at a different level from the upper surface of the second part (110b). For example, the upper surface of the first part (110a) may be positioned at a lower level than the upper surface of the second part (110b). In one example, the vertical length of the first part (110a) of the bit line structure (110) may be smaller than the vertical length of the second part (110b) of the bit line structure (110).

[0070] In one example, a third part (110c) of the bit line structure (110) is positioned between the first part (110a) and the second part (110b) and may have an inclined surface (110s). The third part (110c) may overlap in a vertical direction (Z direction) with an active pattern (140) and an insulating pattern (135) positioned between the back gate structure (120) and the word line structure (150). The upper surface of the third part (110c) may correspond to the surface profiles of the lower surface of the active pattern (140) and the lower surface of the insulating pattern (135). For example, the lower surface of the active pattern (140) may have a groove shape that narrows toward the bottom, and the lower surface of the insulating pattern (135) may have an inclined surface that increases in vertical level as it gets closer to the word line structure (150).

[0071] In one example, the vertical level of the slope (110s) of the third part (110c) may be higher as it is adjacent to the word line structure (150). In one example, the maximum vertical length of the third part (110c) may be greater than the vertical length of the second part (110b), and the minimum vertical length of the third part (110c) may be smaller than the vertical length of the first part (110a).

[0072] Contact patterns (170) can be placed on active patterns (140) and can be electrically connected to active patterns (140). Contact patterns (170) can electrically connect active patterns (140) and an information storage structure (180).

[0073] Although the lower surface of the contact patterns (170) is shown to be in contact with the active patterns (140), the back gate dielectric layer (122), and the insulating pattern (135), according to embodiments, the lower surface of the contact patterns (170) may also be in contact with the upper gate capping pattern (156b) and / or the upper back gate capping pattern (126b).

[0074] The contact patterns (170) may include a conductive material, for example, doped single-crystal silicon, doped polycrystalline silicon, a metal, a conductive metal nitride, a metal-semiconductor compound, a conductive metal oxide, a conductive graphene, a carbon nanotube, or a combination thereof. In an exemplary embodiment, the contact patterns (170) may include a first contact layer comprising polycrystalline silicon and a second contact layer disposed on the first contact layer and comprising a silicide material. In another example, the contact patterns (170) may include a first contact layer comprising a silicide material and a second contact layer disposed on the first contact layer and comprising a metal material. However, depending on the embodiment, the number of layers of the contact patterns (170) and the type of material may vary.

[0075] The memory cell array region (CA) may further include first contact insulation patterns (175) disposed between contact patterns (170). Each of the first contact insulation patterns (175) may extend vertically and come into contact with the word line structure (150). The first contact insulation patterns (175) may spatially separate and electrically insulate the contact patterns (170).

[0076] The memory cell array region (CA) may further include second contact insulation patterns (176) disposed on the first contact insulation patterns (175).

[0077] The information storage structure (180) may include first electrodes (182) electrically connected to the contact patterns (170), a second electrode (186) covering the first electrodes (182), and a dielectric layer (184) between the first electrodes (182) and the second electrode (186). The information storage structure (180) may completely overlap or partially overlap the contact patterns (170) in a vertical direction (Z direction). The first electrodes (182) may be placed on the contact patterns (170) by penetrating the second contact insulation pattern (176). The information storage structure (180) may correspond to the information storage element (DS) of FIG. 1.

[0078] The information storage structure (180) may be a capacitor that stores information in a DRAM. For example, the dielectric layer (184) of the information storage structures (180) may be a dielectric layer of the capacitor of the DRAM, and the dielectric layer (184) may include a high dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0079] The information storage structure (180) may be a structure that stores information of DRAM and other memory. For example, the dielectric layer (184) of the information storage structures (180) may be a capacitor dielectric layer of a ferroelectric memory (FeRAM). In this case, the dielectric layer (184) may be a ferroelectric layer capable of recording data using a polarization state. In another embodiment, the ferroelectric layer may also include a lower dielectric layer comprising at least one of silicon oxide or a high-k dielectric and a ferroelectric layer disposed on the lower dielectric layer.

[0080] The first structure (ST1) may further include a lower insulating layer (19) disposed below the bit line structure (110), wiring layers (112), vias (105), contact vias (106), and first bonding pads (BP1). The memory cell array region (CA) may further include bit line contact vias (115), and the first peripheral circuit region (PERI1) may further include a first upper insulating structure (21) disposed on the lower insulating layer (19) on the side of the bit line structure (110), a second upper insulating structure (23) on the first upper insulating structure (21), connection pads (114) disposed on the first upper insulating structure (21), upper pads (190) disposed on the second upper insulating structure (23), a lower contact plug (117) connecting the wiring layers (112) and the connection pads (114), and an upper contact plug (119) connecting the connection pads (114) and the upper pads (190).

[0081] The lower insulating layer (19) may be in contact with the lower surface of the bit line structure (110). Via (105) may connect the wiring layers (112), contact vias (106) may connect the wiring layers (112) and the first bonding pads (BP1), and bit line contact vias (115) may connect the wiring layer (112) and the bit line structure (110). The wiring layers (112), vias (105), contact vias (106), and bit line contact vias (115) may be embedded within the lower insulating layer (19). Each of the vias (105), contact vias (106), and bit line contact vias (115) may have a shape that narrows toward the top, and the lower insulating layer (19) may be arranged in multiple layers.

[0082] The first upper insulating structure (21) may be placed on the lower insulating layer (19) and positioned on the side of the cell transistor (CTR) of FIG. 1. The lower contact plug (117) may connect the wiring layer (112) and the connection pad (114) by penetrating the lower insulating layer (19) and the first upper insulating structure (21) which are positioned on the upper part of the wiring layer (112). The lower contact plug (117) may have a shape in which the width decreases toward the top.

[0083] The second upper insulating structure (23) can cover the side and top surfaces of the information storage structure (180) on the first upper insulating structure (21). The upper contact plug (119) can penetrate the second upper insulating structure (23) to connect the upper pad (190) and the connection pad (114). The upper contact plug (119) may have a shape in which the width decreases toward the bottom. The upper pads (190) may be input / output pads.

[0084] The lower insulating layer (19) and the first and second upper insulating structures (21, 23) may include silicon oxide or silicon nitride.

[0085] The first bonding pads (BP1) may be arranged along the lower surface of the lower insulating layer (19). For example, the lower surfaces of the first bonding pads (BP1) may be in a co-plane with the lower surface of the lower insulating layer (19). At least some of the first bonding pads (BP1) may be connected to the contact via (106).

[0086] The second peripheral circuit region (PERI2) of the second structure (ST2) may include a peripheral device isolation layer (6) and a peripheral transistor (PTR) disposed on the upper surface of the second substrate (3).

[0087] The second substrate (3) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate (3) may further include impurities. The second substrate (3) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0088] The peripheral device isolation layer (6) defines peripheral active regions within the second substrate (3) and may extend downward from the upper surface of the second substrate (3). The peripheral device isolation layer (6) may include an insulating material. For example, the peripheral device isolation layer (6) may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be composed of a single layer or multiple layers.

[0089] The peripheral transistor (PTR) may include peripheral source / drain regions (SD), a peripheral gate dielectric layer (GO), and a peripheral gate electrode (GE). The peripheral transistor (PTR) may be a planar type transistor. For example, the peripheral source / drain regions (SD) may be placed on the upper surface of the second substrate (3), and the channel region of the peripheral transistor (PTR) may be placed between the peripheral source / drain regions (SD). The channel region may be co-planar with the upper surface of the peripheral source / drain regions (SD) and may be in contact with the lower surface of the peripheral gate electrode (GE). The peripheral transistor (PTR) may be a component of the subword line drivers and sense amplifiers described above.

[0090] The second structure (ST2) may further include an upper insulating layer (9), wiring layers (12), vias (15), and second bonding pads (BP2) disposed on the upper surface. The upper insulating layer (9) may cover the upper surface of the second substrate (3) and may cover a peripheral transistor (PTR). The wiring layers (12) may be embedded within the upper insulating layer (9) and may be arranged in multiple layers. The vias (15) may electrically connect the wiring layers (12).

[0091] The second bonding pads (BP2) may be arranged along the upper surface of the upper insulating layer (9). For example, the upper surfaces of the second bonding pads (BP2) may be co-surfaced with the upper surface of the upper insulating layer (9). The second bonding pads (BP2) may be bonded to the first bonding pads (BP1). Each of the second bonding pads (BP2) may be electrically connected to at least one of the wiring layers (12) and vias (15). Additionally, the peripheral transistor (PTR) may be electrically connected to at least one of the wiring layers (12) and vias (15).

[0092] The bonding of the first and second bonding pads (BP1, BP2) may be, for example, copper (Cu)-copper (Cu) bonding. However, it is not limited thereto, and the first and second structures (ST1, ST2) of the semiconductor device (100) may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0094] FIGS. 4b to 4e are enlarged views according to different embodiments of region A of the semiconductor device of FIG. 3.

[0095] Referring to FIG. 4b, the semiconductor device (100a) may include a bit line structure (110_1). The remaining components shown in FIG. 4b, excluding the bit line structure (110_1), may be identical to or correspond to the components shown in FIG. 3. The bit line structure (110_1) may include a first portion (110a) that overlaps vertically with the back gate structure (120), a second portion (110b_1) that overlaps vertically with the word line structure (150), and a third portion (110c) disposed between the first portion (110a) and the second portion (110b_1) and having an inclined surface (110s). In one example, the upper surface of the first portion (110a) and the upper surface of the second portion (110b) may be flat. In one example, the upper surface of the first portion (110a) may be in contact with the lower surface of the back gate structure (120). The word line structure (150) may be placed on the upper surface of the second part (110b_1). The upper surface of the second part (110b_1) may be co-plane with the lower surface of the lower gate capping pattern (156a) of the word line structure (150). In one example, the vertical length of the first part (110a) may be smaller than the vertical length of the second part (110b_1). In one example, the maximum vertical length of the third part (110c) may be substantially the same as the vertical length of the second part (110b_1).

[0096] In one example, the third part (110c) of the bit line structure (110_1) overlaps the active pattern (140) and the insulating pattern (135) in a vertical direction (Z direction), and the lower surface of the active pattern (140) may have a shape protruding toward the lower surface of the third part (110c) of the bit line structure (110_1), and the lower surface of the insulating pattern (135) may have an inclined surface corresponding to the inclined surface profile of the third part (110c).

[0098] Referring to FIG. 4c, the semiconductor device (100b) may include a bit line structure (110_2). The remaining components shown in FIG. 4c, excluding the bit line structure (110_2), may be identical to or correspond to the components shown in FIG. 3. In one example, the bit line structure (110_2) may include a first part (110a) that overlaps vertically with the back gate structure (120), a second part (110b_2) that overlaps vertically with the word line structure (150), and a third part (110c) that is positioned between the first part (110a) and the second part (110b_2) and has an inclined surface (110s). In one example, the upper surface of the first part (110a) and the upper surface of the second part (110b_2) may have a flat shape.

[0099] In one example, the back gate structure (120) is positioned on the upper surface of the first part (110a), and the word line structure (150) may be positioned on the upper surface of the second part (110b_2). In one example, the vertical length of the first part (110a) may be smaller than the vertical length of the second part (110b_2). The second part (110b_2) may be in contact with a portion of the side of the insulation pattern (135). The upper surface of the second part (110b_2) may be positioned at a higher level than the inclined surface (110s) of the third part (110c). For example, the maximum vertical length of the inclined surface (110s) of the third part (110c) may be smaller than the vertical length of the second part (110b_2).

[0101] Referring to FIG. 4d, the semiconductor device (100c) may include a bit line structure (110_3). The remaining configurations shown in FIG. 4d, excluding the bit line structure (110_3), may be identical to or correspond to the configurations shown in FIG. 3. In one example, the bit line structure (110_3) may include a first part (110a) that overlaps vertically with the back gate structure (120), a second part (110b_3) that overlaps vertically with the word line structure (150), and a third part (110c) that is positioned between the first part (110a) and the second part (110b_3) and has an inclined surface (100s).

[0102] The lower surface of the word line structure (150) may be embedded within the second part (110b_3). In one example, the upper surface of the first part (110a) may be positioned at substantially the same level as the upper surface of the second part (110b_3). That is, the vertical length of the first part (110a) may be substantially the same as the vertical length of the second part (110b_3). In one example, the lower surface of the back gate structure (120) and the lower surface of the word line structure (150) may be positioned at the same level. In one example, the third part (110c) overlaps the active pattern (140) and the insulating pattern (135) in the vertical direction (Z direction) and may be in contact with the side of the lower gate capping pattern (156a) of the word line structure (150).

[0103] In another embodiment, the lower surface of the word line structure (150) may be embedded within the second part (110b_3). In one example, the upper surface of the first part (110a) may be positioned at a higher level than the upper surface of the second part (110b_3). That is, the vertical length of the first part (110a) may be greater than the vertical length of the second part (110b_3). In one example, the lower surface of the back gate structure (120) may be positioned at a higher level than the lower surface of the word line structure (150).

[0105] Referring to FIG. 4e, the semiconductor device (100d) may include active patterns (140"), a silicide pattern (145"), and a bit line structure (100_4). The remaining components, excluding the active patterns (140"), the silicide pattern (145"), and the bit line structure (100_4), may be identical to or correspond to the components shown in FIG. 3. In one example, the bit line structure (100_4) may include a first portion (110a_4) that overlaps vertically with the back gate structure (120), the active pattern (140"), and the insulating pattern (135), and a second portion (110b_4) that overlaps vertically with the word line structure (150).

[0106] In one example, the upper surface of the first part (110a_4) and the upper surface of the second part (110b_4) may each have a flat shape. The upper surface of the first part (110a_4) may be in contact with the lower surface of the back gate structure (120), the lower surface of the silicide pattern (145"), and the lower surface of the insulation pattern (135). The lower surface of the back gate structure (120), the lower surface of the silicide pattern (145"), and the lower surface of the insulation pattern (135) may form a co-surface.

[0107] In one example, the upper surface of the first part (110a_4) may be positioned at a lower level than the upper surface of the second part (110b_4). The vertical length of the first part (110a_4) may be smaller than the vertical length of the second part (110b_4). In one example, the lower surface of the word line structure (150) may be positioned at a higher level than the lower surface of the back gate structure (120), the lower surface of the silicide pattern (145) and the lower surface of the insulation pattern (135).

[0109] FIG. 5 is a vertical cross-sectional view showing another embodiment along the line I-I' of the semiconductor device of FIG. 2.

[0110] Referring to FIG. 5, the semiconductor device (100') may include a first structure (ST1) and a second structure (ST2) disposed below the first structure (ST1). In one example, a memory cell array region (CA) and a first peripheral circuit region (PERI1) may be disposed on a second peripheral circuit region (PERI2) of the second structure (ST2).

[0111] A semiconductor device (100') may include a lower insulating layer (19) disposed below an information storage structure (180), an information storage structure (180), contact patterns (170) disposed on the information storage structure (180), first and second contact insulating patterns (175, 176), active patterns (140) disposed on the contact patterns (170), word line structures (150), back gate structures (120), and a bit line structure (110) disposed on the active patterns (140) and extending in a first direction (X direction). That is, the memory cell array region (CA) of the semiconductor device (100') may include an information storage structure (180) disposed below a first structure (ST1) and a bit line structure (110) disposed above a first structure (ST1). The semiconductor device (100') may further include a first substrate insulating layer (102) disposed on a bit line structure (110), and a first substrate (101) disposed on the first substrate insulating layer (102). The first substrate insulating layer (102) may be disposed between the first substrate (101) and the bit line structure (110). The first substrate (101) may include a bare silicon substrate.

[0112] The first structure (ST1) of the semiconductor device (100') may further include a second upper insulating structure (23) disposed on the side of the information storage structure (180) and placed on the lower insulating layer (19), a first upper insulating structure (21) disposed on the second upper insulating structure (23), connection pads (114) disposed on the second upper insulating structure (23), upper pads (190) disposed on the first upper insulating structure (21), a lower contact plug (117) connecting the wiring layers (112) and the connection pads (114), and an upper contact plug (119) connecting the connection pads (114) and the upper pads (190). The first upper insulating structure (21) may be disposed on the side of the first substrate (101), the side of the first substrate insulating layer (102), the side of the word line structure (150) disposed at the outermost edge, and the side of the contact insulating pattern (176). The upper surface of the first substrate (101) can form a co-surface with the upper surface of the first upper insulating structure (21).

[0113] The first structure (ST1) of the semiconductor device (100') may further include a bit line contact pad (113) disposed on the second upper insulating structure (23), a first bit line contact plug (116) connecting the wiring layer (112) and the bit line contact pad (113), and a second bit line contact plug (118) connecting the bit line contact pad (113) and the bit line structure (110). The first bit line contact plug (116) may have a shape that narrows toward the top, and the second bit line contact plug (118) may have a shape that narrows toward the bottom.

[0115] FIG. 6 is a schematic perspective view of a semiconductor device according to another embodiment. FIG. 7 is a vertical cross-sectional view showing one embodiment of the semiconductor device of FIG. 6. FIG. 7 is a vertical cross-sectional view showing another embodiment along the line I-I' of the semiconductor device of FIG. 2.

[0116] Referring to FIGS. 6 and 7, a semiconductor device (100) may include a first structure (ST1) and a second structure (ST2) disposed on the first structure (ST1). The first structure (ST1) may include a memory cell array region (CA) and a first peripheral circuit region (PERI1). The second structure (ST2) may include a second peripheral circuit region (PERI2).

[0117] A memory cell array region (CA) of a semiconductor device (100) may include a first substrate (101), a first substrate insulating layer (102) on the first substrate (101), a bit line structure (110) disposed on the first substrate insulating layer (102), back gate structures (120), active patterns (140), word line structures (150), contact patterns (170), and an information storage structure (180). A memory cell array region (CA) of a semiconductor device (100') may include an information storage structure (180) disposed on top of a first structure (ST1) and a bit line structure (110) disposed on bottom of a first structure (ST1).

[0118] A semiconductor device (100) may include a first upper insulating structure (21) disposed on the side of a bit line structure (110), the side of a word line structure (150) disposed at the outermost edge, and the side of a contact insulating pattern (176) disposed at the outermost edge, a second upper insulating structure (23) disposed on the side and upper surface of an information storage structure (180), a bit line contact pad (113) disposed on the first upper insulating structure (21), and a connection pad (114) disposed on the first upper insulating structure (21) and disposed at the same level as the bit line contact pad (113).

[0119] A second structure (ST2) of a semiconductor device (100) is disposed on a first structure (ST1), and a second peripheral circuit region (PERI2) of the second structure (ST2) may include a second substrate insulating layer (13) disposed on a second upper insulating structure (23), a second substrate (3) on the second substrate insulating layer (13), a peripheral device isolation layer (6) disposed on the upper surface of the second substrate (3), and a peripheral transistor (PTR). The second structure (ST2) may further include an upper insulating layer (9), wiring layers (12), vias (15), first and second connecting wires (16, 17) connected to the wiring layers (12) and vias (15), and an upper pad (190) disposed on the upper insulating layer (9). The wiring layers (12), vias (15), and the first and second connecting wires (16, 17) may be embedded within the upper insulating layer (9). The pad (190) and the second connecting wire (17) can be connected through the wiring layer (12) and vias (15).

[0120] The semiconductor device (100) may further include an upper contact plug (119) connecting a second connection wire (17) and a connection pad (114), a first bit line contact plug (116) connecting a bit line structure (110) and a bit line contact pad (113), and a second bit line contact plug (118) connecting a first connection wire (16) and a bit line contact pad (113).

[0121] The upper contact plug (119) can be connected to the connection pad (114) by penetrating the upper insulating layer (9), the second substrate (3), the second substrate insulating layer (13), and the second upper insulating structure (23) below the second connecting wire (17). The first bit line contact plug (116) can be connected to the bit line structure (110) by penetrating the first upper insulating structure (21) below the bit line contact pad (113). The second bit line contact plug (118) can be connected to the bit line contact pad (113) by penetrating the upper insulating layer (9), the second substrate (3), the second substrate insulating layer (13), and the second upper insulating structure (23) below the first connecting wire (16). In one example, the upper contact plug (119) and each of the first and second bit line contact plugs (116, 117) may have a shape that narrows toward the bottom.

[0122] The upper surface of the second upper insulating structure (23) of the first structure (ST1) can be bonded to the lower surface of the second substrate insulating layer (13) of the second structure (ST2). The upper surface of the first structure (ST1) and the lower surface of the second structure (ST2) can be bonded to form a bonding surface. The first structure (ST1) and the second structure (ST2) of the semiconductor device (100) can come into contact with each other and be bonded by dielectric-to-dielectric bonding.

[0124] FIGS. 8a to 35 are cross-sectional views illustrating an embodiment of a method for manufacturing a semiconductor device of FIG. 1.

[0125] FIGS. 8a, FIGS. 9, FIGS. 10a, and FIGS. 11a are plan views for explaining a method of manufacturing a memory cell array region (e.g., memory cell array region (CA)) of a semiconductor device of FIG. 1. FIGS. 8b, FIGS. 10b, and FIGS. 11b are vertical cross-sectional views along the line II-II' of the semiconductor device of FIGS. 8a, FIGS. 10a, and FIGS. 11a, and FIGS. 12 to 36 are vertical cross-sectional views for explaining a method of manufacturing a semiconductor device after FIG. 11. FIGS. 8b, FIGS. 10b, FIGS. 11b, and FIGS. 12 to 35 illustrate vertical cross-sectional views corresponding to FIG. 4a.

[0126] Referring to FIGS. 8a and 8b, a semiconductor substrate (100P) may be prepared, and a first mask pattern (PM1) may be formed on the semiconductor substrate (100P). The first mask pattern (PM1) may include first openings (OPN1) that extend along a first direction (X direction) and are spaced apart in a second direction (Y direction). The upper surface of the semiconductor substrate (100P) may be exposed through the first openings (OPN1).

[0127] In one example, the semiconductor substrate (100P) may include a bare silicon substrate. The first mask pattern (PM1) may include silicon oxide.

[0129] Referring to FIG. 9, a semiconductor substrate (101P) can be etched using a first mask pattern (PM1) as an etching mask to form auxiliary trenches (AT), and a first insulating material (INS1) can be filled into the auxiliary trenches (AT). An anisotropic dry etching process or a wet etching process can be performed on the upper surface of the semiconductor substrate (101P) exposed through the first openings (OPN1) of the first mask pattern (PM1). By the etching process, auxiliary trenches (AT) can be formed in which the side and upper surfaces of the semiconductor substrate (101P) are exposed, and each of the auxiliary trenches (AT) can extend in a first direction (X direction) and be spaced apart from each other in a second direction (Y direction). The first insulating material (INS1) filled into each of the auxiliary trenches (AT) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0131] Referring to FIG. 10a and FIG. 10b, a second mask pattern (PM2) can be formed on the first mask pattern (PM1). By utilizing the second mask pattern (PM2) as an etching mask, the first mask pattern (PM1) and the semiconductor substrate (101P) formed below the first mask pattern (PM1) can be etched to form a first trench (T1).

[0132] In one example, the second mask pattern (PM2) may include second openings (OPN2) that extend along a second direction (Y direction) and are spaced apart in a second direction (X direction). A first insulating material (INS1) and a first mask pattern (PM1) may be exposed through the second openings (OPN2). In one example, the second mask pattern (PM2) may be used as an etching mask to perform an anisotropic dry etching process or a wet etching process on the first mask pattern (PM1) exposed through the second openings (OPN2) and on the semiconductor substrate (101P) beneath the first mask pattern (PM1) to form first trenches (T1). The second mask pattern (PM2) may include a material having etch selectivity for the first mask pattern (PM1). For example, the second mask pattern (PM2) may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), and / or silicon carbonate (SiOC). For example, the second mask pattern (PM2) may include a material containing silicon oxynitride (SiON) and carbon, for example, an ACL (Amorphous Carbon Layer). The first trench (T1) may have a constant width in the vertical direction (Z direction).

[0134] Referring to FIGS. 11a and 11b, an insulating liner (IPa) can be formed to conformally cover the sidewall of the first trench (T1). The insulating liner (IPa) can be formed according to the surface profile of the sidewall of the first trench (T1). The bottom surface of the semiconductor substrate (101P) within the first trench (T1) can be exposed from the insulating liner (IPa). The insulating liner (IPa) may include an insulating material such as silicon nitride. The insulating liner (IPa) can be formed using a deposition process. For example, the deposition process may include a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process.

[0136] Referring to FIG. 12, a second trench (T2) can be formed by an etching process on the bottom surface within the first trench (T1). The sidewall of the second trench (T2) may be positioned inward from the sidewall of the first trench (T1) where an insulating liner (IPa) is formed. The second trench (T2) may be formed by an isotropic etching process on the bottom surface within the first trench (T1). The second width in the first direction (X direction) within the second trench (T2) may be larger than the first width in the first direction (X direction) of the first trench (T1). In one example, the second trench (T2) may be adjacent to the bottom surface of the semiconductor substrate (101P) below the first trench (T1). In one example, the vertical length of the side wall of the first trench (T1) may be longer than the vertical length of the side wall of the second trench (T2). However, this is not limited thereto, and the vertical length of the side wall of the first trench (T1) may be equal to or smaller than the vertical length of the side wall of the second trench (T2). In this document, the first trench (T1) and the second trench (T2) may be referred to as 'trench structures'.

[0138] Referring to FIG. 13, a second insulating material (INS2P) can be filled into the first trench (T1) and the second trench (T2). The second insulating material (INS2P) may include an insulating material such as silicon oxide.

[0140] Referring to FIG. 14, the second insulating material (INS2P) can be partially etched to expose the insulating liner (IPa) and a portion of the sidewall of the second trench (T2). The second insulating material (INS2P) formed within the first trench (T1) can be removed to expose the insulating liner (IPa), and a portion of the second insulating material (INS2P) formed within the second trench (T2) can be removed to expose a portion of the sidewall of the second trench (T2). As the second insulating material (INS2P) is partially etched, it may remain as a first substrate insulating pattern (INS2) covering the bottom surface of the second trench (T2).

[0142] Referring to FIG. 15, a first conductive material (MLa) can be formed in the first and second trenches (T1, T2) on the first substrate insulating pattern (INS2). The first conductive material (MLa) can cover the second mask pattern (PM2) and fill the interior of the first and second trenches (T1, T2). The first conductive material (MLa) may include a conductive material. For example, the first conductive material (MLa) may be composed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or a combination thereof.

[0144] Referring to FIG. 16, a first conductive pattern (MPa) can be formed by removing the remaining first conductive material (ML1a), excluding the first conductive material (ML1a) formed within the second trench (T2). The upper surface of the second mask pattern (PM2) of FIG. 15 and the first conductive material (ML1a) formed within the first trench (T1) can be removed. As a portion of the first conductive material (ML1a) is etched, the first conductive material (ML1a) within the second trench (T2) may remain as the first conductive pattern (MPa) on the first substrate insulation pattern (INS2).

[0146] Referring to FIG. 17, the second mask pattern (PM2) can be removed to expose the upper surface of the first mask pattern (PM1), and the insulating liner (IPa) can be removed to expose the side wall of the first trench (T1).

[0148] Referring to FIG. 18, a first insulating layer (ILa) can be formed conformally covering the upper surface of the first mask pattern (PM1), the sidewall of the first trench (T1), and the upper surface of the first conductive pattern (MPa). The first insulating layer (ILa) can be formed by the deposition process mentioned with reference to FIG. 11a and FIG. 11b.

[0150] Referring to FIG. 19, the first insulating layer (ILa) formed on the upper surface of the first mask pattern (PM1) can be removed to expose the upper surface of the first mask pattern (PM1). The first insulating layer (ILa), which conformally covers the sidewall of the first trench (T1) and the upper surface of the first conductive pattern (MPa), may remain as a back gate dielectric layer (122). A first insulating pattern (126a) may be formed within the first trench (T1). The first insulating pattern (126a) may be formed on the back gate dielectric layer (122) that overlaps with the upper surface of the first conductive pattern (MPa). The vertical length of the first insulating pattern (126a) may be smaller than the vertical length of the first trench (T1). The back gate dielectric layer (122) of FIG. 19 may correspond to the back gate dielectric layer (122) of FIG. 4a, and the first insulating pattern (126a) may correspond to the lower back gate insulating pattern of FIG. 4a.

[0152] Referring to FIG. 20, a back gate electrode (124) can be formed on a first insulating pattern (126a). The lower surface of the back gate electrode (124) is in contact with the first insulating pattern (126a), and the side surface of the back gate electrode (124) can be surrounded by a back gate dielectric layer (122). The upper surface of the back gate electrode (124) can be placed at a lower level than the upper surface of the semiconductor substrate (101P). In one example, the vertical length of the back gate electrode (124) may be smaller than the vertical length of the first trench (T1). The back gate electrode (124) of FIG. 20 may correspond to the back gate electrode (124) of FIG. 4a.

[0154] Referring to FIG. 21, a second insulating pattern (126b) can be formed on the back gate electrode (124). The lower surface of the second insulating pattern (126b) is in contact with the upper surface of the back gate electrode (124), and the side of the second insulating pattern (126b) can be surrounded by a back gate dielectric layer (122). The upper surface of the second insulating pattern (126b) can be co-planar with the upper surface of the first mask pattern (PM1). The second insulating pattern (126b) of FIG. 21 may correspond to the upper back gate insulating pattern (126b) of FIG. 4a. The back gate electrode (124), the first insulating pattern (126a), the second insulating pattern (126b), and the back gate dielectric layer (122) can form a back gate structure (120).

[0156] Referring to FIG. 22, the first mask pattern (PM1) can be removed to expose the upper surface of the semiconductor substrate (101P) and the side of the back gate dielectric layer (122) protruding over the upper surface of the semiconductor substrate (101P).

[0158] Referring to FIG. 23, a first spacer layer (ILb) can be formed to cover the upper surface of a semiconductor substrate (101P), the side of a back gate dielectric layer (122), and the upper surface of a second insulating pattern (126b) with a uniform thickness. The width of the protruding portion (101b) of the semiconductor substrate (101P'), which will be described later, can be determined according to the thickness of the first spacer layer (ILb). The first spacer layer (ILb) may be made of an insulating material. For example, the first spacer layer (ILb) may be made of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, and combinations thereof.

[0160] Referring to FIGS. 23 and 24, the first spacer layer (ILb) may include a first etched region (EA1) covering a semiconductor substrate (101P) and a first non-etched region (NEA1) covering the side of the back gate dielectric layer (122) and the top surface of the second insulating pattern (126b). An anisotropic etching process may be performed on the first etched region (EA1) of the first spacer layer (ILb) to remove the first etched region (EA1) of the first spacer layer (ILb) and a portion of the semiconductor substrate (101P) that overlaps with the first etched region (EA1). By removing the portion of the semiconductor substrate (101P) that overlaps with the first etched region (EA1), a semiconductor substrate (101P') may be formed.

[0161] A semiconductor substrate (101P') may include a body portion (101a) surrounding a first substrate insulating pattern (INS2) and a first conductive pattern (MPa), and protruding portions (101b) protruding from the upper surface of the body portion (101a) and separated from each other on both sides of each back gate structure (120). A first spacer layer (ILb) may remain as a first spacer pattern (123) corresponding to a first non-etched region (NEA1) as the first etched region (EA1) is removed. The first spacer pattern (123) may surround the side of the back gate dielectric layer (122) and the upper surface of the second insulating pattern (126b) on the protruding portions (101b).

[0163] Referring to FIG. 25, a second spacer layer (ILc) can be formed that covers the upper surface of the body portion (101a), the side of the protruding portions (101b) protruding from the upper surface of the body portion (101a), and the side and upper surface of the first spacer pattern (123) with a uniform thickness.

[0164] The second spacer layer (ILc) may include the same material as the first spacer pattern (123), but is not limited thereto. For example, the second spacer layer (ILc) may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, and combinations thereof. In another example, the second spacer layer (ILc) may include at least one high-k dielectric. The high-k dielectric may include a metal oxide or a metal oxynitride. For example, the high-k dielectric may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0166] Referring to FIGS. 25 and 26, the second spacer layer (ILc) may include a second etched region (EA2) covering the semiconductor substrate (101P') and a second non-etched region (NEA2) covering the side of the protruding portions (101b) and the side and top surface of the first spacer pattern (123). An etching process may be performed on the second etched region (EA2) of the second spacer layer (ILc) to remove the second etched region (EA2) of the second spacer layer (ILc) and a portion of the semiconductor substrate (101P') that overlaps with the second etched region (EA2).

[0167] In one example, through an etching process for a second etching region (EA2) of a second spacer layer (ILc), the body portion (101a) connected to the protrusions (101b) of the semiconductor substrate (101P') is removed, and the protrusions (101b) may remain as active patterns (140) formed on both sides of each of the word line structures (150), and the body portion (101a) of the semiconductor substrate (101P') may remain as a semiconductor substrate (101) that forms a co-plane with the lower surface of the first substrate insulating pattern (INS2). In one example, as the body portion (101a) surrounding the side of the first conductive pattern (MPa) and the side of the first substrate insulating pattern (INS2) is removed, the side of the first conductive pattern (MPa) and the side of the first substrate insulating pattern (INS2) may be exposed from the semiconductor substrate (101). The second spacer layer (ILc) may remain as a second spacer pattern (135P) corresponding to the second non-etched region (NEA2) as the second etched region (EA2) is removed. In a process in which the side of the first conductive pattern (MPa) and the side of the first substrate insulating pattern (INS2) are etched in a horizontal direction with respect to the semiconductor substrate (101P') overlapping the second etched region (EA2) are exposed, the lower surface of the second spacer pattern (135P) may have an inclined surface (SP) by the selective etching ratio of the second spacer layer (ILc) for the protruding parts (101b).

[0169] Referring to FIG. 27, a third insulating material (INS3P) can be formed on a semiconductor substrate (101). The third insulating material (INS3P) may be formed on the side of the first substrate insulating pattern (INS2), the side of the first conductive pattern (MPa), and the lower and side surfaces of the second spacer pattern (135P). The upper surface of the third insulating material (INS3P) may be co-planar with the upper surface of the second spacer pattern (135P). In one example, the third insulating material (INS3P) may include the same insulating material as the second insulating material (INS2P) of FIG. 13. However, it is not limited thereto, and the third insulating material (INS3P) may include an insulating material including silicon oxide, etc.

[0171] Referring to FIG. 28, the third insulating material (INS3P) can be etched to expose the side of the first conductive pattern (MPa) and the side and bottom of the second spacer pattern (135P). With a partial etching process of the third insulating material (INS3P), the remaining third insulating material (INS3P) may remain as a second substrate insulating pattern (INS3) that co-faces with the upper surface of the first substrate insulating pattern (INS2). In one example, the first substrate insulating pattern (INS2) and the second substrate insulating pattern (INS3) may form the first substrate insulating layer (102).

[0173] Referring to FIG. 29, a second conductive material (MLb) can be formed on the first substrate insulating layer (102). The second conductive material (MLb) can be formed on the side of the first conductive pattern (MPa) and on the bottom and side of the second spacer pattern (135P) on the first substrate insulating layer (102). The top surface of the second conductive material (MLb) can be co-planar with the top surface of the second spacer pattern (135P). The second conductive material (MLb) may include the same conductive material as the first conductive material (MLa) of FIG. 15. However, it is not limited to this, and the second conductive material (MLb) may be composed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or a combination thereof.

[0175] Referring to FIG. 30, the second conductive material (MLb) can be etched to expose at least a portion of the side of the second spacer pattern (135P). With a partial etching process of the second conductive material (MLb), the remaining second conductive material (MLb) may remain as a second conductive pattern (MPb) positioned on the side of the first conductive pattern (MPa), covering the bottom surface of the active patterns (140) and the bottom surface of the second spacer pattern (135P). The top surface of the first conductive pattern (MPa) may be positioned at a lower level than the top surface of the second conductive pattern (MPb) exposed between the second spacer patterns (135P). In another example, the second conductive pattern (MPb) may cover a portion of the side of the second spacer pattern (135P). In this case, the maximum vertical level of the inclined surface (SP) of the second spacer pattern (135P) may be placed at a level lower than the top surface of the second conductive pattern (MPb). The first conductive pattern (MPa) and the second conductive pattern (MPb) may form the bit line structure (110) of FIG. 4a. The silicide pattern (145) of FIG. 4a may be formed in the portion in contact with the bottom surface of each active pattern (140) in the first conductive pattern (MPa) and in the portion in contact with the bottom surface of each active pattern (140) in the second conductive pattern (MPb).

[0176] The portion of the first challenge pattern (MPa) that overlaps vertically with the back gate structure (120) may correspond to the first portion (110a) of the bit line structure (110) of FIG. 4a, and the portion of the first challenge pattern (MPa) that overlaps vertically with the active patterns (140), the portion of the second challenge pattern (MPb) that overlaps vertically with the active patterns (140), and the portion of the second spacer pattern (135P) that overlaps vertically may correspond to the second portion (110b) of the bit line structure (110) of FIG. 4a.

[0178] Referring to FIG. 31, a sacrificial layer (SL) can be formed on a second conductive pattern (MPb) exposed between the sides of a second spacer pattern (135P). The sacrificial layer (SL) can be formed to cover the upper surface of the second conductive pattern (MPb) and the sides and upper surfaces of the second spacer pattern (135P). The sacrificial layer (SL) may include a carbon-containing material. For example, the sacrificial layer (SL) may include a Spin-on Hardmask (SOH) and / or an Amorphous Carbon Layer (ACL).

[0180] Referring to FIGS. 31 and 32, a planarization process can be performed so that the upper surface of the active patterns (140) is exposed. In one example, a planarization process can be performed on the sacrificial layer (SL), the back gate dielectric layer (122), the second insulating pattern (126b), the first spacer pattern (123), and the second spacer pattern (135P) until the upper surface of the active patterns (140) is exposed. Through the planarization process, the first spacer pattern (123) on the active patterns (140) can be removed. The sacrificial layer (SL) formed at a level lower than the upper surface of the active pattern (140) can remain surrounded by the insulating pattern (135) on the second conductive pattern (MPb). The second spacer pattern (135P) can remain as the insulating pattern (135) formed on the side of the active patterns (140). The upper surface of the active pattern (140) may form a co-surface with the upper surface of the insulating pattern (135) and the upper surface of the second insulating pattern (126b). The insulating pattern (135) of FIG. 32 may correspond to the insulating pattern (135) of FIG. 4a.

[0182] Referring to FIGS. 33 and 34, the remaining sacrificial layer (SL) of FIG. 32 can be removed, and a word line structure (150) can be formed on the bit line structure (110) exposed between the insulating patterns (135). Referring to FIG. 33, a lower gate capping pattern (156a) can be formed on the bit line structure (110) exposed between the insulating patterns (135). Referring to FIG. 34, a first word line (154a) and a second word line (154b) spaced apart in a first direction (X direction) can be formed on the lower gate capping pattern (156a), and an upper gate capping pattern (156b) can be formed between the first word line (154a) and the second word line (154b) and on the first and second word lines (154a, 154b). Word lines (154) including first and second word lines (154a, 154b) and gate capping patterns (156) including lower and upper gate capping patterns (156a, 156b) can form a word line structure (150).

[0184] Referring to FIG. 35, contact patterns (170) can be formed on active patterns (140), and an information storage structure (180) can be formed on the contact patterns (170). A method for manufacturing a semiconductor device may further include the steps of forming first contact insulation patterns (175) between the contact patterns (170) and forming second contact insulation patterns (176) on the first contact insulation patterns (175). In one embodiment, after forming the information storage structure (180), the steps of removing the first substrate insulation layer (102) and the semiconductor substrate (101) below the bit line structure (110) and forming a wiring structure (e.g., vias (105), contact vias (106), wiring layer (112), and first bonding pads (BP1)) below the bit line structure (110) may be performed. In another example, after forming an information storage structure (180), wiring structures (e.g., vias (105), contact vias (106), wiring layer (112), and first bonding pads (BP1)) of FIG. 5 may be formed, or a second upper insulation structure (23) may be formed on the information storage structure (180) and then bonded to the second structure (ST2).

[0185] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the claims. Explanation of the symbols

[0186] 100: Semiconductor device 122: Back gate dielectric layer 110: Bit line structure 124: Back gate electrode 120: Back gate structure 126: Back gate capping pattern 135: Insulation pattern 154: Word Line 140: Active pattern 156: Gate capping pattern 150: Word line structure 110a: Part 1 170: Contact Pattern 110b: Part 2 180: Information storage structures 110c: Part 3 ST1: 1st Structure 110s, SP: Inclined surface ST2: 2nd Structure

Claims

Claim 1 A semiconductor device comprising: a bit line structure extending in a first direction; back gate structures disposed on the bit line structure and each comprising a back gate electrode; word line structures disposed alternately with the back gate structures in the first direction, wherein each of the word line structures comprises a first word line and a second word line adjacent to each other in the first direction; active patterns disposed between the back gate structures and the word line structures and connected to the bit line structure; contact patterns disposed on each of the active patterns and connected to each of the active patterns; and an information storage structure on the contact patterns, wherein the bit line structure comprises a first portion vertically overlapping with each of the back gate structures, a second portion vertically overlapping with each of the word line structures, and a third portion having an inclined surface that contacts each of the active patterns between the first portion and the second portion. Claim 2 A semiconductor device according to claim 1, wherein the upper surface of the first part is positioned at a lower level than the upper surface of the second part. Claim 3 A semiconductor device according to claim 1, wherein the inclined surface becomes higher as it is adjacent to the word line structures. Claim 4 A semiconductor device according to claim 1, wherein the lower surface of each of the active patterns has a shape protruding toward the lower surface of the third part of the bit line structure. Claim 5 A semiconductor device according to claim 1, further comprising a silicide pattern disposed between the lower surface of each of the active patterns and the third portion of the bit line structure. Claim 6 A semiconductor device comprising: a bit line structure extending in a first direction; first, second, and third active patterns arranged sequentially in the first direction on the bit line structure and connected to the bit line structure; a back gate electrode structure disposed between the first active pattern and the second active pattern and including a back gate dielectric layer and a back gate electrode disposed on the back gate dielectric layer; a word line structure disposed between the second active pattern and the third active pattern; contact patterns disposed on each of the first, second, and third active patterns and connected to the first, second, and third active patterns; and an information storage structure disposed on the contact patterns, wherein the bit line structure includes a first portion vertically overlapping with the back gate electrode structure and a second portion vertically overlapping with the word line structure and disposed at a different level from the first portion, and the upper surface of the first portion and the upper surface of the second portion are disposed at different levels. Claim 7 A semiconductor device according to claim 6, wherein the lower surface of each of the first, second, and third active patterns is disposed at a lower level than the upper surface of the first part and the upper surface of the second part. Claim 8 A semiconductor device according to claim 6, wherein the lower surface of each of the first, second, and third active patterns has a shape in which the width becomes narrower as it faces the lower surface of the bit line structure. Claim 9 A semiconductor device according to claim 6, further comprising: a substrate insulating layer disposed below the lower surface of the bit line structure; and a bare silicon substrate disposed below the lower surface of the substrate insulating layer. Claim 10 A first structure including a memory cell array region; and a second structure vertically superimposed with the first structure and including a peripheral circuit region, wherein the memory cell array region is Bit line structure extending in the first direction; A word line structure disposed on the bit line structure and comprising a gate capping pattern and a first word line and a second word line adjacent to each other in the first direction on the gate capping pattern; Active patterns disposed on the bit line structure and disposed on both sides of the word line structure; Insulating patterns disposed between each of the above-mentioned word line structures and each of the above-mentioned active patterns; Contact patterns disposed on each of the above active patterns and connected to each of the above active patterns; and A semiconductor device comprising an information storage structure on the above contact patterns, wherein the bit line structure is in contact with the lower surface of the insulation patterns and includes a portion having an inclined surface in which the vertical level increases as it is adjacent to the word line structure.

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