Multilayer electronic component

Abstract

A stacked electronic component according to one embodiment of the present invention comprises: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body; wherein the dielectric layer includes a central portion spaced apart from the internal electrode and including a first dielectric crystal grain, and an interface portion disposed between the internal electrode and the central portion and including a second dielectric crystal grain, and when the average size of the first dielectric crystal grain is Gs1, the average size of the second dielectric crystal grain is Gs2, the number of moles of Gd relative to 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd relative to 100 moles of Ti in the interface portion is Mgd2, Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.0 can be satisfied.

Description

Technology Field

[0001] The present invention relates to a stacked electronic component. Background Technology

[0003] A Multi-Layered Ceramic Capacitor (MLCC), a type of multilayer electronic component, is a chip-shaped capacitor mounted on the printed circuit boards of various electronic products—such as video devices like Liquid Crystal Displays (LCDs) and Plasma Display Panels (PDPs), computers, smartphones, and mobile phones—that serves to charge or discharge electricity.

[0004] Multilayer ceramic capacitors can be used as components in various electronic devices due to their advantages of being compact, guaranteeing high capacitance, and being easy to mount. As various electronic devices, such as computers and mobile devices, become smaller and more powerful, there is an increasing demand for miniaturization and / or higher capacitance of multilayer ceramic capacitors.

[0005] In addition, as the usage environments of multilayer ceramic capacitors become more diverse, reliability at high voltages is also required.

[0007] MLCCs used in high-voltage environments are called high-voltage MLCCs, and their rated voltage is 250V or higher. Since high-voltage MLCCs have a significantly higher rated voltage than general MLCCs, there is a risk that cracks may occur due to electrostriction when an electric field is applied, reduced reliability against moisture, and reduced breakdown voltage may occur. The problem to be solved

[0009] One of the various objectives of the present invention is to provide a stacked electronic component with excellent reliability.

[0010] One of the various objectives of the present invention is to provide a stacked electronic component capable of suppressing electrostriction phenomena.

[0011] One of the various objectives of the present invention is to provide a stacked electronic component capable of securing high capacity.

[0013] However, the purpose of the present invention is not limited to the above description and may be more easily understood in the process of explaining specific embodiments of the present invention. means of solving the problem

[0015] A stacked electronic component according to one embodiment of the present invention comprises: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body; wherein the dielectric layer includes a central portion spaced apart from the internal electrode and including a first dielectric crystal grain, and an interface portion disposed between the internal electrode and the central portion and including a second dielectric crystal grain, and when the average size of the first dielectric crystal grain is Gs1, the average size of the second dielectric crystal grain is Gs2, the number of moles of Gd relative to 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd relative to 100 moles of Ti in the interface portion is Mgd2, Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.0 can be satisfied. Effects of the invention

[0017] As one of the various effects of the present invention, the reliability of a stacked electronic component can be improved by controlling the average size of the dielectric crystal grains and the Gd content at the interface and central portions of the dielectric layer.

[0019] However, the various and beneficial advantages and effects of the present invention are not limited to those described above and may be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0021] FIG. 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. Figure 2 schematically illustrates the II' cross-sectional view of Figure 1. Figure 3 schematically illustrates the cross-sectional view of Figure 1 along line II-II'. Figure 4 shows the body of Figure 1 disassembled. Figure 5 is an enlarged view of the K1 region of Figure 2. FIG. 6 is a drawing corresponding to FIG. 5 according to another embodiment of the present invention. FIG. 7 is a drawing corresponding to FIG. 5 according to another embodiment of the present invention. Specific details for implementing the invention

[0022] Embodiments of the present invention will be described below with reference to specific embodiments and the attached drawings. However, embodiments of the present invention may be modified in various different forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0024] Furthermore, in order to clearly explain the invention in the drawings, parts unrelated to the explanation are omitted, and the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation; thus, the invention is not necessarily limited to what is illustrated. Additionally, components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0025] In the drawing, the X direction may be defined as the first direction, stacking direction, or thickness (T) direction, the Y direction as the second direction or length (L) direction, and the Z direction as the third direction or width (W) direction.

[0027] Stacked electronic components

[0029] FIG. 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention.

[0030] Figure 2 schematically illustrates the II' cross-sectional view of Figure 1.

[0031] Figure 3 schematically illustrates the cross-sectional view of Figure 1 along line II-II'.

[0032] Figure 4 shows the body of Figure 1 disassembled.

[0033] Figure 5 is an enlarged view of the K1 region of Figure 2.

[0035] Hereinafter, a stacked electronic component (100) according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5. In addition, a multilayered ceramic capacitor (hereinafter referred to as 'MLCC') will be described as an example of a stacked electronic component, but the present invention is not limited thereto and may be applied to various stacked electronic components using ceramic materials, such as inductors, piezoelectric elements, varistors, or thermistors.

[0037] A stacked electronic component (100) according to one embodiment of the present invention comprises: a body (110) including a dielectric layer (111) and internal electrodes (121, 122) alternately disposed with said dielectric layer; and external electrodes (131, 132) disposed on said body; The dielectric layer (111) includes a central portion (CP) that is spaced apart from the internal electrode and includes a first dielectric grain (G1), and an interface portion (IP1, IP2) that is disposed between the internal electrode and the central portion and includes a second dielectric grain (G2). When the average size of the first dielectric grain is Gs1, the average size of the second dielectric grain is Gs2, the number of moles of Gd relative to 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd relative to 100 moles of Ti in the interface portion is Mgd2, Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.0 can be satisfied.

[0039] Adding Gd to the dielectric layer can suppress electrostriction by lowering the dielectric constant, but there was a concern that the capacitance of the multilayer ceramic capacitor would decrease.

[0040] According to one embodiment of the present invention, when the Gd content of the interface portions (IP1, IP2) is increased compared to the central portion (CP) and the average size of the dielectric grains is reduced, the reliability of the stacked electronic component (100) can be improved by suppressing the electrostriction phenomenon while suppressing the capacity reduction due to Gd addition.

[0042] Hereinafter, each component included in the stacked electronic component (100) according to one embodiment of the present invention will be described.

[0044] The body (110) may have dielectric layers (111) and internal electrodes (121, 122) alternately stacked.

[0045] There are no specific restrictions on the specific shape of the body (110), but as illustrated, the body (110) may be formed in a cuboid shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the body (110) during the firing process, the body (110) may not have a cuboid shape with perfect straight lines, but may have a substantially cuboid shape.

[0046] The body (110) may have first and second faces (1, 2) facing in a first direction, third and fourth faces (3, 4) connected to the first and second faces (1, 2) and facing in a second direction, and fifth and sixth faces (5, 6) connected to the first and second faces (1, 2) and facing in a third direction.

[0047] As the margin region where the internal electrodes (121, 122) are not placed on the dielectric layer (111) overlaps, a step difference occurs due to the thickness of the internal electrodes (121, 122), so that the corner connecting the first surface and the third to fifth surfaces and / or the corner connecting the second surface and the third to fifth surfaces may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, due to shrinkage behavior during the sintering process of the body, the corner connecting the first surface (1) and the third to sixth surfaces (3, 4, 5, 6) and / or the corner connecting the second surface (2) and the third to sixth surfaces (3, 4, 5, 6) may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the body (110) may be rounded by performing a separate process, so that the corner connecting the first face and the third to sixth faces and / or the corner connecting the second face and the third to sixth faces may have a round shape.

[0048] Meanwhile, in order to suppress the step difference caused by the internal electrodes (121, 122), after lamination, the internal electrodes are cut so that they are exposed to the fifth and sixth surfaces (5, 6) of the body, and then a single dielectric layer or two or more dielectric layers are laminated in the third direction (width direction) on both sides of the capacitance forming part (Ac) to form a side margin part (114, 115), the part connecting the first surface and the fifth and sixth surfaces and the part connecting the second surface and the fifth and sixth surfaces may not have a contracted shape.

[0050] A plurality of dielectric layers (111) forming the body (110) are in a sintered state, and the boundaries between adjacent dielectric layers (111) can be integrated to such an extent that it is difficult to verify them without using a scanning electron microscope (SEM). There is no particular need to limit the number of dielectric layers stacked, and it can be determined by considering the size of the stacked electronic component. For example, the body can be formed by stacking 400 or more dielectric layers.

[0052] Referring to FIG. 5, the dielectric layer (111) may include a central portion (CP) that is spaced apart from the internal electrodes (121, 122) and includes a first dielectric crystal grain (G1), and an interface portion (IP1, IP2) that is disposed between the internal electrodes (121, 122) and the central portion (CP) and includes a second dielectric crystal grain (G2).

[0053] In addition, when the average size of the first dielectric grain (G1) is Gs1, the average size of the second dielectric grain (G2) is Gs2, the number of moles of Gd relative to 100 moles of Ti in the central part (CP) is Mgd1, and the number of moles of Gd relative to 100 moles of Ti in the interface part (IP1, IP2) is Mgd2, Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.0 can be satisfied. Accordingly, the electrostriction phenomenon can be suppressed while suppressing the capacity reduction due to Gd addition.

[0054] If the average size of the first dielectric grain (Gs1) is smaller than the average size of the second dielectric grain (Gs2), it may be difficult to suppress the electro-striction phenomenon.

[0055] If Mgd1 is equal to or greater than Mgd2, there is a concern that the capacity may be reduced. For example, Mgd1 may be 2.0 or less. Meanwhile, the central portion (CP) does not necessarily have to contain Gd, and the central portion (CP) may not contain Gd, and accordingly, Mgd1 may be 0.

[0056] If Mgd2 is less than 4.0, there is a concern that the effect of suppressing total strain expansion of the central part (CP) may be insufficient, and if Mgd2 is greater than 25.0, there is a concern that the capacity may decrease. Therefore, it is desirable to satisfy 4.0≤Mgd2≤25.0, and more preferably 5.0≤Mgd2≤10.0.

[0058] In one embodiment, Gs1 and Gs2 may satisfy Gs2 / Gs1 ≥ 0.5. This is because if the difference in grain size becomes too large, there is a risk of other side effects occurring.

[0060] Meanwhile, there is no need to specifically limit the specific ranges of Gs1 and Gs2, respectively.

[0061] For example, in one embodiment, the Gs1 may be 300 nm or more and 700 nm or less, and the Gs2 may be 150 nm or more and 600 nm or less. Accordingly, the effects of suppressing capacity degradation and suppressing total distortion of the present invention can be further improved.

[0062] In one embodiment, Gs1 and Gs2 may satisfy Gs1-Gs2≤100nm. This is because if the difference in grain size becomes too large, there is a risk of other side effects occurring.

[0064] Meanwhile, the average size of the first dielectric grain (Gs1), the average size of the second dielectric grain (Gs2), the number of moles of Gd relative to 100 moles of Ti in the central part (Mgd1), and the number of moles of Gd relative to 100 moles of Ti in the interface part (Mgd2) may be measured from images observed using SEM-EDS (Scanning Electron Microscope-Energy Dispersive X-ray Spectrometer), TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), or FE-SEM-EDS (Field Emission-scanning Electron Microscope-Energy Dispersive X-ray Spectrometer).

[0065] More specifically, the stacked electronic component (100) is polished to the third direction 1 / 2 point to expose the first and second direction cross-sections of the stacked electronic component (100). Afterward, the average size of the dielectric grains at the interface and the center of the dielectric layer placed at the center of the first direction of the capacitance forming part (Ac) can be measured using FE-SEM-EDS (acceleration voltage: 2 kV, magnification: 50,000x). Since the size of the dielectric grains changes rapidly at the boundary between the interface and the center, the interface and the center can be easily distinguished in the image scanned by the SEM. The size of the dielectric grains may be the equivalent diameter measured using image analysis software (ImageJ), and the sizes of 30 or more dielectric grains at the interface and the center, respectively, can be averaged to form Gs1 and Gs2.

[0066] In addition, the content (mol%) of Gd and Ti is measured at the interface and the center, respectively. From this, Mgd1 and Mgd2 can be obtained by calculating the number of moles of Gd relative to 100 moles of Ti contained in the interface and the center, respectively.

[0067] Meanwhile, 10 dielectric layers are selected and placed in the upper, central, and lower parts of the first direction of the capacitance forming part (Ac), and Gs1, Gs2, Mgd1, and Mgd2 are calculated from a total of 30 dielectric layers, and then the average value of those values ​​is calculated to further generalize Gs1, Gs2, Mgd1, and Mgd2.

[0069] In one embodiment, the internal electrodes (121, 122) include a first internal electrode (121) and a second internal electrode (122) that are alternately arranged with the dielectric layer (111) in between, and the interface portions (IP1, IP2) may include a first interface portion (IP1) arranged between the central portion (CP) and the first internal electrode (121) and a second interface portion (IP2) arranged between the central portion (CP) and the second internal electrode (122).

[0071] In one embodiment, when the average thickness of the first interface (IP1) is tdi1, the average thickness of the second interface (IP2) is tdi2, and the average thickness of the central part (CP) is tdc, tdi1 / tdc ≤ 0.2 and tdi2 / tdc ≤ 0.2 may be satisfied. If tdi1 / tdc is greater than 0.2 or tdi2 / tdc is greater than 0.2, there is a concern that the capacity reduction suppression effect according to the present invention may be insufficient.

[0073] Meanwhile, there is no need to specifically limit the specific ranges of tdi1, tdi2, and tdc, respectively.

[0074] For example, in one embodiment, the tdi1 and tdi2 may each be 200 nm or more and 500 nm or less.

[0075] In one embodiment, the tdc may be 1000 nm or more.

[0076] In one embodiment, the sum of tdi1, tdi2, and tdc may be 1.4 μm or more and 10.0 μm or less. Here, the sum of tdi1, tdi2, and tdc may represent the average thickness (td) of the dielectric layer.

[0078] Here, tdi1, tdi2, and tdc may represent the thickness in the first direction. tdi1, tdi2, and tdc can be measured by scanning the cross-sections of the body (110) in the first and second directions with a scanning electron microscope (SEM) at a magnification of 10,000. The thicknesses of the first interface (IP1), the second interface (IP2), and the central part (CP) can be measured at 30 equal intervals in the second direction, respectively, and the average value of each can be measured. The 30 equal intervals can be designated in the capacitance forming part (Ac) to be described later. Furthermore, if this average value measurement is extended to 10 dielectric layers (111) and the average value is measured, tdi1, tdi2, and tdc can be further generalized.

[0080] In one embodiment, the dielectric constant of the interface portion (IP1, IP2) may be 1500 or less, and the dielectric constant of the central portion (CP) may be 2000 or more. Accordingly, the capacity degradation suppression and electrostriction phenomenon suppression effects of the present invention can be further improved.

[0082] Meanwhile, referring to FIG. 6, the second dielectric crystal grain (G2') included in the interface portion (IP1, IP2) of the dielectric layer (111') may have a core-shell structure including a core (G2c) and a shell (G2s) surrounding at least a part of the core (G2c). In this case, the atomic percentage of Gd content included in the shell (G2s) may be higher than the atomic percentage of Gd content included in the core (G2c). In this case, the first dielectric crystal grain (G1) included in the central portion (CP) may not have a core-shell structure.

[0083] However, it is not necessary to be limited thereto, and as illustrated in FIG. 7, the first dielectric crystal grain (G1') and the second dielectric crystal grain (G2') included in the dielectric layer (111'') may both have a core-shell structure. Referring to FIG. 7, the first dielectric crystal grain (G1') included in the central part (CP) of the dielectric layer (111') may also have a core-shell structure including a core (G1c) and a shell (G1s) surrounding at least a part of the core (G1c). In this case, the atomic percentage of Gd content included in the shell (G1s) may be higher than the atomic percentage of Gd content included in the shell (G1s).

[0085] The method of forming the dielectric layer (111) is not specifically limited.

[0086] For example, a ceramic green sheet can be prepared by applying a ceramic slurry containing an organic solvent and a binder onto a carrier film, such that the interface portion of the ceramic sheet has a higher Gd content than the central portion. Subsequently, a dielectric layer can be formed by sintering the ceramic green sheet.

[0087] The ceramic powder is not particularly limited as long as sufficient capacitance can be obtained, but, for example, barium titanate-based (BaTiO3) powder can be used as the ceramic powder. To give a more specific example, the ceramic powder is BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1), Ba(Ti 1-y Ca y )O3 (0 <y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 <x<1, 0<y<1) 및 Ba(Ti 1-y Zr y )O3(0 <y<1) 중 하나 이상일 수 있다.

[0088] Accordingly, in one embodiment, the dielectric layer (111) is BaTiO3, (Ba1-x Ca x )TiO3(0 <x<1), Ba(Ti 1-y Ca y )O3(0 <y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 <x<1, 0<y<1) 및 Ba(Ti 1-y Zr y )O3(0 <y<1) 중 하나 이상을 주성분으로 포함할 수 있다. 여기서, 주성분의 의미는 주성분 100몰 대비 주성분을 제외한 나머지 성분들의 몰수가 30몰 이하인 것을 의미할 수 있다.

[0090] The body (110) may include a capacitance forming part (Ac) in which a capacitance is formed by including a first internal electrode (121) and a second internal electrode (122) that are positioned facing each other with a dielectric layer (111) in between, and cover parts (112, 113) formed on the upper and lower sides of the first direction of the capacitance forming part (Ac).

[0091] In addition, the capacitance forming part (Ac) is a part that contributes to the capacitance formation of the capacitor, and can be formed by repeatedly stacking a plurality of first and second internal electrodes (121, 122) with a dielectric layer (111) in between.

[0093] The cover portion (112, 113) may include an upper cover portion (112) positioned above the first direction of the capacity forming portion (Ac) and a lower cover portion (113) positioned below the first direction of the capacity forming portion (Ac).

[0094] The upper cover portion (112) and lower cover portion (113) can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion (Ac), respectively, and can basically perform the role of preventing damage to the internal electrode due to physical or chemical stress.

[0095] The upper cover portion (112) and lower cover portion (113) above do not include an internal electrode and may include the same material as the dielectric layer (111).

[0096] That is, the upper cover portion (112) and the lower cover portion (113) may include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

[0097] Meanwhile, the thickness of the cover portion (112, 113) does not need to be specifically limited. For example, the thickness (tc) of the cover portion (112, 113) may be 100 μm or less.

[0098] The average thickness (tc) of the cover portion (112, 113) may mean the first direction size and may be the average value of the first direction sizes of the cover portion (112, 113) measured at five equally spaced points on the upper or lower part of the capacitance forming portion (Ac).

[0100] In addition, a margin portion (114, 115) may be disposed on the side of the above-mentioned capacity forming portion (Ac).

[0101] The margin portions (114, 115) may include a first margin portion (114) disposed on the fifth surface (5) of the body (110) and a second margin portion (115) disposed on the sixth surface (6). That is, the margin portions (114, 115) may be disposed on both end surfaces in the width direction of the ceramic body (110).

[0102] The margin portion (114, 115) may refer to the area between the two ends of the first and second internal electrodes (121, 122) and the boundary surface of the body (110) in a cross-section cut in the width-thickness (WT) direction of the body (110), as shown in FIG. 5.

[0103] The margin portion (114, 115) can basically perform the role of preventing damage to the internal electrode due to physical or chemical stress.

[0104] The margin portion (114, 115) may be formed by applying a conductive paste to the ceramic green sheet, excluding the area where the margin portion is to be formed, to form an internal electrode.

[0105] In addition, to suppress the step difference caused by the internal electrodes (121, 122), after lamination, the internal electrodes may be cut so that they are exposed to the fifth and sixth sides (5, 6) of the body, and then a single dielectric layer or two or more dielectric layers may be laminated in the third direction (width direction) on both sides of the capacitance forming part (Ac) to form a margin part (114, 115).

[0106] Meanwhile, the width of the margin portion (114, 115) does not need to be specifically limited. For example, the average width of the margin portion (114, 115) may be 100 μm or less.

[0107] The average width of the margin portion (114, 115) may refer to the average size in the third direction (MW1) of the area where the internal electrode is spaced apart from the fifth surface and the average size in the third direction (MW2) of the area where the internal electrode is spaced apart from the sixth surface, and may be the average value of the third direction sizes of the margin portion (114, 115) measured at five equally spaced points on the side of the capacitance forming portion (Ac).

[0108] Accordingly, in one embodiment, the average size (MW1, MW2) of the third direction of the area where the internal electrodes (121, 122) are spaced apart from the fifth and sixth surfaces may each be 100 μm or less.

[0110] The internal electrodes (121, 122) may include first and second internal electrodes (121, 122). The first and second internal electrodes (121, 122) are alternately arranged to face each other with the dielectric layer (111) constituting the body (110) in between, and may be exposed to the third and fourth surfaces (3, 4) of the body (110), respectively.

[0111] The first internal electrode (121) may be spaced apart from the fourth surface (4) and exposed through the third surface (3), and the second internal electrode (122) may be spaced apart from the third surface (3) and exposed through the fourth surface (4). The first external electrode (131) may be disposed on the third surface (3) of the body and connected to the first internal electrode (121), and the second external electrode (132) may be disposed on the fourth surface (4) of the body and connected to the second internal electrode (122).

[0112] That is, the first internal electrode (121) is connected to the first external electrode (131) but not to the second external electrode (132), and the second internal electrode (122) is connected to the second external electrode (132) but not to the first external electrode (131). Accordingly, the first internal electrode (121) may be formed at a certain distance from the fourth surface (4), and the second internal electrode (122) may be formed at a certain distance from the third surface (3). In addition, the first and second internal electrodes (121, 122) may be arranged at a distance from the fifth and sixth surfaces of the body (110).

[0113] The conductive metal included in the internal electrode (121, 122) may be one or more of Ni, Cu, Pd, Ag, Au, Pt, In, Sn, Al, W, Ti and alloys thereof, but the present invention is not limited thereto.

[0115] The average thickness (te) of the internal electrode does not need to be specifically limited. In this case, the thickness of the internal electrode (121, 122) may refer to the first direction size of the internal electrode (121, 122).

[0116] However, in order to more easily achieve miniaturization and high capacity of the stacked electronic component, the average thickness of the internal electrodes (121, 122) may be 0.4 μm or less.

[0117] Here, the average thickness (te) of the internal electrode can be measured by scanning the cross-sections of the body (110) in the first and second directions with a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, the thickness can be measured at multiple points of a single internal electrode (121, 122), for example, at 30 equally spaced points in the second direction, and the average value can be measured. The 30 equally spaced points can be designated in the capacitance forming unit (Ac). In addition, if this average value measurement is extended to 10 internal electrodes (121, 122) and the average value is measured, the average thickness of the internal electrode (121, 122) can be further generalized.

[0119] External electrodes (131, 132) can be placed on the third side (3) and the fourth side (4) of the body (110).

[0120] The external electrodes (131, 132) may each be disposed on the third and fourth surfaces (3, 4) of the body (110) and may include the first and second external electrodes (131, 132) connected to the first and second internal electrodes (121, 122), respectively.

[0121] Referring to FIG. 1, the external electrodes (131, 132) may be arranged to cover both ends of the second direction of the side margin portions (114, 115).

[0122] In this embodiment, a structure is described in which a stacked electronic component (100) has two external electrodes (131, 132), but the number or shape of the external electrodes (131, 132) may change depending on the shape of the internal electrodes (121, 122) or other purposes.

[0124] Meanwhile, the external electrodes (131, 132) can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc., and furthermore, they can have a multilayer structure.

[0125] For example, the external electrode (131, 132) may include an electrode layer (131a, 132a) disposed on the body (110) and a plating layer (131b, 132b) formed on the electrode layer (131a, 132a).

[0126] As a more specific example of the electrode layer (131a, 132a), the electrode layer (131a, 132a) may be a fired electrode including a conductive metal and glass, or a resin-based electrode including a conductive metal and resin.

[0127] Additionally, the electrode layers (131a, 132a) may be formed such that a sintered electrode and a resin-based electrode are sequentially formed on the body. Additionally, the electrode layers (131a, 132a) may be formed by transferring a sheet containing a conductive metal onto the body, or by transferring a sheet containing a conductive metal onto a sintered electrode.

[0128] The conductive metal included in the electrode layer (131a, 132a) may be a material with excellent electrical conductivity and is not specifically limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys.

[0130] The plating layer (131b, 132b) serves to improve mounting characteristics. The type of plating layer (131b, 132b) is not specifically limited and may be a plating layer comprising one or more of Ni, Sn, Pd and alloys thereof, and may be formed in multiple layers.

[0131] As a more specific example regarding the plating layer (131b, 132b), the plating layer (131b, 132b) may be a Ni plating layer or a Sn plating layer, and may be in a form where a Ni plating layer and a Sn plating layer are sequentially formed on the electrode layer (131a, 132a), or may be in a form where a Sn plating layer, a Ni plating layer, and a Sn plating layer are sequentially formed. Additionally, the plating layer (131b, 132b) may include a plurality of Ni plating layers and / or a plurality of Sn plating layers.

[0133] The size of the stacked electronic component (100) does not need to be specifically limited. For example, the size of the stacked electronic component (100) may be 0201 (length × width, 0.2mm × 0.1mm), 0603 (length × width, 0.6mm × 0.3mm), 1005 (length × width, 1.0mm × 0.5mm), 2012 (length × width, 2.0mm × 1.2mm), 3216 (length × width, 3.2mm × 1.6mm), 3225 (length × width, 3.2mm × 2.5mm), etc.

[0135] Method for manufacturing stacked electronic components

[0136] Hereinafter, an example of a method for manufacturing a stacked electronic component (100) according to an embodiment of the present invention is described. However, the method for manufacturing the stacked electronic component (100) of the present invention is not limited thereto.

[0138] First, a ceramic green sheet can be prepared by applying a ceramic slurry containing ceramic powder, an organic solvent, and a binder onto a carrier film, such that the interface of the ceramic sheet has a higher Gd content than the center.

[0140] Subsequently, a ceramic green sheet for capacitance forming can be produced by forming an internal electrode pattern by printing a conductive paste for internal electrodes containing metal powder, a binder, an organic solvent, etc., on a ceramic green sheet with a predetermined thickness using a screen printing method or a gravure printing method.

[0141] A laminate can be obtained by stacking ceramic green sheets for a capacitance forming part in the X direction. At this time, ceramic green sheets without an internal electrode pattern can be stacked on the upper and lower parts of the laminate to form cover parts (112, 113) after sintering.

[0143] Subsequently, the laminate is cut to have a predetermined chip size. At this time, the ends of the internal electrode patterns are exposed on both sides facing the third direction of the cut chip.

[0144] Next, a sheet for forming margin portions can be attached to both sides of the third direction of the cut chip and then fired to form a body (110) and side margin portions (114, 115). The firing temperature may be, for example, 1000°C or higher and 1400°C or lower, but the present invention is not limited thereto.

[0145] The sheet for forming the margin does not need to be specifically limited, and the general ceramic green sheet described above can be used.

[0147] Next, external electrodes (131, 132) are formed. For example, if the base electrode layer (131a, 132a) includes a sintered electrode layer, the body (110) may be dipped into a conductive paste for external electrodes comprising metal powder, glass frit, a binder, and an organic solvent, and then the conductive paste for external electrodes may be sintered at a temperature of 500°C to 900°C to form the sintered electrode layer.

[0148] For example, if the base electrode layer (131a, 132a) includes a resin electrode layer, the body can be dipped into a conductive resin composition comprising metal powder, resin, binder, and organic solvent, and then heat-treated to cure at a temperature of 250°C to 550°C to form a resin electrode layer.

[0149] In addition, an electrolytic plating method and / or an electroless plating method may be additionally performed to form a plating layer (131b, 132b) on the base electrode layer (131a, 132a).

[0151] (Experimental Example)

[0152] A sample chip of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm, thickness: approximately 0.5 mm) was prepared using the manufacturing method described above.

[0153] A sample chip was fabricated such that the average size of the first dielectric grain (Gs1), the average size of the second dielectric grain (Gs2), the number of moles of Gd relative to 100 moles of Ti in the central part (Mgd1), and the number of moles of Gd relative to 100 moles of Ti in the interface part (Mgd2) satisfy Table 1 below.

[0154] The average size of the first dielectric grain (Gs1), the average size of the second dielectric grain (Gs2), the number of moles of Gd relative to 100 moles of Ti in the central part (Mgd1), and the number of moles of Gd relative to 100 moles of Ti in the interface part (Mgd2) were measured by analyzing the first and second direction cross-sections polished to the third direction 1 / 2 point of the sample chip using FE-SEM-EDS (acceleration voltage: 2 kV, magnification: 50,000x).

[0155] The capacitance of the sample chip was measured using an LCR meter under 1 kHz conditions, and the relative values ​​are listed in Table 1 below.

[0156] In addition, moisture resistance reliability was assessed by mounting the sample chip on a substrate and applying a high voltage (1 kV) for 1,000 hours at a temperature of 85°C and a relative humidity of 85%. If the insulation resistance decreased to 1 / 100 or less of the initial value, it was marked as 'X', and if the insulation resistance remained above 1 / 100 of the initial value, it was marked as '○'. In the case of 'X', it can be judged that the electro-striction suppression effect is insufficient as cracks caused by electro-striction phenomena occur, and in the case of '○', it can be seen that the electro-striction phenomenon is suppressed and no cracks occur, and the electro-striction suppression effect is judged to be excellent.

[0158] Test number 1 2 3 4 5 6 7 Gs1 480 480 450 480 475 475 440 Gs2 480 450 450 390 380 200 450 Mgd1 0 0 2.0 0.0 1.0 1.0 4.0 Mgd2 0 2.0 2.0 7.0 10.0 28.0 2.0 volume(%) 106.34 104.08 102.02 100.0 98.8 96.05 85.05 Moisture resistance reliability X X X ○ ○ ○ ○

[0160] Referring to Table 1, it can be seen that Test No. 1, where Mgd1 and Mgd2 are 0, has the best capacity but inferior moisture resistance. Test Nos. 2 and 3, which have a small amount of Gd added, also show inferior moisture resistance. In the case of Test Nos. 6 and 7, it can be seen that the capacity decreased due to the large amount of Gd added.

[0161] On the other hand, in the case of test numbers 4 and 5, which satisfy Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.0, it can be confirmed that the capacity degradation is suppressed while the moisture resistance reliability is excellent.

[0163] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the aforementioned embodiments and accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

[0165] Furthermore, the expression "one embodiment" as used in this disclosure does not imply identical embodiments, but is provided to emphasize distinct features of each. However, the presented one embodiment does not exclude implementation in combination with features of other one embodiments. For example, even if a matter described in a specific one embodiment is not described in another one embodiment, it may be understood as a description related to another one embodiment, provided that there is no description in another one embodiment that contradicts or conflicts with such matter.

[0166] The terms used in this disclosure are used merely to describe one embodiment and are not intended to limit this disclosure. Whereby, singular expressions include plural expressions unless the context clearly indicates otherwise. Explanation of the symbols

[0168] 100: Stacked electronic components 110: Body 111: Genome layer IP1, IP2: Interface CP: Central 112, 113: Cover section 114, 115: Margin 121, 122: Internal electrodes 131, 132: External electrodes 131a, 132a: Electrode layer 131b, 132b: Plating layer

Claims

Claim 1 A stacked electronic component comprising: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body; wherein the dielectric layer includes a central portion spaced apart from the internal electrode and including a first dielectric crystal grain, and an interface portion disposed between the internal electrode and the central portion and including a second dielectric crystal grain, wherein the average size of the first dielectric crystal grain is Gs1, the average size of the second dielectric crystal grain is Gs2, the number of moles of Gd relative to 100 moles of Ti in the central portion is Mgd1, and the number of moles of Gd relative to 100 moles of Ti in the interface portion is Mgd2, satisfying Gs2 / Gs1<1, Mgd1 / Mgd2<1, and 4.0≤Mgd2≤25.

0. Claim 2 In claim 1, the above Gs1 and Gs2 are stacked electronic components satisfying Gs2 / Gs1≥0.

5. Claim 3 A stacked electronic component according to claim 1, wherein Gs1 is 300 nm or more and 700 nm or less, and Gs2 is 150 nm or more and 600 nm or less. Claim 4 In claim 1, the above Gs1 and Gs2 are stacked electronic components satisfying Gs1-Gs2≤100nm. Claim 5 In claim 1, the Mgd2 is a stacked electronic component satisfying 5.0≤Mgd2≤10.

0. Claim 6 A stacked electronic component according to claim 1, wherein Mgd1 is 0. Claim 7 A stacked electronic component according to claim 1, wherein the internal electrodes include first and second internal electrodes alternately arranged with the dielectric layer in between, and the interface portion includes a first interface portion arranged between the central portion and the first internal electrode and a second interface portion arranged between the central portion and the second internal electrode. Claim 8 A stacked electronic component according to claim 7, wherein the average thickness of the first interface is tdi1, the average thickness of the second interface is tdi2, and the average thickness of the central portion is tdc, satisfying tdi1 / tdc≤0.2 and tdi2 / tdc≤0.

2. Claim 9 In claim 8, the above tdi1 and tdi2 are stacked electronic components each having a length of 200 nm or more and 500 nm or less. Claim 10 In claim 8, the above tdc is a stacked electronic component having a thickness of 1000 nm or more. Claim 11 A stacked electronic component according to claim 8, wherein the sum of tdi1, tdi2, and tdc is 1.4 μm or more and 10.0 μm or less. Claim 12 In claim 1, the dielectric layer is BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1), Ba(Ti 1-y Ca y )O3(0 <y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 <x<1, 0<y<1) 및 Ba(Ti 1-y Zr y )O3(0 <y<1) 중 하나 이상을 주성분으로 포함하는 적층형 전자 부품. Claim 13 A stacked electronic component according to claim 1, wherein the dielectric constant of the interface portion is 1500 or less, and the dielectric constant of the central portion is 2000 or more. Claim 14 In claim 1, the second dielectric crystal grain is a stacked electronic component having a core-shell structure. Claim 15 In claim 14, the first dielectric crystal grain is a stacked electronic component having a core-shell structure.

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