Semiconductor device and method for fabricating thereof

Abstract

The invention provides a semiconductor device capable of improving electrical characteristics and reliability. The semiconductor device comprises an upper electrode, a lower electrode comprising a first metal element, a lower insert electrode film disposed between the upper electrode and the lower electrode, having a rutile structure and comprising an oxide of the lower electrode, a lower interface electrode film disposed between the lower insert electrode film and the upper electrode, having a rutile structure and comprising an oxide of a second metal element different from the first metal element, and a capacitor dielectric film disposed between the lower interface electrode film and the upper electrode, having a tetragonal crystal system and comprising an oxide of a third metal element different from the second metal element.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device using a capacitor as a data storage element and a method for manufacturing the same. Background Technology

[0002] Recently, as semiconductor devices have become larger in capacity and more highly integrated, design rules have also been continuously decreasing. This trend is also evident in DRAM, a type of memory semiconductor device. For a DRAM device to operate, each cell requires a capacitance of a certain level or higher.

[0003] An increase in capacitance increases the amount of charge stored in the capacitor, thereby improving the refresh characteristics of the semiconductor device. The improved refresh characteristics of the semiconductor device can improve the yield of the semiconductor device.

[0004] To increase capacitance, methods are being studied to utilize dielectric films with high dielectric constants in capacitors or to increase the contact area between the capacitor's bottom electrode and the dielectric film. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor device capable of improving electrical characteristics and reliability.

[0006] Another problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device that can improve electrical characteristics and reliability.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] One aspect of the semiconductor device of the present invention for solving the above problem comprises an upper electrode, a lower electrode comprising a first metal element, a lower insert electrode film disposed between the upper electrode and the lower electrode and having a rutile structure and comprising an oxide of the lower electrode, a lower interface electrode film disposed between the lower insert electrode film and the upper electrode and having a rutile structure and comprising an oxide of a second metal element different from the first metal element, and a capacitor dielectric film disposed between the lower interface electrode film and the upper electrode and having a tetragonal crystal system and comprising an oxide of a third metal element different from the second metal element.

[0009] Another aspect of the semiconductor device of the present invention for solving the above problem comprises a landing pad on a substrate, a lower electrode connected to the landing pad and extending in one direction and comprising a first metal element, a support pattern in contact with a part of the lower electrode and comprising a first surface and a second surface opposite in one direction, wherein the sidewall of the support pattern connects the first surface and the second surface of the support pattern and the support pattern in contact with the lower electrode, a lower insertion electrode film in contact with the lower electrode and comprising an oxide of the lower electrode, a lower interface electrode film in contact with the lower insertion electrode film and the support pattern, extending along the first surface and the second surface of the support pattern and comprising an oxide of a second metal element, a capacitor dielectric film in contact with the lower interface electrode film and the support pattern, extending along the first surface and the second surface of the support pattern and comprising an oxide of a third metal element, and an upper electrode on the capacitor dielectric film.

[0010] Another aspect of the semiconductor device of the present invention for solving the above problem comprises an upper electrode, a lower electrode comprising a first metal element or a nitride of the first metal element, a lower insert electrode film in contact with the lower electrode between the upper electrode and the lower electrode and comprising an oxide of the lower electrode, a lower interface electrode film in contact with the lower insert electrode film between the lower insert electrode film and the upper electrode and having a rutile structure and comprising an oxide of a second metal element different from the first metal element, and a capacitor dielectric film in contact with the lower interface electrode film between the lower interface electrode film and the upper electrode and having a tetragonal crystal structure and comprising an oxide of a third metal element different from the second metal element, wherein the preferred growth crystal plane of the capacitor dielectric film on the lower electrode is the (110) plane.

[0011] One aspect of the method for manufacturing a semiconductor device according to the present invention for solving the above other problems comprises forming a free lower electrode containing a first metal element, oxidizing a portion of the free lower electrode to form a lower electrode and a lower insert electrode film, wherein the lower insert electrode film contains an oxide of the free lower electrode, and after forming the lower insert electrode film, forming a lower electrode interface film containing an oxide of a second metal element different from the first metal element on the lower insert electrode film, and forming a capacitor dielectric film containing an oxide of a third metal element different from the second metal element on the lower electrode interface film.

[0012] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0013] FIG. 1 is an exemplary drawing for illustrating a semiconductor device according to some embodiments. Figure 2 is a graph for explaining the metal elements included in the lower electrode, lower insertion electrode film, lower interface electrode film, and capacitor dielectric film of Figure 1. Figure 3 is an enlarged view of section P of Figure 1. FIG. 4 is a schematic layout of a semiconductor device according to some embodiments. Figure 5 is a layout showing only the word line and cell active area of ​​Figure 4. FIG. 6 is an exemplary cross-sectional view taken along A-A of FIG. 4. Figure 7 is an exemplary cross-sectional view taken along B-B of Figure 4. Figure 8 is an enlarged view of section Q of Figure 6. Figure 9 is a plan view cut along C-C of Figure 6. Figures 10 and 11 are enlarged drawings of the R1 and R2 portions of Figure 9. FIG. 12 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 13 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 14 is a perspective view for explaining the semiconductor device of FIG. 13. Figure 15 is a cross-sectional view taken along D-D and E-E of Figure 13. Figure 16 is an enlarged view to explain part S of Figure 15. FIG. 17 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 18 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 19 is a perspective view for explaining the semiconductor device of FIG. 18. FIG. 20 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 21 to 24 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. FIGS. 25 to 29 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0014] In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0015] With reference to FIGS. 1 to 3, a semiconductor device according to some embodiments will be described.

[0016] FIG. 1 is an exemplary drawing for explaining a semiconductor device according to some embodiments. FIG. 2 is a graph for explaining metal elements included in the lower electrode, lower insertion electrode film, lower interface electrode film, and capacitor dielectric film of FIG. 1. FIG. 3 is an enlarged view of section P of FIG. 1.

[0017] For reference, FIG. 3 may be a diagram illustrating the crystal plane and crystal growth direction of one of the crystal grains included in the capacitor dielectric film.

[0018] Referring to FIGS. 1 to 3, a semiconductor device according to some embodiments may include a capacitor structure (CS).

[0019] A capacitor structure (CS) can be placed on a first substrate (10) and a lower insulating film (20).

[0020] The first substrate (10) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the first substrate (10) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0021] A lower insulating film (20) may be disposed on a first substrate (10). The lower insulating film (20) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide. The above low dielectric constant material may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof, but is not limited thereto.

[0022] A capacitor structure (CS) may be disposed on a first substrate (10). The capacitor structure (CS) may include a lower electrode (30), a lower insertion electrode film (32), a lower interface electrode film (34), a capacitor dielectric film (40), and an upper electrode (50).

[0023] The lower insert electrode film (32), the lower interface electrode film (34), and the capacitor dielectric film (40) are disposed between the lower electrode (30) and the upper electrode (50). The lower insert electrode film (32) and the lower interface electrode film (34) are disposed between the lower electrode (30) and the capacitor dielectric film (40). The lower interface electrode film (34) is disposed between the lower insert electrode film (32) and the capacitor dielectric film (40). The capacitor structure (CS) can store charge within the capacitor dielectric film (40) by utilizing the potential difference generated between the lower electrode (30) and the upper electrode (50).

[0024] The lower electrode (30) may include a first metal element (M1). The lower electrode (30) may include a metal film formed of the first metal element (M1) or a metal nitride film formed of a nitride of the first metal element (M1).

[0025] The first metal element (M1) may include, for example, cobalt (Co), copper (Cu), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), or vanadium (V), but is not limited thereto.

[0026] The lower insert electrode membrane (32) may be placed on the lower electrode (30). The lower insert electrode membrane (32) may be placed between the lower electrode (30) and the lower interface electrode membrane (34). The lower insert electrode membrane (32) is in contact with the lower electrode (30).

[0027] The lower insert electrode membrane (32) may include an oxide of the lower electrode (30). The lower insert electrode membrane (32) may include an oxide of the first metal element (M1) or an oxynitride of the first metal element (M1). For example, the lower insert electrode membrane (32) may be formed by oxidizing the lower electrode (30).

[0028] The lower insert electrode film (32) can induce a crystalline phase of the capacitor dielectric film (40). For example, the lower insert electrode film (32) may have a rutile structure. The first metal element (M1) included in the lower electrode (30) may be a metal that can induce a crystalline phase of the capacitor dielectric film (40), such as an oxide of the first metal element (M1) or an oxynitride of the first metal element (M1). Alternatively, the oxide of the first metal element (M1) or the oxynitride of the first metal element (M1) may have a rutile structure.

[0029] For example, the lower insert electrode membrane (32) may include an oxide of a first metal element (M1) having a rutile structure. For another example, the lower insert electrode membrane (32) may include an oxynitride of a first metal element (M1) having a rutile structure.

[0030] The lower interface electrode film (34) can be placed on the lower insert electrode film (32). The lower interface electrode film (34) can be in contact with the lower insert electrode film (32).

[0031] The lower interface electrode film (34) may include a second metal element (M2) different from the first metal element (M1) included in the lower electrode (30). For example, the lower interface electrode film (34) may include an oxide of the second metal element (M2). The second metal element (M2) may include, for example, one of cobalt (Co), molybdenum (Mo), niobium (Nb), tin (Sn), tantalum (Ta), titanium (Ti), or vanadium (V), but is not limited thereto.

[0032] The lower interface electrode film (34) can induce a crystalline phase of the capacitor dielectric film (40). For example, the lower interface electrode film (34) may have a rutile structure. The oxide of the second metal element (M2) may have a rutile structure. The lower interface electrode film (34) may include an oxide of the second metal element (M2) having a rutile structure.

[0033] In some cases, the lower interface electrode film (34) may include a first dopant element. The first dopant element included in the lower interface electrode film (34) may be different from the second metal element (M2). The lower interface electrode film (34) may include an oxide of the second metal element (M2) doped with the first dopant element.

[0034] For example, the first dopant element may include at least one of niobium (Nb), tin (Sn), or tantalum (Ta). The lower interface electrode film (33) may include the first dopant element at a concentration of 5 at.% (atomic percent) or less.

[0035] If the content of the first dopant element exceeds 5 at.%, the crystallinity of the lower interface electrode film (34) may be weakened. In other words, in at least a portion of the lower interface electrode film (34), the rutile structure of the lower interface electrode film (34) may be broken.

[0036] For example, the thickness (t1) of the lower insert electrode film (32) may be greater than or equal to the thickness (t2) of the lower interface electrode film (34). If the thickness (t2) of the lower interface electrode film (34) is greater than the thickness (t1) of the lower insert electrode film (32), the crystallinity induction of the capacitor dielectric film (40) may be weakened.

[0037] The capacitor dielectric film (40) can be placed on the lower interface electrode film (34). The capacitor dielectric film (40) is placed between the lower interface electrode film (34) and the upper electrode (50). The capacitor dielectric film (40) can be in contact with the lower interface electrode film (34).

[0038] The capacitor dielectric film (40) may include a third metal element (M3) different from the second metal element (M2) included in the lower interface electrode film (34). For example, the capacitor dielectric film (40) may include an oxide of the third metal element (M3).

[0039] The capacitor dielectric film (40) may include an oxide of a crystalline third metal element (M3). The capacitor dielectric film (40) may include a crystalline metal oxide. For example, the capacitor dielectric film (40) may have a tetragonal crystal system. The capacitor dielectric film (40) may include an oxide of a third metal element (M3) having a tetragonal crystal system.

[0040] The third metal element (M3) may include, for example, at least one of zirconium (Zr), hafnium (Hf), titanium (Ti), or strontium (Sr). For example, the capacitor dielectric film (40) may include one of zirconium oxide, hafnium oxide, titanium oxide, or strontium-titanium oxide, but is not limited thereto. The oxide of the third metal element (M3) may have a tetragonal crystal structure.

[0041] For example, the capacitor dielectric film (40) may have a rutile structure included in a tetragonal crystal system. The capacitor dielectric film (40) may include an oxide of a third metal element (M3) having a rutile structure.

[0042] In FIGS. 1 and 3, the capacitor dielectric film (40) may include a crystal plane (40_CXP) grown in the crystal direction (40_CXD). The capacitor dielectric film (40) may include at least one crystal grain. Each crystal grain included in the capacitor dielectric film (40) may include a crystal plane (40_CXP) grown in the crystal direction (40_CXD).

[0043] The crystal plane (40_CXP) of the capacitor dielectric film may be the preferred growth crystal plane of the capacitor dielectric film (40). The crystal direction (40_CXD) of the capacitor dielectric film may be the direction in which the preferred growth crystal plane of the capacitor dielectric film (40) is grown. For example, on the lower electrode (30), the preferred growth crystal plane of the capacitor dielectric film (40) may be the (110) plane. In other words, on the lower electrode (30), the direction in which the capacitor dielectric film (40) is preferentially grown may be the

[0110] direction.

[0044] Each crystal grain included in the capacitor dielectric film (40) may include crystal planes. In a semiconductor device according to embodiments of the present invention, each crystal grain included in the capacitor dielectric film (40) may include a (110) plane grown in the

[0110] direction, which is the primary growth direction. Alternatively, the capacitor dielectric film (40) may include crystal grains comprising oxide crystals of a third metal element (M3) grown in the

[0110] direction.

[0045] In some cases, the capacitor dielectric film (40) may include a second dopant element. The second dopant element included in the capacitor dielectric film (40) may be different from the third metal element (M3). The capacitor dielectric film (40) may include an oxide of the third metal element (M3) doped with the second dopant element.

[0046] For example, the second dopant element may include at least one of aluminum (Al), barium (Ba), beryllium (Be), germanium (Ge), magnesium (Mg), niobium (Nb), silicon (Si), tantalum (Ta), or yttrium (Y), but is not limited thereto.

[0047] The capacitor dielectric film (40) is shown as a single film, but is not limited thereto.

[0048] The upper electrode (50) may be disposed on the capacitor dielectric film (40). The upper electrode (50) may include a conductive material. For example, the upper electrode (50) may include a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, molybdenum nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, niobium, nickel, copper, molybdenum or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide, molybdenum oxide, etc.), but is not limited thereto.

[0049] By placing a lower insert electrode film (32) and a lower interface electrode film (34) having a rutile structure between the lower electrode (30) and the capacitor dielectric film (40), the capacitor dielectric film (40) may include crystal grains having a tetragonal crystal structure. The metal oxide included in the capacitor dielectric film (40) may have various structures. However, since the lower insert electrode film (32) and the lower interface electrode film (34) having a rutile structure induce crystallinity and a crystal structure of the capacitor dielectric film (40), the capacitor dielectric film (40) may have a crystal structure and crystallinity with a higher dielectric constant. Through this, the performance and reliability of the semiconductor device can be improved.

[0050] FIG. 4 is a schematic layout of a semiconductor device according to some embodiments. FIG. 5 is a layout showing only the word line and cell active region of FIG. 4. FIG. 6 is an exemplary cross-sectional view cut along A-A of FIG. 4. FIG. 7 is an exemplary cross-sectional view cut along B-B of FIG. 4. FIG. 8 is an enlarged view of section Q of FIG. 6. FIG. 9 is a plan view cut along C-C of FIG. 6. FIG. 10 and FIG. 11 are enlarged views of sections R1 and R2 of FIG. 9. For convenience of explanation, parts that overlap with those described using FIG. 1 to 3 are briefly described or omitted.

[0051] For reference, FIGS. 10 and FIGS. 11 may be drawings for illustrating the crystal plane and crystal growth direction of one of the crystal grains included in the first capacitor dielectric film.

[0052] In the drawings relating to a semiconductor device according to some embodiments, a Dynamic Random Access Memory (DRAM) is illustrated as an example, but is not limited thereto.

[0053] Referring to FIGS. 4 and FIGS. 5, a semiconductor device according to some embodiments may include a plurality of cell active regions (ACTs).

[0054] The cell active region (ACT) can be defined by a cell device isolation film (105) formed within the second substrate (100 in FIG. 6). As the design rules of the semiconductor device are reduced, the cell active region (ACT) can be arranged in the form of a bar of a diagonal line or oblique line as illustrated. For example, the cell active region (ACT) can extend in a third direction (DR3).

[0055] A plurality of gate electrodes may be arranged extending in a first direction (DR1) across the cell active region (ACT). The plurality of gate electrodes may be arranged parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines (WL). The word lines (WL) may be arranged at equal intervals. The width of the word lines (WL) or the spacing between the word lines (WL) may be determined according to design rules.

[0056] Each cell active area (ACT) can be divided into three parts by two word lines (WL) extending in the first direction (DR1). The cell active area (ACT) may include a storage connection area (103b) and a bit line connection area (103a). The bit line connection area (103a) may be located in the middle part of the cell active area (ACT), and the storage connection area (103b) may be located at the end of the cell active area (ACT).

[0057] For example, the bit line connection area (103a) may be an area connected to the bit line (BL), and the storage connection area (103b) may be an area connected to the first capacitor structure (190 in FIG. 6). Alternatively, the bit line connection area (103a) may correspond to a common drain area, and the storage connection area (103b) may correspond to a source area. Each word line (WL) and the adjacent bit line connection area (103a) and storage connection area (103b) may form a transistor.

[0058] A plurality of bit lines (BL) extending in a second direction (DR2) orthogonal to the word line (WL) may be arranged on the word line (WL). The plurality of bit lines (BL) may extend parallel to each other. The bit lines (BL) may be arranged at equal intervals. The width of the bit lines (BL) or the spacing between the bit lines (BL) may be determined according to design rules.

[0059] The fourth direction (DR4) may be orthogonal to the first direction (DR1), the second direction (DR2), and the third direction (DR3). The fourth direction (DR4) may be the thickness direction of the substrate (100).

[0060] A semiconductor memory device according to some embodiments may include various contact arrays formed on a cell active region (ACT). The various contact arrays may include, for example, a direct contact (DC), a buried contact (BC), and a landing pad (LP).

[0061] Here, the direct contact (DC) may refer to a contact that electrically connects the cell active region (ACT) to the bit line (BL). The buried contact (BC) may be a connection pad that connects the cell active region (ACT) to the lower electrode (191 in FIG. 6) of the first capacitor structure. Due to the arrangement structure, the contact area between the buried contact (BC) and the cell active region (ACT) may be small. Accordingly, a conductive landing pad (LP) may be introduced to expand the contact area with the cell active region (ACT) and to expand the contact area with the lower electrode (191) of the first capacitor structure.

[0062] In a semiconductor device according to some embodiments, a landing pad (LP) may be placed between a buried contact (BC) and a lower electrode (191) of a first capacitor structure. By expanding the contact area through the introduction of the landing pad (LP), the contact resistance between the cell active region (ACT) and the lower electrode (191) of the first capacitor structure may be reduced.

[0063] The direct contact (DC) can be connected to the bit line connection area (103a). The buried contact (BC) can be connected to the storage connection portion (103b).

[0064] As the buried contact (BC) is positioned at both ends of the cell active region (ACT), the landing pad (LP) may be positioned adjacent to both ends of the cell active region (ACT) and partially overlap with the buried contact (BC). Alternatively, the buried contact (BC) may be formed to overlap with the cell active region (ACT) and the cell device separator (105 in FIG. 6) located between adjacent word lines (WL) and between adjacent bit lines (BL).

[0065] The word line (WL) can be formed as a structure embedded within the second substrate (100 in FIG. 6). The word line (WL) can be positioned across the cell active region (ACT) between the direct contact (DC) or the embedded contact (BC). As illustrated, two word lines (WL) can be positioned to cross one cell active region (ACT). As the cell active region (ACT) extends along the third direction (DR3), the word line (WL) can have an angle of less than 90 degrees with the cell active region (ACT).

[0066] Direct contacts (DC) and buried contacts (BC) can be arranged symmetrically. As a result, direct contacts (DC) and buried contacts (BC) can be arranged in a straight line along the first direction (DR1) and the second direction (DR2). Meanwhile, unlike direct contacts (DC) and buried contacts (BC), landing pads (LP) can be arranged in a zigzag shape in the second direction (DR2) where the bit line (BL) extends. Additionally, landing pads (LP) can be arranged to overlap with the same side portion of each bit line (BL) in the first direction (DR1) where the word line (WL) extends.

[0067] For example, each landing pad (LP) of the first line may overlap with the left side of the corresponding beat line (BL), and each landing pad (LP) of the second line may overlap with the right side of the corresponding beat line (BL).

[0068] Referring to FIGS. 4 to 11, a semiconductor device according to some embodiments may include a plurality of cell gate structures (110), a plurality of bit line structures (140ST), a plurality of storage contacts (120), a plurality of bit line contacts (146), and a first capacitor structure (190).

[0069] The second substrate (100) may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the second substrate (100) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0070] The cell device isolation layer (105) can be formed within the second substrate (100). The cell device isolation layer (105) may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell device isolation layer (105) may define a cell active region (ACT) within the memory cell region.

[0071] The cell active region (ACT) defined by the cell device separator (105) may have a long island formation including a short axis and a long axis as illustrated in FIGS. 4 and 5. The cell active region (ACT) may have a diagonal shape having an angle of less than 90 degrees with respect to the word line (WL) formed within the cell device separator (105). Additionally, the cell active region (ACT) may have a diagonal shape having an angle of less than 90 degrees with respect to the bit line (BL) formed on the cell device separator (105).

[0072] The cell element separator (105) may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but is not limited thereto.

[0073] Although the cell element separator (105) is depicted as being formed as a single insulating film, this is for convenience of explanation only and is not limited thereto. Depending on the distance between adjacent cell active regions (ACTs), the cell element separator (105) may be formed as a single insulating film or as a plurality of insulating films.

[0074] Although the upper surface (105US) of the cell element separator and the upper surface of the second substrate (100) are depicted as being on the same plane, this is for convenience of explanation only and is not limited thereto.

[0075] A cell gate structure (110) may be disposed within a second substrate (100) and a cell device isolation layer (105). The cell gate structure (110) may be formed across the cell device isolation layer (105) and the cell active region (ACT) defined by the cell device isolation layer (105).

[0076] The cell gate structure (110) may include a cell gate trench (115), a cell gate insulating film (111), a cell gate electrode (112), a cell gate capping pattern (113), and a cell gate capping conductive film (114).

[0077] Here, the cell gate electrode (112) may correspond to the word line (WL). For example, the cell gate electrode (112) may be the word line (WL) of FIG. 4. Unlike what is shown, the cell gate structure (110) may not include a cell gate capping conductive film (114).

[0078] Although not illustrated, the cell gate trench (115) may be relatively deep within the cell device separator (105) and relatively shallow within the cell active regions (ACTs). The bottom surface of the word line (WL) may be curved. That is, the depth of the cell gate trench (115) in the cell device separator (105) may be greater than the depth of the cell gate trench (115) in the cell active region (ACT).

[0079] The cell gate insulating film (111) may extend along the sidewalls and bottom surface of the cell gate trench (115). The cell gate insulating film (111) may extend along the profile of at least a portion of the cell gate trench (115).

[0080] The cell gate insulating film (111) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. High dielectric constant materials may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0081] The cell gate electrode (112) can be placed on the cell gate insulating film (111). The cell gate electrode (112) can fill a portion of the cell gate trench (115). The cell gate capping conductive film (114) can extend along the upper surface of the cell gate electrode (112).

[0082] The cell gate electrode (112) may include at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a conductive metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode (112) may include, for example, TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrO, RuO, or a combination thereof, but is not limited thereto.

[0083] The cell gate capping conductive film (114) may include, for example, one of polysilicon, polysilicon-germanium, amorphous silicon, or amorphous silicon-germanium, but is not limited thereto.

[0084] A cell gate capping pattern (113) may be placed on a cell gate electrode (112) and a cell gate capping conductive film (114). The cell gate capping pattern (113) may fill the cell gate trench (115) remaining after the cell gate electrode (112) and the cell gate capping conductive film (114) are formed. Although the cell gate insulating film (111) is illustrated as extending along the sidewall of the cell gate capping pattern (113), it is not limited thereto.

[0085] The cell gate capping pattern (113) may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, or silicon oxycarbonitride.

[0086] The upper surface (113US) of the cell gate capping pattern is shown to be in the same plane as the upper surface (105US) of the cell device separator, but is not limited thereto.

[0087] Although not shown, an impurity doping region may be formed on at least one side of the cell gate structure (110). The impurity doping region may be the source / drain region of the transistor. The impurity doping region may be formed in the storage connection region (103b) and the bit line connection region (103a) of FIG. 5.

[0088] In FIG. 5, if the transistor comprising each word line (WL) and adjacent bit line connection region (103a) and storage connection region (103b) is an NMOS, the storage connection region (103b) and the bit line connection region (103a) may include at least one of doped n-type impurities, for example, phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). If the transistor comprising each word line (WL) and adjacent bit line connection region (103a) and storage connection region (103b) is a PMOS, the storage connection region (103b) and the bit line connection region (103a) may include at least one of doped p-type impurities, for example, boron (B) or gallium (Ga).

[0089] The bit line structure (140ST) may include a cell conductive line (140) and a cell line capping film (144). The cell conductive line (140) may be disposed on a second substrate (100) on which a cell gate structure (110) is formed and on a cell device isolation film (105). The cell conductive line (140) may intersect the cell device isolation film (105) and the cell active region (ACT) defined by the cell device isolation film (105). The cell conductive line (140) may be formed to intersect the cell gate structure (110). Here, the cell conductive line (140) may correspond to a bit line (BL). For example, the cell conductive line (140) may be the bit line (BL) of FIG. 4.

[0090] The cell conductive line (140) may comprise, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a two-dimensional (2D) material, or a metal. In a semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material may comprise a two-dimensional allotrope or a two-dimensional compound, and may comprise, for example, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), or tungsten disulfide (WS2), but is not limited thereto. That is, since the above-described two-dimensional materials are listed only as examples, the two-dimensional material that may be included in the semiconductor device of the present invention is not limited by the above-described material.

[0091] Although the cell conductive line (140) is depicted as a single film, this is for convenience of explanation only and is not limited thereto. That is, unlike what is depicted, the cell conductive line (140) may include multiple conductive films in which conductive materials are stacked.

[0092] A cell line capping film (144) may be disposed on a cell conductive line (140). The cell line capping film (144) may extend in a second direction (DR2) along the upper surface of the cell conductive line (140). The cell line capping film (144) may comprise, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride.

[0093] In a semiconductor device according to some embodiments, the cell line capping film (144) may comprise silicon nitride. The cell line capping film (144) is depicted as a single film, but is not limited thereto.

[0094] The bit line spacer (150) can be placed on the sidewalls of the cell conduction line (140) and the cell line capping film (144). The bit line spacer (150) extends in a second direction (DR2).

[0095] Although the bit line spacer (150) is depicted as a single film, this is for convenience of explanation only and is not limited thereto. That is, unlike what is depicted, the bit line spacer (150) can have a multi-film structure. The bit line spacer (150) may include, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), air, or a combination thereof, but is not limited thereto.

[0096] The lower cell insulating film (135) may be disposed on the second substrate (100) and the cell element separator (105). More specifically, the lower cell insulating film (135) may be disposed on the upper surface (105US) of the second substrate (100) and the cell element separator where the bit line contact (146) and the storage contact (120) are not formed. The lower cell insulating film (135) may be disposed between the second substrate (100) and the cell conductive line (140), and between the cell element separator (105) and the cell conductive line (140).

[0097] The lower cell insulating film (135) may be a single film, but as illustrated, the lower cell insulating film (135) may be a multi-film comprising a first lower cell insulating film (136) and a second lower cell insulating film (137). For example, the first lower cell insulating film (136) may comprise silicon oxide and the second lower cell insulating film (137) may comprise silicon nitride, but is not limited thereto. Unlike illustrated, the lower cell insulating film (135) may be a triple film comprising silicon oxide, silicon nitride, and silicon oxide, but is not limited thereto.

[0098] A bit line contact (146) can be placed between the cell conduction line (140) and the second substrate (100). The cell conduction line (140) can be placed on the bit line contact (146).

[0099] A bit line contact (146) can be placed between the bit line connection area (103a) of the cell active area (ACT) and the cell conduction line (140). The bit line contact (146) can be connected to the bit line connection area (103a).

[0100] The bit line contact (146) may include an upper surface (146US) connected to the cell conduction line (140). Although the width of the bit line contact (146) in the first direction (DR1) is depicted as constant as it moves away from the upper surface (146US) of the bit line contact, this is for convenience of explanation only and is not limited thereto.

[0101] The bit line contact (146) can electrically connect the cell conductive line (140) and the second substrate (100). Here, the bit line contact (146) may correspond to a direct contact (DC). The bit line contact (146) may include, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, or a metal.

[0102] In the portion of the cell conductive line (140) where the bit line contact (146) is formed, the bit line spacer (150) may be disposed on the second substrate (100) and the cell device separator (105). The bit line spacer (150) may be disposed on the sidewalls of the cell conductive line (140), the cell line capping film (144), and the bit line contact (146).

[0103] In the remainder of the cell conductive line (140) where the bit line contact (146) is not formed, a bit line spacer (150) may be placed on the lower cell insulating film (135). The bit line spacer (150) may be placed on the sidewalls of the cell conductive line (140) and the cell line capping film (144).

[0104] A fence pattern (170) may be disposed on the second substrate (100) and the cell device separator (105). The fence pattern (170) may be formed to overlap with a cell gate structure (110) formed within the second substrate (100) and the cell device separator (105).

[0105] The fence pattern (170) may be placed between bit line structures (140ST) extending in the second direction (DR2). The fence pattern (170) may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0106] A storage contact (120) may be placed between adjacent cell conduction lines (140) in a first direction (DR1). A storage contact (120) may be placed on both sides of the cell conduction lines (140). More specifically, a storage contact (120) may be placed between bit line structures (140ST). A storage contact (120) may be placed between adjacent fence patterns (170) in a second direction (DR2).

[0107] The storage contact (120) may overlap with the second substrate (100) and the cell device isolation film (105) between adjacent cell conduction lines (140). The storage contact (120) may be connected to the cell active region (ACT). More specifically, the storage contact (120) may be connected to the storage connection portion (103b). Here, the storage contact (120) may correspond to the buried contact (BC) of FIG. 4.

[0108] The storage contact (120) may include, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a conductive metal oxide, or a metal.

[0109] A storage pad (160) may be placed on a storage contact (120). The storage pad (160) may be electrically connected to the storage contact (120). The storage pad (160) may be connected to a storage connection portion (103b) of a cell active area (ACT). Here, the storage pad (160) may correspond to a landing pad (LP).

[0110] The storage pad (160) may overlap with a portion of the upper surface of the bit line structure (140ST). The storage pad (160) may include, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, or a metal.

[0111] The pad isolation insulating layer (180) may be placed on the storage pad (160) and the bit line structure (140ST). For example, the pad isolation insulating layer (180) may be placed on the cell line capping layer (144). The pad isolation insulating layer (180) may define a storage pad (160) that forms a plurality of isolated regions.

[0112] The pad separation insulating layer (180) does not cover the upper surface (160US) of the storage pad. The pad separation insulating layer (180) may fill the pad separation recess. The pad separation recess may separate adjacent storage pads (160). For example, the upper surface (160US) of the storage pad may lie on the same plane as the upper surface (180US) of the pad separation insulating layer, but is not limited thereto.

[0113] The pad separation insulating film (180) comprises an insulating material and can electrically separate a plurality of storage pads (160) from each other. For example, the pad separation insulating film (180) may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, but is not limited thereto.

[0114] The first etch stop layer (196) may be disposed on the upper surface (160US) of the storage pad and the upper surface (180US) of the pad separation insulating layer. The first etch stop layer (196) may include, for example, at least one of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbonitride, or silicon boronitride.

[0115] The first capacitor structure (190) may be placed on the storage pad (160). The first capacitor structure (190) may be electrically connected to the storage pad (160). A portion of the first capacitor structure (190) may be placed within the first etch stop layer (196).

[0116] The first capacitor structure (190) may include a first lower electrode (191), a first lower insertion electrode film (192), a first lower interface electrode film (193), a first capacitor dielectric film (194), and a first upper electrode (195).

[0117] The first lower insertion electrode film (192), the first lower interface electrode film (193), and the first capacitor dielectric film (194) are disposed between the first lower electrode (191) and the first upper electrode (195). The first lower insertion electrode film (192) and the first lower interface electrode film (193) are disposed between the first lower electrode (191) and the first capacitor dielectric film (194). The first lower interface electrode film (193) is disposed between the first lower insertion electrode film (192) and the first capacitor dielectric film (194).

[0118] The first lower electrode (191) may be connected to the storage pad (160). For example, the first lower electrode (191) may be in contact with at least a portion of the upper surface (160US) of the storage pad exposed by the first etch stop layer (196). In FIG. 6, the first lower electrode (191) is shown as being in the form of a pillar extending in the fourth direction (DR4) from the upper surface (160US) of the storage pad, but this is merely exemplary. As another example, the first lower electrode (191) may be in the form of a cylinder extending in the fourth direction (DR4) from the upper surface (160US) of the storage pad.

[0119] At least one support pattern (60, 65) may be placed on the first etch stop film (196). At least one support pattern (60, 65) may support the first lower electrode (191).

[0120] For example, a plurality of support patterns (60, 65) may be disposed on the first etch stop layer (196). The plurality of support patterns (60, 65) may include a first support pattern (60) and a second support pattern (65) disposed sequentially on the first etch stop layer (196).

[0121] The first support pattern (60) and the second support pattern (65) may be spaced apart from the first etch stop film (196) in a fourth direction (DR4). The first support pattern (60) and the second support pattern (65) may be spaced apart from each other in a fourth direction (DR4).

[0122] The first support pattern (60) and the second support pattern (65) may each come into contact with a part of the first lower electrode (191). The first support pattern (60) and the second support pattern (65) may each come into contact with the side wall of the first lower electrode (191). Although the number of support patterns in contact with the first lower electrode (191) is shown as two, this is for convenience of explanation only and is not limited thereto.

[0123] To explain using the second support pattern (65) as an example, the second support pattern (65) may include a first surface (65_S1) and a second surface (65_S2) opposite in the fourth direction (DR4). The second surface (65_S2) of the second support pattern may face the cell conduction line (140). The second support pattern (65) may include a side wall (65_SS) connecting the first surface (65_S1) and the second surface (65_S2) of the second support pattern. The side wall (65_SS) of the second support pattern may come into contact with the first lower electrode (191). As with the second support pattern (65) described above, the first support pattern (60) may include a first surface, a second surface, and a side wall.

[0124] The first support pattern (60) and the second support pattern (65) may each include, for example, at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, or silicon oxycarbonitride.

[0125] The first lower insert electrode membrane (192) may be placed on the first lower electrode (191). The first lower insert electrode membrane (192) is in contact with the first lower electrode (191).

[0126] Since the first lower insert electrode film (192) is formed by oxidizing the first lower electrode (191), the first lower insert electrode film (192) is not placed on the first supporter pattern (60) and the second supporter pattern (65). For example, the first lower insert electrode film (192) is not placed on the first surface of the first supporter pattern (60), the second surface of the first supporter pattern (60), the first surface (65_S1) of the second supporter pattern, and the second surface (65_S2) of the second supporter pattern. The first lower insert electrode film (192) is not placed on the upper surface of the first etch stop film (196).

[0127] The first lower interface electrode film (193) may be disposed on the first lower electrode (191), the first supporter pattern (60), and the second supporter pattern (65). The first lower interface electrode film (193) may be disposed on the first lower insert electrode film (192).

[0128] The first lower interface electrode film (193) may extend along the sidewall and upper surface of the first lower electrode (191). The first lower interface electrode film (193) may extend along the first surface of the first supporter pattern (60), the second surface of the first supporter pattern (60), the first surface (65_S1) of the second supporter pattern, and the second surface (65_S2) of the second supporter pattern. The first lower interface electrode film (193) may extend along the upper surface of the first etch stop film (196).

[0129] The first lower interface electrode film (193) can be in contact with the first lower insert electrode film (192). The first lower interface electrode film (193) can be in contact with the first supporter pattern (60), the second supporter pattern (65), and the first etch stop film (196).

[0130] The first capacitor dielectric film (194) may be disposed on the first lower interface electrode film (193). The first capacitor dielectric film (194) may extend along the profile of the first lower interface electrode film (193). The first capacitor dielectric film (194) may be in contact with the first lower interface electrode film (193).

[0131] For example, the first capacitor dielectric film (194) may extend along the first surface of the first supporter pattern (60), the second surface of the first supporter pattern (60), the first surface (65_S1) of the second supporter pattern, and the second surface (65_S2) of the second supporter pattern.

[0132] The first lower insert electrode film (192), the first lower interface electrode film (193), and the first capacitor dielectric film (194) may be disposed on the sidewall and upper surface of the first lower electrode (191). The first lower interface electrode film (193) and the first capacitor dielectric film (194) may be disposed on the first surface of the first supporter pattern (60), the second surface of the first supporter pattern (60), the first surface (65_S1) of the second supporter pattern, and the second surface (65_S2) of the second supporter pattern.

[0133] The first upper electrode (195) may be placed on the first capacitor dielectric film (194). The first upper electrode (195) may fill the space between adjacent first lower electrodes (191). The first upper electrode (195) may fill the space between the first supporter pattern (60) and the second supporter pattern (65), and between the first supporter pattern (60) and the first etch stop film (196).

[0134] The first capacitor structure (190) may correspond to the capacitor structure (CS) described above using FIGS. 1 to 3. The first lower electrode (191), the first lower insert electrode film (192), the first lower interface electrode film (193), the first capacitor dielectric film (194), and the first upper electrode (195) may correspond to the lower electrode (30), the lower insert electrode film (32), the lower interface electrode film (34), the capacitor dielectric film (40), and the upper electrode (50), respectively. The material and crystal structure included in the first lower electrode (191), the first lower insert electrode film (192), the first lower interface electrode film (193), the first capacitor dielectric film (194), and the first upper electrode (195) may be substantially the same as the lower electrode (30), the lower insert electrode film (32), the lower interface electrode film (34), the capacitor dielectric film (40), and the upper electrode (50) described above.

[0135] In FIGS. 9 to 11, the first lower insert electrode film (192), the first lower interface electrode film (193), and the first capacitor dielectric film (194) may be sequentially arranged along the perimeter of the first lower electrode (191). The first capacitor dielectric film (194) may include a plurality of crystal grains. Different crystal grains may appear in the R1 portion of FIG. 9 and the R2 portion of FIG. 9.

[0136] Each crystal grain included in the first capacitor dielectric film (194) may include a crystal plane (194_CXP) grown in the crystal direction (194_CXD). The crystal plane (194_CXP) of the first capacitor dielectric film may be the crystal plane of the first capacitor dielectric film (194). The crystal direction (194_CXD) of the first capacitor dielectric film may be the direction in which the crystal plane of the first capacitor dielectric film (194) is grown. On the first lower electrode (191), the crystal plane of the first capacitor dielectric film (194) may be the (110) plane. Each crystal grain included in the first capacitor dielectric film (194) may include a (110) plane grown in the

[0110] direction, which is the crystal plane of the first capacitor dielectric film (194).

[0137] FIG. 12 is a drawing for illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 4 to FIG. 11.

[0138] Referring to FIG. 12, in a semiconductor device according to some embodiments, a node connection pad (125) may be placed at a storage contact (120).

[0139] A node connection pad (125) may be placed on the second substrate (100). The node connection pad (125) may be placed on the storage connection area (103b) of the cell active area (ACT). The node connection pad (125) is connected to the storage connection area (103b).

[0140] With respect to the upper surface (105US) of the cell element separator, the upper surface (125US) of the node connection pad may be lower than the upper surface (146US) of the bit line contact. With respect to the upper surface (105US) of the cell element separator, the upper surface (125US) of the node connection pad may be lower than the bottom surface of the cell conduction line (140).

[0141] The node connection pad (125) can electrically connect the first capacitor structure (190) and the second substrate (100). Here, the node connection pad (125) can correspond to the node pad (XP) of FIG. 4.

[0142] The node connection pad (125) may include, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, or a metal.

[0143] The pad separation structure (145ST) can separate adjacent node connection pads (125) in a first direction (DR1). Although not illustrated, the pad separation structure (145ST) can separate adjacent node connection pads (125) in a second direction (DR2). The pad separation structure (145ST) can cover the upper surface (125US) of the node connection pads.

[0144] The pad separation structure (145ST) may include a pad separation pattern (145) and an upper cell insulating film (130). The upper cell insulating film (130) may be placed on the pad separation pattern (145).

[0145] When the node connection pad (125) includes a first node connection pad and a second node connection pad spaced apart in a first direction (DR1), the pad separation pattern (145) can separate the first node connection pad and the second node connection pad in the first direction (DR1). Although not illustrated, the pad separation pattern (145) can also separate adjacent node connection pads (125) in a second direction (DR2).

[0146] The upper cell insulating film (130) can cover the upper surface (125US) of the node connection pad. When the node connection pad (125) includes a first node connection pad and a second node connection pad spaced apart in a first direction (DR1), the upper cell insulating film (130) can cover the upper surface of the first node connection pad and the upper surface of the second node connection pad.

[0147] The upper surface (130US) of the upper cell insulating film may be placed on the same plane as the upper surface (146US) of the bit line contact. That is, with respect to the upper surface (105US) of the cell element separator, the height of the upper surface (130US) of the upper cell insulating film may be the same as the height of the upper surface (146US) of the bit line contact.

[0148] The cell conduction line (140) may be placed on the upper surface of the pad separation structure (145ST). The cell conduction line (140) may be placed on the upper surface (130US) of the upper cell insulating film. The upper surface of the pad separation structure (145ST) may be the upper surface (130US) of the upper cell insulating film. The upper surface of the pad separation structure (145ST) may be placed coplanar with the bottom surface of the cell conduction line (140). Although not illustrated, the pad separation pattern (145) and the upper cell insulating film (130) may be placed between adjacent bit line contacts (146) in the second direction (DR2).

[0149] The pad separation pattern (145) may include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a combination thereof. The upper cell insulating film (130) may be a single film, but as illustrated, the upper cell insulating film (130) may be a multi-film comprising a first upper cell insulating film (131) and a second upper cell insulating film (132). For example, the first upper cell insulating film (131) may include a silicon oxide film and the second upper cell insulating film (132) may include a silicon nitride film, but is not limited thereto. The width of the upper cell insulating film (130) in the first direction (DR1) is illustrated as decreasing as it moves away from the second substrate (100), but is not limited thereto.

[0150] A storage pad (160) can be placed on each node connection pad (125). The storage pad (160) can be electrically connected to the node connection pad (125).

[0151] FIG. 13 is a layout diagram illustrating a semiconductor device according to some embodiments. FIG. 14 is a perspective view illustrating the semiconductor device of FIG. 13. FIG. 15 is a cross-sectional view taken along D-D and E-E of FIG. 13. FIG. 16 is an enlarged view illustrating section S of FIG. 15.

[0152] Referring to FIGS. 13 to 16, a semiconductor device according to some embodiments may include a second substrate (100), a plurality of first conductive lines (220), a channel layer (230), a gate electrode (240), a gate insulating film (250), and a second capacitor structure (290).

[0153] A semiconductor device according to some embodiments may be a memory device comprising a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (230) extends along a vertical direction (fourth direction (DR4)) from the second substrate (100).

[0154] A first lower insulating film (212) may be disposed on the second substrate (100). A plurality of first conductive lines (220) may be spaced apart from each other in a first direction (DR1) and extended in a second direction (DR2) on the first lower insulating film (212). A plurality of first insulating patterns (222) may be disposed on the first lower insulating film (212) to fill the space between the plurality of first conductive lines (220). The plurality of first insulating patterns (222) may be extended in the second direction (DR2). The upper surface of the plurality of first insulating patterns (222) may be disposed at the same level as the upper surface of the plurality of first conductive lines (220). The plurality of first conductive lines (220) may function as bit lines (BL).

[0155] A plurality of first conductive lines (220) may comprise a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (220) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, but are not limited thereto. A plurality of first conductive lines (220) may comprise a single layer or a multilayer of the aforementioned materials. In exemplary embodiments, a plurality of first conductive lines (220) may comprise graphene, a carbon nanotube, or a combination thereof.

[0156] The channel layer (230) may be arranged in a matrix form spaced apart in a first direction (DR1) and a second direction (DR2) on a plurality of first conductive lines (220). The channel layer (230) may have a first width according to the first direction (DR1) and a first height according to the fourth direction (DR4), and the first height may be greater than the first width. Here, the fourth direction (DR4) may be, for example, a direction perpendicular to the upper surface of the second substrate (100). For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. Although not illustrated, the bottom portion of the channel layer (230) functions as a first source / drain region, the upper portion of the channel layer (230) functions as a second source / drain region, and a portion of the channel layer (230) between the first and second source / drain regions may function as a channel region.

[0157] For example, the channel layer (230) may include an oxide semiconductor, and for example, the oxide semiconductor is Inx Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yIt may include O or a combination thereof. The channel layer (230) may include a single layer or a multilayer of the oxide semiconductor. In some examples, the channel layer (230) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (230) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer (230) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer (230) may be polycrystalline or amorphous, but is not limited thereto. As another example, the channel layer (230) may include graphene, carbon nanotubes, or a combination thereof. As yet another example, the channel layer (230) may include a silicon-based semiconductor material. The channel layer (230) may include a single-crystal semiconductor material, for example, single-crystal silicon or single-crystal silicon-germanium, but is not limited thereto.

[0158] The gate electrode (240) may extend in a first direction (DR1) on both sidewalls of the channel layer (230). The gate electrode (240) may include a first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230) and a second sub-gate electrode (240P2) facing the second sidewall opposite the first sidewall of the channel layer (230). As one channel layer (230) is disposed between the first sub-gate electrode (240P1) and the second sub-gate electrode (240P2), the semiconductor device may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (240P2) and forming only the first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230). The gate electrode (240) can function as a word line (WL) of the memory cell. The material contained in the gate electrode (240) may be the same as described for the cell gate electrode (112).

[0159] The gate insulating film (250) surrounds the sidewalls of the channel layer (230) and may be interposed between the channel layer (230) and the gate electrode (240). For example, as shown in FIG. 13, the entire sidewall of the channel layer (230) may be surrounded by the gate insulating film (250), and a portion of the sidewall of the gate electrode (240) may be in contact with the gate insulating film (250). In other embodiments, the gate insulating film (250) may extend in the extension direction of the gate electrode (240) (i.e., the first direction (DR1)), and only two sidewalls of the channel layer (230) facing the gate electrode (240) may be in contact with the gate insulating film (250). In exemplary embodiments, the gate insulating film (250) may be made of silicon oxide, silicon oxynitride, a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0160] A plurality of second insulation patterns (232) may be extended along a second direction (DR2) on a plurality of first insulation patterns (222). A channel layer (230) may be disposed between two adjacent second insulation patterns (232) among the plurality of second insulation patterns (232). Additionally, between two adjacent second insulation patterns (232), a first filling layer (234) and a second filling layer (236) may be disposed in the space between two adjacent channel layers (230). The first filling layer (234) may be disposed at the bottom of the space between two adjacent channel layers (230). The second filling layer (236) may be formed on the first filling layer (234) to fill the remainder of the space between two adjacent channel layers (230). The upper surface of the second buried layer (236) is positioned at the same level as the upper surface of the channel layer (230), and the second buried layer (236) can cover the upper surface of the gate electrode (240). Alternatively, a plurality of second insulating patterns (232) may be formed as a material layer continuous with a plurality of first insulating patterns (222), or the second buried layer (236) may be formed as a material layer continuous with the first buried layer (234).

[0161] A capacitor contact (260) may be disposed on the channel layer (230). The capacitor contact (260) may be arranged in a matrix form that is vertically overlapped with the channel layer (230) and spaced apart in a first direction (DR1) and a second direction (DR2). The capacitor contact (260) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO, RuO, or a combination thereof, but is not limited thereto. An upper insulating film (262) may surround the sidewalls of the capacitor contact (260) on a plurality of second insulating patterns (232) and a second embedded layer (236).

[0162] A second etch stop layer (270) may be disposed on the upper insulating layer (262). A second capacitor structure (290) may be disposed on the second etch stop layer (270).

[0163] The second capacitor structure (290) may include a second lower electrode (291), a second lower insert electrode film (292), a second lower interface electrode film (293), a second capacitor dielectric film (294), and a second upper electrode (295).

[0164] The second lower electrode (291) can be electrically connected to the upper surface of the capacitor contact (260) by penetrating the second etch stop layer (270). The second lower electrode (291) may be formed as a pillar type extending in the fourth direction (DR4), but is not limited thereto. In exemplary embodiments, the second lower electrode (291) may be arranged in a matrix form that is positioned to overlap vertically with the capacitor contact (260) and spaced apart in the first direction (DR1) and the second direction (DR2). Alternatively, a landing pad may be further positioned between the capacitor contact (260) and the second lower electrode (291), so that the second lower electrode (291) may be arranged in a hexagonal shape.

[0165] At least one support pattern (60, 65) may be disposed on the second etch stop film (270). At least one support pattern (60, 65) may support the second lower electrode (291). Since the description of the first support pattern (60) and the second support pattern (65) has been explained using FIGS. 4 to 12, it will be omitted below.

[0166] Unlike what is illustrated, the semiconductor device according to some embodiments may not include at least one support pattern (60, 65) supporting the sidewall of the second lower electrode (291).

[0167] The second lower insert electrode membrane (292) may be placed on the second lower electrode (291). The second lower insert electrode membrane (292) is in contact with the second lower electrode (291). The second lower insert electrode membrane (292) is not placed on the first supporter pattern (60) and the second supporter pattern (65).

[0168] The second lower interface electrode film (293) may be disposed on the second lower electrode (291), the first support pattern (60), and the second support pattern (65). The second lower interface electrode film (293) may be disposed on the second lower insert electrode film (292). The second lower interface electrode film (293) may be in contact with the second lower insert electrode film (292). The second lower interface electrode film (293) may be in contact with the first support pattern (60), the second support pattern (65), and the second etch stop film (270).

[0169] The second capacitor dielectric film (294) may be disposed on the second lower interface electrode film (293). The second capacitor dielectric film (294) may extend along the profile of the second lower interface electrode film (293). The second capacitor dielectric film (294) may be in contact with the second lower interface electrode film (293).

[0170] The second upper electrode (295) can be placed on the second capacitor dielectric film (294).

[0171] The second capacitor structure (290) may correspond to the capacitor structure (CS) described above using FIGS. 1 to 3. The second lower electrode (291), the second lower insert electrode film (292), the second lower interface electrode film (293), the second capacitor dielectric film (294), and the second upper electrode (295) may correspond to the lower electrode (30), the lower insert electrode film (32), the lower interface electrode film (34), the capacitor dielectric film (40), and the upper electrode (50), respectively. As shown in FIG. 16, the second lower insert electrode film (292), the second lower interface electrode film (293), and the second capacitor dielectric film (294) may be stacked sequentially on the second lower electrode (291).

[0172] FIG. 17 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 13 to 16.

[0173] Referring to FIG. 17, a semiconductor device according to some embodiments may further include a back gate electrode (255).

[0174] The back gate electrode (255) may be disposed between adjacent channel layers (230) in the second direction (DR2). For example, the back gate electrode (255) may be disposed within the second buried layer (236).

[0175] A voltage is applied to the back gate electrode (255) so that the threshold voltage of the vertical channel transistor can be adjusted. By adjusting the threshold voltage of the vertical channel transistor, the leakage current characteristics can be prevented from degrading.

[0176] The back gate electrode (255) includes a conductive material and may include at least one of, for example, a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material and a metal.

[0177] FIG. 18 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 19 is a perspective view for illustrating the semiconductor device of FIG. 18.

[0178] Referring to FIGS. 18 and 19, a semiconductor device according to some embodiments may include a second substrate (100), a plurality of first conductive lines (220A), a channel structure (230A), a contact gate electrode (240A), a plurality of second conductive lines (242A), and a second capacitor structure (290). A semiconductor device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0179] A plurality of active regions (ACs) may be defined in the second substrate (100) by a first device isolation pattern (212A) and a second device isolation pattern (214A). A channel structure (230A) may be disposed within each active region (AC). The channel structure (230A) may include a first active pillar (230A1) and a second active pillar (230A2) extending in a vertical direction, and a connecting portion (230L) connected to the bottom portion of the first active pillar (230A1) and the bottom portion of the second active pillar (230A2). A third source / drain region (SD1) may be disposed within the connecting portion (230L). A fourth source / drain region (SD2) may be disposed above the first and second active pillars (230A1, 230A2). The first active pillar (230A1) and the second active pillar (230A2) can each form an independent unit memory cell.

[0180] A plurality of first conductive lines (220A) may extend in a direction intersecting each of the plurality of active regions (AC), for example, in a second direction (DR2). One of the plurality of first conductive lines (220A) may be placed on a connection (230L) between a first active pillar (230A1) and a second active pillar (230A2). One first conductive line (220A) may be placed on a third source / drain region (SD1). Another first conductive line (220A) adjacent to one first conductive line (220A) may be placed between two channel structures (230A). One of the plurality of first conduction lines (220A) can function as a common bit line included in two unit memory cells formed by a first active pillar (230A1) and a second active pillar (230A2) disposed on both sides of one first conduction line (220A).

[0181] A contact gate electrode (240A) may be disposed between two adjacent channel structures (230A) in the second direction (DR2). For example, a contact gate electrode (240A) may be disposed between a first active pillar (230A1) included in one channel structure (230A) and a second active pillar (230A2) of the adjacent channel structure (230A). A contact gate electrode (240A) may be shared by the first active pillar (230A1) and the second active pillar (230A2) disposed on both side walls. A fourth gate insulating film (250A) may be disposed between the contact gate electrode (240A) and the first active pillar (230A1), and between the contact gate electrode (240A) and the second active pillar (230A2). A plurality of second conductive lines (242A) may extend in a first direction (DR1) on the upper surface of the contact gate electrode (240A). A plurality of second conductive lines (242A) may function as word lines of a memory cell.

[0182] A capacitor contact (260A) may be disposed on the channel structure (230A). The capacitor contact (260A) may be disposed on the fourth source / drain region (SD2), and a second capacitor structure (290) may be disposed on the capacitor contact (260A).

[0183] FIG. 20 is a drawing for illustrating a semiconductor device according to some embodiments. For reference, FIG. 20 may be a cross-sectional view of a semiconductor device.

[0184] Referring to FIG. 20, a semiconductor device according to some embodiments may include a second substrate (100), a lower structure (310) on the second substrate (100), a plurality of structures (LS) and a plurality of first insulating layers (321) alternately stacked on the second substrate (100), and a second conductive pattern (350).

[0185] Each of the plurality of structures (LS) may include an active layer (330) extending in a first direction (DR1), a first conductive pattern (340) extending in a second direction (DR2) perpendicular to the first direction (DR1) and intersecting the active layer (330), a gate insulating pattern (342) between the active layer (330) and the first conductive pattern (340), a gate capping layer (344) between the first conductive pattern (340) and the second conductive pattern (350), a third lower electrode (391) of the third capacitor structure (390), and a second insulating layer (322) between the first conductive pattern (340) and the third lower electrode (391).

[0186] The third capacitor structure (390) may include a third lower electrode (391), a third lower insert electrode film (392), a third lower interface electrode film (393), a third capacitor dielectric film (394), and a third upper electrode (395). The third lower insert electrode film (392), the third lower interface electrode film (393), and the third capacitor dielectric film (394) are disposed between the third lower electrode (391) and the third upper electrode (395). The third lower insert electrode film (392) and the third lower interface electrode film (393) are disposed between the third lower electrode (391) and the third capacitor dielectric film (394). The third lower interface electrode film (393) is disposed between the third lower insert electrode film (392) and the third capacitor dielectric film (394).

[0187] A lower structure (310) may be disposed on a second substrate (100). A plurality of structures (LS) and a plurality of first insulating layers (321) may be laminated on the lower structure (310). The lower structure (310) may include an element region on the second substrate (100) and an insulating region covering the element region. The insulating region may be formed of insulating layers comprising at least one of an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0188] A plurality of structures (LS) and a plurality of first insulating layers (321) may form a molded structure on a second substrate (100). A plurality of structures (LS) may be disposed between a plurality of first insulating layers (321) and may be spaced apart from each other in a fourth direction (DR4) by a plurality of first insulating layers (321). A first insulating layer (321) may extend along a first direction (DR1), and its end may extend into a second conductive pattern (350). A second insulating layer (322) may be disposed between the first insulating layer (321) and the active layer (330), and between the first conductive pattern (340) and the third capacitor structure (390). A first insulating layer (321) and a second insulating layer (322) may each include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The first insulating layer (321) may be extended horizontally longer than the second insulating layer (322). The thickness of the second insulating layer (322) may be thicker than the thickness of the first insulating layer (321).

[0189] The active layer (330) is disposed on the second substrate (100) and may extend horizontally in the first direction (DR1). The active layer (330) may be stacked in a plurality spaced apart from each other in the fourth direction (DR4) and arranged in a plurality in the second direction (DR2). The active layer (330) arranged in a plurality in the fourth direction (DR4) may be disposed between a plurality of first insulating layers (321). The active layer (330) may have a line shape, a bar shape, or a pillar shape extending in the first direction (DR1) while intersecting the first conductive pattern (340). The active layer (330) may include a semiconductor material, for example, silicon, germanium, or silicon-germanium.

[0190] The active layer (330) may include a first impurity region (330a), a second impurity region (330b), and a channel region (330c). The first impurity region (330a) may be electrically connected to the second conductivity pattern (350). The second impurity region (330b) may be electrically connected to the third lower electrode (391) of the third capacitor structure (390). The length in the first direction (DR1) of the second impurity region (330b) may be longer than the length in the first direction (DR1) of the first impurity region (330a), but is not limited thereto. The channel region (330c) may be disposed between the first impurity region (330a) and the second impurity region (330b). The channel region (330c) may overlap with the first conductivity pattern (340). The first impurity region (330a) and the second impurity region (330b) are spaced apart from each other in the horizontal direction and are placed at the same level, and the channel region (330c) may be a horizontal channel region.

[0191] The first impurity region (330a) and the second impurity region (330b) can be formed by performing a doping or ion implantation process of impurities on the active layer (330). The first impurity region (330a) and the second impurity region (330b) may contain n-type or p-type impurities.

[0192] A portion of the first impurity region (330a) may correspond to the source region of the transistor, a portion of the second impurity region (330b) may correspond to the drain region of the transistor, and a channel region (330c) may correspond to the channel of the transistor. A portion of the first impurity region (330a) may provide a first contact region for directly connecting the source region of the transistor to the second conduction pattern (350), i.e., the bit line (BL), and a portion of the second impurity region (330b) may provide a second contact region for directly connecting the drain region of the transistor to the information storage structure (DS).

[0193] In another example, the active layers (330) may comprise at least one of an oxide semiconductor, for example, hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), and indium-tin-zinc oxide (ITZO).

[0194] In another example, the active layer (330) may include a two-dimensional material (2D material) in which atoms form a predetermined crystal structure and can form a channel of a transistor. The two-dimensional material layer included in the active layer (330) may include at least one of a TMD material layer (Transition Metal Dichalcogenide material layer), a black phosphorous material layer, and an hBN material layer (hexagonal Boron-Nitride material layer). For example, the two-dimensional material layer included in the active layer (330) may include at least one of BiOSe, Crl, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials capable of forming a two-dimensional material.

[0195] The first conductive pattern (340) is placed on the second substrate (100) and can be extended horizontally in the second direction (DR2). The first conductive pattern (340) can be stacked in multiple numbers spaced apart from each other in the fourth direction (DR4) and arranged in multiple numbers in the first direction (DR1). The first conductive pattern (340) can be placed between the channel region (330c) of the active layer (330) and the first insulating layer (321). The first conductive pattern (340) can be placed on the upper and lower surfaces of the active layer (330). The first conductive pattern (340) can have a line shape, a bar shape, or a column shape that intersects the second conductive pattern (350) and extends in the second direction (DR2). Although not illustrated, a plurality of first conductive patterns (340) stacked in a fourth direction (DR4) within a single memory cell may be extended to different lengths in a second direction (DR2) to provide a contact area in which each upper surface is exposed.

[0196] The first conductive pattern (340) may include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, or a metal silicide. The first conductive pattern (340) may be a word line (WL) and may be referred to as a 'gate electrode'.

[0197] A gate insulation pattern (342) may be disposed between the first conductive pattern (340) and the active layer (330). The gate insulation pattern (342) may be formed to have a thickness substantially conformal to the inner space of a gap region formed by etching a second insulation layer (322) from the side between adjacent first insulation layers (321). The gate insulation pattern (342) may comprise silicon oxide, silicon nitride, or a high-dielectric (high-k) material.

[0198] The gate capping layer (344) may be positioned to fill an area where the first conductive pattern (340) is partially removed from the side. For example, the side of the gate capping layer (344) may be in contact with the side of the first conductive pattern (340), and the top and bottom surfaces may be covered by the gate insulating pattern (342). The gate capping layer (344) may electrically insulate the first conductive pattern (340) and the second conductive pattern (350).

[0199] The second conductive pattern (350) may be extended vertically in the fourth direction (DR4) on the second substrate (100). The second conductive pattern (350) may be arranged in multiple numbers in the second direction (DR2). The second conductive pattern (350) may be positioned adjacent to the first impurity region (330a) and the first end surface of the active layer (330). The second conductive pattern (350) may have an inclined inner surface facing the inclined sides of the first epitaxial layer (335a). Multiple active layers (330) stacked in the fourth direction (DR4) may be electrically connected to a single second conductive pattern (350). The second conductive pattern (350) may have a line shape, a bar shape, or a column shape extending in the fourth direction (DR4). Although not illustrated, the semiconductor device may further include upper wiring that is disposed on the second conductive pattern (350), connected to the second conductive pattern (350), and extends in the first direction (DR1). The second conductive pattern (350) may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, or a metal silicide.

[0200] The third capacitor structure (390) may be positioned adjacent to the second impurity region (330b) and the second end surface of the active layer (330). The third capacitor structure (390) may be electrically connected to the active layer (330). The third lower electrode (391) may have a cylinder shape, but is not limited thereto, and in the embodiments, may have a pillar shape.

[0201] The third lower electrode (391) can be formed to have a substantially conformal thickness in the inner space of the gap region formed by etching the second insulating layer (322) from the side. The third lower electrode (391) may be in a state where the nodes are separated by structures (LS) by removing the portion on the side of the first insulating layer (321) after depositing a conductive material.

[0202] The third lower insert electrode film (392), the third lower interface electrode film (393), the third capacitor dielectric film (394), and the third upper electrode (395) can be sequentially placed on the third lower electrode (391).

[0203] The third capacitor structure (390) may correspond to the capacitor structure (CS) described above using FIGS. 1 to 3. The third lower electrode (391), the third lower insert electrode film (392), the third lower interface electrode film (393), the third capacitor dielectric film (394), and the third upper electrode (395) may correspond to the lower electrode (30), the lower insert electrode film (32), the lower interface electrode film (34), the capacitor dielectric film (40), and the upper electrode (50), respectively. The material and crystal structure included in the third lower electrode (391), the third lower insert electrode film (392), the third lower interface electrode film (393), the third capacitor dielectric film (394), and the third upper electrode (395) may be substantially the same as the lower electrode (30), the lower insert electrode film (32), the lower interface electrode film (34), the capacitor dielectric film (40), and the upper electrode (50) described above.

[0204] FIGS. 21 to 24 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIGS. 1 to 3 are briefly explained or omitted.

[0205] Referring to FIG. 21, a lower insulating film (20) and a pre lower electrode (30P) can be formed on the first substrate (10).

[0206] A lower insulating film (20) may be formed on a substrate (10). A free lower electrode (30P) may be formed on the lower insulating film (20). The free lower electrode (30P) may include a first metal element (M1 in FIGS. 1 to 3). The free lower electrode (30P) may include a metal film formed of the first metal element (M1), or a metal nitride film formed of a nitride of the first metal element (M1).

[0207] Referring to FIG. 22, a portion of the free lower electrode (30P) can be oxidized to form a lower insert electrode film (32).

[0208] The lower insert electrode film (32) can be formed using an oxidation process (25). The lower insert electrode film (32) contains the oxide of the free lower electrode (30P). While the lower insert electrode film (32) is being formed, the remainder of the free lower electrode (30P) can become the lower electrode (30).

[0209] Referring to FIGS. 22 and 23, after the lower insertion electrode film (32) is formed, the lower interface electrode film (34) can be formed after the lower insertion electrode film (32).

[0210] The lower insert electrode film (32) and the lower interface electrode film (34) can be formed through different processes. Alternatively, the lower insert electrode film (32) is not formed by oxidation of the free lower electrode (30P) while the lower interface electrode film (34) is being formed, and the lower insert electrode film (32) can be formed through a separate process different from that of the lower interface electrode film (34).

[0211] Referring to FIG. 24, the capacitor dielectric film (40) can be formed on the lower interface electrode film (34).

[0212] Next, in FIG. 1, the upper electrode (50) can be formed on the capacitor dielectric film (40).

[0213] FIGS. 25 to 29 are intermediate drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those explained using FIGS. 6 to 11 are briefly explained or omitted.

[0214] Referring to FIG. 25, a plurality of bit line structures (140ST), a plurality of storage contacts (120), a plurality of bit line contacts (146), and a plurality of storage pads (160) may be formed on the second substrate (100).

[0215] The first etch stop layer (196) can be formed on the storage pad (160) and the pad separation insulating layer (180).

[0216] A first mold layer (70), a first support film (60L), a second mold layer (75), and a second support film (65L) may be sequentially formed on a first etch stop film (196). The first mold layer (70) and the second mold layer (75) may each include silicon oxide, but are not limited thereto. The first support film (60L) and the second support film (65L) may include an insulating material having an etch selectivity ratio with respect to the first mold layer (70) and the second mold layer (75).

[0217] Referring to FIG. 26, a plurality of lower electrode holes (190H) may be formed within the first mold layer (70), the first supporter film (60L), the second mold layer (75), and the second supporter film (65L).

[0218] Each lower electrode hole (190H) can penetrate the first mold layer (70), the first support film (60L), the second mold layer (75), and the second support film (65L). Each lower electrode hole (190H) can penetrate the first etch stop film (196) to expose the storage pad (160).

[0219] Referring to FIGS. 26 and 27, a first lower electrode (191) can be formed within the lower electrode hole (190H).

[0220] The first lower electrode (191) can fill the lower electrode hole (190H). The first lower electrode (191) can be connected to the storage pad (160).

[0221] Referring to FIGS. 27 and 28, openings can be formed in the first support membrane (60L) and the second support membrane (65L), respectively, to form the first support pattern (60) and the second support pattern (65).

[0222] Although not illustrated, the first support pattern (60) and the second support pattern (65) may each include a through hole. By using the through hole of the first support pattern (60) and the through hole of the second support pattern (65), the first mold layer (70) and the second mold layer (75) can be removed.

[0223] More specifically, a through hole may be formed in the second supporter membrane (65L) to form a second supporter pattern (65). The through hole of the second supporter pattern (65) may expose the second mold layer (75). The second mold layer (75) may be removed using the through hole of the second supporter pattern (65). Subsequently, a through hole may be formed in the first supporter membrane (60L) to form a first supporter pattern (60). The through hole of the first supporter pattern (60) may be formed at a position corresponding to the through hole of the second supporter pattern (65). The through hole of the first supporter pattern (60) may expose the first mold layer (70). The first mold layer (70) may be removed using the through hole of the first supporter pattern (60).

[0224] After the first mold layer (70) and the second mold layer (75) are removed, a portion of the exposed first lower electrode (191) may be oxidized. Through this, a first lower insert electrode film (192) may be formed on the first lower electrode (191).

[0225] Referring to FIGS. 28 and 29, after the first lower insertion electrode film (192) is formed, the first lower interface electrode film (193) can be formed.

[0226] The first capacitor dielectric film (194) can be formed on the first lower interface electrode film (193).

[0227] Next, referring to FIG. 6, a first upper electrode (195) can be formed on the first capacitor dielectric film (194).

[0228] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0229] 30, 191, 291, 391: Lower electrode 32, 192, 292, 392: Lower insertion electrode membrane 34, 193, 293, 393: Lower interface electrode film 40, 194, 294, 394: Capacitor dielectric film 50, 195, 295, 395: Upper electrode CS, 190, 290, 390: Capacitor structure

Claims

Claim 1 A semiconductor device comprising: an upper electrode; a lower electrode comprising a first metal element; a lower insert electrode film disposed between the upper electrode and the lower electrode, having a rutile structure and comprising an oxide of the lower electrode; a lower interface electrode film disposed between the lower insert electrode film and the upper electrode, having a rutile structure and comprising an oxide of a second metal element different from the first metal element; and a capacitor dielectric film disposed between the lower interface electrode film and the upper electrode, having a tetragonal crystal system and comprising an oxide of a third metal element different from the second metal element. Claim 2 A semiconductor device according to claim 1, wherein the preferred growth crystal plane of the capacitor dielectric film on the lower electrode is the (110) plane. Claim 3 In claim 1, the capacitor dielectric film is a semiconductor device having a rutile structure. Claim 4 A semiconductor device according to claim 1, wherein the first metal element comprises one of cobalt (Co), copper (Cu), molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), or vanadium (V). Claim 5 A semiconductor device according to claim 1, wherein the second metal element comprises one of cobalt (Co), molybdenum (Mo), niobium (Nb), tin (Sn), tantalum (Ta), titanium (Ti), or vanadium (V). Claim 6 A landing pad on a substrate; a lower electrode connected to the landing pad, extending in one direction, and comprising a first metal element; a support pattern in contact with a portion of the lower electrode and comprising a first surface and a second surface opposite in the one direction, wherein the sidewall of the support pattern connects the first surface of the support pattern and the second surface of the support pattern and contacts the lower electrode; a lower insert electrode film in contact with the lower electrode and comprising an oxide of the lower electrode; a lower interface electrode film in contact with the lower insert electrode film and the support pattern on the lower insert electrode film and the support pattern, extending along the first surface of the support pattern and the second surface of the support pattern, and comprising an oxide of a second metal element; a capacitor dielectric film in contact with the lower interface electrode film on the lower interface electrode film, extending along the first surface of the support pattern and the second surface of the support pattern, and comprising an oxide of a third metal element. A semiconductor device comprising an upper electrode on the dielectric film of the capacitor. Claim 7 A semiconductor device according to claim 6, wherein the lower insertion electrode film is not disposed on the first surface of the supporter pattern and the second surface of the supporter pattern. Claim 8 A semiconductor device in claim 6, wherein the lower insertion electrode film and the lower interface electrode film each have a rutile structure, and the capacitor dielectric film has a tetragonal crystal structure. Claim 9 A semiconductor device according to claim 6, wherein the first metal element is different from the second metal element and the third metal element is different from the second metal element. Claim 10 A semiconductor device comprising: an upper electrode; a lower electrode comprising a first metal element or a nitride of the first metal element; a lower insert electrode film in contact with the lower electrode between the upper electrode and the lower electrode and comprising an oxide of the lower electrode; a lower interface electrode film in contact with the lower insert electrode film between the lower insert electrode film and the upper electrode, having a rutile structure and comprising an oxide of a second metal element different from the first metal element; and a capacitor dielectric film in contact with the lower interface electrode film between the lower interface electrode film and the upper electrode, having a tetragonal crystal structure and comprising an oxide of a third metal element different from the second metal element, wherein the preferred growth crystal plane of the capacitor dielectric film on the lower electrode is the (110) plane.

Images