Liquid crystal display panel and liquid crystal display apparatus comprising the same

Abstract

A liquid crystal display panel according to one embodiment of the present specification includes a front substrate including a plurality of pixel regions, a rear substrate including a color filter corresponding to each of the plurality of pixel regions, and a liquid crystal layer located between the front substrate and the rear substrate. The front substrate includes a vibration generating part configured on a base substrate, a planarization layer covering the vibration generating part, and a pixel array layer configured on the planarization layer.

Description

Technology Field

[0001] This specification relates to a liquid crystal display device, and more specifically, to a liquid crystal display panel that outputs sound and a liquid crystal display device including the same. Background Technology

[0002] Liquid crystal display devices are installed in electronic products or home appliances such as televisions, monitors, laptop computers, smartphones, tablet computers, electronic pads, wearable devices, watch phones, portable information devices, navigation systems, or vehicle control display devices, and are used as screens to display images.

[0003] Liquid crystal displays display images on a liquid crystal display panel, and generally require separate speakers to provide sound. When speakers are placed on a liquid crystal display, they occupy space, which creates problems that impose constraints on the design and spatial arrangement of the liquid crystal display. The problem to be solved

[0004] The inventors of this specification recognized the aforementioned problems and continuously conducted various studies and experiments on liquid crystal display panels capable of outputting sound. Through these continuous studies and experiments, the inventors of this specification invented a liquid crystal display panel capable of outputting sound and a liquid crystal display device including the same.

[0005] The problem to be solved according to one embodiment of the present specification is to provide a liquid crystal display panel capable of outputting sound and a liquid crystal display device including the same. means of solving the problem

[0006] A liquid crystal display panel according to one embodiment of the present specification includes a front substrate including a plurality of pixel regions, a rear substrate including a color filter corresponding to each of the plurality of pixel regions, and a liquid crystal layer located between the front substrate and the rear substrate. The front substrate includes a vibration generating part configured on a base substrate, a planarization layer covering the vibration generating part, and a pixel array layer configured on the planarization layer. Effects of the invention

[0007] According to one embodiment of the present specification, a liquid crystal display panel capable of outputting sound and a liquid crystal display device including the same can be provided.

[0008] According to one embodiment of the present specification, a speaker-integrated liquid crystal display panel capable of outputting sound while displaying an image and a liquid crystal display device including the same can be provided, thereby enabling the realization of ESG (environment social governance) through the effects of lightweighting and / or uni-materialization.

[0009] A liquid crystal display device according to one embodiment of the present specification can provide a user with a haptic texture and / or haptic feedback vibration in accordance with the haptic vibration of the liquid crystal display panel corresponding to a user touch. Brief explanation of the drawing

[0010] FIG. 1 is a perspective view showing a liquid crystal display device according to one embodiment of the present specification. Figure 2 is a cross-sectional view showing the cross-section of line I-I' shown in Figure 1. Figure 3 is a plan view showing the liquid crystal display panel and driving circuit shown in Figure 2. Figure 4 is a plan view showing a single pixel illustrated in Figure 3. Figure 5 is a cross-sectional view of line II-II' shown in Figure 4. Figure 6 is another cross-sectional view of line II-II' shown in Figure 4. Figure 7 is a cross-sectional view of line III-III' shown in Figure 3. FIG. 8 is a plan view showing a part of each of the vibration generating part and the pad part according to one embodiment of the present specification. FIG. 9 is a perspective view showing a part of the vibration generating unit illustrated in FIG. 8. Figure 10 is a cross-sectional view of line IV-IV' shown in Figure 8. FIG. 11 is a plan view showing a part of each of the vibration generating part and the pad part according to another embodiment of the present specification. FIG. 12 is a perspective view showing a part of the vibration generating unit illustrated in FIG. 11. Figure 13 is a cross-sectional view of the line V-V' shown in Figure 11. FIG. 14 is a plan view showing a part of each of the vibration generating part and the pad part according to another embodiment of the present specification. Figure 15 is a cross-sectional view of line VI-VI' shown in Figure 14. Specific details for implementing the invention

[0011] Where terms such as “comprising,” “having,” or “consisting of” are used in this specification, other parts may be added unless terms such as “only” are used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise. Where it is stated that a component or layer “contacts” or “overlaps” with another component or layer, it should be understood that while the component or layer may directly contact or overlap with the other component or layer, other components may also be interposed between each component that may indirectly contact or overlap unless specifically stated otherwise.

[0012] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and technically, various interlocking and operation are possible. Furthermore, each embodiment may be implemented independently of one another or together in an associated relationship. The embodiments of this specification are described below through the attached drawings and examples. For the convenience of explanation, the scale of the components depicted in the drawings differs from the actual scale and is therefore not limited to the scale depicted in the drawings.

[0013] Referring to FIGS. 1 to 3, a liquid crystal display device according to one embodiment of the present specification includes a liquid crystal display panel (10).

[0014] The liquid crystal display panel (10) may be configured to display an image and output sound according to vibration (or self-vibration). For example, the liquid crystal display panel (10) may be configured to display an image and simultaneously output sound according to vibration (or self-vibration).

[0015] The liquid crystal display panel (10) may include a front substrate (100), a rear substrate (200), and a liquid crystal layer (300).

[0016] The front substrate (100) may be a first substrate, an external substrate, a thin-film transistor array substrate, or a screen. The front substrate (100) may include a display area (DA) and a non-display area (NDA).

[0017] The display area (DA) may be an area where an image is displayed. For example, the display area (DA) may be a screen. The non-display area (NDA) may include the edge area of ​​the front substrate (110) surrounding the display area (DA).

[0018] The front substrate (100) may include a vibration generating unit (130). The vibration generating unit (130) may include a piezoelectric vibration layer containing a piezoelectric material. The vibration generating unit (130) may be configured to vibrate the front substrate (100) or the liquid crystal display panel (10) according to the vibration (or displacement or driving) of the piezoelectric vibration layer. Accordingly, the front substrate (100) or the liquid crystal display panel (10) may vibrate according to the vibration of the vibration generating unit (130) to output sound (S) in the front direction (FD). For example, sound (S) may be output from the screen of the liquid crystal display panel (10) to the front direction (FD) of the liquid crystal display panel (10).

[0019] The vibration generating part (130) is configured between the front substrate (100) and the rear substrate (300) and can be covered by a flattening layer formed on the front substrate (100).

[0020] The front substrate (100) or display area (DA) may further include a pixel array layer configured on the flattening layer.

[0021] The pixel array layer may include a plurality of gate lines (GL) and a plurality of data lines (DL) that are configured on a flattening layer to intersect each other and define a plurality of pixel regions, and a plurality of pixels (SP) configured for each pixel region formed by the intersection of the plurality of gate lines (GL) and the plurality of data lines (DL).

[0022] Each of the plurality of pixels (SP) may be a subpixel constituting a single unit pixel (UP). For example, a single unit pixel (UP) may include a red subpixel, a green subpixel, and a blue subpixel, but is not limited thereto, and may further include a white subpixel.

[0023] Each of the plurality of pixels (SP) may include a plurality of thin-film transistors (TFTs) configured in each of the plurality of pixel regions and connected to an adjacent data line (DL) and an adjacent gate line (GL). Each of the plurality of pixels (SP) may include a pixel electrode (PE) connected to the thin-film transistor (TFT) and a common electrode (CE) superimposed on the pixel electrode (PE).

[0024] A common electrode (CE) may be divided into a plurality of touch electrodes (TE) that overlap with one or more of a plurality of pixel regions. The plurality of touch electrodes (TE) may be configured to overlap with one or more pixel regions depending on the touch resolution. Each of the plurality of touch electrodes (TE) may be electrically connected to a corresponding touch line (TL) among a plurality of touch lines (or common voltage lines) (TL).

[0025] The vibration generating unit (130) may be configured to overlap with a plurality of gate lines (GL) and a plurality of data lines (DL). The vibration generating unit (130) may be configured to overlap with each of the plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of touch lines (TL). For example, the vibration generating unit (130) may have a line width wider than each of the plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of touch lines (TL).

[0026] The rear substrate (200) may be a second substrate, an internal substrate, or a color filter array substrate. The rear substrate (200) may be configured to cover a portion of the front substrate (100). The rear substrate (200) may have a smaller size (or smaller area) than the front substrate (100). For example, the rear substrate (200) may have a size corresponding to the remaining portion of the front substrate (100), excluding one edge portion.

[0027] The rear substrate (200) may include a color filter layer (230). The color filter layer (230) may include a color filter configured to overlap with each pixel area of ​​a plurality of pixels (SP) provided on the front substrate (100).

[0028] The front substrate (100) may further include a first region overlapping with the rear substrate (200), a second region extending from the first region, and a pad portion (170) configured in the second region.

[0029] The pad portion (170) may be configured on one side edge portion (or second area) extending from one side of the display area (DA).

[0030] The pad portion (170) may be configured to be electrically connected to each of the plurality of data lines (DL) configured in the pixel array layer. The pad portion (170) may be configured to supply (or transmit) a data signal (or data voltage) to each of the plurality of data lines (DL). The pad portion (170) may be configured to be electrically connected to the vibration generating portion (130). The pad portion (170) may be configured to supply (or transmit) a vibration driving signal (or voice signal) to the vibration generating portion (130).

[0031] The pad portion (170) may be configured to be electrically connected to each of the plurality of touch lines (TL). The pad portion (170) may be configured to supply (or transmit) a touch driving signal (or touch driving pulse) or a common voltage to each of the plurality of touch lines (TL).

[0032] The front substrate (100) or non-display area (NDA) may further include gate driving circuits (11A, 11B). The gate driving circuits (11A, 11B) may be formed in the non-display area (NDA) on one or both sides of the short side of the front substrate (100) in conjunction with the manufacturing process of the thin-film transistor (TFT) of each pixel (SP), and may be electrically connected to each of the plurality of gate lines (GL) formed in the display area (DA). The gate driving circuits (11A, 11B) may be electrically connected to the pad portion (170) through a gate control signal line (GCL). The gate driving circuits (11A, 11B) may be configured to generate a gate signal (or scan signal) according to the gate control signal supplied through the pad portion (170) and the gate control signal line (GCL) and supply it to the corresponding gate line (GL). For example, the gate driving circuit (11A, 11B) may be configured as a shift register including a transistor formed by the same process as the thin-film transistor (TFT) provided in each pixel (SP).

[0033] Referring to FIG. 2, the rear substrate (200) can be bonded to the remaining portion (or first region) of the front substrate (100), excluding the edge portion (or second region) of the front substrate (100), by means of a sealant (350) with the liquid crystal layer (300) in between.

[0034] The liquid crystal layer (300) may be interposed (or filled) between the front substrate (100) and the rear substrate (200). The liquid crystal layer (300) may be composed of a liquid crystal in which the arrangement direction of the liquid crystal molecules changes according to the electric field formed by the data voltage applied to the pixel electrode (PE) and the common voltage applied to the common electrode (CE) for each pixel.

[0035] The liquid crystal display panel (10) may further include a first polarizing member (400) and a second polarizing member (500). The first polarizing member (400) may be attached to the rear surface of the rear substrate (200). The first polarizing member (400) may be configured to polarize light incident from the liquid crystal layer (300). The second polarizing member (500) may be attached to the front surface of the front substrate (100). The second polarizing member (500) may be configured to polarize light emitted to the outside through the front substrate (100).

[0036] A liquid crystal display panel (10) can display an image according to light passing through the liquid crystal layer (300) by driving the liquid crystal layer (300) according to the electric field formed at each pixel (SP) by the data voltage applied to each pixel (SP) and the common voltage.

[0037] In a liquid crystal display panel (10) according to one embodiment of the present specification, since the front substrate (100) forms an image display surface, the entire front surface can be exposed to the outside without any part being covered by a separate mechanism. Accordingly, the bezel forming the border of the liquid crystal display device is completely omitted, or even if a bezel is formed, its width is very small, so the overall aesthetic design of the liquid crystal display device can be improved.

[0038] Referring to FIGS. 2 and FIGS. 3, a liquid crystal display panel (10) according to one embodiment of the present specification may further comprise an edge sealing member (600).

[0039] The edge sealing member (600) may be formed to surround at least one side of the liquid crystal display panel (10). The edge sealing member (600) may be formed to cover each side and each corner of the liquid crystal display panel (10). The edge sealing member (600) may serve to protect the side of the liquid crystal display panel (10) from external impact or to prevent side light leakage of the liquid crystal display panel (10). For example, the edge sealing member (600) may be made of a colored resin or a light-blocking resin to prevent side light leakage.

[0040] A liquid crystal display device according to one embodiment of the present specification may further include a panel driving circuit (30).

[0041] The panel driving circuit (30) may be configured to display an image on the liquid crystal display panel (10) and to vibrate the vibration generating unit (130) provided on the liquid crystal display panel (10). The panel driving circuit (30) may be connected to a pad unit (170) provided on the front substrate (100) of the liquid crystal display panel (10). The panel driving circuit (30) may be configured to apply a data signal to a plurality of data lines (DL) through the pad unit (170), apply a gate control signal to a gate driving circuit (11A, 11B) through the pad unit (170) and a gate control signal line (GCL), and apply a vibration driving signal to the vibration generating unit (130) through the pad unit (170).

[0042] A panel driving circuit (30) according to one embodiment of the present specification may include a plurality of flexible circuit films (31), a data driving integrated circuit (32), a printed circuit board (33), and a timing control unit (34).

[0043] Each of the plurality of flexible circuit films (31) can be attached to the pad portion (170) and the printed circuit board (33). One side of each of the plurality of flexible circuit films (31) can be connected to the pad portion (170) by a reverse bonding method. By doing so, each of the plurality of flexible circuit films (31) may not protrude in the lateral direction of the front board (100). The first and / or last of the plurality of flexible circuit films (31) can be connected to the gate driving circuits (11A, 11B) through the pad portion (170).

[0044] The data driving integrated circuit (32) can be mounted on each of the plurality of flexible circuit films (31). The data driving integrated circuit (32) can be configured to convert digital image data input from the timing control unit (34) through the printed circuit board (33) into an analog data signal and supply it to the corresponding data line (DL) through the pad unit (170).

[0045] The data driving integrated circuit (32) can be connected to each of the plurality of touch electrodes (TE) through each of the plurality of touch lines (TL). Each of the plurality of touch electrodes (TE) can be electrically connected to the corresponding touch line (TL) among the plurality of touch lines (TL).

[0046] The data driving integrated circuit (32) may be configured to apply a common voltage to a plurality of touch electrodes (TE) during a display period and to apply a touch driving signal (or touch driving pulse) to each of the plurality of touch electrodes (TE) during a touch sensing period. For example, the data driving integrated circuit (32) may be configured to apply a touch driving signal to a plurality of touch electrodes (TE) during a touch sensing period and to detect a change in capacitance of each of the plurality of touch electrodes (TE) to output touch raw data. For example, the data driving integrated circuit (32) may be configured to detect a change in capacitance of each of the plurality of touch electrodes (TE) based on a magnetic capacitance method, but is not limited thereto.

[0047] A printed circuit board (33) may be electrically connected to the other side of each of a plurality of flexible circuit films (31) and configured to transmit a signal necessary for driving a liquid crystal display panel (10) to the corresponding flexible circuit film (310).

[0048] The timing control unit (34) may be mounted on a printed circuit board (33). For example, the timing control unit (34) may be configured to control the driving of the data driving integrated circuit (32) and the gate driving circuits (11A, 11B), respectively, and to provide digital image data input from the outside to the corresponding data driving integrated circuit (32).

[0049] The timing control unit (34) can generate touch position data based on touch raw data provided from the data driving integrated circuit (32) and provide it to the host control unit.

[0050] The panel driving circuit (30) may further include a power circuit (35) that generates various power sources (or driving voltages) required for driving the liquid crystal display panel (10), and a memory element, etc.

[0051] A liquid crystal display device or panel driving circuit (30) according to one embodiment of the present specification may further include a vibration driving circuit (36).

[0052] The vibration driving circuit (36) may be mounted on a printed circuit board (33). The vibration driving circuit (36) may be configured to vibrate a vibration generating unit (130) configured on a liquid crystal display panel (10) or a front board (100). The vibration driving circuit (36) may be configured to generate a vibration driving signal based on input sound source data. For example, the vibration driving circuit (36) may include an acoustic processing circuit that generates an acoustic signal from sound source data, and an amplifier circuit that amplifies the acoustic signal to output a vibration driving signal. For example, the amplifier circuit may include a pre-amplifier circuit and a main amplifier circuit. Accordingly, the vibration generating unit (130) vibrates according to the vibration driving signal, and the front board (100) or the liquid crystal display panel (10) vibrates according to the vibration of the vibration generating unit (130) to generate (or output) one or more of vibration and sound (S). For example, when the vibration generating unit (130) vibrates, one or more of vibration and sound (S) may be generated (or output) in the area corresponding to each of the plurality of gate lines (GL) and the plurality of data lines (DL).

[0053] The vibration driving circuit (36) may be configured to vibrate the vibration generating unit (130) in response to haptic data provided from the display host control unit or the timing control unit (34). For example, the vibration driving circuit (36) may be configured to generate a haptic vibration signal corresponding to the haptic data. Accordingly, the vibration generating unit (130) haptic vibrates according to the haptic vibration signal, and the front substrate (100) or the liquid crystal display panel (10) vibrates according to the haptic vibration of the vibration generating unit (130) to generate (or output) a haptic texture and / or haptic feedback vibration that responds to the user's touch.

[0054] The liquid crystal display device may further include a backlight unit (50).

[0055] A backlight unit (50) may be configured to irradiate light onto a liquid crystal display panel (10). The backlight unit (50) may be positioned below a rear substrate (200) of the liquid crystal display panel (10) and configured to irradiate light onto the rear substrate (200). The backlight unit (50) may include a light guide plate (51), a light source (52), a reflective sheet (53), and an optical sheet member (54).

[0056] The light guide plate (51) may be formed in a flat plate shape (or wedge shape) and configured to direct light incident from a light source (52) toward a liquid crystal display panel (10) through a light receiving surface. The light source (52) may be configured to be positioned opposite a light receiving surface provided on at least one side of the light guide plate (51) to irradiate light onto the light guide plate (51). The light source (52) may include a plurality of light-emitting diodes. A reflective sheet (53) may be placed on the lower surface of the light guide plate (51) and configured to reflect light incident from the light guide plate (51) toward the liquid crystal display panel (10). An optical sheet member (54) may be placed on the light guide plate (51) and configured to improve the brightness characteristics of the light proceeding from the light guide plate (51) toward the liquid crystal display panel (10). For example, the optical sheet member (54) may be composed of one or more diffusion sheets and one or more prism sheets, or may be composed of a composite functional sheet that simultaneously performs the function of diffusing and concentrating light.

[0057] The liquid crystal display device may further include a panel support (70).

[0058] The panel support member (70) accommodates the backlight unit (50) and the panel driving circuit (30), and can be coupled to the rear edge portion of the liquid crystal display panel (10) so that the entire front surface of the liquid crystal display panel (10) is exposed to the outside. The panel support member (70) may include a guide frame (71), a panel coupling member (72), a support case (73), and a rear cover (75).

[0059] The guide frame (71) is formed in the shape of a square frame to support the rear edge portion of the liquid crystal display panel (10) and can be coupled to the rear edge portion of the liquid crystal display panel (10) through a panel coupling member (72), but is not limited thereto and can also be coupled to the first polarizing member (400) of the liquid crystal display panel (10). The panel coupling member (72) may include double-sided tape, a thermosetting adhesive, or a photocurable adhesive.

[0060] The support case (or support cover) (73) may be formed to have a storage space. The support case (73) may be configured to support (or store) the backlight unit (50) and also support the guide frame (51). The sides of the support case (73) may be surrounded by the guide frame (71). Optionally, the support case (73) may be omitted depending on the design aspects, weight reduction, and slimming of the liquid crystal display device.

[0061] The rear cover (750) may have a storage space. The rear cover (750) may be configured to house the support case (73) and surround the guide frame (71) and the side of the liquid crystal display panel (10) so that the entire front of the liquid crystal display panel (10) is exposed to the outside. For example, the rear cover (750) may be made of plastic or metal.

[0062] Hereinafter, a liquid crystal display panel (10) according to one embodiment of the present specification will be described with reference to FIGS. 4 and FIGS. 5.

[0063] A liquid crystal display panel (10) according to one embodiment of the present specification may be driven in a fringe field switching manner to create an image by driving liquid crystal molecules (310) of a liquid crystal layer (300) located on a pixel area through a slit (SL) formed between a common electrode (CE) and a pixel electrode (PE). A liquid crystal display panel (10) according to another embodiment may be driven in a plane switching manner to create an image by driving liquid crystal molecules (310) of a liquid crystal layer (300) by a horizontal electric field between a common electrode (CE) and a pixel electrode (PE), in which the common electrode (CE) and the pixel electrode (PE) are spaced apart from each other and arranged parallel to each other.

[0064] A liquid crystal display panel (10) according to one embodiment of the present specification can output sound (S) or output sound (S) while displaying an image by vibrating according to the vibration of a vibration generating unit (130) and outputting one or more of sound (S) and vibration in the front direction (FD).

[0065] Referring to FIGS. 4 and FIGS. 5, a liquid crystal display panel (10) according to one embodiment of the present specification may include a front substrate (100) and a rear substrate (200).

[0066] The front substrate (100) may include a base substrate (110), a vibration generating part (130), a flattening layer (140), and a pixel array layer (150).

[0067] The base substrate (110) may be made of glass or transparent plastic. The base substrate (110) may include a front surface (110a) and a back surface (110b). The front surface (110a) of the base substrate (110) may be the front surface of the liquid crystal display panel (10).

[0068] A vibration generating unit (130) may be configured on a base substrate (110). A vibration generating unit (130) may be configured on the back surface (110b) of the base substrate (110). A vibration generating unit (130) may be configured to vibrate the base substrate (110) or the front substrate (100). A vibration generating unit (130) may be configured to correspond to the remaining area excluding the opening area of ​​each of the plurality of pixel regions. A vibration generating unit (130) may be configured to have a mesh shape corresponding to the remaining area excluding the opening area of ​​each of the plurality of pixel regions.

[0069] A vibration generating unit (130) according to one embodiment of the present specification may include a first electrode layer (131), a piezoelectric vibration layer (133), and a second electrode layer (135).

[0070] The first electrode layer (131) can be formed on the base substrate (110).

[0071] The piezoelectric vibrating layer (133) may be formed on the first electrode layer (131). The piezoelectric vibrating layer (133) may be laminated (or bonded) to the first electrode layer (131) so as to have the same shape as the first electrode layer (131).

[0072] The piezoelectric vibrating layer (133) may include a piezoelectric material or an electroactive material that includes a piezoelectric effect. The piezoelectric vibrating layer (133) may include at least one of a piezoelectric inorganic material and a piezoelectric organic material. For example, the piezoelectric material may have the characteristic that a potential difference is generated by dielectric polarization due to the change in the relative positions of positive (+) ions and negative (-) ions as pressure or twisting phenomena act on the crystal structure by an external force, and conversely, vibration is generated by an electric field due to an applied voltage. For example, the piezoelectric vibrating layer (133) may be a piezoelectric layer, a piezoelectric material layer, an electroactive layer, a piezoelectric composite layer, a piezoelectric composite, or a piezoelectric ceramic composite, but is not limited thereto.

[0073] The piezoelectric vibrating layer (133) may be composed of a ceramic-based material capable of implementing relatively strong vibrations or a piezoelectric ceramic having a perovskite-based crystal structure. The perovskite crystal structure may have a plate-shaped structure having oriented properties, and / or an inverse piezoelectric effect.

[0074] The piezoelectric ceramic may be composed of a single-crystal ceramic having a single-crystal structure, or a ceramic material having a polycrystalline structure or a polycrystalline ceramic. The piezoelectric material of the single-crystal ceramic may include α-AlPO4, α-SiO2, LiNbO3, Tb2(MoO4)3, Li2B4O7, or ZnO. The piezoelectric material of the polycrystalline ceramic may include a PZT (lead zirconate titanate) material containing lead (Pb), zirconium (Zr), and titanium (Ti), or a PZNN (lead zirconate nickel niobate) material containing lead (Pb), zirconium (Zr), nickel (Ni), and niobium (Nb). For example, the piezoelectric vibrating layer (133) may include at least one of CaTiO3, BaTiO3, and SrTiO3 that do not contain lead (Pb).

[0075] A piezoelectric vibrating layer (133) according to one embodiment of the present specification may be formed (or configured) by a process of forming (or depositing) a piezoelectric material layer (or piezoelectric ceramic layer) on a base substrate (110), a process of patterning the piezoelectric material layer, and a heat treatment process, etc. For example, the piezoelectric material layer may be formed (or configured) by a physical vapor deposition process such as a sputtering process, a chemical vapor deposition process, a sol-gel process using piezoelectric ceramic powder, or a coating process using piezoelectric ceramic powder. The piezoelectric material layer may be patterned by a dry etching process, a wet etching process, or a lift-off process.

[0076] A piezoelectric vibrating layer (133) according to another embodiment of the present specification may be formed (or constructed) on a first electrode layer (131) by a tape casting process (or method). For example, the piezoelectric vibrating layer (133) may be formed (or manufactured) through the steps of preparing a slurry comprising piezoelectric powder (or ceramic powder) and an additive, applying (or tape casting or forming) the slurry onto the first electrode layer (131), and molding (or sintering) the applied (or formed) slurry at least once. For example, the additive added to the slurry may include, but is not limited to, known materials or materials in the field of piezoelectric material compositions. For example, the additive may include, but is not limited to, one or more of a dispersant, a solvent, a binder, and a plasticizer.

[0077] According to one embodiment of the present specification, the binder may include a high-temperature binder. For example, the binder may include glass frit. The binder may remain in a particulate state on the first electrode layer (131) upon drying of the slurry. The binder may change into a liquid state when the piezoelectric particles (or ceramic particles) grow at the molding (or sintering) temperature of the slurry, move to the interface between the first electrode layer (131) and the piezoelectric element, and solidify as the molding temperature decreases, thereby increasing the bonding force (or adhesion force) between the first electrode layer (131) and the piezoelectric element.

[0078] According to another embodiment of the present specification, the piezoelectric vibrating layer (133) is formed on the first electrode layer (131) through a tape casting method, so it is not limited to a specific shape and can be formed in a polygonal shape, a non-square shape, or a line shape.

[0079] The second electrode layer (135) may be formed on the piezoelectric vibrating layer (133). The second electrode layer (135) may be laminated (or bonded) to the piezoelectric vibrating layer (133) so as to have the same shape as the piezoelectric vibrating layer (133).

[0080] According to one embodiment of the present specification, in order to prevent electrical connection (or short circuit) between the first electrode layer (131) and the second electrode layer (135), one or more of the first electrode layer (131) and the second electrode layer (135) may be formed on the remaining portion excluding the edge portion of the piezoelectric vibrating layer (133).

[0081] Each of the first electrode layer (131) and the second electrode layer (135) according to one embodiment of the present specification may be made of a transparent conductive material, a translucent conductive material, or an opaque conductive material. For example, the transparent or translucent conductive material may include ITO (indium tin oxide) or IZO (indium zinc oxide), but is not limited thereto. The opaque conductive material may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), molybdenum (Mo), magnesium (Mg), carbon, or silver (Ag) containing glass frit, or may be made of an alloy thereof, but is not limited thereto. For example, the glass frit may include PbO or Bi2O3-based materials, but is not limited thereto. For example, the first electrode layer (131) and the second electrode layer (135) may each contain silver (Ag) with low resistivity to improve the electrical and / or vibrational characteristics of the piezoelectric vibrating layer (133). For example, carbon may be a carbon material including carbon black, ketjen black, carbon nanotubes, and graphite, but is not limited thereto.

[0082] The piezoelectric vibrating layer (133) can be polarized (or poled) by a polarization voltage applied to the first electrode layer (131) and the second electrode layer (135) through the pad portion (170) in a constant temperature atmosphere or a temperature atmosphere changing from high temperature to room temperature.

[0083] The piezoelectric vibrating layer (133) can vibrate by alternately repeating contraction and / or expansion due to the inverse piezoelectric effect according to the vibration driving signal (or voice signal) applied to the first electrode layer (131) and the second electrode layer (135) through the pad portion (170). For example, the piezoelectric vibrating layer (133) can vibrate in the vertical direction (or thickness direction) and the planar direction by the signal applied to the first electrode layer (131) and the second electrode layer (135). The piezoelectric vibrating layer (133) can improve the acoustic characteristics and / or sound pressure characteristics generated according to the vibration of the vibration generating portion (130) or the front substrate (110) by displacement (or vibration or driving) due to contraction and / or expansion in the planar direction.

[0084] A flattening layer (140) may be formed (or configured) on a base substrate (110) to cover a vibration generating part (130). The flattening layer (140) may be an insulating layer for forming (or configuring) a flat surface on the vibration generating part (130). The flattening layer (140) may be made of a high-heat-resistant organic material. For example, the flattening layer (140) may include a transparent polyimide material or a siloxane material.

[0085] The pixel array layer (150) can be formed (or configured) on the flattening layer (140).

[0086] One or more buffer layers (145) may be additionally formed (or configured) between the pixel array layer (150) and the flattening layer (140). One or more buffer layers (145) may be formed on the flattening layer (140). One or more buffer layers (145) may be made of an inorganic material. For example, a plurality of buffer layers (145) may be made of different inorganic materials.

[0087] The pixel array layer (150) is configured on the flattening layer (140) (or buffer layer (145)) so as to intersect each other and may include a plurality of gate lines (GL) and a plurality of data lines (DL) defining a plurality of pixel regions. Each of the plurality of gate lines (GL) and the plurality of data lines (DL) may be formed (or arranged) on the flattening layer (140) (or buffer layer (145)) so as to overlap with the vibration generating unit (130).

[0088] The pixel array layer (150) may include a plurality of thin-film transistors (TFT), a common electrode (CE), and a plurality of pixel electrodes (PE).

[0089] A plurality of thin-film transistors (TFTs) may be configured in each of a plurality of pixel regions and configured to be connected to an adjacent data line (DL) and an adjacent gate line (GL). A plurality of thin-film transistors (TFTs) may be formed (or placed) on a planarization layer (140) (or buffer layer (145)) so as to overlap with a vibration generating unit (130). The vibration generating unit (130) may include a protrusion (130p) that overlaps with each of the plurality of thin-film transistors (TFTs) configured in each of the plurality of pixel regions. The protrusion (130p) of the vibration generating unit (130) may have a size larger than the thin-film transistor region provided in each of the plurality of pixel regions. For example, a thin-film transistor (TFT) may be placed (or configured) on the protrusion (130p) of the vibration generating unit (130).

[0090] Each of the plurality of thin-film transistors (TFTs) can be used as a driving element for a liquid crystal display device. Each of the plurality of thin-film transistors (TFTs) may include a gate electrode (GE), a gate insulating layer (151), a semiconductor layer (SCL), an interlayer insulating layer (152), a source electrode (SE), and a drain electrode (DE).

[0091] The gate electrode (GE) may protrude from a gate line (GL) disposed on a base substrate (110). The gate electrode (GE) may be formed from a conductive material, for example, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or an alloy thereof, but is not limited thereto.

[0092] The gate insulating layer (151) can be formed to cover the gate line (GL) and the gate electrode (GE). The gate insulating layer (151) can be formed of an inorganic insulating material.

[0093] A semiconductor layer (SCL) may be formed (or placed) on a gate insulating layer (151) so as to overlap (or correspond) with a gate electrode (GE). When a voltage is applied to the gate electrode (GE), the semiconductor layer (SCL) may form a channel for current flow between a source electrode (SE) and a drain electrode (DE). For example, the semiconductor layer (SCL) may be formed of polysilicon (p-Si), amorphous silicon (a-Si), or an oxide semiconductor, but is not limited thereto.

[0094] The interlayer insulating layer (152) may be formed (or placed) to cover the gate insulating layer (151) and the gate electrode (GE). The interlayer insulating layer (152) may be formed of an inorganic insulating material.

[0095] Each of the source electrode (SE) and drain electrode (DE) can be formed (or placed) on the interlayer insulating layer (152) so as to overlap (or correspond) with a part of the active layer (121).

[0096] The source electrode (SE) and the drain electrode (DE) are electrically connected to the semiconductor layer (SCL) through via holes formed in the interlayer insulating layer (152). The source electrode (SE) can be electrically connected to the source region of the semiconductor layer (SCL) through source via holes formed in the interlayer insulating layer (152) on the source region of the semiconductor layer (SCL). The drain electrode (DE) can be electrically connected to the drain region of the semiconductor layer (SCL) through drain via holes formed in the interlayer insulating layer (152) on the drain region of the semiconductor layer (SCL). For example, the drain electrode (DE) can protrude from a data line (DL) placed on the base substrate (110). The source electrode (SE) and drain electrode (DE) may be formed from a conductive material, for example, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but are not limited thereto.

[0097] The pixel array layer (150) may further include a passivation layer (153) and a protection layer (154).

[0098] A passivation layer (153) may be formed (or disposed) on a base substrate (110) to cover a plurality of thin-film transistors (TFTs). The passivation layer (153) may be an insulating layer for protecting the plurality of thin-film transistors (TFTs) and may be made of an inorganic material, but is not limited thereto. For example, the passivation layer (153) may be omitted.

[0099] The protective layer (154) may be formed (or arranged) to cover a plurality of thin-film transistors (TFTs) or passivation layers (153). The protective layer (154) may be an insulating layer for forming (or configuring) a flat surface on the plurality of thin-film transistors (TFTs) or passivation layers (153). The protective layer (154) may be a flattening layer, a second flattening layer, or an overcoat layer. The protective layer (154) may be made of an organic material. The protective layer (154) may be composed of a single layer or multiple layers of polyimide or photoacrylic, but is not limited thereto.

[0100] A common electrode (CE) may be formed (or disposed) on a protective layer (154). The common electrode (CE) may be electrically connected to a corresponding touch line (TL) among a plurality of touch lines (TL). For example, a plurality of touch lines (TL) may be formed (or disposed) together with a data line (DL), but is not limited thereto. A plurality of touch lines (TL) may be formed (or disposed) on an interlayer insulating layer (152) so as to overlap with a vibration generating part (130).

[0101] A common electrode (CE) may be divided into a plurality of touch electrodes (TE) (or a plurality of common electrode blocks) that overlap with one or more of the plurality of pixel regions. A single common electrode (CE) or a single touch electrode (TE) may be formed (or placed) in common on two or more pixels (SP). The plurality of touch electrodes (TE) may constitute a magnetic capacitive touch element, but are not limited thereto.

[0102] The pixel array layer (150) may further include an insulating layer (155). The insulating layer (155) may be formed (or disposed) on the protective layer (153) to cover the common electrode (CE). The insulating layer (155) may be made of an inorganic insulating material or an organic insulating material.

[0103] A pixel electrode (PE) may be formed (or disposed) on an insulating layer (155) of each of a plurality of pixel regions. The pixel electrode (PE) may be formed on an insulating layer (155) so as to overlap with a common electrode (CE) in each of the plurality of pixel regions. The pixel electrode (PE) may overlap with the common electrode (CE) with the insulating layer (155) in between. For example, the common electrode (CE) may overlap with the plurality of pixel electrodes (PE) formed in each of the plurality of pixel regions.

[0104] A pixel electrode (PE) can be formed (or arranged) to be electrically connected to the source electrode (SE) of the corresponding thin-film transistor (TFT). The pixel electrode (PE) can be electrically connected to the source electrode (SE) of the corresponding thin-film transistor (TFT) through an electrode contact hole (ECH) formed in the insulating layer (155), the protective layer (154), and the passivation layer (153). In FIG. 5, the pixel electrode (PE) is electrically connected to the source electrode (SE) of the thin-film transistor (TFT), but is not limited thereto; the pixel electrode (PE) may also be electrically connected to the drain electrode (DE) of the thin-film transistor (TFT), in which case the source electrode (SE) of the thin-film transistor (TFT) is electrically connected to the data line (DL).

[0105] The pixel electrode (PE) may be formed (or configured) to have a plurality of slits (SL). For example, the pixel electrode (PE) may be formed (or configured) in a straight shape or in at least one curved shape (e.g., a zigzag shape).

[0106] According to another embodiment of the present specification, the common electrode (CE) may have a plurality of slits (SL), and the pixel electrode (PE) may be formed (or arranged) to have a single electrode structure within the pixel area.

[0107] A common electrode (CE) can be electrically connected to a corresponding touch line (TL) among a plurality of touch lines (TL) by a line connection pattern (LCP) formed together with a pixel electrode (PE). The line connection pattern (LCP) can form an island shape on an insulating layer (155) together with the pixel electrode (PE). The line connection pattern (LCP) can be directly connected (or in contact) with a portion of the common electrode (CE) placed on the corresponding touch line (TL), and can be electrically connected to the corresponding touch line (TL) through a line contact hole (LCH) formed in the insulating layer (155), the protective layer (154), and the passivation layer (153). Accordingly, the common electrode (CE) can receive a common voltage or a touch driving signal through the line connection pattern (LCP) with the corresponding touch line (TL).

[0108] Each of the common electrode (CE) and the pixel electrode (PE) may be made of a transparent conductive material. For example, the transparent conductive material may be made of tin oxide, indium tin oxide, indium zinc oxide, indium zinc tin oxide, etc., but is not limited thereto.

[0109] The pixel array layer (150) may further include a first alignment layer (156). The first alignment layer (156) may be formed to set the pretilt angle of the liquid crystal molecules (310). For example, the first alignment layer (156) may include fine grooves formed by a rubbing process.

[0110] The rear substrate (200) may include a second base substrate (210) and a color filter layer (230).

[0111] The second base substrate (210) may be made of glass or transparent plastic. The second base substrate (210) may include a front surface (210a) and a back surface (210b). The back surface (210b) of the second base substrate (210) may be the back surface of the liquid crystal display panel (10).

[0112] A color filter layer (230) may be formed (or placed) on the front surface (210a) of the second base substrate (210). The color filter layer (230) may include color filters (231, 233, 235) corresponding to each of the plurality of pixel regions. For example, the color filter layer (210) may include a red color filter (231), a green color filter (233), and a blue color filter (235).

[0113] The edge portions of the red color filter (231), the green color filter (233), and the blue color filter (235) can overlap. For example, one edge portion of the red color filter (231) can be covered by the green color filter (233), and the other edge portion of the red color filter (231) can be covered by the blue color filter (235).

[0114] The rear substrate (200) may further include a second alignment layer (250). The second alignment layer (250) may be formed to set the pretilt angle of the liquid crystal molecules (310). For example, the second alignment layer (250) may include fine grooves formed by a rubbing process.

[0115] The front substrate (100) and the rear substrate (200) can be bonded together with a liquid crystal layer (300) in between by a sealant (350; see FIG. 7). For example, the rear substrate (200) can be bonded with the remaining portion (or first region) of the front substrate (100), excluding one edge portion (or second region), by a sealant (350) with a liquid crystal layer (300) in between.

[0116] The sealant (350) may be formed (or placed) along the edge portion of the rear substrate (200). The sealant (350) may be formed to overlap a portion of the first and second alignment films (156, 250).

[0117] The liquid crystal layer (300) may be interposed (or filled) between the front substrate (100) and the rear substrate (200). The liquid crystal layer (300) may be filled in a space surrounded by a sealant (350). The liquid crystal layer (300) may be composed of a liquid crystal in which the arrangement direction of the liquid crystal molecules changes according to the electric field formed by the data voltage applied to the pixel electrode (PE) and the common voltage applied to the common electrode (CE) for each pixel.

[0118] In each of the plurality of pixels (SP), when a common voltage is applied to the common electrode (CE) and a data voltage is applied to the pixel electrode (PE) through the thin-film transistor (TFT), a fringe field is formed between the pixel electrode (PE) and the common electrode (CE) through the slit (SL) of the pixel electrode (PE), and the liquid crystal molecules (310) of the liquid crystal layer (300) are driven by the fringe field, and the light transmittance that transmits the display area from the backlight unit changes according to the degree of driving (or rotation) of the liquid crystal molecules (310), so that an image can be displayed according to the amount of light of each pixel (SP).

[0119] Since the liquid crystal display device according to one embodiment of the present specification forms a screen of a front substrate (100), there is a need to prevent or minimize the reflection of external light by a metal line (or metal layer) disposed (or configured) on the front substrate (100). To this end, the liquid crystal display panel (10) or the front substrate (100) according to one embodiment of the present specification may further include a reflection reduction part (120).

[0120] A reflection reduction member (120) may be formed (or configured) on the front substrate (100) to block or absorb external light incident through the base substrate (110) of the front substrate (100). For example, the reflection reduction member (120) may be an anti-reflection member, a light blocking member, a light absorption member, a light absorption pattern layer, and a high heat-resistant black matrix, but is not limited thereto.

[0121] The reflection reduction member (120) may be disposed (or interposed) between the base substrate (110) of the front substrate (100) and the vibration generating member (130). The reflection reduction member (120) may be formed (or disposed) to be in direct contact with the back surface (110b) of the base substrate (110). The vibration generating member (130) may be disposed (or configured) on the reflection reduction member (120). For example, the first electrode layer (131) of the vibration generating member (130) may be disposed (or configured) on the reflection reduction member (120) and may be in direct contact with the reflection reduction member (120).

[0122] The reflection reduction member (120) may be formed (or configured) to have the same shape in a planar manner as the vibration generating member (130). For example, the reflection reduction member (120) may be formed to have the same width, the same size, and the same planar shape as the vibration generating member (130).

[0123] The reflection reduction unit (120) is formed (or arranged) to overlap with each of the plurality of gate lines (GL) and the plurality of data lines (DL), and can block or absorb light incident on each of the plurality of gate lines (GL) and the plurality of data lines (DL). The reflection reduction unit (120) is formed (or arranged) to overlap with each of the plurality of touch lines (TL) and the plurality of thin-film transistors (TFT), and can block or absorb light incident on each of the plurality of touch lines (TL) and the plurality of thin-film transistors (TFT). For example, the reflection reduction unit (120) may be configured to have a mesh shape corresponding to the remaining area excluding the aperture area of ​​each of the plurality of pixel regions.

[0124] The reflection reduction part (120) may be made of a material capable of blocking or absorbing light. For example, the reflection reduction part (120) may be made of an oxide-based black dye and a high-heat-resistant black resin. For example, the reflection reduction part (120) may be a black material, a polyamide, or a light-absorbing material. In this case, the light-absorbing material may include amorphous silicon (a-Si). Amorphous silicon (a-Si) is used to convert solar energy into electrical energy due to its high light absorption rate, and it has the characteristic of having a light absorption rate approximately 100 times higher than that of crystalline silicon. For example, the high-heat-resistant black resin of the reflection reduction part (120) is composed of carbon black surface-treated with silicon (Si) as a base, and may include Si-based oligomers, multifunctional monomers, solvents, and photoinitiators, but is not limited thereto.

[0125] A liquid crystal display panel (10) and a liquid crystal display device including the same according to one embodiment of the present specification can vibrate according to the vibration of a vibration generating unit (130) to generate (or output) one or more of sound (S) and vibration. Since the liquid crystal display device according to one embodiment of the present specification uses the entire surface of the front substrate (100) or the liquid crystal display panel (10) as a diaphragm that generates sound, a wide sound field can be formed, and high-quality sound (S) without distortion can be output to the front direction (FD) of the liquid crystal display panel (10). Furthermore, the liquid crystal display device according to one embodiment of the present specification can provide haptic texture and / or haptic feedback vibration to the user according to the haptic vibration of the vibration generating unit (130) corresponding to user touch. Also, the liquid crystal display device according to one embodiment of the present specification can provide a speaker-integrated liquid crystal display panel (10) capable of outputting sound (S) while displaying an image, can be made slimmer and lighter, and the overall aesthetic appeal of the design can be improved.

[0126] FIG. 6 is a modified version of the vibration generating unit described with reference to FIGS. 1 to 5. Accordingly, in the following description, only the vibration generating unit and related components will be described, and the remaining components will be given the same reference numerals as in FIGS. 4 and FIG. 5, and redundant descriptions thereof will be omitted.

[0127] Referring to FIG. 6, in a liquid crystal display panel (10) or liquid crystal display device according to one embodiment of the present specification, the piezoelectric vibration layer (133) of the vibration generating unit (130) may include two or more piezoelectric layers (133a1, 133a2) and one or more intermediate electrode layers (133b1).

[0128] According to another embodiment of the present specification, the piezoelectric vibration layer (133) of the vibration generating unit (130) may include a first piezoelectric layer (133a1), a second piezoelectric layer (133a2), and an intermediate electrode layer (133b1).

[0129] The first piezoelectric layer (133a1) may be formed on the first electrode layer (131). The first piezoelectric layer (133a1) may be laminated (or bonded) to the first electrode layer (131) so as to have the same shape as the first electrode layer (131). The first piezoelectric layer (133a1) may be in direct contact with the first electrode layer (131).

[0130] The second piezoelectric layer (133a2) may be placed (or interposed) between the first piezoelectric layer (133a1) and the second electrode layer (135). The second piezoelectric layer (133a2) may be laminated (or bonded) to the first piezoelectric layer (133a1) so as to have the same shape as the first piezoelectric layer (133a1). The second piezoelectric layer (133a2) may be in direct contact with the second electrode layer (135).

[0131] An intermediate electrode layer (133b1) may be placed (or interposed) between the first piezoelectric layer (133a1) and the second piezoelectric layer (133a2). The intermediate electrode layer (133b1) may be formed (or laminated) on the first piezoelectric layer (133a1). The intermediate electrode layer (133b1) may be laminated (or bonded) to the first piezoelectric layer (133a1) so as to have the same shape as the first piezoelectric layer (133a1). The intermediate electrode layer (133b1) may be in direct contact with the first piezoelectric layer (133a1).

[0132] The second piezoelectric layer (133a2) may be formed (or laminated) on the intermediate electrode layer (133b1). The second piezoelectric layer (133a2) may be in direct contact with the intermediate electrode layer (133b1).

[0133] The first piezoelectric layer (133a1) and the second piezoelectric layer (133a2) may include a piezoelectric material. The intermediate electrode layer (133b1) may be made of the same conductive material as the first electrode layer (131) and the second electrode layer (135).

[0134] The first piezoelectric layer (133a1) and the second piezoelectric layer (133a2) can be polarized to be displaced (or vibrated or driven) in the same direction.

[0135] The first electrode layer (131) and the second electrode layer (135) can receive a first vibration driving signal. The intermediate electrode layer (133b1) can receive a second vibration driving signal different from the first vibration driving signal. For example, the first vibration driving signal may be a positive polarity vibration driving signal and the second vibration driving signal may be a negative polarity vibration driving signal, but is not limited thereto.

[0136] A vibration generating unit (130) according to another embodiment of the present specification includes two or more piezoelectric layers (133a1, 133a2), so that the amount of displacement or amplitude displacement can be maximized or increased, thereby maximizing or increasing the amount of displacement (or bending force or driving force) or amplitude displacement of the front substrate (100) or liquid crystal display panel (10), and thereby improving the acoustic characteristics and sound pressure characteristics of the low frequency range generated by the vibration of the front substrate (100) or liquid crystal display panel (10).

[0137] FIG. 7 is a drawing for explaining the pad portion described with reference to FIGS. 1 to 6. Accordingly, in the following description, only the pad portion and related components will be described, and the remaining components will be given the same reference numerals as FIGS. 1 to 6, and redundant descriptions thereof will be omitted.

[0138] Referring to FIG. 3 and FIG. 7, in a liquid crystal display panel (10) or liquid crystal display device according to one embodiment of the present specification, the pad portion (170) may include a plurality of pads (171).

[0139] A plurality of pads (171) may be arranged at predetermined intervals along the longitudinal direction of the gate line (GL). A first group of the plurality of pads (171) may be configured to be electrically connected to each of the plurality of data lines (DL). A second group of the plurality of pads (171) may be configured to be electrically connected to the gate control signal line (GCL). A third group of the plurality of pads (171) may be configured to be electrically connected to each of the first electrode layer (131) and the second electrode layer (135) of the vibration generating unit (130).

[0140] Each of the plurality of pads (171) may include a pad electrode line (170a) and a pad electrode (170b).

[0141] A pad electrode line (170a) may be formed (or placed) on a buffer layer (145). A pad electrode line (170a) may be formed (or placed) together with a gate line (GL). A pad electrode line (170a) may be formed (or placed) to be electrically connected to any one of the first electrode layer (131) and the second electrode layer (135) of the vibration generating unit (130), a plurality of data lines (DL), and a gate control signal line (GCL).

[0142] A pad electrode (170b) may be formed (or placed) on an insulating layer (155) of a pixel array layer (150) so as to overlap with a portion of a pad electrode line (170a). The pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through via holes formed in the insulating layer (155), passivation layer (153), interlayer insulating layer (152), and gate insulating layer (151) of the pixel array layer (150). The pad electrode (170b) may be formed (or placed) together with a pixel electrode (PE).

[0143] Each of the plurality of pads (171) may further include an intermediate pad electrode (170c).

[0144] An intermediate pad electrode (170c) may be placed (or interposed) between a portion of the pad electrode line (170a) and the pad electrode (170b). The intermediate pad electrode (170c) may be formed (or placed) on the interlayer insulating layer (152) and may be electrically connected to a portion of the pad electrode line (170a) through via holes formed in the interlayer insulating layer (152) and the gate insulating layer (151). The intermediate pad electrode (170c) may be formed (or placed) together with the data line (DL).

[0145] The pad electrode (170b) can be electrically connected to the intermediate pad electrode (170c) through via holes formed in the insulating layer (155) and the passivation layer (153). Accordingly, the pad electrode (170b) can be electrically connected to the pad electrode line (170a) through the intermediate pad electrode (170c).

[0146] Each of the plurality of pads (171) can be electrically connected to a flexible circuit film (31) of a panel driving circuit (30). The flexible circuit film (31) can be attached to the plurality of pads (171) configured on the substrate (100) by a film attachment process using an anisotropic conductive film.

[0147] In a liquid crystal display panel (10) or liquid crystal display device according to one embodiment of the present specification, a vibration generating unit (130) may be formed (or arranged) to overlap with a pad unit (170). A vibration generating unit (130) may be formed (or arranged) between a front substrate (100) and a pad unit (170). Accordingly, a non-display area (NDA) (or second area) of the front substrate (100) may be utilized as a vibration area (or sound output area) that generates one or more of sound and vibration according to the vibration of the vibration generating unit (130).

[0148] Referring to FIGS. 8 to 10, a vibration generating unit (130) according to one embodiment of the present specification may include a plurality of first lines (130a) and a plurality of second lines (130b).

[0149] A plurality of first lines (130a) may be configured to overlap with each of the plurality of data lines (DL). A plurality of first lines (130a) may have a line width that is relatively wider than each of the plurality of data lines (DL). A plurality of first lines (130a) may be placed (or interposed) between each of the plurality of data lines (DL) and the reflection reduction unit (120).

[0150] A plurality of second lines (130b) may be configured to overlap with each of the plurality of gate lines (GL) and to intersect with the plurality of first lines (130a). The plurality of second lines (130b) may have a line width that is relatively wider than each of the plurality of gate lines (GL). The plurality of second lines (130b) may be placed (or interposed) between each of the plurality of gate lines (GL) and the reflection reduction unit (120).

[0151] A plurality of first lines (130a) and a plurality of second lines (130b) may be arranged on the same layer above the reflection reduction section (120). A plurality of first lines (130a) and a plurality of second lines (130b) may be connected to each other at an intersection area (or intersection section). For example, a plurality of first lines (130a) and a plurality of second lines (130b) may be arranged on the same layer to have a mesh shape connected to each other.

[0152] A vibration generating part (130) according to one embodiment of the present specification may further include a plurality of protrusions (130p).

[0153] Each of the plurality of protrusions (130p) protrudes from the intersection of the plurality of first lines (130a) and the plurality of second lines (130b) and may overlap with the thin-film transistor. Each of the plurality of protrusions (130p) may be placed (or configured) below the thin-film transistor placed in the pixel area.

[0154] Each of the plurality of first lines (130a), plurality of second lines (130b), and plurality of protrusions (130p) includes a first electrode layer (131), a piezoelectric vibration layer (133), and a second electrode layer (135), as described with reference to FIG. 4, so a redundant description thereof is omitted.

[0155] In a vibration generating unit (130) according to one embodiment of the present specification, each end of a plurality of first lines (130a) may be disposed in a pad unit (170) (or pad area). A portion of the first electrode layer (131) disposed at each end of a plurality of first lines (130a) may be exposed for electrical connection with the pad unit (170). For example, by removing both the piezoelectric vibration layer (133) and the second electrode layer (135) disposed on the first electrode layer (131) formed at each end of a plurality of first lines (130a), a portion of the first electrode layer (131) in each of the plurality of first lines (130a) may not be covered by the piezoelectric vibration layer (133) and the second electrode layer (135), but may be covered by a flattening layer (140).

[0156] According to another embodiment of the present specification, the liquid crystal display panel may include a plurality of vibration regions.

[0157] As an example, the liquid crystal display panel may include a left vibration area and a right vibration area, in which case each of the plurality of second lines (130b) may be disconnected (or separated) at the boundary between the left vibration area and the right vibration area of ​​the liquid crystal display panel. Accordingly, the vibration generating unit (130) placed in the left vibration area of ​​the liquid crystal display panel may output left sound according to the vibration, and the vibration generating unit (130) placed in the right vibration area of ​​the liquid crystal display panel may output right sound according to the vibration.

[0158] As another example, the liquid crystal display panel may include an intermediate vibration area between the left vibration area and the right vibration area, in which case each of the plurality of second lines (130b) may be disconnected (or separated) at each of the first boundary of the left vibration area and the intermediate vibration area and the second boundary of the intermediate vibration area and the right vibration area of ​​the liquid crystal display panel. Accordingly, the vibration generating unit (130) placed in the left vibration area of ​​the liquid crystal display panel may output left sound according to the vibration, the vibration generating unit (130) placed in the right vibration area of ​​the liquid crystal display panel may output right sound according to the vibration, and the vibration generating unit (130) placed in the intermediate vibration area of ​​the liquid crystal display panel may output center sound according to the vibration.

[0159] A pad portion (170) according to one embodiment of the present specification may include a plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C).

[0160] A plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C) may be arranged at preset intervals along the length direction of the gate line (GL).

[0161] A plurality of first pads (171A) may be configured to be electrically connected to each of a plurality of data lines (DL). A plurality of first pads (171A) may be individually connected to a plurality of data lines (DL).

[0162] One or more second pads (171B) may be configured to be electrically connected to the first electrode layer (131) of the vibration generating unit (130). One or more second pads (171B) may be configured to be electrically connected to the first electrode layer (131) of one or more of the first lines (130a). For example, the plurality of first lines (130a) may be individually connected to the plurality of second pads (171B), in which case the first vibration driving signal may be uniformly applied to the entire first electrode layer (131) of the vibration generating unit (130).

[0163] One or more third pads (171C) may be configured to be electrically connected to the second electrode layer (135) of the vibration generating unit (130). One or more third pads (171C) may be configured to be electrically connected to the second electrode layer (135) of one or more of the first lines (130a). For example, the plurality of first lines (130a) may be individually connected to the plurality of third pads (171C), in which case the second vibration driving signal may be uniformly applied to the entire second electrode layer (135) of the vibration generating unit (130).

[0164] Each of the plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C) may include a pad electrode line (170a) and a pad electrode (170b).

[0165] Each pad electrode line (170a) of each of the plurality of first pads (171A) may be configured to be electrically connected to the corresponding data line (DL) among the plurality of data lines (DL). For example, each pad electrode line (170a) of each of the plurality of first pads (171A) may be placed on the buffer layer (145) and extended to overlap with a part of the data line (DL), and may be electrically connected to a part of the data line (DL) through a first via hole (VH1) formed in the interlayer insulating layer (152). For example, each pad electrode line (170a) of the plurality of first pads (171A) may have a planar "┛" shape, but is not limited thereto.

[0166] Each pad electrode (170b) of each of the plurality of first pads (171A) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). Each pad electrode (170b) of each of the plurality of first pads (171A) may be electrically connected to a portion of the pad electrode line (170a) through a second via hole (VH2) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). Accordingly, a data signal applied to each of the plurality of first pads (171A) may be applied to the corresponding data line through the pad electrode (170b) and the pad electrode line (170a).

[0167] One or more pad electrode lines (170a) of the second pads (171B) may be configured to be electrically connected to the first electrode layer (131) of one or more of the first lines (130a). For example, one or more pad electrode lines (170a) of the second pads (171B) may be placed on the buffer layer (145) and may be electrically connected to the first electrode layer (131) of the first line (130a) through a third via hole (VH3) formed in the buffer layer (145) and the planarization layer (140). For example, one or more pad electrode lines (170a) of the second pads (171B) may have a planar line shape, but are not limited thereto.

[0168] One or more pad electrodes (170b) of the second pad (171B) may be positioned to overlap with the ends of one or more of the first lines (130a). One or more pad electrodes (170b) of the second pad (171B) may be positioned between the pad electrode (170b) of the first pad (171A) and the pad electrode (170b) of the third pad (171C).

[0169] One or more pad electrodes (170b) of the second pad (171B) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of the second pad (171B) may be electrically connected to a portion of the pad electrode line (170a) through a fourth via hole (VH4) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through a fifth via hole (VH5) formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a first vibration driving signal applied to one or more second pads (171B) can be applied entirely to the first electrode layer (131) of the vibration generating unit (130) through the pad electrode (170b) and the pad electrode line (170a).

[0170] One or more pad electrode lines (170a) of third pads (171C) may be configured to be electrically connected to the second electrode layer (135) of one or more of the first lines (130a). For example, one or more pad electrode lines (170a) of third pads (171C) may be placed on a buffer layer (145) and extended to overlap with a portion of the second electrode layer (135) of the first line (130a), and may be electrically connected to the second electrode layer (135) of the first line (130a) through a sixth via hole (VH6) formed in the buffer layer (145) and the flattening layer (140). For example, one or more pad electrode lines (170a) of third pads (171C) may have a planar "┗" shape, but are not limited thereto.

[0171] One or more pad electrodes (170b) of third pads (171C) may be disposed on one side of the pad electrodes (170b) of one or more second pads (171B). One or more pad electrodes (170b) of third pads (171C) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of third pads (171C) may be electrically connected to a portion of the pad electrode line (170a) through a seventh via hole (VH7) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through an eighth via hole formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a second vibration driving signal applied to one or more third pads (171C) can be applied entirely to the second electrode layer (135) of the vibration generating unit (130) through the pad electrode (170b) and the pad electrode line (170a).

[0172] FIGS. 11 to 13 show a modified structure of the first line of the pad section and vibration generating section described with reference to FIGS. 8 to 10. Accordingly, in the following description, only the modified configuration will be described, and the remaining configurations will be given the same reference numerals as in FIGS. 8 to 10, and redundant descriptions thereof will be omitted. The description of FIGS. 8 to 10 may be included in the description of FIGS. 11 to 13.

[0173] Referring to FIGS. 11 to 13, in a vibration generating unit (130) according to another embodiment of the present specification, a first electrode layer (131), a piezoelectric vibration layer (133), and a second electrode layer (135) of each of a plurality of first lines (130a) may be formed (or arranged) to have the same line width and the same length.

[0174] One or more of the plurality of first lines (130a) may include an electrode protrusion (131p) protruding from the first electrode layer (131).

[0175] The electrode protrusion (131p) can be configured to be exposed without being covered by the piezoelectric vibrating layer (133) and the second electrode layer (135). For example, the piezoelectric vibrating layer (133) and the second electrode layer (135) placed on the electrode protrusion (131p) can be removed. Accordingly, the first electrode layer (131) and the second electrode layer (135) of a plurality of first lines (130a) can be arranged side by side in a planar manner.

[0176] The electrode protrusion (131p) may protrude (or extend) from one side of the end portion of the first electrode layer (131). For example, the end portion of each of the first electrode layer (131) of the plurality of first lines (130a) may have a planar "┓" or "ⓒ" shape due to the electrode protrusion (131p).

[0177] The reflection reduction part (120) may include an extension part (120p) that overlaps with the electrode protrusion part (131p). For example, the end part of the reflection reduction part (120) that overlaps with each of the plurality of first lines (130a) may have a planar "┓" or "ⓒ" shape due to the extension part (120p).

[0178] A pad portion (170) according to another embodiment of the present specification may include a plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C).

[0179] Each of the plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C) may include a pad electrode line (170a) and a pad electrode (170b).

[0180] Each pad electrode line (170a) of each of the plurality of first pads (171A) may be configured to be electrically connected to the corresponding data line (DL) among the plurality of data lines (DL). For example, each pad electrode line (170a) of each of the plurality of first pads (171A) may be placed on the buffer layer (145), extended to overlap with a part of the data line (DL), and electrically connected to a part of the data line (DL) through a first via hole (VH1) formed in the interlayer insulating layer (152). For example, each pad electrode line (170a) of the plurality of first pads (171A) may have a planar "┛" shape, but is not limited thereto.

[0181] Each pad electrode (170b) of each of the plurality of first pads (171A) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). Each pad electrode (170b) of each of the plurality of first pads (171A) may be electrically connected to a portion of the pad electrode line (170a) through a second via hole (VH2) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). Accordingly, a data signal applied to each of the plurality of first pads (171A) may be applied to the corresponding data line through the pad electrode (170b) and the pad electrode line (170a).

[0182] One or more pad electrode lines (170a) of a second pad (171B) may be configured to be electrically connected to the electrode protrusions (131p) of the first electrode layer (131) of one or more of the first lines (130a). For example, one or more pad electrode lines (170a) of a second pad (171B) may be placed on a buffer layer (145) and may be electrically connected to the electrode protrusions (131p) of the first electrode layer (131) of the first line (130a) through via holes formed in the buffer layer (145) and the flattening layer (140). For example, one or more pad electrode lines (170a) of a second pad (171B) may have a planar line shape, but are not limited thereto.

[0183] One or more pad electrodes (170b) of the second pads (171B) may be positioned on one side of one or more of the first lines (130a) among the plurality of first lines (130a). One or more pad electrodes (170b) of the second pads (171B) may be positioned to overlap with the electrode protrusions (131p) of one or more of the first lines (130a) among the plurality of first lines (130a).

[0184] One or more pad electrodes (170b) of the second pads (171B) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of the second pads (171B) may be electrically connected to a portion of the pad electrode line (170a) through a third via hole (VH3) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through via holes formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a first vibration driving signal applied to one or more second pads (171B) can be applied to the first electrode layer (131) of the vibration generating unit (130) entirely through the pad electrode (170b), the pad electrode line (170a), and the electrode protrusion (131p).

[0185] One or more pad electrode lines (170a) of third pads (171C) may be configured to be electrically connected to the second electrode layer (135) of the corresponding first line (130a) among a plurality of first lines (130a). For example, one or more pad electrode lines (170a) of third pads (171C) may be placed on a buffer layer (145) and extended to overlap with a portion of the second electrode layer (135) of the first line (130a), and may be electrically connected to the second electrode layer (135) of the first line (130a) through a fourth via hole (VH4) formed in the buffer layer (145) and the flattening layer (140). For example, one or more pad electrode lines (170a) of third pads (171C) may have a planar line shape, but are not limited thereto.

[0186] One or more pad electrodes (170b) of the third pad (171C) may be positioned to overlap with the ends of one or more of the first lines (130a). One or more pad electrodes (170b) of the third pad (171C) may be positioned between the pad electrode (170b) of the first pad (171A) and the pad electrode (170b) of the second pad (171B).

[0187] One or more pad electrodes (170b) of third pads (171C) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of third pads (171C) may be electrically connected to a portion of the pad electrode line (170a) through a fifth via hole (VH5) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through a sixth via hole (VH6) formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a second vibration driving signal applied to one or more third pads (171C) can be applied entirely to the second electrode layer (135) of the vibration generating unit (130) through the pad electrode (170b) and the pad electrode line (170a).

[0188] According to another embodiment of the present specification, since the electrode protrusion (131p) of the first electrode layer (131) of each of the plurality of first lines (130a) and the second electrode layer (135) are arranged side by side, the width of the pad portion (170) is reduced, and as a result, the width of the non-display area (NDA) can be reduced.

[0189] FIGS. 14 and 15 show a modified structure of the pad section and vibration generating section described with reference to FIGS. 8 to 10. Accordingly, in the following description, only the modified configuration will be described, and the remaining configurations will be given the same reference numerals as in FIGS. 8 to 10, and redundant descriptions thereof will be omitted. The description of FIGS. 8 to 10 may be included in the description of FIGS. 14 and 15.

[0190] Referring to FIG. 14 and FIG. 15, in a vibration generating unit (130) according to another embodiment of the present specification, the piezoelectric vibration layer (133) of the vibration generating unit (130) may include two or more piezoelectric layers (133a1, 133a2) and one or more intermediate electrode layers (133b1). For example, the vibration generating unit (130) may include a first electrode layer (131), a first piezoelectric layer (133a1), an intermediate electrode layer (133b1), a second piezoelectric layer (133a2), and a second electrode layer (135).

[0191] Each of the first electrode layer (131), first piezoelectric layer (133a1), intermediate electrode layer (133b1), second piezoelectric layer (133a2), and second electrode layer (135) of the plurality of first lines (130a) can be formed (or arranged) to have the same line width and the same length.

[0192] Each end of a plurality of first lines (130a) may be placed in a pad portion (170) (or pad area). A portion of the first electrode layer (131) placed at each end of a plurality of first lines (130a) may be exposed for electrical connection with the pad portion (170). For example, a portion of the first electrode layer (131) in each of the plurality of first lines (130a) may be covered by a flattening layer (140) by removing all of the first piezoelectric layer (133a1), intermediate electrode layer (133b1), second piezoelectric layer (133a2), and second electrode layer (135) placed on the first electrode layer (131) formed at each end of a plurality of first lines (130a).

[0193] The first piezoelectric layer (133a1) and the intermediate electrode layer (133b1) of each of the plurality of first lines (130a) may be spaced apart from the end of the first electrode layer (131). A portion of the intermediate electrode layer (133b1) of each of the plurality of first lines (130a) may be exposed for electrical connection with the pad portion (170). For example, a portion of the intermediate electrode layer (133b1) in each of the plurality of first lines (130a) may be covered by a flattening layer (140) by removing both the second piezoelectric layer (133a2) and the second electrode layer (135) placed on the intermediate electrode layer (133b1) spaced apart from the end of the first electrode layer (131) of each of the plurality of first lines (130a).

[0194] Each intermediate electrode layer (133b1) of a plurality of first lines (130a) is exposed between the first electrode layer (131) and the second electrode layer (135), and can be covered by a flattening layer (140) without being covered by the second piezoelectric layer (133a2) and the second electrode layer (135).

[0195] A pad portion (170) according to another embodiment of the present specification may include a plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C).

[0196] A plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C) may be arranged at preset intervals along the length direction of the gate line (GL).

[0197] A plurality of first pads (171A) may be configured to be electrically connected to each of a plurality of data lines (DL). A plurality of first pads (171A) may be individually connected to a plurality of data lines (DL).

[0198] One or more second pads (171B) may be configured to be commonly connected to the first electrode layer (131) and the second electrode layer (135) of the vibration generating unit (130). One or more second pads (171B) may be configured to be commonly connected to the first electrode layer (131) and the second electrode layer (135) of each of the plurality of first lines (130a). For example, the plurality of first lines (130a) may be individually connected to the plurality of second pads (171B), in which case the first vibration driving signal may be uniformly applied to the entire first electrode layer (131) and the second electrode layer (135) of the vibration generating unit (130).

[0199] One or more third pads (171C) may be configured to be electrically connected to the intermediate electrode layer (133b1) of the vibration generating unit (130). One or more third pads (171C) may be configured to be electrically connected to the intermediate electrode layer (133b1) of each of the plurality of first lines (130a). For example, the plurality of first lines (130a) may be individually connected to the plurality of third pads (171C), in which case the second vibration driving signal may be uniformly applied to the entire intermediate electrode layer (133b1) of the vibration generating unit (130).

[0200] Each of the plurality of first pads (171A), one or more second pads (171B), and one or more third pads (171C) may include a pad electrode line (170a) and a pad electrode (170b).

[0201] Each pad electrode line (170a) of each of the plurality of first pads (171A) may be configured to be electrically connected to the corresponding data line (DL) among the plurality of data lines (DL). For example, each pad electrode line (170a) of each of the plurality of first pads (171A) may be placed on the buffer layer (145), extended to overlap with a part of the data line (DL), and electrically connected to a part of the data line (DL) through a first via hole (VH1) formed in the interlayer insulating layer (152). For example, each pad electrode line (170a) of the plurality of first pads (171A) may have a planar "┛" shape, but is not limited thereto.

[0202] Each pad electrode (170b) of each of the plurality of first pads (171A) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). Each pad electrode (170b) of each of the plurality of first pads (171A) may be electrically connected to a portion of the pad electrode line (170a) through a second via hole (VH2) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). Accordingly, a data signal applied to each of the plurality of first pads (171A) may be applied to the corresponding data line through the pad electrode (170b) and the pad electrode line (170a).

[0203] One or more pad electrode lines (170a) of the second pads (171B) may be configured to be commonly connected to the first electrode layer (131) and the second electrode layer (135) of one or more of the first lines (130a). For example, one or more pad electrode lines (170a) of the second pads (171B) may be placed on the buffer layer (145) and electrically connected to the first electrode layer (131) of the first line (130a) through a third via hole (VH3) formed in the buffer layer (145) and the flattening layer (140), and at the same time electrically connected to the second electrode layer (135) of the first line (130a) through a fourth via hole (VH4). One side of the pad electrode line (170a) of the second pad (171B) may be electrically connected to the first electrode layer (131) of the first line (130a) through the third via hole (VH3), and the other side of the pad electrode line (170a) of the second pad (171B) may be electrically connected to the second electrode layer (135) of the first line (130a) through the fourth via hole (VH4). An intermediate portion between one side and the other side of the pad electrode line (170a) of the second pad (171B) may be positioned between the first line (130a) and the pad electrode line (170a) of the first pad (171A). For example, one or more pad electrode lines (170a) of the second pad (171B) may have a planar "⊃" shape, but are not limited thereto.

[0204] One or more pad electrodes (170b) of the second pad (171B) may be positioned to overlap with the ends of one or more of the first lines (130a). One or more pad electrodes (170b) of the second pad (171B) may be positioned between the pad electrode (170b) of the first pad (171A) and the pad electrode (170b) of the third pad (171C).

[0205] One or more pad electrodes (170b) of the second pad (171B) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of the second pad (171B) may be electrically connected to a portion of the pad electrode line (170a) through a fifth via hole (VH5) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through a sixth via hole (VH6) formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a first vibration driving signal applied to one or more second pads (171B) can be applied to the first electrode layer (131) and the second electrode layer (135) of the vibration generating unit (130), respectively, through the pad electrode (170b) and the pad electrode line (170a), either entirely (or commonly).

[0206] One or more pad electrode lines (170a) of third pads (171C) may be configured to be electrically connected to an intermediate electrode layer (133b1) of one or more of the first lines (130a). For example, one or more pad electrode lines (170a) of third pads (171C) may be placed on a buffer layer (145) and extended to overlap a portion of the intermediate electrode layer (133b1) of the first line (130a), and may be electrically connected to the intermediate electrode layer (133b1) of the first line (130a) through a sixth via hole (VH6) formed in the buffer layer (145) and the flattening layer (140). For example, one or more pad electrode lines (170a) of third pads (171C) may have a planar "┗" shape, but are not limited thereto.

[0207] One or more pad electrodes (170b) of third pads (171C) may be disposed on one side of the pad electrodes (170b) of one or more second pads (171B). One or more pad electrodes (170b) of third pads (171C) may be formed (or disposed) on the insulating layer (155) of the pad region and configured to be electrically connected to the pad electrode line (170a). One or more pad electrodes (170b) of third pads (171C) may be electrically connected to a portion of the pad electrode line (170a) through a seventh via hole (VH7) formed in the insulating layer (155), the passivation layer (153), the interlayer insulating layer (152), and the gate insulating layer (151). For example, the pad electrode (170b) may be electrically connected to a portion of the pad electrode line (170a) through an intermediate pad electrode (170c). The intermediate pad electrode (170c) can be electrically connected to a portion of the pad electrode line (170a) through an eighth via hole formed in the interlayer insulating layer (152) and the gate insulating layer (151). Accordingly, a second vibration driving signal applied to one or more third pads (171C) can be applied entirely to the intermediate electrode layer (133b1) of the vibration generating unit (130) through the pad electrode (170b) and the pad electrode line (170a).

[0208] It will be obvious to those skilled in the art to which this specification belongs that the above-described specification is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of this specification. Explanation of the symbols

[0209] 10: Liquid crystal display panel 30: Panel driving circuit 100: Front board 110: Base board 120: Reflection reduction unit 130: Vibration generation unit 140: Flattening layer 150: Pixel array layer 170: Pad section 200: Rear circuit board 230: Color filter layer 300: Liquid crystal layer

Claims

Claim 1 A liquid crystal display panel comprising: a front substrate including a plurality of pixel regions; a rear substrate including a color filter corresponding to each of the plurality of pixel regions; and a liquid crystal layer located between the front substrate and the rear substrate, wherein the front substrate comprises: a base substrate; a vibration generating part configured on the base substrate; a flattening layer covering the vibration generating part; and a pixel array layer configured on the flattening layer. Claim 2 In claim 1, the vibration generating part comprises a piezoelectric vibration layer comprising a piezoelectric material, a liquid crystal display panel. Claim 3 A liquid crystal display panel according to claim 1, wherein the vibration generating part comprises: a first electrode layer configured on the base substrate; a piezoelectric vibration layer comprising a piezoelectric material configured on the first electrode layer; and a second electrode layer configured on the piezoelectric vibration layer. Claim 4 A liquid crystal display panel according to claim 1, wherein the pixel array layer is configured on the planarization layer to intersect each other and includes a plurality of gate lines and a plurality of data lines defining the plurality of pixel regions, and the vibration generating unit is configured to overlap with the plurality of gate lines and the plurality of data lines. Claim 5 In claim 4, the vibration generating unit comprises: a plurality of first lines superimposed with each of the plurality of data lines; and a plurality of second lines superimposed with each of the plurality of gate lines and intersecting with the plurality of first lines, forming a liquid crystal display panel. Claim 6 In claim 5, the plurality of first lines and the plurality of second lines are arranged on the same layer to have a mesh shape connected to each other, forming a liquid crystal display panel. Claim 7 In claim 5, each of the plurality of first lines and the plurality of second lines comprises: a first electrode layer formed on the base substrate; a piezoelectric vibration layer comprising a piezoelectric material formed on the first electrode layer; and a second electrode layer formed on the piezoelectric vibration layer, wherein the liquid crystal display panel. Claim 8 In claim 7, the pixel array layer further comprises: a plurality of thin-film transistors configured in each of the plurality of pixel regions and connected to adjacent data lines and adjacent gate lines; a plurality of pixel electrodes configured in each of the plurality of pixel regions and connected to the corresponding thin-film transistors among the plurality of thin-film transistors; and a common electrode superimposed with the plurality of pixel electrodes, forming a liquid crystal display panel. Claim 9 In claim 8, the liquid crystal display panel, wherein the common electrode is divided into a plurality of touch electrodes that overlap with one or more of the plurality of pixel regions. Claim 10 In claim 8, the vibration generating portion protrudes from the intersection of the plurality of first lines and the plurality of second lines and includes a plurality of protrusions superimposed on each of the plurality of thin-film transistors, and each of the plurality of protrusions includes the first electrode layer, the piezoelectric vibration layer, and the second electrode layer, a liquid crystal display panel. Claim 11 In claim 7, the front substrate further comprises: a first region superimposed with the rear substrate; a second region extending from the first region; and a pad portion configured in the second region, wherein the vibration generating portion is configured to superimpose with the pad portion, a liquid crystal display panel. Claim 12 A liquid crystal display panel according to claim 11, wherein the pad portion comprises: a plurality of first pads electrically connected to each of the plurality of data lines; one or more second pads electrically connected to the first electrode layer of one or more of the plurality of first lines; and one or more third pads electrically connected to the second electrode layer of one or more of the plurality of first lines. Claim 13 In claim 12, the vibration generating part further comprises an electrode protrusion protruding from one side of the first electrode layer of one or more of the plurality of first lines, and the one or more second pads are electrically connected to the electrode protrusion, a liquid crystal display panel. Claim 14 In claim 11, the piezoelectric vibrating layer comprises two or more piezoelectric layers configured between the first electrode layer and the second electrode layer; and one or more intermediate electrode layers configured between the two or more piezoelectric layers, forming a liquid crystal display panel. Claim 15 In claim 14, the pad portion comprises: a plurality of first pads electrically connected to each of the plurality of data lines; one or more second pads commonly connected to the first electrode layer and the second electrode layer of one or more of the plurality of first lines; and one or more third pads electrically connected to the intermediate electrode layer of one or more of the plurality of first lines, a liquid crystal display panel. Claim 16 A liquid crystal display panel according to any one of claims 1 to 15, further comprising a reflection reduction member disposed between the base substrate and the vibration generating member, wherein the reflection reduction member is made of a light-blocking material and has the same shape in planar relation to the vibration generating member. Claim 17 A liquid crystal display device comprising: a liquid crystal display panel according to any one of claims 1 to 15; a backlight unit for irradiating light onto the liquid crystal display panel; and a panel driving circuit connected to the liquid crystal display panel. Claim 18 In claim 17, the liquid crystal display panel further comprises a reflection reduction member disposed between the base substrate and the vibration generating member, wherein the reflection reduction member is made of a light-blocking material and has the same shape in planar relation to the vibration generating member, a liquid crystal display device. Claim 19 In claim 17, the liquid crystal display device, wherein the panel driving circuit includes an amplifier circuit that applies a vibration driving signal to the vibration generating part configured in the liquid crystal display panel. Claim 20 A liquid crystal display device according to claim 19, wherein the vibration generating part is displaced according to the vibration driving signal, and the front substrate vibrates according to the displacement of the vibration generating part to generate one or more of acoustic and haptic vibrations.

Images