Backside contacts used to form a gate tie-down

Abstract

A technique for forming an integrated circuit having a back conductive contact as part of a gate tie-down structure is provided herein. A back cavity below a gate structure and an adjacent source region may be formed using back lithography and anisotropic etching. The back cavity is then filled with a conductive material to form a back contact. A semiconductor device comprises a gate structure around or otherwise on a semiconductor region extending from a first source region to a second source or drain region. A substrate below the semiconductor device is removed and replaced with a back dielectric material. A lithography operation on the back dielectric material may be performed in conjunction with one or more anisotropic etchings to form a first cavity below the gate structure and a second cavity below the first source region. A back conductive contact is then formed within the back cavity.

Description

Background Technology

[0001] As the size of integrated circuits continues to decrease, many challenges arise. For example, reducing the size of memory and logic cells within interconnect structures is becoming increasingly difficult, just as reducing device spacing in device layers is becoming more challenging. Due to the small size of transistor elements such as the transistor gate, source, or drain, it can be difficult to provide effective contact while maintaining the required operating speed and power requirements. Therefore, several non-obvious challenges remain regarding the formation of these high-density semiconductor devices. Brief explanation of the drawing

[0002] FIGS. 1a and FIGS. 1b are cross-sectional views of different semiconductor devices in an integrated circuit comprising at least one gate tie-down device using a back contact according to some embodiments of the present disclosure. FIGS. 2a and FIGS. 2o are cross-sectional views illustrating different steps in an exemplary process for forming an integrated circuit having a rear-coupled gate tie-down structure according to some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional view of a chip package comprising one or more semiconductor dies according to some embodiments of the present disclosure. FIG. 4 is a flowchart of a manufacturing process for a semiconductor device having at least one back-coupled gate tie-down structure according to an embodiment of the present disclosure. FIG. 5 illustrates a computing system comprising one or more integrated circuits as described in various ways in this specification according to embodiments of the present disclosure. The following detailed description will proceed with reference to exemplary embodiments, but many alternatives, modifications, and variations of the present disclosure will be apparent in light of the present disclosure. As further understood, the drawings are not necessarily drawn to scale or are not intended to limit the present disclosure to the specific configurations depicted. For example, while some drawings generally depict perfectly straight, right-angled, and smooth surfaces, actual implementations of integrated circuit structures may not be perfectly straight and right-angled considering the actual limitations of the processing equipment and techniques used (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies or otherwise be non-smooth. Specific details for implementing the invention

[0003] The present specification provides a technique for forming an integrated circuit having one or more gate tie-down structures formed using back contacts. According to some embodiments, a back cavity located beneath both the gate structure and its adjacent source region is formed using back lithography and anisotropic etching. The back cavity is then filled with a conductive material to form back contacts beneath both the gate and the adjacent source region. The technique can be used for any number of integrated circuit applications and is particularly useful for logic and memory cells, such as cells using finFETs, gate-all-around transistors (e.g., ribbonFETs and nanowire FETs), or forksheet transistors. In an example, the semiconductor device includes a gate structure around or on a semiconductor region. The semiconductor region may be, for example, a fin of semiconductor material extending from the source region to the drain region, or one or more nanowires, nanoribbons, or nanosheets of semiconductor material extending from the source region to the drain region. The substrate beneath the semiconductor device may be removed from the back to expose a sub-fin region beneath the semiconductor region. The sub-pin region can be removed using back-side etching and replaced with a dielectric material. A lithography operation on any back-side dielectric material can be performed with anisotropic etching through the back-side dielectric material to form a first cavity that exposes the lower surface of a given gate structure and a second cavity that exposes the lower surface of an adjacent source region. One or more conductive materials can be formed within the first and second cavities to create back-side contacts. A back-side conductive layer can be used to short-circuit the back-side contacts together, which effectively blocks the transistor and acts as an electrical insulating structure. Numerous variations and embodiments will be apparent from the present disclosure.

[0004] General Overview

[0005] As previously mentioned, several non-obvious challenges remain regarding integrated circuit manufacturing. For example, it is important to isolate semiconductor devices from one another to provide desired circuit and logic arrangements. Several different isolation structures and techniques are used to provide electrical isolation. One such structure is a fin isolation structure that electrically isolates different parts of a semiconductor fin. Since several devices can be formed along the length of a single fin, fin isolation structures can be used to isolate devices along the fin. A fin isolation structure typically comprises dielectric material formed within a trench that penetrates a given fin and extends perpendicularly to the length of the fin. However, the etching process used to form the trench, which is later filled with dielectric material, can undergo significant deformation across a given die, which may require over-etching in certain areas to ensure the isolation structure extends through the entire height of the device. Over-etching can damage other semiconductor features, such as spacer structures, leading to device degradation or inoperability.

[0006] Another type of isolation structure is the gate tie-down, which involves a transistor where the gate is electrically shorted to the source region. This forms a dummy gate structure that is permanently 'off', providing electrical isolation between devices on both sides of the dummy gate structure. However, adding more front contacts to the gate and source regions to form this gate tie-down increases routing complexity for front interconnects and creates an inefficient routing design.

[0007] Accordingly, according to embodiments of the present disclosure, a technique is provided herein for directly etching a cavity through one or more back dielectric materials using a lithographic operation to expose the lower surfaces of a predetermined transistor gate and source region. The cavity may then be filled with any number of conductive materials to form a first back contact below the gate structure and a second back contact below the source region. According to some embodiments, a reactive ion etching (RIE) treatment may be used on the back to expose the lower surfaces of the gate structure and source region, which creates a back cavity having inwardly tapered sidewalls. Due to this tapering, the width of the resulting back contact is also tapered. In one example, the lower surface of the first back contact (e.g., away from the gate structure) is wider than the width of the first back contact at the lower surface of the gate structure (e.g., at least 3 nm wider). The location of the first back contact can be lithographically patterned to be within the width of the gate structure, which may be, for example, less than 30 nm, e.g., between 15 nm and 25 nm. Similarly, the location of the second back contact can be lithographically patterned to be within the width of the source region, which may also be, for example, less than 30 nm. In some other embodiments, the first back contact below the gate structure is formed using back lithography, whereas the second back contact below the source region is formed using a self-alignment process. For example, the self-alignment process uses a sacrificial material formed below the source region during front processing, which is later removed from the back to form a self-alignment cavity below the source region. The second contact is then formed within the self-alignment cavity.

[0008] According to an embodiment, the integrated circuit comprises a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction above the semiconductor region, a gate structure, a dielectric structure below the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region, and a conductive layer below the dielectric structure. Both the first back conductive contact and the second back conductive contact are in direct contact with the conductive layer.

[0009] According to another embodiment, the electronic device comprises a chip package having one or more dies. At least one of the one or more dies comprises a semiconductor region extending in a first direction from a first source region to a second source or drain region, a gate structure extending in a second direction different from the first direction over the semiconductor region, a dielectric structure below the gate structure, the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, and a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region. The first back conductive contact has a width tapered along the first direction such that the first width of the first back conductive contact at the lower surface of the dielectric structure is greater than the second width of the first back conductive contact at the lower surface of the gate structure.

[0010] According to another embodiment, a method for forming an integrated circuit comprises the steps of: forming a pin comprising a semiconductor material—the pin extends over a substrate—; forming a dielectric layer adjacent to a sub-pin of the pin; forming a sacrificial gate and spacer structure on the pin; removing a portion of the pin not covered by the sacrificial gate and spacer structure; forming source and drain regions on the exposed end of the semiconductor material and on the sub-pin; replacing the sacrificial gate with a gate structure; removing a portion of the substrate from the back of the integrated circuit; removing the sub-pin from the back and replacing the sub-pin with a dielectric filler; etching a first cavity through the dielectric filler so that the lower surface of the gate structure is exposed within the first cavity; etching a second cavity through the dielectric filler so that the lower surface of the source region is exposed within the second cavity—the second cavity is adjacent to the first cavity—; and forming a first conductive contact in the first cavity and forming a second conductive contact in the second cavity.

[0011] According to another embodiment, the integrated circuit comprises a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction over the semiconductor region, a dielectric structure below the gate structure, the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, and a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region. The distance along the first direction between the first back conductive contact and the second back conductive contact is, for example, less than 10 nm.

[0012] The technique may be used with any type of non-planar transistor, including, for example, finFETs (sometimes called double-gate transistors or tri-gate transistors), nanowire and nanoribbon transistors (sometimes called gate-all-around transistors), or stacked versions of any of these architectures. The source and drain regions may be, for example, doped portions of a specific fin or substrate or epitaxial region deposited during the etching and replacement source / drain formation process. The type of dopant within the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure may be implemented by a gate-first process or a gate-last process (sometimes called a replacement metal gate (RMG) process), or any other gate formation process. Any number of semiconductor materials may be used to form the transistor, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0013] The use of the techniques and structures provided herein may be detected using tools such as several suitable exemplary analytical tools, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), electron microscopy including nanobeam electron diffraction (NBD or NBED) and reflection electron microscopy (REM), composite mapping, X-ray crystallography or diffraction (XRD), energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SIMS), atomic probe imaging or tomography, local electrode atomic probe (LEAP) techniques, 3D tomography, or high-resolution physical or chemical analysis. For example, in some exemplary embodiments, these tools may indicate the presence of back contacts beneath one or more gate structures and beneath source regions adjacent to one or more gate structures, wherein at least the back contacts formed beneath the gate structures have a tapered profile indicating a back RIE process (e.g., the width of the contacts gradually decreases as they rise toward the lower surface of the gate structures). According to some embodiments, a rear conductive layer is present to short-circuit a plurality of rear contacts.

[0014] It should be readily understood that the terms “on” and “up” in this disclosure should be interpreted in the broadest sense to include not only the meaning of “immediately above” something, but also the meaning of being above something having an intermediate feature or layer between them. Additionally, spatially relative terms such as “below,” “below,” “lower,” “on,” “upper,” “top,” “bottom,” etc., may be used in this specification for convenience of explanation to describe the relationship of one element or feature to other element(s) or feature(s) shown in the drawings. Spatially relative terms are intended to include other directions of the device in use or operation in addition to the directions shown in the drawings. The device may be oriented otherwise (rotated 90 degrees or in other directions), and the spatially relative terms used in this specification may be interpreted accordingly.

[0015] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A monolayer is a layer composed of a single atomic layer of a given material. A layer may extend across the entire structure below or above, or may have a scale smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure, and the layer may have a thickness thinner than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes in between. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether planar or curved) with a relatively uniform thickness across the entire layer. When multiple layers formed of the same material (e.g., the same dielectric material) are formed on top of each other, they may be collectively referred to as a single layer.

[0016] The “compositionally different” or “compositionally distinct” materials used herein refer to two materials having different chemical compositions. These compositional differences may be due to, for example, a component present in one material but not in the other (e.g., SiGe is compositionally different from silicon), or because one material is identical in composition to another material but the concentration of at least one of these components in one material is intentionally provided differently from that of the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different from SiGe having 25 atomic percent germanium). In addition to this diversity of chemical compositions, the materials may have distinct dopants (e.g., gallium and magnesium), or they may have the same dopant but at different concentrations. In another embodiment, compositionally distinct materials may further refer to two materials having different crystallographic orientations. For example, (110) silicon is compositionally distinct or different from (100) silicon. For example, stacks with different orientations can be created using blanket wafer layer transfer. If the two materials are fundamentally different, one of the materials has a component that is not present in the other.

[0017] Architecture

[0018] FIG. 1a is a cross-sectional view taken through a semiconductor device (101) along a ‘fin’ direction according to an embodiment of the present disclosure, illustrating a semiconductor body extending between the source or drain regions of each semiconductor device. Each semiconductor device may be a non-planar metal oxide semiconductor (MOS) transistor, such as, for example, a tri-gate (e.g., finFET) or a gate all-around (GAA) transistor, but other transistor topologies and types may also benefit from the techniques provided herein. An example of the present specification illustrates a semiconductor device having a GAA structure (e.g., having a nanoribbon, nanowire, or nanosheet extending between the source and drain regions). Other examples may have a fork sheet structure having a p-type device and an n-type device separated by a dielectric spine or structure. Any of the semiconductor devices (101) may be a p-channel device (e.g., PMOS) or an n-channel device (e.g., NMOS).

[0019] The semiconductor material used for each semiconductor device may be formed on or on a semiconductor substrate. According to some embodiments, the substrate is removed after all topside processing is completed and replaced with a base dielectric layer (102). The base dielectric layer (102) may represent any number of dielectric layers and / or materials. In some examples, the base dielectric layer (102) comprises one or more silicon dioxide layers.

[0020] One or more semiconductor regions of the device may include fins that may be intrinsic to the substrate (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate, for example. Alternatively, the fins may be formed from a material deposited on the substrate. In one of these exemplary cases, a blanket layer of SiGe may be deposited on a silicon substrate, then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another embodiment, the fins may include alternating material layers (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires, nanoribbons, and nanosheets during a gate formation process, and one type of alternating layer may be selectively etched away to release another type of alternating layer within the channel region during the gate formation process, so that a gate all-around process or a forksheet gate process may be performed. Again, in some examples, the alternating layer may be blanket-deposited and then etched into a fin or deposited within a fin-shaped trench.

[0021] A semiconductor device (101) comprises one or more semiconductor regions (also referred to as channel regions), such as one or more nanoribbons (104), extending between epitaxial source or drain regions (106a–106d) (collectively referred to as source or drain regions (106)) in a first direction. Either of the source or drain regions (106) may serve as a source region or drain region depending on the application and dopant profile. Any semiconductor material suitable for the source and drain regions (e.g., Group IV and Group III-V semiconductor materials) may be used for any of the illustrated source or drain regions (106). In such cases, the composition and doping of the source or drain regions (106) may be the same or different depending on the polarity of the transistor. In an example, a p-channel device has a high concentration of p-type dopants in the associated source or drain region (106), and an n-channel device has a high concentration of n-type dopants in the associated source or drain region (106). An exemplary p-type dopant includes boron, and an exemplary n-type dopant includes phosphorus or arsenic. Any number of source and drain configurations and materials may be used. In some examples, the p-type source or drain region (106) includes silicon germanium doped with boron, and the n-type source or drain region (106) includes silicon doped with phosphorus.

[0022] The gate structure extends over the nanoribbon (104) of each semiconductor device (101) in a second direction (e.g., in and out of the page) to form the transistor gate of each corresponding semiconductor device (101). Each gate structure may include a corresponding gate electrode (108) and a gate dielectric (109). According to some embodiments, the gate electrode (108) may consist of a conductive filler and one or more metal work function layers. The gate dielectric (109) may represent any number of dielectric layers. The conductive filler may include any sufficiently conductive material such as a metal, a metal alloy, or doped polysilicon. In some examples, the conductive filler includes tungsten (W), but other metals or conductive materials such as aluminum (Al), molybdenum (Mo), ruthenium (Ru), cobalt (Co), or doped polysilicon may be used. In some embodiments, the p-channel device has a gate electrode (108) having one or more work function layers of tantalum nitride (TaN) and / or tungsten (W). In some embodiments, the n-channel device has a gate electrode (108) having one or more work function layers of titanium aluminum carbide.

[0023] The gate dielectric (109) may comprise any suitable gate dielectric material(s). In some embodiments, the gate dielectric (109) comprises a layer of a natural oxide material (e.g., silicon dioxide, germanium dioxide, or SiGe oxide) on a nanoribbon (104), and a layer of a high-dielectric constant (high-k) dielectric material (e.g., hafnium oxide or aluminum oxide) on the natural oxide.

[0024] According to some embodiments, a spacer structure (110) and an internal spacer (112) are present along the sidewall of a gate structure (108). The spacer structure (110) and the internal spacer (112) may be any suitable dielectric material, such as silicon nitride, and provide separation between a given gate structure and an adjacent source or drain region (106). The internal spacer (112) may separate adjacent nanoribbons (104) from each other along a third direction (e.g., a vertical direction).

[0025] According to some embodiments, a dielectric filler (114) may be present over a source or drain region (106) within a corresponding source / drain trench of a semiconductor device (101). The upper surface of the dielectric filler (114) may be substantially coplanar with the upper surface of the spacer structure (110). In some examples, the dielectric filler (114) may comprise any suitable dielectric material, such as silicon dioxide.

[0026] According to some embodiments, any number of front contacts (116) are provided through a dielectric filler (114) to contact the upper portion of the source or drain region (106). The front contacts (116) may comprise any suitable conductive material such as tungsten, molybdenum, ruthenium, cobalt, or other metals. The front contacts (116) may all be formed during the same metal deposition process(s) to comprise the same conductive material.

[0027] According to some embodiments, one or more of the source or drain regions (106) have a dielectric cap (118) on their lower surface. The dielectric cap (118) may extend through a portion of the base dielectric layer (102). The dielectric cap (118) may comprise any suitable dielectric material that can directly contact the lowermost surface of their corresponding source or drain regions (106) and has sufficient etching selectivity for the dielectric material of the base dielectric layer (102). Exemplary materials for the dielectric cap (118) include silicon nitride or silicon oxynitride. The dielectric cap (118) and the base dielectric layer (102) together may be part of a base dielectric structure at the bottom of the semiconductor device. Thus, the base dielectric structure may comprise any number of different dielectric layers and / or materials.

[0028] According to some embodiments, a first rear contact (120) is provided on the underside of a corresponding gate structure. In the illustrated example, the first rear contact (120) is in direct contact with the lower surface of the intermediate gate electrode (108). The first rear contact (120) may comprise any of the same materials described above for the front contact (116). In some examples, the first rear contact (120) and the front contact (116) comprise the same conductive material. According to some embodiments, additional dielectric layers and conductive elements may be formed on the underside of the base dielectric layer (102) to form a rear interconnect structure (e.g., a power transfer network and / or a signal routing network).

[0029] According to some embodiments, the first dielectric liner (122) is present around a portion of the first back contact (120), such as between the first back contact (120) and the base dielectric layer (102). The first dielectric liner (122) may be formed within the back cavity before the formation of the first back contact (120), so that the first back contact (120) is punched through a portion of the first dielectric liner (122) to contact the bottom of the gate structure. In some embodiments, the first back contact (120) is also punched through the gate dielectric (109) to make direct contact with the gate electrode (108). The first dielectric liner (122) may be any suitable dielectric material such as silicon nitride, silicon oxycarbon nitride, aluminum oxide, or titanium nitride. The first dielectric liner (122) may have a thickness of, for example, less than 5 nm, or between 1 nm and 3 nm.

[0030] According to some embodiments, the width of the first back contact (120) tapers inward as it rises toward the lower surface of the gate electrode (108). As previously mentioned, this tapering may be caused by a back RIE process to form a cavity in the lower part of the gate structure. In some examples, the first width (w1) of the first back contact (120) along the first direction on the lower surface of the base dielectric layer (102) is, for example, at least 3 nm larger than the second width (w2) of the first back contact (120) along the first direction on the lower surface of the gate structure. The first back contact (120) is lithographically aligned to be seated on the lower surface of the gate structure and has a width (w3) of less than 30 nm along the first direction, for example, between 15 nm and 25 nm.

[0031] According to some embodiments, a second rear contact (124) is provided below a source region (106b) adjacent to a gate structure having a first rear contact (120). In the illustrated example, the second rear contact (124) contacts the lower surface of the source region (106b) and extends into the source region (106b). The second rear contact (124) may comprise any of the same material previously mentioned for the first rear contact (120). In some examples, the first rear contact (120) and the second rear contact (124) comprise the same conductive material.

[0032] According to some embodiments, a second dielectric liner (126) is present around a portion of the second rear contact (124), such as between the second rear contact (124) and the base dielectric layer (102). The second dielectric liner (126) may be formed within the rear cavity before the formation of the second rear contact (124), so that the second rear contact (124) contacts the source region (106b) by punching through a portion of the second dielectric liner (126). The second dielectric liner (126) may have any of the same material as previously mentioned for the first dielectric liner (122) and may have the same range of thickness.

[0033] According to some embodiments, the first back contact (120) and the second back contact (124) are both short-circuited together using a back conductive line (128). The back interconnect layer may include a back dielectric layer (130) and a back conductive line (128). The back conductive line (128) may include any suitable conductive material such as tungsten, molybdenum, ruthenium, cobalt, or other metals. In some embodiments, the back interconnect layer is a single layer of a back interconnect region that may include any number of similar interconnect layers to route signals and power to various transistor elements. In the illustrated example, the gate electrode (108) and the source region (106b) of the intermediate semiconductor device (101) are short-circuited to effectively bias the intermediate semiconductor device (101) to an "off" state, so that the device acts as an electrical insulating structure between adjacent semiconductor devices (101) along the first direction. For example, the leftmost device (101) may have a drain region (106a) and a source region (106b), whereas the rightmost device has a drain region (106c) and a source region (106d). The middle device (101) does not operate as a switching transistor due to a short circuit between its gate and source.

[0034] Other circuit designs or applications may have source or drain regions arranged differently. For example, FIG. 1b illustrates an example where the device (101) at both ends of the intermediate device (101) has sources on both sides of the intermediate device (101). In other words, the leftmost device (101) has a drain region (106a) and a source region (106b), and the rightmost device has a drain region (106d) and a source region (106c). In this arrangement, both source regions (106b and 106c) may be shorted to the gate of the intermediate device. Thus, according to the embodiment, a third rear contact (132) is provided to contact the lower part of the source region (106c). The third rear contact (132) may be similar to the second rear contact (124) discussed earlier.

[0035] In either structure illustrated in FIG. 1a or 1b, the intermediate semiconductor "dummy" device (101) may have a relatively higher threshold voltage (Vt) compared to the neighboring "active" transistor. The threshold voltage may be higher to reduce leakage current across the nanoribbon (104) of the intermediate device (101). Several techniques may be used to increase the threshold voltage of the device. In one example, a different gate electrode material, such as a different work function metal, may be used for the intermediate device to increase Vt compared to other devices that cause an increase in Vt. In another example, a counter-dopant may be injected into the nanoribbon (104) of the intermediate device to reduce leakage current. For example, if the source region (106b) and the source or drain region (106c) contain an n-type dopant, a p-type dopant may be injected into the nanoribbon (104) of the intermediate device, and vice versa.

[0036] Manufacturing methodology

[0037] FIGS. 2a through 2o include cross-sectional views collectively illustrating an exemplary process for forming an integrated circuit composed of a gate structure and a back contact below an adjacent source region according to some embodiments of the present disclosure. FIGS. 2a through 2o show cross-sectional views similar to the cross-sectional view of FIG. 1a across a series of semiconductor devices. The illustrated structure evolves as the process flow continues to reach the structure illustrated in FIG. 2n, which is similar to the structure illustrated in FIG. 1a. Such a structure may be part of an entire integrated circuit (e.g., a processor or memory chip) comprising, for example, digital logic cells and / or memory cells and analog mixed-signal circuits. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit comprising other integrated circuits not illustrated. While exemplary materials and process parameters are given, other materials and process parameters may also be used as will be known from consideration of the present disclosure. Although only two back contacts are shown in the manufacturing process, it should be understood that any number of back contacts can be formed across the integrated circuit using the same process described here.

[0038] FIG. 2a illustrates a cross-sectional view taken through a substrate (201) having a series of material layers formed on the substrate (201) according to an embodiment of the present disclosure. An alternating material layer comprising a sacrificial layer (202) and a semiconductor layer (204) may be deposited on the substrate (201). The alternating layer is used to form a GAA transistor structure. Any number of alternating sacrificial layers (202) and semiconductor layers (204) may be deposited on the substrate (201).

[0039] For example, the substrate (201) may be a bulk substrate comprising a Group IV semiconductor material (such as silicon, germanium, or SiGe), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which a transistor can be formed. Alternatively, the substrate (201) may be a semiconductor-on-insulator substrate having a desired semiconductor layer on a buried insulating layer (e.g., silicon over silicon dioxide). Alternatively, the substrate (201) may be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used.

[0040] According to some embodiments, the semiconductor layer (204) has a different material composition from the sacrificial layer (202). In some embodiments, the semiconductor layer (204) comprises a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). The sacrificial layer (202) comprises a material that can be selectively removed from the semiconductor layer (204). In some examples, for instance, the semiconductor layer (204) is silicon and the sacrificial layer (202) is silicon SiGe, or vice versa. In some other examples where SiGe is used for the semiconductor layer (204) and the sacrificial layer (202), respectively, the germanium concentration differs between the semiconductor layer (204) and the sacrificial layer (202) to allow for etching selectivity. For instance, the semiconductor layer (204) may contain a higher germanium content than the sacrificial layer (202).

[0041] Dimensions may vary depending on the exemplary embodiment, but in some examples, the thickness of each semiconductor layer (204) may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer (204) is substantially the same (e.g., within 1-2 nm). The thickness of each sacrificial layer (202) may be approximately the same as the thickness of each semiconductor layer (204) (e.g., about 5-20 nm). Each semiconductor layer (204) and sacrificial layer (202) may be deposited using any material deposition technique such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), or epitaxial growth.

[0042] FIG. 2b illustrates a cross-sectional view of the structure shown in FIG. 2a after the formation of a cap layer (205) and the subsequent formation of pins below the cap layer (205) according to an embodiment. The cap layer (205) may be any suitable hard mask material, such as carbon hard mask (CHM) or silicon nitride. The cap layer (205) is patterned in rows to form corresponding rows of pins from an alternating stack of a sacrificial layer (202) and a semiconductor layer (204). The cap layer (205) extends along the top of each pin in a first direction.

[0043] According to some embodiments, the anisotropic etching process through the layer stack continues to at least a portion of the substrate (201). The portion of the substrate (201) below the pin is not etched, creating a sub-pin region (206). The etched portion of the substrate (201) not below the pin may be filled with a dielectric filler that acts as a shallow trench insulation (STI) between adjacent pins. Since the dielectric filler extends in a first direction along the side of the sub-pin region (206) inside and outside the page, it is not illustrated in these cross sections. The dielectric filler may be any suitable dielectric material, such as silicon dioxide. According to some embodiments, the sub-pin region (206) represents the remaining portion of the substrate (201) whose sides are surrounded by the dielectric filler.

[0044] FIG. 2c illustrates a cross-sectional view of the structure shown in FIG. 2b after the formation of a sacrifice gate (210) and a spacer structure (212) according to some embodiments. To form a sacrifice gate (210) corresponding to a strip below the gate masking layer, the gate masking layer may first be patterned into a strip extending orthogonally across each pin (e.g., in a second direction). Afterward, the gate masking layer may be removed or left as a cap layer over each sacrifice gate (210). According to some embodiments, the sacrifice gate material is removed from all areas not protected by the gate masking layer. The sacrifice gate (210) may be any suitable material that can be selectively removed without damaging the semiconductor material of the pin. In some examples, the sacrifice gate (210) comprises polysilicon.

[0045] According to some embodiments, a spacer structure (212) is formed along the sidewall of the sacrificial gate (210). The spacer structure (212) may be conformally deposited (e.g., using CVD or ALD) and then etched back from the horizontal surface (e.g., via anisotropic or directional etching) or otherwise removed so that the spacer structure (212) remains mainly on the sidewall of any exposed structure. The width of the spacer structure (212) (along the first direction) may vary from example to example, but in some cases is in the range of 3 nm to 20 nm. According to some embodiments, the spacer structure (212) may be any suitable dielectric material such as silicon nitride, silicon carbon nitride, or silicon oxycarbon nitride. In one such embodiment, to provide some degree of etching selectivity during final gate processing, the spacer structure (212) comprises a nitride and the dielectric filler adjacent to the sub-pin region (206) comprises an oxide.

[0046] FIG. 2d illustrates a cross-sectional view of the structure shown in FIG. 2c after removing the exposed portion of the pin not protected by the sacrificial gate (210) and the spacer structure (212) according to some embodiments. The exposed portion of the pin may be removed using any anisotropic etching process, such as RIE or other directional etching processes. According to some embodiments, the removal of the exposed portion of the pin creates a source / drain trench that alternates with the gate trench (currently filled with the sacrificial gate (210)) along a first direction. In some embodiments, at least a portion of the sub-pin region (206) is also removed so that the upper surface of the sub-pin region (206) is recessed below the upper surface of the adjacent dielectric filler. In some embodiments, the sub-pin region (206) within the source / drain trench is completely removed (as shown) to create a sub-pin cavity (213). It should be noted that due to the deep etching process, the source / drain trench may exhibit a tapering width as it extends deeper. Accordingly, as illustrated, at least the sub-pin cavity (213) may have a tapered width.

[0047] FIG. 2e illustrates a cross-sectional view of the structure shown in FIG. 2d after removing a portion of the sacrificial layer (202) according to an embodiment of the present disclosure. An isotropic etching process may be used to selectively recess the exposed ends of each sacrificial layer (202) (for example, without etching the semiconductor layer (204) relatively little).

[0048] FIG. 2f illustrates a cross-sectional view of the structure shown in FIG. 2e after the formation of an internal spacer (214) according to an embodiment of the present disclosure. The internal spacer (214) may have a material composition similar to or exactly the same as that of the spacer structure (212). Accordingly, the internal spacer (214) may be any suitable dielectric material exhibiting high etching selectivity for semiconductor materials such as silicon and / or silicon germanium. The internal spacer (214) may be conformally deposited on the side of the fin structure using a conformal deposition process, for example, CVD or ALD, and then etched back using an isotropic etching process to expose the end of the semiconductor layer (204). According to some embodiments, the internal spacer (214) has a width similar to that of the spacer structure (212) (for example, along a first direction). According to some embodiments, a portion of the dielectric material used to form the internal spacer (214) remains at the bottom of the source / gate trench as one or more dielectric caps (216). Thus, each dielectric cap (216) may have the same material composition as the internal spacer (214). The dielectric caps (216) may fill a portion of the sub-pin cavity (213) and may exhibit the same tapering width profile as the sub-pin cavity (213).

[0049] FIG. 2g illustrates a cross-sectional view of the structure shown in FIG. 2f after forming source or drain regions (218a–218d) (collectively referred to as source or drain regions (218)) within a source / drain trench according to some embodiments. The source or drain regions (218) may be formed in an area previously occupied by exposed pins between spacer structures (212). According to some embodiments, the source or drain regions (218) are epitaxially grown from exposed semiconductor material at the ends of the semiconductor layer (204). Note that the lower portion of the source or drain regions (218) may also be grown from the exposed sidewall surface of the sub-pin regions (206). According to some embodiments, the source or drain regions (218) are formed directly above the dielectric cap (216) such that the dielectric cap (216) contacts the lower surface of the source or drain regions (218).

[0050] According to some embodiments, a dielectric filler (220) is provided over the source or drain region (218). In some examples, the dielectric filler (220) occupies the remaining volume within the source / drain trench around or over a portion of the source or drain region (218). The dielectric filler (220) may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler (220) extends to and flattened with the upper surface of the spacer structure (212) (e.g., after a polishing procedure).

[0051] FIG. 2h illustrates a cross-sectional view of the structure shown in FIG. 2g after the removal of the sacrificial gate (210) and the sacrificial layer (202) according to some embodiments. In an example where the gate masking layer is still present, it may be removed at this time. When the sacrificial gate (210) is removed, the remaining pin portion extending between the spacer structures (212) is exposed.

[0052] In an example comprising a sacrificial layer (202) and a semiconductor layer (204) with alternating pins, the sacrificial layer (202) is optionally removed to leave a nanoribbon (222) extending between the corresponding source or drain regions (218). Each set of vertical nanoribbons (222) represents a semiconductor region (also called a channel region) of a different semiconductor device. It should be understood that any of the nanoribbons (222) may be nanowires or nanosheets. The sacrificial gate (210) and the sacrificial layer (202) may be removed using the same isotropic etching process or different isotropic etching processes.

[0053] FIG. 2i illustrates a cross-sectional view of the structure shown in FIG. 2h after a gate structure is formed around a suspended nanoribbon (222) according to an embodiment of the present disclosure. As previously mentioned, each gate structure includes a gate electrode (224) and a gate dielectric (225).

[0054] The gate dielectric (225) can be conformally deposited around the nanoribbon (222) using any suitable deposition process, such as ALD. The gate dielectric (225) may comprise any suitable dielectric (e.g., silicon dioxide and / or high dielectric constant dielectric material). Examples of high dielectric constant dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. According to some embodiments, the gate dielectric (225) is hafnium oxide having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric (225) may comprise one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some embodiments, the gate dielectric (225) may be a multilayer structure. For example, the gate dielectric (225) may comprise a first layer on a nanoribbon and a second layer on the first layer. The first layer may be, for example, an oxide of a semiconductor layer (e.g., silicon dioxide), and the second layer may be a high dielectric constant material (e.g., hafnium oxide). In some embodiments, an annealing process may be performed on the gate dielectric (225) to improve quality when the high dielectric constant material is used. In some embodiments, the high dielectric constant material may be nitrided to improve aging resistance.

[0055] The gate electrode (224) may be any standard or proprietary conductive material that can be deposited on the gate dielectric (225) and may include any number of gate cuts. In some embodiments, the gate electrode (224) comprises doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode (224) may include, for example, one or more work function layers, resistance reduction layers, and / or barrier layers. The p-type work function layer comprises, for example, tungsten, and the n-type work function layer comprises, for example, titanium aluminum carbide.

[0056] According to some embodiments, a front contact (226) may be formed through a dielectric filler (220) to contact the upper surface of a source or drain region (218). The front contact (226) may include any suitable conductive material, such as tungsten, cobalt, molybdenum, or ruthenium, to form an electrical contact with the source or drain region (218) below. Although not illustrated, any number of front interconnect layers may be formed on the semiconductor device. The interconnect layers include dielectric layers, conductive vias, and conductive layers for transmitting power and / or signals to various transistor elements.

[0057] FIG. 2j illustrates a cross-sectional view of the structure shown in FIG. 2i after the removal of the substrate (201). Any number of polishing, grinding, or etching processes may be used to remove the bulk portion of the substrate (201). According to some embodiments, the substrate (201) is removed until the lower surface of the dielectric cap (216) and / or the lower surface of the dielectric filler adjacent to the sub-pin region (206) is exposed. The rear exposed sub-pin region (206) may then be etched away using an isotropic etching process. According to some embodiments, the removal of the sub-pin region (206) creates a rear recess (228) between portions of the source or drain region (218) having the dielectric cap (216) at a tip extending downward away from the lower surface of the gate structure.

[0058] FIG. 2k illustrates a cross-sectional view of the structure shown in FIG. 2j after the formation of a base dielectric structure (230) within a rear recess (228) according to some embodiments. One or more dielectric materials or layers may be deposited to form the base dielectric structure (230). Additionally, the base dielectric structure (230) may also include a dielectric filler adjacent to the rear recess (228) in and out of the page. In some examples, the base dielectric structure (230) is considered to also include a dielectric cap (216). The base dielectric structure (230) may include any suitable dielectric material, such as silicon dioxide. According to some embodiments, the lower surface of the base dielectric structure (230) may be polished to become a substantially flat surface. The flat lower surface of the base dielectric structure (230) may be coplanar with the lower surface of the dielectric cap (216) or lower than the lower surface of the dielectric cap (216).

[0059] FIG. 2L illustrates a cross-sectional view of the structure shown in FIG. 2K after forming a masking layer (231) on the rear surface of the structure according to some embodiments. The masking layer (231) may be a photoresist material or a dielectric material having high etching selectivity for the dielectric material of the base dielectric structure (230).

[0060] According to some embodiments, the masking layer (231) is patterned and etched to form any number of openings through the masking layer (231), such as a first opening at the bottom of the gate structure and a second opening at the bottom of the adjacent source region (218b). According to some embodiments, a subsequent directional etching process may then be performed to create a first back cavity (232) and a second back cavity (234). The RIE process may be used to anisotropically etch through any exposed portion of the exposed dielectric material / layer that is not protected by the masking layer (231). In one example, the first back cavity (232) extends only through the base dielectric structure (230) to expose the bottom surface of the gate structure, whereas the second back cavity (234) extends at least partially through the dielectric cap (216) to expose the bottom surface of the source region (218b). According to some embodiments, as a result of the etching process, the first back cavity (232) and the second back cavity (234) each have a tapering profile with a width that decreases from the opening of the cavity toward the lower surface of the gate structure or source region (e.g., on the lower surface of the base dielectric structure (230)). According to some embodiments, the etching process for forming the first back cavity (232) also removes a portion of the gate dielectric (225) to expose the lower surface of the gate electrode (224) within the first back cavity (232).

[0061] In some examples, the first back cavity (232) has a maximum width between about 15 nm and about 20 nm along the bottom surface of the base dielectric structure (230) and a minimum width between about 10 nm and about 15 nm on the bottom surface of the gate structure. Due to standard alignment errors, the alignment of the first back cavity (232) below the gate structure is not perfect, so the first back cavity (232) may be offset from the center of the gate electrode (224) along the first direction, for example, up to 5 nm. Similarly, the alignment of the second back cavity (234) below the source region (218b) is not perfect, so the second back cavity (234) may be offset from the center of the source region (218b) along the first direction, for example, up to 5 nm.

[0062] FIG. 2m illustrates a cross-sectional view of the structure shown in FIG. 2l after forming a dielectric liner (236) according to some embodiments. The dielectric liner (236) may be any suitable dielectric material such as silicon nitride, aluminum oxide, or titanium nitride, and may have a thickness between, for example, about 1 nm and about 3 nm. The dielectric liner (236) may be deposited using any suitable conformal deposition technique such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The dielectric liner (236) may be formed to cover the sidewalls of both the first back cavity (232) and the second back cavity (234) and the exposed bottom surface of the gate structure and source region (218b). In some examples, a portion of the dielectric liner (236) deposited along the bottom surface of the base dielectric structure (230) is removed (e.g., by chemical mechanical polishing). In some other examples, a portion of the genome liner (236) continues to extend along the lower surface of the base genome structure (230).

[0063] FIG. 2n illustrates a cross-sectional view of the structure shown in FIG. 2m after forming a first rear contact (238) in a first rear cavity (232) and a second rear contact (240) in a second rear cavity (234) according to some embodiments. Each of the first rear contact (238) and the second rear contact (240) may comprise any suitable conductive material such as tungsten, ruthenium, molybdenum, or cobalt. According to some embodiments, prior to the deposition of the conductive material to form the rear contacts, directional etching (e.g., RIE) is performed to punch through a portion of the dielectric liner (236) on the lower surface of both the gate structure and the source region (218b). In some examples, this directional etching also punches through the gate dielectric (225), if it is still present, to expose the lower surface of the gate electrode (224). According to some embodiments, in any case, the first back contact (238) is formed directly on the lower surface of the gate electrode (224). According to some embodiments, the directional etching used to punch through the dielectric liner (236) on the lower surface of the source region (218b) may also etch away a portion of the source region (218b) so that the second back contact (240) extends into the portion of the source region (218b). In other examples, the second back contact (240) is placed on the lower surface of the source region (218b) and does not extend into the source region (218b).

[0064] Due to the tapering profile, the width of the first back contact (238) may be, for example, about 3 nm larger than the bottom surface of the base dielectric structure (230) compared to the bottom surface of the gate structure, or between 2 nm and 5 nm larger. In some examples, the first back contact (238) has a maximum width between about 15 nm and about 20 nm along the bottom surface of the base dielectric structure (230) and a minimum width between about 10 nm and about 15 nm on the bottom surface of the gate structure. As previously mentioned, alignment errors during the etching process may cause the first back contact (238) to be offset along the first direction from the center of the gate structure by, for example, up to 3 nm or up to 5 nm.

[0065] The relative size of the first back contact (238) compared to the second back contact (240) is not depicted to scale. In some examples, the second back contact (240) is wider at the base (along the lower surface of the base dielectric structure (230)) compared to the base of the first back contact (238). In some examples, the second back contact (240) extends further into the source region (218b), so that the second back contact (240) extends over the upper surface of the first back contact (238) (e.g., over the lower surface of the gate structure). According to some embodiments, the shortest distance (w4) along the first direction between the first back contact (238) and the second back contact (240) may be, for example, between about 3 nm and about 8 nm, e.g., about 5 nm. It should be understood that the tapered sidewall of the second rear contact (240) may be the product of a rear directional etching process, and that other manufacturing processes used to form the second rear contact (240) may not result in a tapered sidewall.

[0066] FIG. 2o illustrates a cross-sectional view of the structure shown in FIG. 2n after the formation of the first rear interconnect layer according to some embodiments. Any number of rear interconnect layers may be formed to provide a shorted connection between the first rear contact (238) and the second rear contact (240). According to some embodiments, the first rear interconnect layer comprises a rear dielectric layer (242) and a rear conductive trace (244). The rear conductive trace (244) may contact the lower surface of each of the first rear contact (238) and the second rear contact (240) to short them together. Any number of other rear interconnect layers may be formed below the first rear interconnect layer. The rear dielectric layer (242) may be any suitable dielectric material such as silicon dioxide. The rear conductive trace (244) may be any suitable conductive material such as tungsten, ruthenium, molybdenum, or cobalt.

[0067] FIG. 3 illustrates an exemplary embodiment of a chip package (300) according to an embodiment of the present disclosure. As can be seen, the chip package (300) comprises one or more dies (302). One or more dies (302) may comprise at least one integrated circuit having a semiconductor device such as any of the semiconductor devices disclosed herein. In some exemplary configurations, one or more dies (302) may comprise any other circuit portion used to interface with another device formed on the die or another device connected to the chip package (300).

[0068] As can be seen further, the chip package (300) includes a housing (304) bonded to a package substrate (306). The housing (304) may be any standard or proprietary housing and may, for example, provide electromagnetic shielding and environmental protection for the components of the chip package (300). One or more dies (302) may be conductively bonded to the package substrate (306) using a connection (308) which may be implemented by any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonds, for example. The package substrate (306) may be any standard or proprietary package substrate, but in some cases, it includes a dielectric material having conductive paths (e.g., conductive vias and lines) extending through the dielectric material between the faces of the package substrate (306) or between different locations on each face. In some embodiments, the package substrate (306) may have a thickness of less than 1 millimeter (e.g., between 0.1 and 0.5 millimeters), but any number of package geometries may be used. Additional conductive contacts (312) may be placed on opposite sides of the package substrate (306) to make conductive contact, for example, with a printed circuit board (PCB). One or more vias (310) extend through the thickness of the package substrate (306) to provide a conductive path between one or more of the connections (308) and one or more of the contacts (312). For ease of explanation, the vias (310) are shown as a single straight column passing through the package substrate (306), but other configurations (e.g., damascene, dual damascene, through-silicon vias, or interconnect structures that meander through the thickness of the substrate (306) to make contact with one or more intermediate locations within them) may be used. In another embodiment, the vias (310) are formed by a plurality of smaller stacked vias or are staggered at different locations across the package substrate (306).In the illustrated embodiment, the contact (312) is a solder ball (e.g., for a bump-based connection or a ball grid array), but any suitable package bonding mechanism (e.g., a pin of a pin grid array or a land of a land grid array) may be used. In some embodiments, a solder resist is placed between the contacts (312) to prevent short circuits.

[0069] In some embodiments, the mold material (314) may be placed around one or more dies (302) contained within the housing (304) (e.g., as an underfill material between the die (302) and the package substrate (306), and as an overfill material between the die (302) and the housing (304). The dimensions and quality of the mold material (314) may vary from embodiment to embodiment, but in some embodiments, the thickness of the mold material (314) is less than 1 millimeter. Exemplary materials that may be used for the mold material (314) suitably include epoxy mold materials. In some cases, the mold material (314) is thermally conductive in addition to being electrically insulating.

[0070] methodology

[0071] FIG. 4 is a flowchart of a method (400) for forming at least a portion of an integrated circuit according to an embodiment. Various operations of the method (400) may be illustrated in FIGS. 2a-2n. However, the correlation of the various operations of the method (400) with respect to specific components illustrated in the foregoing drawings is not intended to imply any structural and / or usage limitations. Rather, the foregoing drawings provide one exemplary embodiment of the method (400). Other operations may be performed before, during, or after any operation of the method (400). For example, the method (400) does not explicitly describe various standard processes typically performed to form a transistor structure. Some operations of the method (400) may be performed in a different order than the illustrated order.

[0072] The method (400) begins with an operation (402) in which a plurality of parallel semiconductor pins are formed according to some embodiments. The semiconductor material within the pins may be formed from a substrate so that the pins become integral parts of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the pins may be formed from a material deposited on the substrate below. In one exemplary case, a blanket layer of silicon germanium (SiGe) may be deposited on a silicon substrate and then patterned and etched to form a plurality of SiGe pins extending from the substrate. In another such example, non-inherent pins may be formed by a so-called aspect ratio trapping-based process in which the intrinsic pins are etched away to leave pin-shaped trenches, which can then be filled with an alternative semiconductor material (e.g., a Group IV or III-V material). In another embodiment, the fin comprises alternating material layers (e.g., alternating silicon and SiGe layers) that facilitate the formation of nanowires and nanoribbons during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a gate all around (GAA) process can be performed. Again, the alternating layer may be blanket-deposited and then etched into the fin, or deposited into a fin-shaped trench. The fin may also include a cap structure on each fin used to define the position of the fin during the RIE process, for example. The cap structure may be a dielectric material such as silicon nitride.

[0073] The method (400) continues with the operation (404) of forming a dielectric layer around at least one sub-pin portion of the pin. In some embodiments, the dielectric layer extends between each pair of adjacent parallel pins and is elongated in the same direction as the pin. In some embodiments, the anisotropic etching process forming the pin is also etched into a portion of the substrate, and the dielectric layer may be formed within a recessed portion of the substrate. Thus, the dielectric layer acts as a shallow trench insulation (STI) between adjacent pins. The dielectric layer may be any suitable dielectric material, such as silicon dioxide.

[0074] The method (400) continues to the operation (406) of forming a sacrifice gate on at least one of the pins. The sacrifice gate may be patterned using a gate masking layer in a strip extending orthogonally over at least one pin, and a plurality of gate masking layers may be formed to extend parallel to each other (e.g., forming a cross-hatch pattern with the pin). The gate masking layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrifice gate may be formed from any suitable material that can be selectively removed later without damaging the semiconductor material of the pin. In one example, the sacrifice gate comprises polysilicon.

[0075] According to some embodiments, a spacer structure is also formed on at least the sidewall of the sacrificial gate. The spacer structure may be deposited and then etched back so that the spacer structure remains mainly on the sidewall of any exposed structure. In some cases, the spacer structure may also be formed along the sidewall of an exposed pin that extends orthogonally between the strips of the sacrificial gate. According to some embodiments, the spacer structure may be any suitable dielectric material such as silicon nitride or silicon oxynitride.

[0076] The method (400) continues to the operation (408) in which a source or drain region is formed at the opposite end of the pin. The exposed portion of the pin not covered by the sacrificial gate or spacer structure may be removed using any anisotropic etching process, such as reactive ion etching (RIE). Once the exposed portion of the pin is removed, a source or drain region may be formed in the area previously occupied by the exposed portion of the pin between the spacer structures. According to some embodiments, the source or drain region is epitaxially grown from the exposed semiconductor material of the pin (or, in some cases, a nanoribbon, nanowire, or nanosheet) along the outer wall of the spacer structure. In some exemplary embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe). A dielectric filler may be formed between and over the source or drain region along a predetermined source / drain trench. The dielectric filler can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler extends flatly over the source or drain region to the upper surface of the spacer structure. Although some adjacent source or drain regions may have merged together during their growth, the dielectric filler also acts as an electrical insulator between adjacent source or drain regions.

[0077] The method (400) continues to the operation (410) of forming a gate structure on the semiconductor material of the semiconductor pin. (In the case of a GAA structure) a sacrificial gate is first removed along with any sacrificial layer within the exposed pin between the spacer structures. Subsequently, a gate structure may be formed in place of the sacrificial gate. The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, a gate dielectric is first formed on the exposed semiconductor region between the spacer structures, and then a gate electrode is formed within the remainder of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process such as ALD. The gate electrode may include any conductive material such as a metal, a metal alloy, or polysilicon. The gate electrode may be deposited using some examples, such as electroplating, electroless plating, CVD, ALD, PECVD, or PVD.

[0078] The method (400) continues with an operation (412) in which the substrate is removed from the back surface of the structure to expose the lower surface of the sub-pin portion and / or the lower surface of the dielectric layer adjacent to the sub-pin portion. The substrate may be removed using any number of isotropic etching, polishing, or grinding operations. The sub-pin portion may also be removed and replaced with any suitable dielectric material(s), such as silicon dioxide. Any other dielectric material may also be present on the back surface of the structure to collectively form a base dielectric structure on the bottom of the semiconductor device.

[0079] The method (400) continues with the operation (414) of forming a first back cavity through at least a portion of the base dielectric structure on the back surface to expose the lower surface of the gate structure. The back cavity may be formed using an anisotropic etching technique such as RIE. According to some embodiments, the back cavity may have a sidewall that tapers inward toward the exposed lower surface of the gate structure. In some examples, the back cavity has a maximum width between about 15 nm and about 20 nm along the lower surface of the base dielectric structure and a minimum width between about 10 nm and about 15 nm at the lower surface of the gate structure.

[0080] The method (400) continues with the operation (416) in which a second back cavity is formed through at least a portion of the base dielectric structure on the back surface to expose the lower surface of the source region adjacent to the gate structure. The second back cavity may be formed using an anisotropic etching technique such as RIE. According to some embodiments, the second back cavity may have a sidewall that tapers inward toward the exposed lower surface of the source region. In some examples, the same RIE process is used to form both the first back cavity and the second back cavity simultaneously.

[0081] The method (400) continues with the operation (418) in which a first back contact is formed within a first back cavity and a second back contact is formed within a second back cavity. According to some embodiments, the first back contact is formed directly on the exposed surface(s) of the gate structure (e.g., directly on the gate electrode), and the second back contact is formed directly on the exposed surface(s) of the source region. The first and second back contacts may comprise any suitable conductive material such as cobalt, ruthenium, molybdenum, or tungsten. According to some embodiments, a back conductive trace is formed to be underneath and in contact with both the first back contact and the second back contact. The first and second back contacts may have a shortest distance between them, for example, less than 8 nm or about 5 nm.

[0082] Exemplary system

[0083] FIG. 5 is an exemplary computing system implemented with one or more integrated circuit structures as described herein, according to some embodiments of the present disclosure. As can be seen, the computing system (500) accommodates a motherboard (502). The motherboard (502) may include a plurality of components, including but not limited to a processor (504) and at least one communication chip (506), each of which may be physically and electrically connected to the motherboard (502) or otherwise integrated therein. As is understood, the motherboard (502) may be any printed circuit board (PCB), for example, a main board, a daughter board mounted on the main board, or the sole board of the system (500).

[0084] Depending on the application example, the computing system (500) may include one or more other components that may or may not be physically and electrically connected to the motherboard (502). These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, an encryption processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS (global positioning system) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard disk drive, a compact disc (CD), a digital multi-purpose disc (DVD), etc.). Any component included in the computing system (500) may include one or more integrated circuit structures or devices configured according to exemplary embodiments (e.g., a module including one or more semiconductor devices including one or more directly patterned and etched back contacts as part of a gate tie-down structure as provided in various ways herein). In some embodiments, a plurality of functions may be integrated into one or more chips (e.g., note that a communication chip (506) may be part of the processor (504) or otherwise may be integrated into the processor (504)).

[0085] A communication chip (506) enables wireless communication for data transmission to and from a computing system (500). The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of transmitting data using electromagnetic radiation modulated through a non-solid medium. The term does not imply that the associated device does not contain any wires, although it may not in some embodiments. The communication chip (506) may implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system (500) may include a plurality of communication chips (506). For example, the first communication chip (506) may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip (506) may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0086] A processor (504) of a computing system (500) includes an integrated circuit die packaged within the processor (504). In some embodiments, the integrated circuit die of the processor includes an onboard circuitry implemented by one or more semiconductor devices as described in various ways in this specification. The term “processor” may refer to any device or part of a device that processes electronic data from, for example, registers and / or memory and converts said electronic data into other electronic data that can be stored in registers and / or memory.

[0087] The communication chip (506) may also include an integrated circuit die packaged within the communication chip (506). According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various ways in this specification. Note that, as understood in light of this disclosure, multiple standard wireless capabilities may be directly integrated into the processor (504) (e.g., where the functions of any chip (506) are integrated into the processor (504) rather than having a separate communication chip). It is further noted that the processor (504) may be a chipset having such wireless capabilities. In short, any number of processors (504) and / or communication chips (506) may be used. Likewise, any one chip or chipset may have multiple functions integrated within it.

[0088] In various embodiments, the computing system (500) may be a laptop, netbook, notebook, smartphone, tablet, personal handheld terminal (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device using one or more integrated circuit structures or devices formed using the disclosed techniques for processing data, as described in various ways in this specification.

[0089] In some embodiments, it will be understood that various components of the computing system (500) may be combined or integrated into a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0090] Additional exemplary embodiments

[0091] The following examples relate to additional embodiments, from which numerous substitutions and configurations will become apparent.

[0092] Example 1 is an integrated circuit comprising a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction above the semiconductor region, a gate structure, a dielectric structure below the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region, and a conductive layer below the dielectric structure. Both the first back conductive contact and the second back conductive contact are in direct contact with the conductive layer.

[0093] Example 2 includes the integrated circuit of Example 1 and further includes a dielectric liner between the first back conductive contact and the dielectric structure.

[0094] Example 3 includes the integrated circuit of Example 2, and the dielectric liner includes silicon and nitrogen.

[0095] Example 4 includes the integrated circuit of Example 2, and the dielectric liner includes aluminum and oxygen.

[0096] Example 5 includes an integrated circuit of any one of Examples 2 to 4, wherein at least a portion of the dielectric liner is in contact with at least a portion of the lower surface of the gate structure.

[0097] Example 6 includes an integrated circuit of any one of Examples 1 to 5, wherein the first back-side conductive contact has a tapered width along a first direction such that the first width of the first back-side conductive contact at the lower surface of the dielectric structure is greater than the second width of the first back-side conductive contact at the lower surface of the gate structure.

[0098] Example 7 includes the integrated circuit of Example 6, and the first width is at least 3 nm larger than the second width.

[0099] Example 8 includes an integrated circuit of any one of Examples 1 to 7, and the gate structure includes a gate dielectric and a gate electrode on the gate dielectric.

[0100] Example 9 includes the integrated circuit of Example 8, wherein the first back conductive contact extends through the thickness of the gate dielectric and is in direct contact with the gate electrode.

[0101] Example 10 includes the integrated circuit of Example 8 or Example 9, and the first back conductive contact includes the same conductive material as the gate electrode.

[0102] Example 11 includes an integrated circuit of any one of Examples 1 to 10, and the gate structure has a width of 30 nm or less along the first direction.

[0103] Example 12 includes an integrated circuit of any one of Examples 1 to 11, and the distance along the first direction between the first back conductive contact and the second back conductive contact is less than 10 nm.

[0104] Example 13 includes an integrated circuit of any one of Examples 1 to 12, wherein the second source or drain region is the second source region, and the integrated circuit further includes a third rear conductive contact that extends through a dielectric structure and contacts the lower surface of the second source region.

[0105] Example 14 includes an integrated circuit of any one of Examples 1 to 13, and the semiconductor region includes a plurality of semiconductor nanoribbons.

[0106] Example 15 includes the integrated circuit of Example 14, and the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0107] Example 16 is a die containing an integrated circuit of any one of Examples 1 to 15.

[0108] Example 17 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies comprises a semiconductor region extending in a first direction from a first source region to a second source or drain region, a gate structure extending in a second direction different from the first direction over the semiconductor region, a dielectric structure below the gate structure, the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, and a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region. The first back conductive contact has a tapered width along the first direction such that the first width of the first back conductive contact at the lower surface of the dielectric structure is greater than the second width of the first back conductive contact at the lower surface of the gate structure.

[0109] Example 18 includes the electronic device of Example 17, and at least one of the one or more dies further includes a dielectric liner between the first back conductive contact and the dielectric layer.

[0110] Example 19 includes the electronic device of Example 18, and the dielectric liner includes silicon and nitrogen.

[0111] Example 20 includes the electronic device of Example 18, and the dielectric liner includes aluminum and oxygen.

[0112] Example 21 includes an electronic device of any one of Examples 18 to 20, and at least a portion of the dielectric liner is in contact with at least a portion of the lower surface of the gate structure.

[0113] Example 22 includes an electronic device of any one of Examples 17 to 21, wherein at least one of one or more dies further includes a conductive layer below the dielectric layer, and both the first rear conductive contact and the second rear conductive contact are in direct contact with the conductive layer.

[0114] Example 23 includes the electronic device of Example 22, and further includes a third back conductive contact that extends through a dielectric layer and contacts the lower surface of a second source or drain region.

[0115] Example 24 includes an electronic device of any one of Examples 17 to 23, wherein the first width is at least 3 nm larger than the second width.

[0116] Example 25 includes an electronic device according to any one of Examples 17 to 24, and the gate structure includes a gate dielectric and a gate electrode formed on the gate dielectric.

[0117] Example 26 includes the electronic device of Example 25, and the first back conductive contact extends through the thickness of the gate dielectric and is in direct contact with the gate electrode.

[0118] Example 27 includes the electronic device of Example 25 or Example 26, and the first back conductive contact includes the same conductive material as the gate electrode.

[0119] Example 28 includes an electronic device according to any one of Examples 17 to 27, and the gate structure has a width of 30 nm or less along the first direction.

[0120] Example 29 includes an electronic device of any one of Examples 17 to 28, and the distance along the first direction between the first back conductive contact and the second back conductive contact is less than 10 nm.

[0121] Example 30 includes an electronic device of any one of Examples 17 to 29, and the semiconductor region includes a plurality of semiconductor nanoribbons.

[0122] Example 31 includes the electronic device of Example 30, and the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0123] Example 32 includes an electronic device of any one of Examples 17 to 31, and further includes a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0124] Example 33 is a method for forming an integrated circuit. The method comprises the steps of: forming a pin comprising a semiconductor material—the pin extends over a substrate—; forming a dielectric layer adjacent to a sub-pin of the pin; forming a sacrificial gate and spacer structure over the pin; removing a portion of the pin not covered by the sacrificial gate and spacer structure; forming source and drain regions on the exposed end of the semiconductor material and over the sub-pin; replacing the sacrificial gate with a gate structure; removing a portion of the substrate from the back of the integrated circuit; removing the sub-pin from the back and replacing the sub-pin with a dielectric filler; etching a first cavity through the dielectric filler so that the lower surface of the gate structure is exposed within the first cavity; etching a second cavity through the dielectric filler so that the lower surface of the source region is exposed within the second cavity—the second cavity is adjacent to the first cavity—; and forming a first conductive contact in the first cavity and forming a second conductive contact in the second cavity.

[0125] Example 34 includes the method of Example 33, wherein etching the first cavity includes etching the first cavity using reactive ion etching (RIE), and etching the second cavity includes etching the second cavity using RIE.

[0126] Example 35 includes the method of Example 33 or Example 34, and the dielectric filler has the same material composition as the dielectric layer.

[0127] Example 36 includes the method of any one of Examples 33 to 35, wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric. The method further includes the steps of forming a dielectric liner in a first cavity; removing a portion of the dielectric liner on the lower surface of the gate structure; and etching through the gate dielectric in the first cavity to expose the gate electrode.

[0128] Example 37 includes the method of Example 36, and forming the first conductive contact includes forming the first conductive contact directly on the dielectric liner and on the gate electrode.

[0129] Example 38 is an integrated circuit comprising a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction over the semiconductor region, a dielectric structure below the gate structure, the first source region and the second source or drain region, a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure, and a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region. The distance along the first direction between the first back conductive contact and the second back conductive contact is less than 10 nm.

[0130] Example 39 includes the integrated circuit of Example 38 and further includes a dielectric liner between the first back conductive contact and the dielectric structure.

[0131] Example 40 includes the integrated circuit of Example 39, and the dielectric liner includes silicon and nitrogen.

[0132] Example 41 includes the integrated circuit of Example 39, and the dielectric liner includes aluminum and oxygen.

[0133] Example 42 includes an integrated circuit of any one of Examples 39 to 41, wherein at least a portion of the dielectric liner is in contact with at least a portion of the lower surface of the gate structure.

[0134] Example 43 includes an integrated circuit of any one of Examples 38 to 42, wherein the first back-side conductive contact has a tapered width along a first direction such that the first width of the first back-side conductive contact at the lower surface of the dielectric structure is greater than the second width of the first back-side conductive contact at the lower surface of the gate structure.

[0135] Example 44 includes the integrated circuit of Example 43, and the first width is at least 3 nm larger than the second width.

[0136] Example 45 includes an integrated circuit of any one of Examples 38 to 44, and the gate structure includes a gate dielectric and a gate electrode on the gate dielectric.

[0137] Example 46 includes the integrated circuit of Example 45, and the first back conductive contact extends through the thickness of the gate dielectric and is in direct contact with the gate electrode.

[0138] Example 47 includes the integrated circuit of Example 45 or Example 46, and the first back conductive contact includes the same conductive material as the gate electrode.

[0139] Example 48 includes an integrated circuit of any one of Examples 38 to 47, and the gate structure has a width of 30 nm or less along the first direction.

[0140] Example 49 includes an integrated circuit of any one of Examples 38 to 48, further includes a conductive layer at the bottom of a dielectric structure, and both the first rear conductive contact and the second rear conductive contact are in direct contact with the conductive layer.

[0141] Example 50 includes an integrated circuit of any one of Examples 38 to 49 and further includes a third rear conductive contact that extends through a dielectric structure and contacts the lower surface of a second source or drain region.

[0142] Example 51 includes an integrated circuit of any one of Examples 38 to 50, and the semiconductor region includes a plurality of semiconductor nanoribbons.

[0143] Example 52 includes the integrated circuit of Example 51, and the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0144] Example 53 is a die containing an integrated circuit of any one of Examples 38 to 52.

[0145] The foregoing description of the embodiments of the present disclosure is provided for illustrative and illustrative purposes only. It is not intended to be comprehensive or to limit the content of the disclosure to the exact form disclosed. Many modifications and variations are possible in light of the present disclosure. The scope of the present disclosure is intended to be limited by the claims appended herein, rather than by this detailed description.

Claims

Claim 1 An integrated circuit comprising: a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction above the semiconductor region; a dielectric structure below the gate structure, the first source region and the second source or drain region; a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure; a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region; and a conductive layer below the dielectric structure, wherein both the first back conductive contact and the second back conductive contact are in direct contact with the conductive layer. Claim 2 An integrated circuit according to claim 1, further comprising a dielectric liner between the first rear conductive contact and the dielectric structure. Claim 3 In paragraph 2, the dielectric liner comprises silicon and nitrogen, an integrated circuit. Claim 4 In paragraph 2, the dielectric liner comprises aluminum and oxygen, an integrated circuit. Claim 5 An integrated circuit according to paragraph 2, wherein at least a portion of the dielectric liner contacts at least a portion of the lower surface of the gate structure. Claim 6 An integrated circuit according to claim 1, wherein the first rear conductive contact has a tapered width along the first direction such that the first width of the first rear conductive contact at the lower surface of the dielectric structure is greater than the second width of the first rear conductive contact at the lower surface of the gate structure. Claim 7 In paragraph 6, the integrated circuit, wherein the first width is at least 3 nm larger than the second width. Claim 8 An integrated circuit according to any one of claims 1 to 7, wherein the gate structure comprises a gate dielectric and a gate electrode on the gate dielectric, and the first back conductive contact extends through the thickness of the gate dielectric and is in direct contact with the gate electrode. Claim 9 In claim 8, the first rear conductive contact comprises the same conductive material as the gate electrode, in an integrated circuit. Claim 10 An integrated circuit according to any one of claims 1 to 7, wherein the gate structure has a width of 30 nm or less along the first direction. Claim 11 An integrated circuit according to any one of claims 1 to 7, wherein the distance along the first direction between the first rear conductive contact and the second rear conductive contact is less than 10 nm. Claim 12 An integrated circuit according to any one of claims 1 to 7, wherein the second source or drain region is a second source region, and the integrated circuit further comprises a third rear conductive contact extending through the dielectric structure and contacting the lower surface of the second source region. Claim 13 An integrated circuit according to any one of claims 1 to 7, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons. Claim 14 A die comprising an integrated circuit of any one of claims 1 to 7. Claim 15 An electronic device comprising a chip package including one or more dies, wherein at least one of the one or more dies is A semiconductor region extending in a first direction from a first source region to a second source or drain region, and A gate structure extending in a second direction different from the first direction on the semiconductor region, and The above gate structure, the dielectric layer below the first source region and the second source or drain region, and A first rear conductive contact extending through the dielectric layer and in contact with the lower surface of the gate structure, and It includes a second rear conductive contact that extends through the dielectric layer and contacts the lower surface of the first source region, and An electronic device in which the first rear conductive contact has a tapered width along the first direction such that the first width of the first rear conductive contact at the lower surface of the dielectric layer is greater than the second width of the first rear conductive contact at the lower surface of the gate structure. Claim 16 An electronic device according to claim 15, wherein at least one of the above one or more dies further comprises a dielectric liner between the first back conductive contact and the dielectric layer. Claim 17 An electronic device according to claim 16, wherein at least a portion of the dielectric liner contacts at least a portion of the lower surface of the gate structure. Claim 18 An electronic device according to claim 15, wherein at least one of the above one or more dies further comprises a conductive layer below the dielectric layer, and the first rear conductive contact and the second rear conductive contact are both in direct contact with the conductive layer. Claim 19 An electronic device according to claim 15, wherein at least one of the one or more dies further comprises a third rear conductive contact extending through the dielectric layer and contacting the lower surface of the second source or drain region. Claim 20 An electronic device according to any one of claims 15 to 19, wherein the distance along the first direction between the first rear conductive contact and the second rear conductive contact is less than 10 nm. Claim 21 An integrated circuit comprising: a semiconductor device having a semiconductor region extending in a first direction from a first source region to a second source or drain region and a gate structure extending in a second direction different from the first direction above the semiconductor region; a dielectric structure below the gate structure, the first source region and the second source or drain region; a first back conductive contact extending through the dielectric structure and in contact with the lower surface of the gate structure; and a second back conductive contact extending through the dielectric structure and in contact with the lower surface of the first source region, wherein the distance along the first direction between the first back conductive contact and the second back conductive contact is less than 10 nm. Claim 22 An integrated circuit according to claim 21, further comprising a dielectric liner between the first rear conductive contact and the dielectric structure. Claim 23 In claim 21, the first back-side conductive contact has a tapered width along the first direction such that the first width of the first back-side conductive contact at the lower surface of the dielectric structure is at least 3 nm larger than the second width of the first back-side conductive contact at the lower surface of the gate structure, an integrated circuit. Claim 24 An integrated circuit according to any one of claims 21 to 23, further comprising a conductive layer on the lower portion of the dielectric structure, wherein both the first rear conductive contact and the second rear conductive contact are in direct contact with the conductive layer. Claim 25 An integrated circuit according to any one of claims 21 to 23, further comprising a third rear conductive contact extending through the dielectric structure and in contact with the lower surface of the second source or drain region.

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