Electronic devices and methods of manufacturing electronic devices

Abstract

In one example, the electronic device includes an electronic component comprising an upper side, a lower side, a side, and a component interconnect adjacent to the upper side. The encapsulant includes an encapsulant upper side, an encapsulant lower side, and an encapsulant side. The substrate includes a dielectric structure comprising a first dielectric layer and a second dielectric layer formed on the first dielectric layer and having a side end interposed between the side of the electronic component and the encapsulant side. The substrate includes a conductive structure comprising a first conductive layer and a second conductive layer coupled to the first conductive layer. The second conductive layer includes a first region extending to overlap the side end of the second dielectric layer and a substrate edge terminal covering a portion of the first dielectric layer. Other examples and related methods are also disclosed herein.

Description

Technology Field

[0001] The present invention generally relates to electronic devices, and more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0003] Conventional semiconductor packages and methods for forming semiconductor packages are insufficient, for example, resulting in excessive costs, reduced reliability, relatively low performance, or excessively large package sizes. Additional limitations and disadvantages of existing and traditional approaches will become apparent to those skilled in the art through a comparison with such approaches with reference to the present disclosure and drawings. Brief explanation of the drawing

[0005] FIG. 1 illustrates a cross-sectional view of an exemplary electronic device. FIG. 2 shows a partial cross-sectional view in which the exemplary electronic device of FIG. 1 is connected to an assembly of the next stage. FIGS. 3a, 3b, 3c, 3d, 3e, 3f, 3g and 3h illustrate partial cross-sectional views of an exemplary method for manufacturing an exemplary electronic device. FIG. 4a illustrates a partial cross-sectional view of an exemplary electronic device. FIG. 4b illustrates a partial cross-sectional view of an exemplary electronic device. FIG. 5 illustrates a cross-sectional view of an exemplary electronic device. FIG. 6 shows a partial cross-sectional view in which the exemplary electronic device of FIG. 5 is connected to an assembly of the next stage. FIGS. 7a, 7b, 7c, 7d, 7e, and 7f illustrate exemplary partial cross-sectional views of a method for manufacturing an exemplary electronic device. Specific details for implementing the invention

[0006] The following discussion provides various examples of semiconductor devices and methods for manufacturing semiconductor devices. These examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "examples" and "for example" are non-limiting.

[0007] The drawings describe the general configuration, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily complicating the invention. Additionally, the elements in the drawings are not necessarily drawn to their actual size. For example, to aid in understanding the examples discussed in the invention, the dimensions of some elements in the drawings may be exaggerated compared to others. Identical reference numerals in different drawings indicate identical elements.

[0008] The term "or" means one or more of the items in the list connected by "or". For example, "x or y" means any element of the set of three elements {(x), (y), (x, y)}. As another example, "x, y or z" means any element of the set of seven elements {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0009] The terms "comprises," "including," "includes," and / or "comprises" specify the existence of the feature specified as an "open" term, but do not exclude the existence or addition of one or more other features.

[0010] In this specification, terms such as “first,” “second,” etc., may be used to describe various elements, and these elements should not be limited by such terms. These terms are used merely to distinguish one element from another. Accordingly, for example, the first element discussed in this specification may be named the second element without departing from the teachings of this specification.

[0011] Unless otherwise specified, the term “combined” may be used to describe cases where two elements are in direct contact or are indirectly connected through one or more other elements. For example, if element A is combined with element B, element A may be in direct contact with element B or indirectly connected to element B through an intermediate element C. Likewise, the terms “on” or “on” may be used to describe two elements in direct contact with each other or two elements indirectly connected through one or more other elements. As used herein, the term “combined” may mean electrical coupling or mechanical coupling.

[0012] This specification includes structures and methods related to electronic devices using wafer-level packaging. More specifically, structures and methods are described for improving the manufacturability of wafer-level substrates, such as redistribution layer (RDL) substrates used in fine-pitch fan-out configurations, for example. This may be referred to as a wafer-level fan-out configuration or WLFO. In some examples, substrate edge terminals are provided that extend to and terminate at the side edge of the substrate to provide a wettable flank configuration. In some examples, the substrate edge terminals are configured to further extend and overlap the edge of an encapsulant covering an internal electronic component. This wettable side structure protects the underlying conductor (e.g., copper (Cu)) and enables soldering in the outer side area of ​​the substrate edge terminal to allow for the verification of a good solder fillet joint and consequently a good electrical connection through optical inspection.

[0013] In one example, the electronic device includes an electronic component comprising an upper side, a lower side opposite to the upper side, a side connecting the upper side and the lower side, and a component interconnect adjacent to the upper side. The encapsulant includes an encapsulant upper side, an encapsulant lower side, and an encapsulant side, wherein the upper side of the electronic component is exposed from the encapsulant upper side and the encapsulant side covers the side of the electronic component. The substrate includes a dielectric structure comprising a first dielectric layer and a second dielectric layer formed on the first dielectric layer, wherein the dielectric structure includes a side end inserted between the side of the electronic component and the encapsulant side; and a conductive structure comprising a first conductive layer connected to the component interconnect and a second conductive layer connected to the first conductive layer. The second conductive layer includes a substrate edge terminal that extends to overlap the side end of the second dielectric layer and includes a first region covering a portion of the first dielectric layer.

[0014] For example, an electronic device includes an electronic component comprising an upper side, a lower side opposite to the upper side, a side connecting the upper side and the lower side, and a component interconnect adjacent to the upper side. An encapsulant includes an upper side of the encapsulant, a lower side of the encapsulant, and a side of the encapsulant. The upper side of the electronic component is exposed from the upper side of the encapsulant, and the side of the encapsulant covers the side of the electronic component. A substrate includes a dielectric structure comprising a first dielectric layer and a second dielectric layer formed on the first dielectric layer, wherein the dielectric structure includes a side end disposed between the side of the electronic component and the side of the encapsulant. A conductor structure includes a first conductive layer comprising a substrate internal terminal coupled to the component interconnect, and a second conductive layer comprising a substrate external terminal and a substrate edge terminal coupled to the first conductive layer. The substrate edge terminal includes a first region extending to overlap the side end of the second dielectric layer and to cover a portion of the first dielectric layer adjacent to the encapsulant side.

[0015] For example, a method for manufacturing an electronic device includes the step of providing an electronic component comprising an upper side, a lower side opposite to the upper side, a side connecting the upper side and the lower side, and a component interconnect adjacent to the upper side. The method includes the step of providing an encapsulant comprising an encapsulant upper side, an encapsulant lower side, and an encapsulant side. The upper side of the electronic component is exposed from the encapsulant upper side, and the encapsulant side covers the side of the electronic component. The method includes the step of providing a substrate comprising a dielectric structure comprising a first dielectric layer and a second dielectric layer formed on the first dielectric layer, and a side end disposed between the side of the electronic component and the encapsulant side; and the step of providing a conductive structure comprising a first conductive layer connected to a component interconnect and a second conductive layer connected to the first conductive layer. The second conductive layer includes a substrate edge terminal comprising a first region that extends to overlap the side end of the second dielectric layer and covers a portion of the first dielectric layer. The first region defines an outwardly facing side surface.

[0016] This specification includes other examples. These examples can be found in the drawings, claims, or description in this specification.

[0017] FIG. 1 illustrates a cross-sectional view of an electronic device (100) according to the present description. In this example, the electronic device (100) is illustrated as a WFLO structure having a wettable side configuration. In this example, the electronic device (100) may include a substrate (110), an electronic component (120), and an encapsulant (140).

[0018] In this example, the substrate (110) is illustrated as a redistribution layer (RDL) substrate. The RDL substrate may include one or more conductive redistribution layers (e.g., a conductor structure (112)) and one or more dielectric layers (e.g., a dielectric structure (111)), which may be formed layer by layer on an electronic component to which the RDL substrate is electrically coupled, or (b) formed layer by layer on a workpiece. As described below, the RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer (including the electronic component (120) and the encapsulant (140)) in a wafer-level process, and / or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process.

[0019] The RDL substrate may be formed by a stacking process in which one or more dielectric layers (e.g., dielectric layers (111a and 111b) of the dielectric structure (111)) and one or more conductive layers (e.g., conductive layers (112a and 112b) of the conductor structure (112)) are alternately stacked, and the conductive layers define a conductivity redistribution pattern or trace, which is configured to collectively (a) fan out electrical traces outside the footprint of the electronic device and / or (b) fan in electrical traces inside the footprint of the electronic device. The conductivity pattern may be formed using a plating process, for example, an electroplating process or an electroless plating process. The conductivity pattern may include an electrically conductive material, for example, copper (Cu) or other platingable metals. The location of the conductivity pattern may be created, for example, through a photolithography process and a photopatterning process that forms a photolithography mask using a photoresist material.

[0020] The dielectric layer of the RDL substrate (e.g., dielectric layers (111a and 111b)) can be patterned by a photopatterning process, which may include a photolithography mask that exposes desired features, such as vias within the dielectric layer, to light. The dielectric layer may be made of a photodefinable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB)-based resin, or polybenzoxazole (PBO). This dielectric material may be attached as a pre-formed film or coated in liquid form by spun-on or other methods. To properly form the desired photodefinable features, this photodefinable dielectric material may be filler-free, without structural reinforcement, or without fibers, woven structures, or other particles that could interfere with light during the photopatterning process. In some examples, this filler-free nature of the filler-free dielectric material may reduce the thickness of the resulting dielectric layer.

[0021] The photo-defined dielectric material described above may be an organic material, but in other examples, the dielectric material of the RDL substrate may comprise one or more inorganic dielectric layers. Some examples of inorganic dielectric layers include silicon nitride (Si₂). N₄), silicon oxide (SiO₂) ), and / or SiON may be included. The inorganic dielectric layer may be formed by growing the inorganic dielectric layer using an oxidation or nitridation process instead of using photo-defined organic dielectric materials. Such inorganic dielectric layers are filler-free and may not contain fibers, wovens, or other heterogeneous inorganic particles. The RDL substrate may also omit the permanent core structure generally associated with the laminate substrate. The substrate (110) disclosed herein may constitute and refer to the RDL substrate.

[0022] In the present example, the substrate (110) may include an inner side of the substrate (110a), an outer side of the substrate (110b) opposite to the inner side of the substrate (110a), a dielectric structure (111), and a conductor structure (112). In some examples, the dielectric structure (111) includes a first dielectric layer (111a) defining the inner side of the substrate (110a) and a second dielectric layer (111b) defining the outer side of the substrate (110b). In some examples, the dielectric layer (111a) includes a first side width and the dielectric layer (111b) includes a second side width smaller than the first side width, so that an upper portion of the dielectric layer (111a) is exposed from the dielectric layer (111b) near the side edge of the electronic device (100). This can form a step shape between the first dielectric layer (111a) and the second dielectric layer (111b) in the cross-sectional view. The substrate (110) may include or be referred to as a fan-out RDL layer.

[0023] In some examples, the conductive structure (112) may include a conductive layer (112a) and a conductive layer (112b). In some examples, the conductive layer (112a) includes a substrate internal terminal (112c) adjacent to the substrate internal side (110a), and the conductive layer (112b) includes a substrate external terminal (112d) and a substrate edge terminal (112e) adjacent to the substrate external side (110b). According to the present description, the substrate edge terminal (112e) is adjacent to the peripheral edge of the substrate (110). The substrate internal terminal (112c) may also be referred to as an internal contact pad, and the substrate external terminal (112d) and the substrate edge terminal (112e) may also be referred to as an external contact pad or an external land. In some examples, the conductive layer (112b) includes a seed layer (1120). In some examples, the conductive layer (112a) may include a seed layer similar to the conductive layer (112b). In other examples, an additional conductive layer may be used.

[0024] According to the description, the substrate edge terminal (112e) includes a region (1121) that extends laterally outward in the direction of the side edge of the electronic device (100). In some examples, the region (1121) of the substrate edge terminal (112e) extends to overlap with the outer end of the dielectric layer (111b) and extends over the region of the dielectric layer (111a). In this example, the region (1121) includes both vertical and horizontal regions or segments. In some examples, the segments may extend in different directions. In some examples, the directions may be substantially orthogonal to each other. In some examples, the segments may be at an angle to each other. The region (1121) of the substrate edge terminal (112e) may be composed of or referred to as a wettable side region, a wettable side surface, or an outward side surface, and is configured to increase the wettable area of ​​the attachment material when connecting the electronic device (100) to the next assembly step. These attachment materials include, for example, solder. In this example, the substrate edge terminal (112e) is located on the dielectric layer (111a) and includes a segment at the same interconnect level as the conductive layer (112a).

[0025] In some examples, the electronic component (120) includes an upper side (120a), a lower side (120b) opposite to the upper side (120a), and a side (120c) connecting the upper side (120a) and the lower side (120b). The upper side (120a) may also be referred to as the upper side of the component, the lower side (120b) may also be referred to as the lower side of the component, and the side (120c) may also be referred to as the side of the component. In this example, the side (120c) may define the perimeter or installation area of ​​the electronic component (120).

[0026] In the present example, the electronic component (120) includes a component interconnect (121) adjacent to the upper side (120a) and connected to the conductive structure (112). In some examples, the component interconnect (121) is connected to the substrate internal terminal (112c) of the conductive layer (112a). The upper side (120a) may be configured or referred to as the first surface or active surface of the electronic component (120), and the lower side (120b) may be configured or referred to as the second surface or inactive surface of the electronic component (120). In other examples, the lower side (120b) may be the active surface of the electronic component and may be coupled to the conductive structure (112) using a clip or other conductive connection structure.

[0027] In some examples, the encapsulant (140) encapsulates or covers the lower side (120b) and the side (120c) of the electronic component (120). The encapsulant (140) includes an upper side (140a), a lower side (140b) opposite to the upper side (140a), and a side (140c) connecting the upper side (140a) and the lower side (140b). The upper side (140a) may be referred to as the upper side of the encapsulant, the lower side (140b) may be referred to as the lower side of the encapsulant, and the side (140c) may be referred to as the side of the encapsulant.

[0028] In this example, the upper side (120a) of the electronic component (120) is exposed from the encapsulant (140) at the upper side (140a). In this example, the upper side (120a) is covered by a substrate (110) comprising a dielectric structure (111) and a conductive structure (112). In this example, the conductive layer (112b) includes a substrate edge terminal (112e) that extends horizontally to a position close to the side (140c) of the encapsulant (140). In this example, the side (140c) and the end region of the dielectric layer (111a) do not have the conductive layer (112b). As described later, the substrate edge terminal may extend to overlap with the end region of the dielectric layer (111a) and may extend over the exposed area of ​​the upper side (140a) of the encapsulant (140).

[0029] The substrate (110) and the encapsulant (140) may be referred to as an electronic package or a package. The electronic package can prevent the electronic component (120) from being exposed to external elements and / or the environment. The electronic package can also provide electrical coupling between the electronic component (120) and an external component or another electronic package.

[0030] FIG. 2 illustrates a partial cross-sectional view in which an electronic device (100) is connected to a next-stage assembly, such as an assembly board (151). In this example, the assembly board (151) includes a printed circuit board (PCB) or a mounting substrate. In some examples, the assembly board (151) includes a conductive trace (153) located near the upper side of the assembly board (151). In this example, the substrate outer terminal (112d) and the substrate edge terminal (112e) of the conductive layer (112b) are attached to the conductive trace (153) using an adhesive material (154), such as solder. According to the present disclosure, the area (1121) of the substrate edge terminal (112e) provides an additional surface area for the adhesive material (154) compared to conventional devices. Among other things, this improves the ability to perform necessary visual inspections of the bonded surface.

[0031] FIGS. 3a through 3h illustrate cross-sectional views of an exemplary method for manufacturing an exemplary electronic device such as the electronic device (100) shown in FIG. 1.

[0032] FIG. 3a is a cross-sectional view of an electronic device (100) in the initial stage of manufacturing. In the example shown in FIG. 3a, the electronic device (100) is depicted as a plurality of electronic devices (100) including electronic components (120) and encapsulants (140) coupled to a carrier (160).

[0033] In this example, the electronic component (120) is provided covered by an encapsulant (140), and the upper side (120a) of the electronic component (120) is exposed from the upper side (140a) of the encapsulant (140). In some examples, the carrier (160) may be provided as a circular wafer in a wafer-level process or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. In some examples, the carrier (160) may be composed of silicon, glass, ceramic, or other materials known to a person of ordinary knowledge in the art. In some examples, the thickness of the carrier (160) is in the range of about 3 microns to 300 microns.

[0034] In some examples, the electronic component (120) may be composed of or referred to as a semiconductor die, a semiconductor chip, or a semiconductor package, respectively. A semiconductor die or chip may include an integrated circuit die separated from a semiconductor wafer. The electronic component (120) may include a digital signal processor (DSP), a network processor, a power management device, an audio processor, an RF circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory, and an application-specific integrated circuit (ASIC). In other examples, the electronic component (120) may include a power semiconductor device such as a metal oxide semiconductor field-effect transistor (MOSFET) or a bipolar transistor device. The electronic component (120) may include an active or passive component. The thickness of the electronic component (120) may be from about 20 μm to about 1000 μm. In some examples, the electronic component (120) may perform computation and control processing, store data, or remove noise from electrical signals.

[0035] In some examples, the electronic component (120) may include a component interconnect (121) adjacent to the upper side (120a). In some examples, the component interconnect may be located on or overlay the upper side (120a). The component interconnect (121) may include or refer to a terminal, bond pad, bump, filler, pad, or solder ball. The component interconnect (121) may be provided as an electrical contact between the electronic component (120) and the substrate (110). In some examples, the component interconnect (121) may include copper (Cu), lead (Pb), tin (Sn), aluminum (Al), palladium (Pd), titanium (Ti), tungsten (W), titanium / tungsten (Ti / W), nickel (Ni), gold (Au), silver (Ag), or tin / silver (SnAg).

[0036] In some examples, the encapsulant (140) may comprise an epoxy resin or a phenolic resin, carbon black, a silica filler, or other materials known to a person skilled in the art. In some examples, the encapsulant (140) may be composed of or referred to as a body, a molded body, a molding compound, a resin, a sealant, a filler-reinforcing polymer, or an organic body.

[0037] In some examples, the encapsulant (140) may be located on the side (120c) and lower side (120b) of the electronic component (120). In some examples, the upper side (120a) of the electronic component (120) may be exposed outside the encapsulant (140) from the upper side (140a) of the encapsulant (140). In some examples, the upper side (120a) and the upper side (140a) may be located substantially on the same plane. In some examples, a portion of the encapsulant (140) is located between the side (120c) of the electronic component (120) facing each other. In other examples, the lower side (120b) of the electronic component (120) may be exposed from the encapsulant (140) at the lower side (140b).

[0038] In some examples, the encapsulant (140) may be provided by compression molding, transfer molding, liquid phase molding, vacuum lamination, paste printing, or film assist molding. Compression molding may be a process of supplying a fluid resin to a mold in advance and then placing an electronic component into the mold to cure the fluid resin, and transfer molding may be a process of supplying a fluid resin from a gate (supply port) of the mold to the periphery of the electronic component and then curing it. The encapsulant (140) may have a thickness of about 100 μm to about 1000 μm. The encapsulant (140) may protect the electronic component (120) from external elements or environmental exposure.

[0039] FIG. 3b illustrates an electronic device (100) after additional processes. In this example, the fabrication of the substrate (110) may begin with a build-up process to form a dielectric layer (111a) on the upper side (120a) of the electronic component (120) and the upper side (140a) of the encapsulant (140). In some examples, the dielectric layer (111a) may be composed of a photodefinable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB)-based resin, or polybenzoxazole (PBO). To allow for the proper formation of desired photodefinable features, these photodefinable dielectric materials may be filler-free, without structural reinforcement or fibers, weaves, or other particles that could interfere with light during the photopatterning process. In some examples, the filler-free nature of these filler-free dielectric materials may reduce the thickness of the resulting dielectric layer. In some examples, when the dielectric layer (111a) comprises an organic dielectric material, the dielectric layer (111a) may be provided by pre-formed film attachment, spin coating, spray coating, printing, or other techniques known to those skilled in the art. In some examples, the layer (111a) is silicon nitride (Si N₄, silicon oxide (SiO₂) It may be composed of an inorganic dielectric such as ), and / or SiON. This inorganic dielectric may be filler-free, without fibers, weaves, or other heterogeneous inorganic particles. In some examples, where the dielectric layer (111a) comprises an inorganic dielectric, the dielectric layer (111a) may be provided by pre-formed film attachment, spin coating, spray coating, printing, oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or other processes known to a person skilled in the art. In some examples, the thickness of the dielectric layer (111a) may be between about 1 micron and about 10 microns.

[0040] FIG. 3c illustrates an electronic device (100) after additional processing. In this example, the dielectric layer (111a) is patterned to provide an opening to expose a portion of the component interconnect (121) between the electronic components (120) and a portion of the encapsulant (140). In some examples, photolithography and etching processes are used to pattern the dielectric layer (111a). Then, a conductive material can be provided over the dielectric layer (111a) and the encapsulant (140) to pattern the internal terminal (112c) connected to the component interconnect (121), the dielectric layer (111a), and the conductive layer (112a) over the substrate.

[0041] The conductive layer (112a) may form a conductive pattern, which may be referred to as a conductive pattern, and this is an example of a first conductive pattern. In some examples, the conductive layer (112a) may comprise Cu, Al, Pd, Ti, W, TiW, Ni, Au, Ag, or SnAg and may be provided by sputtering, electroless plating, electroplating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to those skilled in the art. The position of the conductive layer (112a) on the dielectric layer (111a) may be created, for example, using a photolithography process and a photopatterning process in which a photolithography mask is formed using a photoresist material and then an etching process is performed.

[0042] In some examples, the conductive layer (112a) may include or refer to one or more conductors, conductive materials, conductive paths, conductive patterns, redistribution layers (RDL), wiring layers, traces, vias, lands, pads, or under-bump metallization (UBM). In some examples, the substrate internal terminals (112c) may also be referred to as pads, lands, UBMs, or studs. The conductive layer (112a) may be an example of a first conductive pattern. In some examples, the thickness of the conductive layer (112a) may be between 1 micron and about 40 microns. In other examples, the thickness of the conductive layer (112a) may be between about 1 micron and about 10 microns.

[0043] FIG. 3d illustrates an electronic device (100) after additional processing. In this example, a dielectric layer (111b) is provided on top of a conductive layer (112a), a dielectric layer (111a), and an encapsulant (140). In some examples, the dielectric layer (111b) may comprise a material similar to the dielectric layer (111a), may be provided using a similar process, and may have a similar thickness. In other examples, the dielectric layer (111b) may comprise a material different from the dielectric layer (111a), be provided using a different process, or have a different thickness. In this example, the dielectric layer (111a) and the dielectric layer (111b) form a dielectric structure (111). It is understood that in some examples, an additional dielectric layer may be used. The total thickness of all layers of the dielectric structure (111) may define the thickness of the substrate (110). In some examples, the total thickness of the dielectric structure (111) may be between about 10 microns and about 1000 microns.

[0044] FIG. 3e illustrates an electronic device (100) after additional processing. In this example, the dielectric layer (111b) is patterned to provide an opening for exposing a portion of the conductive layer (112a), a portion of the dielectric layer (111a), and a portion of the encapsulant (140) between the electronic components (120). Photolithography and etching processes may be used for patterning the dielectric layer (111b). In this example, the dielectric layer (111b) is positioned laterally recessed from the dielectric layer (111a) to provide a stepped region (114). In other words, in each electronic device (100), the lateral width of the dielectric layer (111b) is smaller than the lateral width of the dielectric layer (111a).

[0045] FIG. 3f illustrates an electronic device (100) after an additional process. In this example, a seed layer (1120) is provided over a dielectric layer (111b), a portion of a conductive layer (112a), a portion of a dielectric layer (111a), and a portion of an encapsulant (140). In some examples, the seed layer (1120) comprises a conductive material such as titanium copper (TiCu). In some examples, the thickness of the titanium layer may range from about 50 nanometers (nm) to 100 nm, and the thickness of the copper layer may range from about 150 nm to about 250 nm. In an example where the electronic component (120) comprises a power device, the thickness of the copper layer may be thicker than 250 nm. In some examples, the seed layer (1120) may be formed by electroless plating, electroplating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to a person skilled in the art.

[0046] FIG. 3g illustrates an electronic device (100) after additional processes. In this example, a mask (51) is provided over a portion of the seed layer (1120). In some examples, after the masking layer is provided, an opening is provided to expose a portion of the seed layer (1120) to which a conductive layer (112b) is to be provided. In some examples, the mask (51) comprises a dry resist provided using a photolithography process, and its thickness may be in the range of about 20 microns to about 50 microns. Then, a conductive layer (112b) having a substrate external terminal (112d) is provided within the opening of the mask (51). In some examples, the conductive layer (112b) is provided using a plating process. In some examples, the conductive layer (112b) is composed of CuNiAu and its thickness may be in the range of about 5 microns to about 25 microns. In some examples, the thickness may range from about 5 microns to about 15 microns. In other examples, the conductive layer (112b) may additionally include a solder layer such as SnAg provided through a plating process or SnAgCu (SAC) provided through a ball drop process (e.g., see solder layer (112f) in FIG. 4b).

[0047] The conductive layer (112b) may be composed of or referred to as a conductor, conductive material, conductive path, conductive pattern, RDL, wiring layer, trace, via, land, pad, or under bump metallization (UBM). In some examples, the substrate outer terminal (112d) and the substrate edge terminal (112e) may be referred to as a second-stage pad, pad, or land. The conductive layer (112b) is an example of a second conductive pattern.

[0048] In this example, the conductive layer (112b) includes a substrate outer terminal (112d) and a substrate edge terminal (112e). According to this description, the substrate edge terminal (112e) includes a region (1121) that extends laterally outward in the direction of the side edge of the electronic device (100). In some examples, the region (1121) extends to overlap with the outer end of the dielectric layer (111b) and extends over the region of the dielectric layer (111a). In this example, the region (1121) includes both vertical and horizontal regions or segments. In some examples, the segments may extend in different directions. In some examples, the directions may be substantially orthogonal to each other. In this example, the region (1121) of the substrate edge terminal (112e) is located between the side (120c) of the electronic component and the side (140c) of the encapsulant (140). In other words, the region (1121) is outside the footprint or perimeter of the electronic component (120). In some examples, the segments may be angled to each other. The region (1121) may constitute or refer to a wettable side region, a wettable side surface, or an outward side surface, and is configured to increase the wettable area of ​​the attachment material when connecting the electronic device (100) to the next stage of assembly. Such attachment materials include, for example, solder. The region (1121) is an example of a first wettable side region or a first outward side surface.

[0049] In the present example, the substrate (110) comprises a dielectric structure (111), which includes dielectric layers (111a and 111b), and a conductive structure (112), which includes conductive layers (112a and 112b), a substrate internal terminal (112c), a substrate external terminal (112d), and a substrate edge terminal (112e) having a region (1121). The substrate (110) composed of the dielectric structure (111) and the conductive structure (112) can support an electronic component (120) and can connect the electronic component (120) to an external device. It is understood that additional dielectric layers or conductive layers may be used with the substrate (110). In some examples, traces or vias connect the substrate external terminal (112d) and the substrate edge terminal (112e) to the substrate internal terminal (112c). In some examples, the substrate outer terminal (112d) and the substrate edge terminal (112e) may protrude outward from the dielectric layer (111b).

[0050] In this example, the substrate (110) includes an inner substrate (110a) adjacent to the upper side (140a) of the encapsulant (140) and the upper side (120a) of the electronic component (120), and an outer substrate (110b) located opposite the inner substrate (110a).

[0051] In some examples, after the conductive layer (112b) is provided, the mask (51) can be removed, and the corresponding area of ​​the seed layer (1120) covered by the mask (51) can be removed, for example, using an etching process. In some examples, the conductive layer (112b) can act as a mask during the removal process of the exposed area of ​​the seed layer (1120). In a subsequent step, a singulation process can be used to separate the structure into individual electronic devices (100), as illustrated in FIG. 3h. In some examples, the structure can be separated through the encapsulant (140) using laser separation or sawing singulation. In some examples, the singulation process defines a side (140c) of the encapsulant (140). In this example, the side (140c) of the encapsulant (140) includes a separated surface and is not a formed surface. In some examples, the carrier (160) may be removed after the singulation process. In other examples, the carrier (160) may be removed before the singulation process.

[0052] FIG. 4a illustrates a partial cross-sectional view of an electronic device (100A) according to the present description. The electronic device (100A) has similarities to the electronic device (100), and such similarities are not repeated herein. In this example, the substrate edge terminal (112e) additionally includes a region (1121a) of the conductive layer (112b) that extends more horizontally toward the side (140c) of the encapsulant (140). In these examples, the region (1121a) covers the end surface of the dielectric layer (111a) and extends over and contacts the upper side (140a) of the encapsulant (140). According to the present description, the region (1121a) provides an additional surface area for the attachment material when the electronic device (100A) is attached to the next stage assembly. Among other things, this improves the ability to perform the necessary visual inspection of the bonded surface.

[0053] FIG. 4b illustrates an exemplary partial cross-sectional view of an electronic device (100B) according to the present description. The electronic device (100B) has similarities to the electronic device (100), and such similarities will not be repeated herein. In the present example, the conductive layer (112b) further comprises a solder layer (112f) formed on top of the conductive layer (112b). In some examples, the solder layer (112f) may be composed of SnAg provided using a plating process or SnAgCu (SAC) provided using a ball drop process. In some examples, the solder layer (112f) may be provided as a semi-ball structure. The solder layer (112f) is shown in FIG. 4b in a state after a reflow process. The solder layer (112f) may include or be referred to as solder or a solder structure. It is understood that other solder materials may be used, and that the solder layer (112f) may be used with all examples described herein.

[0054] FIG. 5 illustrates a cross-sectional view of an electronic device (200) according to the present description. In this example, the electronic device (200) is illustrated as a WFLO structure including a wettable side configuration. In this example, the electronic device (200) may include a substrate (110), an electronic component (120), and an encapsulant (140). The electronic device (200) has some structural similarities with the electronic device (100), and such similarities will not be repeated here. In this regard, only specific differences between the electronic devices will be described.

[0055] According to the description, the encapsulant (140) of the electronic device (200) includes a tapered edge (140d) that may extend from the upper side (140a) of the encapsulant (140) to the side (140c). The tapered edge (140d) may include, or may be referred to as, a concave portion, a concave sidewall, an inclined sidewall, or a groove. Additionally, the substrate edge terminal (112e) in the electronic device (200) further includes a region (1122) that extends laterally to cover the side edge of the dielectric layer (111a), the upper side (140a), and the inclined edge (140d) of the encapsulant (140). In this example, the substrate edge terminal (112e) is terminated on the encapsulant (140) at a position below the upper side (140a) of the encapsulant (140). In other examples, the edges extending into the encapsulant (140) may be less tapered or substantially vertical than those shown in FIG. 5.

[0056] In some examples, the encapsulant (140) includes a ledge (140e) adjacent to the bottom of the sloped edge (140d) where the substrate edge terminal (112e) is not present. This prevents the electronic device (200) from being singulated through the substrate edge terminal (112e) when separated into individual devices. In other examples, the substrate edge terminal (112e) may cover the ledge (140e). Similar to region (1121), region (1122) may constitute or refer to a wettable side region or an outward-facing side surface and is configured to increase the wettable area of ​​the attachment material when connecting the electronic device (200) to the assembly of the next stage. Such attachment materials include, for example, solder.

[0057] FIG. 6 illustrates a partial cross-sectional view of an electronic device (200) connected to an assembly board (151). In this example, the substrate outer terminal (112d) and the substrate edge terminal (112e) are attached to a conductive trace (153) via an adhesive material (154). According to this description, the regions (1121) and (1122) of the substrate edge terminal (112e) provide additional surface areas for the adhesive material (154) compared to the existing device. This improves, among other things, the ability to perform necessary visual inspections of the bonded surface. In some examples, the adhesive material (154) may overlap with or contact the protrusion (140e).

[0058] FIGS. 7a through 7f illustrate cross-sectional views of an exemplary method for manufacturing an exemplary electronic device, such as the electronic device (200) shown in FIG. 5. The method described in FIGS. 7a through 7f has some similarities to the method described in FIGS. 3a through 3h, and such similarities will not be repeated here. In this regard, only specific differences between the methods will be described.

[0059] FIG. 7a is a cross-sectional view of an electronic device (200) in the manufacturing stage. In the example shown in FIG. 7a, the electronic device (200) is shown as a plurality of electronic components (120) and encapsulant (140) coupled to a carrier (160). In this example, prior to the seed layer (1120) and the conductive layer (112b) being provided, a portion of the substrate (110) is provided on the upper side (140a) of the encapsulant (140) and the upper side (120a) of the electronic components (120), as previously described (e.g., see FIG. 3a and FIG. 3e). As illustrated in FIG. 7a, an opening (1110a) is provided in the dielectric layer (111a) so that a portion of the upper side (140a) of the encapsulant (140) is exposed, which may correspond to singulation lines or scribe grids for separating the electronic device (200) into individual devices. In another example, the dielectric layer (111a) may have a shape in which the thickness is reduced at the singulation lines.

[0060] FIG. 7b illustrates an electronic device (200) after additional processing. In this example, a groove (1440) is formed within the opening (1110a) and extends partially into the encapsulant (140) from the upper side (140a). This provides a beveled edge (140d) to the encapsulant (140). In some examples, a dicing blade with a beveled chamfered edge may be used to form the groove (1440) in the encapsulant (140). In other examples, laser scribing or etching may be used to form the groove (1440). In some examples, the groove (1440) extends to a depth of about 25 microns to about 250 microns or more within the encapsulant (140). In some examples, the groove (1440) extends to a depth below the lower side (120b) of the electronic component (120). In another example, the groove (1440) extends to a depth between the upper side (120a) and the lower side (120b) of the electronic component (120). After the groove (1440) is formed, the surface of the groove (1440) can be cleaned and prepared for further processing.

[0061] FIG. 7c illustrates an electronic device (200) after additional processing. In this example, a seed layer (1120) is provided over a dielectric layer (111b), a portion of a conductive layer (112a), a portion of a dielectric layer (111a), and a groove (1440). In some examples, the seed layer (1120) comprises a conductive material such as titanium copper (TiCu). In some examples, the thickness of the titanium layer may range from about 50 nanometers (nm) to 100 nm, and the thickness of the copper layer may range from about 150 nm to about 250 nm. In an example where the electronic component (120) includes a power device, the thickness of the copper layer may be thicker than 250 nm. In some examples, the seed layer (1120) may be formed by electroless plating, electroplating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to a person skilled in the art. The tapered edge (140d) improves the step coverage of the seed layer (1120) within the groove (1440), thereby improving coverage of the area (1122) of the conductive layer (112b).

[0062] FIG. 7d illustrates an electronic device (200) after additional processing. In this example, a mask (51) is provided on a portion of the seed layer (1120). In some examples, after the masking layer is provided, an opening is provided to expose a portion of the seed layer (1120) to which a conductive layer (112b) is to be provided, which is patterned. In some examples, the mask (51) comprises a dry resist provided using a photolithography process and may have a thickness ranging from about 20 microns to about 50 microns. A conductive layer (112b) having a substrate outer terminal (112d) and a substrate edge terminal (112e) is provided within the opening of the mask (51). In some examples, the conductive layer (112b) is provided using a plating process. In some examples, the conductive layer (112b) may be composed of CuNiAu and may have a thickness ranging from about 5 microns to about 25 microns. In another example, the conductive layer (112b) may additionally include a solder layer such as SnAg provided using a plating process or SnAgCu (SAC) provided using a ball drop process (e.g., see solder layer (112f) in FIG. 4b).

[0063] According to the present description, the substrate edge terminal (112e) includes a region (1122) that extends laterally outward from the region (1121) and overlaps onto the tapered edge (140d) of the encapsulant (140). In this example, the region (1122) is located between the side (120c) of the electronic component and the side (140c) of the encapsulant (140). Alternatively, the region (1122) is outside the footprint or perimeter of the electronic component (120). The region (1122) may constitute or refer to a wettable side region, a wettable side surface, or an outward side surface, and is configured to increase the wettable area of ​​the attachment material when connecting the electronic device (200) to the assembly of the next stage. Such attachment materials include, for example, solder. The area (1122) is an example of a second wettable lateral area or a second outward-facing lateral surface.

[0064] FIG. 7e illustrates an electronic device (200) after an additional process. In this example, after the conductive layer (112b) is provided, the mask (51) can be removed and the corresponding area of ​​the seed layer (1120) covered by the mask (51) can be removed, for example, using an etching process. In some examples, the conductive layer (112b) can act as a mask while removing the exposed area of ​​the seed layer (1120).

[0065] In this example, the substrate (110) comprises a dielectric structure (111) comprising dielectric layers (111a and 111b), a conductive structure (112) comprising conductive layers (112a and 112b), a substrate internal terminal (112c), a substrate external terminal (112d), and a substrate edge terminal (112e) having a region (1121). It is understood that additional dielectric layers or conductive layers may be used in the substrate (110). In some examples, a trace or via connects the substrate external terminal (112d) and the substrate edge terminal (112e) to the substrate internal terminal (112c).

[0066] FIG. 7f illustrates an electronic device (200) after an additional process. In this example, a singulation process may be used to separate the structure into individual electronic devices (200). In some examples, laser singulation or sawing singulation may be used to separate the structure through the encapsulant (140). In some examples, the singulation process defines a side (140c) of the encapsulant (140). In some examples, the carrier (160) may be removed after the singulation process. In other examples, the carrier (160) may be removed before the singulation process.

[0067] In another example, the groove (1440) is extended to a depth below the lower side (120b) of the electronic component (120), and a removal step is used to remove a portion of the encapsulant (140) from the lower side (140b) until the removal process reaches the lower side of the groove (1440). In another example, a regional separation operation can be performed through the lower side of the groove (1440), and the removal process can be performed and terminated on the lower side where partial singulation has been achieved. Back grinding or etching may be used for the removal process.

[0068] In other examples, a substrate (110) for an electronic device (100) or an electronic device (200) may comprise a pre-formed substrate. The pre-formed substrate may be manufactured before being attached to the electronic device and may include a dielectric layer between each conductive layer. The conductive layer may comprise copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer and may be attached in the form of a pre-formed film rather than in liquid form. It may also comprise a resin containing a filler, such as a fiber (strand), woven fabric, or other inorganic particles, for rigidity or structural support. Since the dielectric layer is non-photodefinable, features such as vias or openings may be formed using a drill or a laser. In some examples, the dielectric layer may be composed of prepreg material or an Ajinomoto build-up film (ABF). The pre-formed substrate may include a permanent core structure or a carrier, such as a dielectric material composed of, for example, bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In another example, the pre-formed substrate may be a coreless substrate with the permanent core structure omitted, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the formation of the dielectric and conductive layers and before attachment of the electronic device. The pre-formed substrate may be a printed circuit board (PCB) or a laminate substrate. Such a pre-formed substrate may be formed through a semi-additive process or a modified-semi-additive process. In an additional example, the substrate (110) may include a multilayer substrate or a molded lead frame.

[0069] In summary, structures and methods related to electronic devices having improved wetting lateral capabilities have been described. More specifically, structures and methods for improving the manufacturability of wafer-level substrates, such as redistribution layer (RDL) substrates, have substrate edge terminals that extend to and terminate at the substrate lateral edge. In some examples, the substrate edge terminals further extend and overlap the edges of the encapsulant covering internal electronic components. This wetting lateral configuration protects the underlying conductor (e.g., copper (Cu)) and allows soldering to occur in this outer lateral region of the substrate edge terminal, thereby enabling optical inspection to confirm good solder fillet joints and consequently good electrical connections.

[0070] While this disclosure refers to specific examples, those skilled in the art will understand that various modifications and equivalent substitutions are possible without departing from the scope of this disclosure. Furthermore, modifications to the disclosed examples are possible without departing from the scope of this disclosure. Accordingly, this disclosure is not limited to the disclosed examples but is intended to include all examples falling within the scope of the appended claims.

Claims

Claim 1 In electronic devices, Upper side; Lower side facing the upper surface; A side connecting the upper and lower sides; and An electronic component including a component interconnect adjacent to the upper side; Incapsulant upper side; Incapsulant lower side; and An encapsulant including an encapsulant side, wherein, the upper side of an electronic component is exposed from the upper side of the encapsulant; the side of the encapsulant covers the side of the electronic component; and The first dielectric layer; and A second dielectric layer having a side end positioned on the first dielectric layer and interposed between the side of the electronic component and the side of the encapsulant; Genome structure including; and A first conductive layer coupled to a component interconnect; and A second conductive layer coupled to a first conductive layer; A conductor structure including, where, An electronic device comprising a substrate including a second conductive layer that includes a substrate edge terminal extending to overlap the side edge of the second dielectric layer and including a first region covering a portion of the first dielectric layer. Claim 2 An electronic device according to claim 1, wherein the first dielectric layer comprises a first side width; the second dielectric layer comprises a second side width smaller than the first side width; and the first region of the substrate edge terminal contacts the upper side of the first dielectric layer adjacent to the encapsulant side. Claim 3 An electronic device according to claim 1, wherein the encapsulant comprises a tapered edge extending from the upper side of the encapsulant to the side of the encapsulant; and the substrate edge terminal comprises a second region extending to cover a portion of the tapered edge. Claim 4 In claim 3, the second region of the substrate edge terminal terminates the position of the tapered edge located between the upper side of the electronic component and the lower side of the electronic component, an electronic device. Claim 5 An electronic device according to claim 1, wherein the first region of the substrate edge terminal comprises segments extending in different directions that define a wetting lateral surface. Claim 6 An electronic device according to claim 1, wherein the first region of the substrate edge terminal contacts the upper side of the encapsulant. Claim 7 An electronic device according to claim 1, wherein the substrate edge terminal overlaps the upper side of the second dielectric layer and protrudes outward from the upper side of the second dielectric layer. Claim 8 An electronic device according to claim 1, further comprising an assembly board including a conductive trace, wherein a substrate edge terminal is coupled to the conductive trace through an attachment material; and the attachment material covers a first region of the substrate edge terminal. Claim 9 An electronic device according to claim 1, wherein the encapsulant side comprises a singulated surface. Claim 10 An electronic device according to claim 1, wherein the substrate comprises a redistribution layer (RDL) substrate; and the second conductive layer comprises a seed layer and a plating material. Claim 11 In electronic devices, Upper side; Lower side facing the upper side; A side connecting the upper and lower sides; and An electronic component including a component interconnect adjacent to the upper side; Incapsulant upper side; Incapsulant lower side; and An encapsulant comprising an encapsulant side, wherein the upper side of an electronic component is exposed from the upper side of the encapsulant; and the encapsulant side covers the side of the electronic component; and The first dielectric layer; and A second dielectric layer having a side end disposed on the first dielectric layer and between the side of the electronic component and the side of the encapsulant, Genome structure including; and A first conductive layer comprising a substrate internal terminal coupled to a component interconnect; and A second conductive layer comprising a substrate external terminal and a substrate edge terminal coupled to a first conductive layer, A conductor structure including, where, An electronic device comprising a substrate, wherein the substrate edge terminal extends to overlap the side edge of a second dielectric layer and includes a first region covering a portion of a first dielectric layer adjacent to the encapsulant side. Claim 12 An electronic device according to claim 11, wherein the encapsulant comprises a tapered edge extending from the upper side of the encapsulant to the side of the encapsulant; and the substrate edge terminal comprises a second region extending to cover a portion of the tapered edge. Claim 13 In claim 12, the second region of the substrate edge terminal terminates the position of the tapered edge located between the upper side of the electronic component and the lower side of the electronic component, an electronic device. Claim 14 In claim 13, the encapsulant side includes a projection adjacent to a lower extension of a tapered edge; and the projection is an electronic device in which a second region of a substrate edge terminal does not exist. Claim 15 An electronic device according to claim 14, further coupled to an assembly board including a conductive trace; a substrate edge terminal coupled to the conductive trace through an attachment material; and the attachment material covering a first region and a second region of the substrate edge terminal and overlapping a protrusion. Claim 16 An electronic device according to claim 12, wherein the first region of the substrate edge terminal defines an outwardly facing side surface. Claim 17 An electronic device according to claim 12, wherein the second conductive layer comprises a seed layer and a plating material. Claim 18 As a method for manufacturing an electronic device, Upper side; Lower side opposite to the upper side; A side connecting the upper and lower sides; and A step of providing an electronic component including a component interconnect adjacent to the upper side; Incapsulant upper side; Incapsulant lower side; and A step of providing an encapsulant including an encapsulant side, wherein: the upper side of an electronic component is exposed from the upper side of the encapsulant; and the encapsulant side covers the side of the electronic component; and The first dielectric layer; and A second dielectric layer having a side end positioned on the first dielectric layer and interposed between the side of the electronic component and the side of the encapsulant; Genome structure including; and A first conductive layer coupled to a component interconnect; and A second conductive layer coupled to a first conductive layer A conductor structure including, where, The second conductive layer includes a substrate edge terminal that extends to overlap the side edge of the second dielectric layer and includes a first region covering a portion of the first dielectric layer; and A method comprising the step of providing a substrate including a first region defining an outwardly facing side surface. Claim 19 In claim 18, the step of providing an encapsulant includes providing a tapered edge extending from the upper side of the encapsulant to the side of the encapsulant; and the step of providing a substrate includes providing a substrate edge terminal comprising a second region extending to cover a portion of the tapered edge. Claim 20 The method of claim 18 further comprises the steps of: providing an assembly board including a conductive trace; and attaching a substrate edge terminal to the conductive trace using an attachment material, wherein the attachment material covers a first region of the substrate edge terminal.

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