Stress layer modification using energetic beam processing through a photoresist mask

Abstract

The method may include the step of providing a stress-compensating laminate on the main surface of a substrate, wherein the stress-compensating laminate comprises a patterned resist layer and a stress-compensating layer disposed below the patterned resist layer. The patterned resist layer may be determined according to a surface map of the main surface of the substrate. The method may further include the step of orienting treatment species toward the stress-compensating laminate, wherein the stress-compensating layer is optionally changed as a function of a position across the substrate.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] The present application claims priority to U.S. Regular Patent Application No. 18 / 399,346 filed by Evans on December 28, 2023, under the title "STRESS LAYER MODIFICATION USING ENERGETIC BEAM PROCESSING THROUGH PHOTORESIST MASK", the entire contents of said patent application incorporated herein by reference.

[0003] The present embodiments relate to stress control in substrates, and more specifically, to stress compensation for managing substrate stress. Background Technology

[0004] Devices such as integrated circuits, memory devices, and logic devices can be fabricated on a substrate, such as a semiconductor wafer, by a combination of deposition processes, etching, ion implantation, annealing, and other processes. Often, the complete fabrication of devices and associated circuits can involve hundreds of operations, including dozens of lithography operations. In particular, lithography operations may require a given mask to be aligned with existing structures to fabricate structures in a given area or level.

[0005] A consequent problem regarding the fabrication of substrates is the occurrence of out-of-plane distortion (OPD) caused by stresses within the wafer, which can be referred to as warping. Such OPD may result from stresses generated within the wafer as a result of processing. Consequently, managing OPD can be important in achieving proper overlay between structures fabricated at different levels of the device. For example, a frequently encountered type of OPD is global substrate curvature, which can occur in many processing instances due to stress accumulation in the wafer as a result of processing operations. A related issue regarding OPD is so-called in-plane distortion, which is associated with distortion within the XY plane of the substrate due to the XYZ distortion characteristics of the OPD.

[0006] One approach to managing wafer (substrate) stress is to provide a stress compensation layer on the back side of the substrate, which can be used to offset existing stress within the substrate and thereby reduce OPD. In certain implementations, ion implantation has been used to implant ions into the stress compensation layer in an attempt to alter the stress state in the stress compensation layer and thereby indirectly change the stress and OPD in the substrate.

[0007] In some approaches, blanket ion implantation can be performed to address global curvature of the substrate by altering the stress state in the stress compensation layer in a uniform manner across the substrate. In other approaches, patterned implantation can be performed to address more diverse OPD patterns in the substrate, such as so-called potato chip curvature or saddle curvature. In known ion implantation approaches, the ion beam can be directed to scan different locations on the substrate to impart a variable ion dose that varies depending on the substrate location.

[0008] Currently, these approaches for implanting ion beams into stress compensation layers of substrates can process substrates at a rate of ~1 to 10 wafers per hour, which may be too slow for commercial wafer manufacturers. Furthermore, patterned ion implantation approaches that utilize scanning of ion beams to generate implantation patterns may lack adequate spatial resolution to address complex patterns of OPDs on the substrate, such as chip-level variations caused by processing operations performed to define circuits on individual die portions of the wafer.

[0009] The embodiments are provided in relation to these and other considerations.

[0010] In one embodiment, a method is provided. The method may include the step of providing a stress-compensating laminate on a main surface of a substrate, wherein the stress-compensating laminate comprises a patterned resist layer and a stress-compensating layer disposed below the patterned layer. The patterned resist layer may be determined according to a surface map of the main surface of the substrate. The method may further include the step of orienting treatment species toward the stress-compensating laminate, wherein the stress-compensating layer is optionally changed as a function of a position across the substrate.

[0011] In another embodiment, the ion implanter may include an ion source for generating an ion beam; a beamline component for changing the scanning of the ion beam; and a controller, wherein the controller includes a processor and a memory unit coupled to the processor and including a scan-type implantation routine. The scan-type implantation routine is operable on the processor to control the ion implanter to impart an implantation pattern within a stress compensation layer on the substrate by receiving a surface map of the substrate and performing scan-type implantation based on the surface map.

[0012] In an additional embodiment, a controller for an ion implanter may include a processor; and a memory unit coupled to the processor and comprising a scan-type implantation routine. The scan-type implantation routine may be operable on the processor to control the ion implanter to impart an implantation pattern within a stress compensation layer on the substrate by receiving a surface map of the substrate and performing scan-type implantation based on the surface map. Brief explanation of the drawing

[0013] FIG. 1a illustrates an exemplary ion implantation system according to the present disclosure. FIG. 1b illustrates additional details of a controller according to some embodiments of the present disclosure. FIG. 2a illustrates an example of a wafer map mapping the surface of a substrate representing the pattern of OPD. FIG. 2b illustrates an exemplary gray-tone resist pattern for managing stress on the substrate of FIG. 2a. FIGS. 3a through 3g depict exemplary steps in processing a substrate to reduce OPD according to some embodiments of the present disclosure. FIG. 3h illustrates an example for processing a stress compensation layer. FIGS. 4a and 4b illustrate two stages for processing a gray tone resist to create a variable resist layer thickness according to one embodiment. FIG. 5a depicts another embodiment using a digital injection mask for substrate-level stress management. FIG. 5b depicts another embodiment using a digital injection mask for chip-level stress management. Figure 6a is a graph showing a three-dimensional surface map of a portion of a substrate at the chip level. FIG. 6b is an example illustrating a three-dimensional surface map of the entire substrate, showing a repeated pattern of OPDs corresponding to 24 different chip regions. Figure 6c depicts a plan view of the substrate of Figure 6b using a gray tone mask to process the repeated pattern of OPD. Fig. 6d depicts a side view of the array of Fig. 6c. FIG. 6e depicts ribbon beam processing of a gray tone resist pattern developed on the substrate of FIG. 6b after the instance of FIG. 6c. Figure 6f depicts an example of non-uniform scanning of the processing beam. Figure 6g depicts a three-dimensional surface map of the substrate of Figure 6b after the processing of Figure 6e and after the subsequent gray tone resist removal. Figure 7 illustrates an exemplary process flow. Figure 8 illustrates an exemplary process flow. Figure 9 illustrates an exemplary process flow. Specific details for implementing the invention

[0014] Now, embodiments of the present invention will be described more fully below with reference to the accompanying drawings, some of which are illustrated. The subject matter of the present disclosure may be embodied in many different forms and should not be interpreted as being limited to the embodiments described herein. Instead, these embodiments are provided so that the present disclosure may be thorough and complete and the scope of the subject matter may be fully conveyed to those skilled in the art. In the drawings, the same numbers throughout refer to the same elements.

[0015] The embodiments described herein relate to techniques and apparatus for improved substrate stress management and associated out-of-plane distortion (OPD) management. These embodiments present an approach utilizing energetic beam processing or energetic particle processing in conjunction with patterned photoresist ("resist") layers and stress control layers to control the damage distribution within the stress control layer in the X, Y, and Z directions, and thereby control OPD on the substrate with better accuracy and resolution.

[0016] Now, referring to FIG. 1a, an exemplary system according to the present disclosure is illustrated. An ion implantation system (hereinafter referred to as the “system”) (10) represents a beamline comprising, among other components, an ion source (14) for generating an ion beam (18), an ion implanter, and a series of beamline components (16). The ion source (14) may include a chamber for receiving a flow of gas (24) and generating ions within it. The ion source (14) may also include an extraction electrode assembly and a power source positioned near the chamber. Although not limited to, the ion source (14) may include a power generator, a plasma exciter, a plasma chamber, and the plasma itself. The plasma source may be an inductively coupled plasma (ICP) source, a toroidal coupled plasma (TCP) source, a capacitively coupled plasma (CCP) source, a helicon source, an electron cyclotron resonance (ECR) source, an indirectly heated cathode (IHC) source, a glow discharge source, an electron beam generating ion source, or other plasma sources known to those skilled in the art. As illustrated, there may be one or more feed sources (28) capable of operating with the chamber of the ion source (14). In various embodiments, different species may be used as ions to be used to treat stress in the film. Non-limiting examples of suitable ions include silicon (Si), boron (B), carbon (C), oxygen (O), germanium (Ge), phosphorus (P), arsenic (As), argon (Ar), krypton (Kr), neon (Ne), and krypton (Kr) for controlling substrate stress.

[0017] Beamline components (16) may include, for example, a mass spectrometer (34) for accelerating, decelerating, shaping, scanning, etc. of the ion beam (18), a first acceleration or deceleration stage (36), a collimator (38), a mass resolving slit (40), and other suitable downstream beamline components, such as an energy filter (42). In certain embodiments, beamline components (16) may filter, focus, accelerate, decelerate, and otherwise manipulate ions or ion beams (18) to have desired species, shape, energy, and other qualities. The ion beam (18) passing through the beamline components (16) may be directed toward a substrate mounted on a platen or clamp within a process chamber (46). As is recognized, the substrate may be moved in one or more dimensions (e.g., translation, rotation, and tilting).

[0018] According to various embodiments of the present disclosure, an ion source (14) may generate an ion beam (18) for processing a substrate by injecting it into a patterned layer to reduce OPD in the substrate. In various embodiments, the ion beam may have a targeted shape, such as a spot beam or a ribbon beam (in cross-section), as is known in the art. In the illustrated Cartesian coordinate system, the propagation direction of the ion beam (18) may be expressed parallel to the Z-axis, whereas the actual trajectories of the ions for the ion beam (18) may vary. To process the substrate, the ion beam (18) may be accelerated to acquire a target energy by establishing a voltage (potential) difference between the ion source (14) and the wafer (substrate). In certain embodiments, the ion beam (18) may be a ribbon beam elongated along the x-direction to cover the entire substrate (100) along the x-direction. As additionally illustrated in FIG. 1, the system (10) may include a controller (50) for controlling the operation of various components of the system (10), including components for scanning the platen (48), tilting the platen (48), scanning the ion beam (18), or adjusting the energy of the ion beam (18). FIG. 1b provides details of an embodiment of the controller (50) which is further discussed below. In this way, the ion beam (18) and / or the platen (48) may be scannable along the Y direction to expose the entire substrate (100).

[0019] FIG. 2a illustrates an example of a wafer map plotting the surface of a substrate (100) showing a pattern of OPD. The OPD as illustrated in FIG. 2a may be a reflection of non-uniform stress within the substrate (100), and accordingly, a pattern of substrate curvature caused at least partially by non-uniform stress is generated. The OPD of FIG. 2a is characterized by a downwardly displaced substrate surface in the uppermost and lowermost regions along the y-axis, and an upwardly displaced substrate surface in the leftmost and rightmost regions along the X-axis, which imparts a saddle shape to the substrate in three dimensions. The center of the substrate (100) can be considered to lie at the zero point along the z-axis. For the illustrated 300 mm diameter wafer (substrate (100)), the maximum downward OPD for 0 is approximately 90 micrometers, while the maximum upward OPD (for the left and right) is approximately 263 micrometers.

[0020] FIG. 2b illustrates an exemplary gray tone resist pattern for managing stress on the substrate of FIG. 2a (for brevity, the word 'resist' as used herein refers to photoresist unless otherwise noted). The resist pattern (101) may be created to provide a mask used in conjunction with ion implantation to reduce or eliminate OPD as illustrated in FIG. 2a. In this example, the resist pattern (101) may represent a gray tone resist pattern formed using a gray tone resist. For the sake of brevity of description, the resist pattern (101) is illustrated as having a plurality of distinct zones illustrated as gray tone zones (102). However, the embodiments encompass more complex patterns of the resist as described in detail below. The resist pattern (101) may include gray tone zones (102) as well as block zones (104). These zones can be designed to attenuate more or fewer ions of an ion beam to be injected into a stress compensation layer (not visible) of a substrate (100) placed under a resist pattern (101).

[0021] In one non-limiting example, block zones (104) may include a resist having a uniform thickness sufficient to block all ions of the ion beam from colliding with the stress compensation layer. Gray tone zones (102) may be defined by resist zones having thicknesses that vary as a function of position across the substrate (in the XY plane), as well as zones where the resist is completely removed. In one embodiment, when the resist pattern (101) is exposed to an ion beam, the ion beam will generate an injection pattern within the stress compensation layer that alters the stress state in the stress compensation layer in a manner that reduces or removes the OPD pattern shown in FIG. 2a.

[0022] To further illustrate the management of substrate stress using gray tone resist patterning in conjunction with ion implantation, FIGS. 3a through 3g depict exemplary steps in processing a substrate to reduce OPD according to some embodiments of the present disclosure. In FIG. 3a, a substrate (100) is shown, which may be a silicon wafer. In some embodiments, the substrate (100) may exhibit curvature including OPD characterized by a complex twisting pattern. In the illustrated example, the substrate is shown, for instance, as a cross-section within the XZ plane of the illustrated Cartesian coordinate system, but relative dimensions in terms of width, substrate thickness, and curvature may not be shown to actual scale. For instance, according to some non-limiting embodiments, the substrate (100) may represent a wafer having a diameter of 200 mm, 300 mm, or other sizes along the main surface. In some embodiments, the thickness of the substrate (100) may be approximately several hundred micrometers. Furthermore, the maximum OPD represented by the substrate (100), in which the OPD can be expressed in terms of deviation from a nominally flat XY plane, can be approximately several hundred micrometers.

[0023] In FIG. 3b, a subsequent instance is shown in which a stress compensation layer (202) is formed on the main surface of the substrate (100). According to some non-limiting embodiments, the stress compensation layer (202) may be a known stress compensation layer material, such as an oxide layer or a nitride layer, including silicon nitride (hereinafter also referred to as "SiN"). Therefore, the stress compensation layer (202) may or may not substantially change the overall stress state of the substrate (100), and accordingly, the pattern of OPD shown in FIG. 3a may continue, as suggested in FIG. 3b.

[0024] In FIG. 3c, a subsequent instance is shown in which a blanket photoresist layer, referred to as a gray tone resist layer (204), is applied to the stress compensation layer (202). The gray tone resist layer (204) may be composed of a known resist material, such as a suitable gray tone resist material. The formation of the gray tone resist layer (204) having a low elastic modulus may produce little to no change in the overall stress state of the substrate (100), and accordingly, the OPD as shown in FIG. 3a may be sustained.

[0025] In FIG. 3d, a subsequent instance is shown in which the gray tone resist layer (204) is treated as a patterned resist layer exhibiting variations in film thickness (meaning thickness along the Z axis) as a function of position along the XY plane. These variations in resist thickness may or may not create exposed areas where the upper surface of the underlying stress compensation layer (202) is exposed. Again, the patterning of the gray tone resist layer (204) may have little or no effect on the pattern of the OPD on the substrate (100).

[0026] In the various embodiments further discussed below, the patterning of the gray tone resist layer (204) may be selected to provide an implantation mask for a subsequent ion implantation process to be performed. The precise pattern of the implantation mask (meaning the patterned gray tone resist layer) may be selected, for example, according to the pattern of the OPD represented by the substrate (100) at the stage of FIG. 3c. In different embodiments, the patterning of the gray tone resist layer (204) may be achieved by exposing the gray tone resist layer to radiation through a gray tone lithography mask that represents a suitable pattern based on the pattern of the OPD. In some examples further discussed below, the resist mask process may be a digital process. After exposure to radiation, the gray tone resist layer (204) may be developed to yield the result of the structure of FIG. 3d. The gray tone lithography mask may be selected, in particular, to vary the degree of exposure of the gray tone resist layer (204) to radiation as a function of position along the XY plane. As a result, the depth of the gray tone resist layer (204) that is altered by radiation will vary along the XY plane, thereby allowing the final thickness of the gray tone resist layer (204) after the subsequent development process to vary. Known gray tone resist masks can provide the ability to vary the resist layer thickness as a function of position along the XY plane on a scale of 100 nm or less. Accordingly, on a lateral (XY) scale of micrometers or more, the variation in the thickness of the gray tone resist layer (204) may appear gradual.

[0027] In some embodiments, the gray tone mask used to pattern the gray tone resist layer (204) may be an imprint mask applied directly to the gray tone resist layer (204) to create a structure as shown in FIG. 3d.

[0028] Referring to FIG. 3e, a subsequent instance is illustrated in which, after patterning, a substrate (100) comprising a stress compensation layer (202) and a gray tone resist layer (204) is exposed to an ion implantation process indicated by an ion beam (206). The ion beam (206) may be selected to have an ion energy suitable for implantation into the substrate (100) in order to change the stress state, particularly within the stress compensation layer (202). In the operation depicted in FIG. 3e, the ion beam (206) is shown as a plurality of ions, and the trajectories of the ions are shown by vertical arrows. Since the ions may exhibit similar energy across the ion beam (206), the implantation depth of the ions into the stress compensation layer (202) is determined, in particular, by the local thickness of the gray tone resist layer (204) as a function of position in the XY plane. As a result, as suggested by the injection profiles (208) associated with different ion positions in FIG. 3e, some regions of the stress compensation layer (202) will receive a relatively larger ion capacity than other regions. Accordingly, in locations where the gray tone resist layer (204) is sufficiently thick, some of the injection profiles (208) may be completely contained within the gray tone resist layer (204); in other regions, the injection profiles may extend into the stress compensation layer by a smaller or larger amount. Consequently, after the injection procedure of FIG. 3e, the amount of injection damage within the stress compensation layer (202) and the resulting stress state will selectively change as a function of the XY position.

[0029] Referring to FIG. 3f, a subsequent instance following the injection process of FIG. 3e is illustrated, wherein the stress state of the stress compensation layer is selectively modified within the XY plane. As a result, by selecting appropriate mask and ion beam parameters, the stress compensation layer (202) exhibits a pattern of injection damage that reflects the pattern of the gray tone resist layer (204), which causes the original OPD of FIG. 3a to be reduced or eliminated, as suggested in FIG. 3f.

[0030] In FIG. 3g, a subsequent processing stage is shown, where a gray tone resist is selectively removed, for example by ashing. Note that a stress compensation layer (202) having a non-uniform injection pattern remains. Accordingly, this non-uniform injection pattern and the resulting non-uniform stress pattern continue to apply force on the substrate (100) so that the substrate is maintained with less OPD.

[0031] In alternative embodiments, at the processing stage illustrated in FIG. 3e, the energy of the ion beam (206) may be adjusted to cause substantial etching of the stress compensation layer (202) in regions where the gray tone resist is completely removed or in regions where the gray tone resist is relatively thin to allow the penetration of ions into the stress compensation layer (202). FIG. 3h illustrates an embodiment in which the stress compensation layer (202) is exposed to an energetic beam to selectively etch the stress compensation layer (202) in regions where the gray tone resist layer is absent or relatively thin. Accordingly, a patterned stress compensation layer having patterned or etched regions is formed. The patterned etched regions may be designed to selectively change the stress state in the stress compensation layer (202) as a function of position in the XY plane, and accordingly, selectively change the stress state in the substrate below—meaning the substrate (100). In this way, a stress pattern is applied to the substrate (100) to reduce existing OPD.

[0032] In different embodiments, selective etching of the stress compensation layer (202) as depicted in FIG. 2h can be performed by an inert ion beam, a reactive ion beam, a radical beam generated from plasma, for example by immersion in a plasma chamber, or by chemical etching.

[0033] According to different embodiments of the present disclosure, a gray tone resist layer may be processed using a gray tone lithography mask having a pattern tailored to create variable thickness in the gray tone resist layer over a suitable length scale to offset the initial substrate OPD. For example, in the case of curvature that creates significant OPD at the wafer level (several centimeters in the XY plane) or at the chip level (several millimeters in the XY plane), stress control within the substrate may be required in the sub-millimeter range along the XY plane to reduce such curvature. Accordingly, in various embodiments, gray tone resist layers having features tailored to vary substantially over a millimeter length scale, a 100-unit micrometer scale, a micrometer scale, or a 100-unit nanometer scale may be manufactured. Such features are readily manufactured according to modern gray tone resist technology.

[0034] In one approach, as previously mentioned, a gray tone resist can be processed using a gray tone mask exposed to suitable radiation to create a desired pattern of the gray tone resist. FIGS. 4a and 4b illustrate two stages for processing the gray tone resist to create a variable effective thickness of the resist layer according to one embodiment. In this example, a light source (252) is used to expose a substrate (250) on which a stress compensation layer (202) and a gray tone resist layer (204) are disposed on top. As in known approaches, a diffuser (not separately illustrated) may optionally be included between the light source (252) and the substrate (250). To create a pattern exposed on the gray tone resist layer (204), a gray tone mask (254) is placed between the gray tone resist layer (204) and the light source (252) to partially attenuate radiation from the light source (252). The gray tone mask (254) may include a patterned area (256) composed of sub-features, the arrangement of which is intended to attenuate radiation passing through the gray tone mask in a manner that varies gradually along the XY plane, for example. For example, the feature size of the patterned features in the patterned area (256) may be designed according to the wavelength of the radiation. For illustrative purposes, the dimensions of the patterned area illustrated along the X and Y directions may be any suitable distance, for example, comparable to the wafer diameter, comparable to the size of the chip (die) on the wafer being processed, or may be less than a millimeter in length. As indicated in FIG. 4a, the attenuation of radiation in the patterned area (256) is greater towards the left side and smaller towards the right side. In the case of a positive resist, this situation will lead to the areas of the gray tone resist layer (204) placed on the right becoming more available to the developer than those areas on the left.As a result, after the exposure in FIG. 4a and subsequent phenomenon, a patterned feature (204A) is formed on the gray tone resist layer (204) as shown in FIG. 4b. In this example, the patterned feature (204A) has a wedge shape with a gradually changing thickness along the X direction. However, any suitable shape including three-dimensional shapes can be imparted to the gray tone resist layer (204) by a suitable design of the patterned gray tone lithography mask.

[0035] In additional embodiments of the present disclosure, a non-gray tone resist layer, such as a known resist having a 'binary' reaction, may be patterned to facilitate selective modification of the underlying stress compensation layer. FIG. 5a depicts another embodiment in which the resist layer is patterned to create a mask that serves as an injection or etching mask to selectively pattern the underlying stress compensation layer. In this example, the resist layer, such as a binary resist, is patterned to form a digitally patterned resist layer illustrated as a resist layer (292), wherein the resist layer (292) partially covers the stress compensation layer (290). In one suitable example of a digital resist pattern, a series of lines may be formed on the resist layer (292), wherein a fixed pitch is implemented between adjacent lines. In order to change the opacity of the digitally patterned resist layer, i.e., the resist layer (292), and accordingly change the degree of exposure of the stress compensation layer (290) to implanted ions or etching species, the duty cycle (line width) of the lines forming the pattern (292A) can be varied as a function of position across the substrate (280). In one example, particularly as illustrated in FIG. 5a, the duty cycle applied to the pulsed deposition beam can be varied for the resist layer (292) to increase toward the middle of the substrate (280). As illustrated in the graph, because the line width is relatively larger toward the middle of the substrate (280), the capacity of energetic species that can affect the stress compensation layer (290) in the middle of the substrate (280) is relatively lower, in contrast to the capacity toward the edges of the substrate (280).In one example, where the substrate is a 300 mm wafer having a thickness of approximately 500 µm to 800 µm, such capacitance variation injected into the stress compensation layer (290) across the substrate (280) as a function of position can offset the global curvature of the substrate (280) (e.g., meaning wafer-level variation as opposed to local variation at the chip level). Note that in the pattern of the resist layer (292), the line pitch may be approximately 1 µm to 10 µm, thereby the line width will vary over a similar range depending on the duty cycle. Furthermore, the resist layer (292) may be arranged as a series of fields, the series of fields having a uniform duty cycle (meaning uniform line width) for the resist lines contained therein, wherein the fields of lines have a width of approximately 1 mm to 10 mm. Accordingly, individual fields of lines may include ~1000 lines of uniform width, where the ion dose received by the stress compensation layer (290) from the ion beam processing the substrate (300) is uniform. Accordingly, the average ion dose received by the substrate (280) may vary in steps of 1 mm to 10 mm width across the substrate (280). However, such step variation on a ~1 mm length scale may nevertheless cause continuous change in the effect on the substrate (280).

[0036] In another example as illustrated in FIG. 5b, a digitally patterned resist layer is illustrated as a resist layer (296) and is formed by a series of chip-scale fields illustrated as fields (296A), which have dimensions of chips such as a side of 1 cm or 2 cm. Within the field (296A), the patterning can proceed at a digitally varying duty cycle at a fixed pitch, as described above, to account for the chip-level OPD or curvature of the substrate (300).

[0037] In the embodiments described above, a gray tone resist process may be used in conjunction with ion implantation to generate an implantation pattern that causes a variable amount of damage as a function of location across the substrate. It should be noted that such a gray tone resist layer may include, in addition to regions where the resist thickness varies, large macroscopic regions (approximately centimeter or millimeter level) where the resist thickness does not vary and consequently the implantation damage does not vary. As mentioned, the precise pattern of such a gray tone resist layer may be determined, for example, by the pattern of OPD measured on the substrate during the formation of the stress compensation layer. In the manufacture of semiconductor or electronic devices on a substrate, such as a silicon wafer, the wafer may be processed in a manner to create an array of similar or identical chip regions that are subsequently cut into individual semiconductor dies. As a result, during processing, a repeatable pattern of device and circuit features may be formed across the substrate, wherein such a repeatable device pattern generates, within the substrate, an accompanying repeatable stress or OPD pattern. In other examples, an array of chip patterns may be generated on a wafer, wherein the chip patterns differ from one another. In any case, variations in OPD across the wafer may represent a length scale of individual chips, such as a signature of several millimeters to several centimeters.

[0038] To address these situations, the present embodiments include approaches for patterning a gray tone resist layer to mimic an OPD pattern on a wafer processed to define an array of chip regions.

[0039] FIG. 6a is a graph presenting a three-dimensional surface map of a portion of a substrate at the chip level. In this example, an array of 24 rectangular zones, illustrated as chip zones (302), is defined on the surface of the substrate (100). FIG. 6b is an example depicting a three-dimensional surface map of the entire substrate (300), illustrating a repeated pattern of OPDs corresponding to 24 different repetitions of the chip zones (302) of FIG. 6a illustrates that the chip zones (302) have a saddle shape, as previously discussed. The substrate (300) may correspond, for example, to a silicon wafer with a diameter of 300 mm. Therefore, each of the chip zones (302) may have a dimension of, for example, 40 mm in the X or Y direction. It should be noted that in this example, the three-dimensional pattern of OPDs is essentially the same in each of the chip zones (302). In other words, on the surface of the substrate (300), a series of 24 different rectangular zones represent a repeated pattern of OPDs that vary on a length scale from millimeters to centimeters. To flatten the substrate and reduce such OPD patterns, a gray tone mask may be designed to have a suitable pattern arranged to facilitate selective patterned injection into the substrate (300).

[0040] In known patterning of wafers, chip-level processing to create repeated device chip patterns, such as the 24 different chip regions illustrated, may also cause variations in the degree of local OPD depending, for example, on the chip location on the wafer. Accordingly, the chip regions (302) may additionally be grouped according to their location on the substrate (300). For the purpose of illustration, a grouping of four different chip regions is illustrated, wherein the grouping is symmetric with respect to the center of the substrate (300). In FIG. 6b, these four different regions are illustrated as region (302A), region (302B), region (302C), and region (302D).

[0041] According to embodiments of the present disclosure, in order to control wafer warping within the requirements for subsequent device processing, an injection pattern may be added to chip-level resist patterns, and such warping may be approximately 100 μm over the entire width of the substrate (300) and may be ~50 times smaller at the chip level.

[0042] FIG. 6c depicts a top view of the substrate of FIG. 6b using a gray tone mask to process a repeated pattern of the OPD of FIG. 6b. FIG. 6d depicts a side view of the array of FIG. 6c. The gray tone mask (310) can generally be designed according to the principles discussed above, particularly in relation to FIG. 4a and FIG. 4b. In this example, the gray tone mask (310) comprises an array of 24 features, illustrated as features (312), having feature shapes illustrated only for illustrative purposes. The features (312) themselves may include resist features or sets of features having variable thickness in the XY plane. Note that the features of the mask (310) can be sized and spaced to overlay chip areas (302) on the substrate (300) when the gray tone mask (310) is aligned on the substrate (300). In FIG. 6c, as further illustrated in FIG. 6d, radiation (330) can be directed through a mask (310) to expose the substrate (300) while a blanket coating of a stress compensation layer (320) and a gray tone resist layer (322) is present. Alternatively, to expose the chip regions (302) individually, a gray tone mask feature having the size of the individual chip region of the chip regions (302) can be stepped across the substrate (300).

[0043] As further illustrated in FIG. 6c, the features (312) may vary in some aspects depending on their position on the gray tone mask (310). For example, following the pattern of the chip regions (302), the features (312) may be grouped into four different groups according to their positions, such as region (312A), region (312B), region (312C), and region (312D). These four different regions may differ from one another in terms of the exact pattern of the features (312) to address local differences in the amount of OPD or pattern between the different regions (302A-302D) on the substrate (300).

[0044] FIG. 6e depicts a gray tone resist pattern (332) developed within a gray tone resist layer (322) on the substrate (300) of FIG. 6b after the instance of FIG. 6c. Subsequently, an ion implantation process may be performed, wherein an ion beam is directed toward the substrate (300) to selectively implant into the stress compensation layer (320) according to the gray tone resist pattern (332). Since the gray tone resist pattern (332) represents a regular array of features overlaying individual features (312), the implantation pattern within the stress compensation layer (320) will reflect a similar pattern. Accordingly, the pattern of implantation damage and stress relief in the substrate (300) will be tailored to mimic the original OPD pattern and, accordingly, locally flatten the substrate within each of the features (312). It should be noted that the approach outlined in FIGS. 6a through 6e facilitates a simpler and faster injection process that can effectively reduce complex OPD patterns on the substrate.

[0045] As further illustrated in FIG. 6e, the gray tone resist pattern (332) may vary in some aspects depending on its location on the gray tone mask substrate (300). For example, following the pattern of the chip regions (302), the final pattern of the gray tone resist pattern (332) may be grouped into four different groups according to the locations, such as region (332A), region (332B), region (332C), and region (332D). These four different regions may differ from one another in terms of the exact pattern of the resist features to resolve local differences in the amount of OPD or pattern between the different regions (302A-302D) on the substrate (300).

[0046] For example, FIG. 6e also depicts an embodiment in which a ribbon processing beam having the width of the substrate (300) can be scanned along the Y direction to expose the entire substrate (300) to processing species, such as ions. Note that in some embodiments, the processing beam may be an ion beam (340) that remains stationary with respect to the Y direction, while the substrate (300) is scanned along the Y direction. In some variations, the ion beam (340) may be a scan-type spot beam that is scanned rapidly along the X-direction at a frequency of ~1 kHz or higher to create a ribbon beam shape, as illustrated, while the scanning of the substrate (300) occurs at a relatively slower speed for a 30 cm wafer, such as several centimeters per second. In some examples, the substrate (300) may be scanned back and forth along the Y direction. After scanning the substrate and / or scanning the ion beam (340) across the substrate (300), ions from the ion beam (340) will be selectively injected into the substrate according to a pattern of gray tone resist pattern (332) including any variations between zones (332A), zone (332B), zone (332C), and zone (332D). This injection can result in selective stress changes within the stress compensation layer (320) by selective injection of ions into different regions of the stress compensation layer (320) as defined by features according to the gray tone resist pattern. As a result, upon exposure to the ion beam (340), such chip regions receiving the ion beam may have reduced OPD. Accordingly, selective and precise modification of the original OPD pattern of the substrate (300) can be achieved in a simple ion exposure process. In one example, the OPD of the substrate (300) in FIG. 6a can be removed at the chip level as well as at the global level across the substrate (300), resulting in a smooth feature-free OPD pattern after the removal of the resist, as shown in FIG. 6g.

[0047] In additional embodiments of the present disclosure, scan-type selective ion implantation may be used in conjunction with the use of the aforementioned gray tone resist mask to control substrate stress and OPD. For example, instead of imparting a uniform ion capacity across the substrate, an ion beam, such as a ribbon ion beam, may be scanned non-uniformly with respect to the substrate to additionally vary the effective ion capacity imparted within the substrate. Non-uniform scanning may refer, for example, to a situation where the scanning rate of the substrate relative to the ion beam varies as a function of the beam position on the substrate. Such non-uniform scanning of the substrate relative to the ion beam may be combined with a variable thickness pattern of the gray tone resist to impart a more complex pattern of implantation damage within the stress compensation layer located beneath the gray tone resist layer. In some examples, where the ion beam can be directed toward the substrate along the Z-axis, the substrate may additionally be rotated around the Z-axis between scans, tilted between scans, tilted and rotated between scans, and so on. In embodiments of an ion beam provided as a scan-type spot beam scanned along the X direction at a frequency of approximately 1 kHz or higher, in order to impart non-uniform ion capacity as a function of position in the XY plane, the scan rate of the scan-type spot beam may vary as a function of position along the X direction along scanning of the substrate along the Y direction. The embodiments are not limited to this context.

[0048] In these latter embodiments, the ion implanter used for implantation into the substrate may receive a set of substrate information containing OPD information of the substrate prior to processing in order to determine an appropriate processing routine for reducing or eliminating OPD by applying a suitable implantation pattern. In addition to the OPD information, the substrate information may include a gray tone resist pattern to be applied to the substrate. Subsequently, the substrate information may be used to determine ion beam processing routine parameters that are tailored to reduce OPD according to a specific OPD pattern and a designed gray tone resist pattern. Such processing parameters may include non-uniform beam scanning conditions, such as variations in the scan speed of the scan-type spot beam, variations in the scan speed of the scanned substrate, rotation of the substrate, tilt of the substrate, etc. An example of a non-uniform implantation pattern that can be utilized by a scan-type ion beam is a beam scanning pattern (350) also illustrated in FIG. 6f, wherein the beam capacity may be increased toward the middle of the substrate (300) as illustrated.

[0049] Referring again to the examples in FIGS. 6a through 6f, in other embodiments, the gray tone resist pattern (332) may be formed in such a way that zones (332A), zone (332B), zone (332C), and zone (332D) all exhibit the same pattern. Instead, to account for local variations in the OPD between zones (302A-302D), a non-uniform beam scanning operation may be performed, wherein a processing beam, such as an ion beam, is scanned differently with respect to the substrate (300) according to the different zones (332A-332D). Accordingly, the scanning of the beam may be performed in such a manner that a lower ion dose is directed toward zone (332D) in contrast to zone (332A). As a result, when exposed to an ion beam (340), the gray tone resist pattern (332) is scanned in a non-uniform manner (when the gray tone resist pattern does not vary between zones (332A-332D)), such chip zones receiving the ion beam may have reduced OPD, as suggested in FIG. 6g. Accordingly, selective and precise modification of the original OPD pattern of the substrate (300) can be achieved in a patterned ion exposure process. In one example, the OPD of the substrate (300) in FIG. 6a can be removed, resulting in a smooth, feature-free OPD pattern after the removal of the resist, as shown in FIG. 6g.

[0050] In additional embodiments, to reduce OPD globally and locally across the substrate (300), the gray tone resist pattern (332) may be arranged such that the patterning differs between different zones (332A-332D), and a non-uniform beam scanning process may be performed on the gray tone resist pattern (332). More generally, according to various embodiments of the present disclosure, a non-uniform beam scanning process that takes into account repeated and non-uniform chip-level photoresist patterns applied over a stress compensation layer may be applied to the substrate.

[0051] To further describe operations related to a non-uniform injection procedure for processing a stress compensation layer (SCL) in conjunction with a patterned gray tone resist layer, FIG. 1b illustrates additional details of a controller (50). In this embodiment, the controller (50) may include a processor (52), such as a known type of microprocessor, a dedicated processor chip, a general-purpose processor chip, or a similar device. The controller (50) may further include a memory or memory unit (54) coupled to the processor (52), wherein the memory unit (54) includes a scan injection routine (56). The scan injection routine (56) may operate on the processor (52) to manage the injection process using an ion beam (18) and a substrate (100) to impart an injection pattern within the stress compensation layer, as discussed above. The memory unit (54) may include a manufactured article. In one embodiment, the memory unit (54) may include any non-transient computer-readable or machine-readable medium, such as an optical, magnetic, or semiconductor storage medium. The storage medium may store various types of computer-executable instructions for implementing one or more of the logic flows described herein. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, such as volatile memory or non-volatile memory, removable or non-removable memory, erasable or inerasable memory, writable or rewriteable memory, etc. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. Examples are not limited to this context.

[0052] In some embodiments, the memory unit (54) may receive and / or store OPD information related to the substrate / stress compensation layer for a given wafer or set of wafers, as discussed above. Examples of OPD information may be wafer surface maps determined from individual wafers or characteristics of a batch of wafers. In some embodiments, the memory unit may store information related to gray tone resist patterns to be applied to the wafer or set of wafers. This information may be expressed in any suitable format, including databases, tabular forms, etc., and may include pre-stored gray tone resist patterns and pre-stored OPD patterns. Subsequently, such information may be used by a scan implantation routine (56) to calculate the best set of parameters to be used in the ion implantation process to manage the OPD in the wafer being implanted. Such an ion implantation process will involve implanting an ion beam pattern into the substrate rather than a uniform ion beam, wherein the uniform ion beam may impart, for example, uniform ion capacity and uniform ion energy across the substrate.

[0053] For example, the information can be used to calculate the residual capacity pattern of ions of a given energy and species to be injected into the stress compensation layer, where the residual capacity pattern is effective for smoothing the OPD. Thus, the residual capacity pattern can be determined by the application of the ion beam pattern to the resist pattern of the gray-tone photoresist layer receiving the injection.

[0054] While the aforementioned embodiments focus on using patterned resist layers in conjunction with ion implantation to selectively pattern a stress compensation layer in order to reduce substrate OPD, in other embodiments, the patterned resist layer may be used as an etching mask to facilitate the selective etching of the stress compensation layer, as suggested in FIG. 3h. Furthermore, the selective etching may be performed by an inert ion beam, a reactive ion beam, a radical beam, etc. In some embodiments, such selective etching may be performed at the chip level, for example, as illustrated in FIG. 6a through 6g. In some examples, the selective etching may be achieved by using a scanning beam in conjunction with the patterned stress compensation layer, including adjusting the beam scanning according to the location of a given chip area on the substrate.

[0055] FIG. 7 illustrates an exemplary process flow. In block (702), a wafer map is received. The wafer map may correspond to a surface map representing a pattern of OPDs across a substrate. The wafer map may correspond to existing OPDs on a substrate at a specific processing instance.

[0056] In block (704), a stress relief pattern for application to the substrate is calculated based on the wafer map. The stress relief pattern can be determined as an equivalent pattern of OPD modification and, additionally, can be used to determine an ion implantation pattern to perform OPD modification by being implanted into the stress compensation layer. Such an ion implantation pattern may take into account, among other features, ion species, ion energy, ion capacity, and the composition of the stress compensation layer. In particular, the stress relief pattern will generate a map of the ion capacity to be imparted into the stress compensation layer as a function of location across the substrate.

[0057] In block (706), a stress compensation layer is provided on the main surface of the substrate. It should be noted that this operation may be performed following the operation in block (704), before the operation of block (704), or simultaneously.

[0058] In block (708), a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray tone resist layer. In other embodiments, the resist layer may be a binary resist or other known resist.

[0059] In block (710), the resist layer is patterned according to a stress relief pattern to form a patterned resist layer. The patterning may be performed using a gray tone mask to form a pattern of zones or multiple zones of variable resist thickness across the surface of the substrate, designed to selectively transmit more or less ion capacity into the stress compensation layer depending on the location on the main surface of the substrate. In some examples, the patterning may be performed according to a digital pattern in which a series of resist lines are characterized by a line pitch, and a variable line width is used to create zones of different overall opacity of the resist. In other examples, an imprint mask having a desired pattern may be used to pattern the resist layer.

[0060] In block (712), blanket exposure of the main surface of the substrate is performed, wherein the blanket exposure directs implanted species toward the main surface of the substrate while the patterned resist layer is in place. The blanket exposure may be performed by scanning the substrate, for example, with an inert ion beam or a reactive ion beam, such as a ribbon beam. In some embodiments, the blanket exposure may result in the implantation of species, such as energetic ions, which are selectively implanted into the stress compensation layer in regions of the resist layer with a smaller thickness or zero thickness.

[0061] In block (714), the resist layer is removed from the substrate after blanket injection.

[0062] FIG. 8 illustrates another exemplary process flow (800). In block (802), a wafer map is received. The wafer map may correspond to a surface map representing a pattern of OPDs across a substrate. The wafer map may correspond to existing OPDs on a substrate at a specific processing instance.

[0063] In block (804), a stress relief pattern for application to the substrate is calculated based on the wafer map. The stress relief pattern can be determined as an equivalent pattern of OPD modification and, additionally, can be used to determine an ion implantation pattern to perform OPD modification by being implanted into the stress compensation layer. Such an ion implantation pattern may take into account, among other features, ion species, ion energy, ion capacity, and the composition of the stress compensation layer. In particular, the stress relief pattern will generate a map of the ion capacity to be imparted into the stress compensation layer as a function of location across the substrate.

[0064] In block (806), a stress compensation layer is provided on the main surface of the substrate. It should be noted that this operation may be performed following the operation in block (804), before the operation of block (804), or simultaneously.

[0065] In block (808), a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray tone resist layer. In other embodiments, the resist layer may be a binary resist or other known resist.

[0066] In block (810), the resist layer is patterned according to a stress relief pattern to form a patterned resist layer. The patterning may be performed to form a pattern of zones or multiple zones of variable resist thickness across the surface of the substrate, designed to selectively transmit more or less ion capacity into the stress compensation layer depending on the location on the main surface of the substrate. In some examples, the patterning may be performed according to a digital pattern in which a series of resist lines are characterized by a line pitch, and a variable line width is used to create zones of different overall opacity of the resist.

[0067] In block (812), exposure to etch species is performed, wherein the etch species are directed toward the main surface of the substrate while the patterned gray tone resist layer is in place. The etch species may be performed by scanning the substrate against, for example, an ion beam or a radical beam, such as a ribbon beam. In other embodiments, the etch species may be provided by exposure to ions and / or radicals in a plasma, including a plasma immersion chamber. In some embodiments, blanket exposure may result in the selective etching of regions of the stress compensation layer where a resist layer of smaller thickness or zero thickness is present.

[0068] In block (814), the resist layer is removed from the substrate after blanket injection.

[0069] FIG. 9 illustrates another exemplary process flow (900). In block (902), a wafer map is received. The wafer map may correspond to a surface map representing a pattern of OPDs across a substrate. The wafer map may correspond to existing OPDs on a substrate at a specific processing instance.

[0070] In block (904), a stress relief pattern for application to the substrate is calculated based on the wafer map. The stress relief pattern can be determined as an equivalent pattern of OPD modification and, additionally, can be used to determine an ion implantation pattern to perform OPD modification by being implanted into the stress compensation layer. Such an ion implantation pattern may take into account, among other features, ion species, ion energy, ion capacity, and the composition of the stress compensation layer. In particular, the stress relief pattern will generate a map of the ion capacity to be imparted into the stress compensation layer as a function of location across the substrate.

[0071] In block (906), a stress compensation layer is provided on the main surface of the substrate. It should be noted that this operation may be performed following the operation in block (804), before the operation of block (804), or simultaneously.

[0072] In block (908), a resist layer is provided on the stress compensation layer. In some embodiments, the resist layer may be a gray tone resist layer. In other embodiments, the resist layer may be a binary resist or other known resist.

[0073] In block (910), the resist layer is patterned according to a stress relief pattern to form a patterned resist layer. The patterning may be performed to form a pattern of zones or multiple zones of variable resist thickness across the surface of the substrate, designed to selectively transmit more or less ion capacity into the stress compensation layer depending on the location on the main surface of the substrate. In some examples, the patterning may be performed according to a digital pattern in which a series of resist lines are characterized by a line pitch, and a variable line width is used to create zones of different overall opacity of the resist.

[0074] In block (912), patterning exposure of the main surface to the treatment species occurs by scanning the treatment beam in a non-uniform manner with respect to the substrate. In one embodiment, the treatment beam may be scanned against a stationary substrate, while in another embodiment, the substrate may be scanned against the stationary treatment beam. In additional embodiments, scanning of both the treatment beam and the substrate may occur. The treatment species may be an inert ion beam or a reactive ion beam used to selectively vary the ion capacity of the implantation species as a function of position across the main surface. Alternatively, the treatment species may be a reactive ion beam or a radical beam used to selectively vary the flux of the ion or radical etching species as a function of position across the main surface of the substrate. Patterning exposure occurs while the patterned resist is in place. Therefore, the combination of the patterning exposure and the patterned resist layer can create an implantation pattern or an etching pattern targeted to the stress compensation layer beneath the patterned resist layer.

[0075] In block (914), the resist layer is removed from the substrate after the patterning exposure.

[0076] The advantages provided by the embodiments are numerous. As a first advantage, with the help of a patterned gray-tone resist layer or a digitally patterned resist layer, a relatively simple ion implantation procedure can reduce the two-dimensional OPD pattern across the substrate. As another advantage, since the fine-scale ion implantation pattern into the substrate can be defined by a pattern formed on the gray-tone resist layer or the digitally patterned resist layer, relatively more precise control of local OPD fluctuations is possible, in contrast to controlling the ion beam to write the implantation pattern within the wafer. In other words, the resist layer can be patterned to generate variable ion capacities into the stress compensation layer extending to at least a micrometer length scale across the substrate surface. Control of this type of capacity fluctuation across the substrate surface may not be achieved by scanning ion beams with a size of approximately centimeters. As an additional advantage, the management of complex patterns of OPD, such as chip-level OPD patterns, can be achieved by creating a pattern on the resist layer to match the OPD patterns using blanket exposure to processing species, or pattern exposure to, for example, a scanning ion beam or a scanning radical beam.

[0077] The scope of this disclosure should not be limited by the specific embodiments described herein. In fact, in addition to those described herein, various other embodiments and modifications to this disclosure will be apparent to those skilled in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, although this disclosure has been described herein in the context of a specific implementation in a specific environment for a specific purpose, those skilled in the art will recognize that its usefulness is not limited thereto and that this disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be interpreted in the full scope and spirit of this disclosure as described herein.

Claims

Claim 1 A method for managing stress in a substrate, comprising the steps of: providing a stress-compensating laminate on a main surface of a substrate — said stress-compensating laminate comprises a patterned resist layer and a stress-compensating layer disposed below said patterned resist layer, wherein said patterned resist layer is determined according to a surface map of the main surface of the substrate —; and orienting treatment species toward said stress-compensating laminate — said stress-compensating layer is optionally changed as a function of a position across the substrate —. Claim 2 A method according to claim 1, wherein the patterned resist layer comprises a gray tone photoresist layer having a resist pattern characterized by a variable resist layer thickness as a function of position across the main surface of the substrate. Claim 3 In paragraph 2, the treatment species are provided in an ion implantation procedure comprising exposing the substrate to an ion beam that provides a uniform ion dose and uniform ion energy across the substrate, wherein at least a portion of the uniform ion dose is selectively blocked by the resist pattern. Claim 4 In paragraph 3, the ion implantation procedure comprises scanning the ion beam with respect to the substrate, wherein an ion beam pattern is implanted into the substrate, and the ion beam pattern comprises a variable ion capacity as a function of position across the substrate. Claim 5 A method according to claim 4, wherein a residual capacity pattern is injected into the stress compensation layer, and the residual capacity pattern is determined by applying the ion beam pattern to the resist pattern of the gray tone photoresist layer. Claim 6 A method according to claim 1, wherein the patterned resist layer has a variable thickness determined according to a three-dimensional surface map of the main surface of the substrate. Claim 7 In paragraph 2, the gray tone photoresist layer is, Depositing a blanket photoresist layer on the stress compensation layer; Performing exposure of the blanket photoresist layer to illumination directed through a gray tone mask configured according to the above resist pattern; and A method formed by developing the blanket photoresist layer after the above exposure. Claim 8 In paragraph 2, the gray tone photoresist layer is, Depositing a blanket photoresist layer on the stress compensation layer; and A method formed by imprinting the blanket photoresist layer according to an imprint mask configured according to the resist pattern. Claim 9 A method according to claim 1, wherein the processing species are provided by exposing the substrate to etching species of a uniform capacity across the substrate, and at least a portion of the etching species of a uniform capacity is selectively blocked from etching the stress compensation layer by the patterned resist layer. Claim 10 A method according to claim 1, wherein the patterned resist layer is a digitally patterned resist layer. Claim 11 An ion implanter comprises: an ion source for generating an ion beam; a beamline component for changing the scanning of the ion beam; and a controller, wherein the controller, processor, and It includes a memory unit coupled to the above processor and comprising a scan injection routine, wherein the scan injection routine is Receive the surface map of the substrate, An ion implanter operable on the processor to control the ion implanter to impart an injection pattern within a stress compensation layer on the substrate by performing scan-type injection based on the surface map. Claim 12 In claim 11, the substrate further comprises a gray tone resist disposed on the stress compensation layer, and the scan-type injection routine is further operable to calculate the injection pattern based on a resist pattern in the gray tone resist, an ion implanter. Claim 13 In claim 12, the resist pattern in the gray tone resist is determined by the surface map of the substrate, an ion implanter. Claim 14 In paragraph 11, the above resist pattern is a digital resist pattern, an ion implanter. Claim 15 In claim 11, the surface map comprises a pattern of chip-level variation in out-of-plane distortion and wafer-level variation in out-of-plane distortion, an ion implanter. Claim 16 A controller for an ion implanter comprises: a processor; and a memory unit coupled to the processor and including a scan-type implantation routine, wherein the scan-type implantation routine is Receive the surface map of the substrate, A controller operable on the processor to control an ion implanter to impart an injection pattern within a stress compensation layer on the substrate by performing scan-type injection based on the surface map. Claim 17 In claim 16, the substrate further comprises a gray tone resist disposed on the stress compensation layer, and the scan-type injection routine is further operable to calculate the injection pattern based on a resist pattern in the gray tone resist, a controller. Claim 18 In paragraph 16, the controller, wherein the resist pattern in the gray tone resist is determined by the surface map of the substrate. Claim 19 In paragraph 17, the above-mentioned register pattern is a digital register pattern, a controller. Claim 20 In claim 16, the surface map comprises a pattern of chip-level variation in out-of-plane distortion and wafer-level variation in out-of-plane distortion, an ion implanter.

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