Memory device with enhanced thermal conductivity

Abstract

Systems, devices, and methods related to memory devices having enhanced thermal conductivity are described. Embodiments of the present technology may include thermal paths, such as a material having a thermal conductivity value below a threshold value, which are added into one or more layers within a memory device structure. The added material may provide a path for dissipating thermal energy from the memory device.

Description

Technology Field

[0001] The present disclosure generally relates to electronic devices, and more specifically, to a memory device having a structure having enhanced thermal conductivity. Background Technology

[0002] A device (e.g., a processor, a memory device, a memory system, or a combination thereof) may include one or more semiconductor circuits configured to store and / or process information. For example, the device may include memory devices such as volatile memory devices, non-volatile memory devices, or combination devices. Memory devices such as dynamic random access memory (DRAM) may utilize electrical energy to store and access data.

[0003] As embedded system technology advances and applications expand, the market is continuously seeking faster, more efficient, and smaller devices. To meet market demand, semiconductor devices are being pushed to their limits through various improvements. Improving devices generally involves increasing circuit density, circuit capacity, operating speed, reliability, and data retention, among other metrics. However, attempts to meet market demand, for instance, by increasing bandwidth capabilities, can often be limited by the thermal conductivity of the device materials. Brief explanation of the drawing

[0004] FIG. 1 is a block diagram of a device according to an embodiment of the present technology. FIG. 2 illustrates a cross-sectional view of a device having a thermal path according to one or more embodiments of the present technology. FIG. 3a illustrates a cross-sectional view of the formation of an isolation layer in a memory device structure according to one or more embodiments of the present technology. FIG. 3b illustrates a cross-sectional view of the formation of local interconnects and wiring in a memory device structure according to one or more embodiments of the present technology. FIG. 3c illustrates a cross-sectional view of the formation of a base dielectric layer of a memory device structure according to one or more embodiments of the present technology. FIG. 4a illustrates a cross-sectional view of the formation of a cell structure in a base dielectric layer within a memory device structure according to one or more embodiments of the present technology. FIG. 4b illustrates a cross-sectional view of the formation of an isolated region for a thermal path in a memory device structure according to one or more embodiments of the present technology. FIG. 4c illustrates a cross-sectional view of the formation of a thermal path in a memory device structure according to one or more embodiments of the present technology. FIG. 5a illustrates a cross-sectional view of a thermal path formed from a base dielectric layer connected to an isolation layer within a memory device structure according to one or more embodiments of the present technology. FIG. 5b illustrates a cross-sectional view of the formation of a thermal path through a base dielectric layer connected to an isolation layer within a memory device structure according to one or more embodiments of the present technology. FIG. 5c illustrates a cross-sectional view of a thermal path in a memory device according to one or more embodiments of the present technology. FIG. 6a illustrates a cross-sectional view of the formation of vias in a memory device structure according to one or more embodiments of the present technology. FIG. 6b illustrates a cross-sectional view of the formation of vias in the end-of-line layer of a memory device structure according to one or more embodiments of the present technology. FIG. 7 illustrates a cross-sectional view of a thermal path on a memory device connected to a logic circuit of a device according to one or more embodiments of the present technology. FIG. 8a is a flowchart illustrating an exemplary method for designing a thermal path for a memory device structure according to one or more embodiments of the present technology. FIG. 8b is a flowchart illustrating an exemplary method for manufacturing a thermal path in one or more layers of a memory device structure according to one or more embodiments of the present technology. FIG. 9 is a schematic diagram of a system including a device according to an embodiment of the present technology. Specific details for implementing the invention

[0005] As described in more detail below, the technology disclosed herein relates, for example, to memory devices having enhanced thermal conductivity, memory systems, devices for systems having memory devices, related methods, etc. Memory devices, such as dynamic random access memory (DRAM), include materials and structures configured to utilize electrical energy to store and access data. With the growth of high-power computing, such as artificial intelligence, virtual reality, and machine learning, bandwidth requirements for memory devices have increased. However, the performance of conventional memory systems has been limited due to the thermal conductivity of materials within the memory devices.

[0006] Embodiments of the present technology may provide an improvement in the thermal conductivity of a memory device by adding a material (e.g., aluminum oxide, aluminum nitride, etc.) to the memory device structure. The added material may have higher thermal conductivity than the dielectric material used within the memory device structure. Additionally, the thermally conductive material may be added at a targeted location to provide a thermal path configured to transfer thermal energy out of the memory device. For example, the thermally conductive material may be located on the same layer as the memory cell and adjacent to the memory cell. Furthermore, the thermally conductive material may overlap each other across layers (e.g., aligned along a vertical line / direction), thereby providing a vertically coupled thermal or thermal dissipation path. The resulting vertical thermal dissipation path may utilize the uplift characteristics of thermal energy to increase dissipation efficiency and, when implemented in a stacked assembly, may provide a new dissipation path for the device located on the lower part of the stack. Additionally, when implemented in circuits with repetitive patterns, such as in memory arrays, the placement of thermally conductive materials can also follow the repetitive pattern and increase heat dissipation for the entire device / assembly.

[0007] In addition, compared to conventional devices, a thermally conductive material can be added to the area occupied by the dielectric material in the conventional device. Accordingly, the embodiments described herein can replace the previous dielectric material to provide a heat dissipation path within the conventional insulating structure (e.g., by using a thermally conductive electrical insulator such as aluminum nitride).

[0008] In some embodiments, a thermally conductive material may be added during the front-end-of-line (FEOL) layer fabrication step. The FEOL layer may include an isolation layer interconnected with a complementary metal-oxide semiconductor (CMOS) formation and local wiring. To form or add the thermally conductive material during the FEOL fabrication step, a base dielectric layer may be formed on the isolation layer. Next, a cell structure (e.g., an individual memory cell) may be formed within the base dielectric layer. Adjacent to the cell structure, an isolated region for a thermal path may be formed within the base dielectric layer. The region of the thermal path may be electrically isolated from regions of the surrounding circuit and regions of contacts, vias, and / or TSVs using the base dielectric layer, for example, by preserving or forming vertical sections or walls surrounding the thermal path sections.

[0009] Thermal paths can be formed within the dielectric layer in the region of the thermal path by adding thermally conductive, electrically non-conductive materials such as aluminum oxide, aluminum nitride, etc. Thermal paths can be formed by a spin coating process, which contains a thermally conductive material as a filler within the base dielectric layer. In some embodiments, thermal paths are formed by a combination of processes such as physical vapor deposition (PVD), molybdenum (MO), or cut metal dielectric (CMD) to form a thermally conductive layer as a functional film, and are removed by a polishing process. The manufacturing process can be completed by implementing a back end-of-line (BEOL) process to form the wiring of the memory device.

[0010] As described in detail below, embodiments of the present technology can provide technical advantages over conventional technologies by providing extensive thermal paths to improve device performance. For example, the cell area of ​​a nominal memory device is approximately 50% of the total device area. The cell material has a relatively higher thermal conductivity than the dielectric film used in the semiconductor manufacturing process. Thermal paths made of a material having higher thermal conductivity than the cell material create a path for thermal energy to escape from the device. Additionally, the size, shape, and content of the thermally conductive material can be used to reduce the mismatch in thermal conductivity across the lateral and planar directions, thereby reducing potential warping issues.

[0011] Embodiments of the present technology introduce a thermal path within a dielectric region to provide higher thermal conductivity while preserving electrical integrity by: 1) using materials such as aluminum oxide, aluminum nitride, etc. to minimize electrical interaction with the circuit; 2) isolating the region of vias / contacts / TSVs to eliminate technical difficulties in forming vias / contacts / TSV structures in the material for the thermal path; and 3) using materials such as aluminum oxide, aluminum nitride, etc., the thermal conductivity of the equivalent layer of the thermal path can be improved (e.g., by a value of 6.7 W / m·K, which is an improvement of 22%, and the temperature is reduced by 7.8% for a single DRAM, 9% for a dual DRAM, and 9.9% for a triple DRAM). Embodiments of the present technology may be applied to semiconductor or other electrical devices, such as NAND flash memory, NOR flash memory, CPU (central processing unit), GPU (graphics processing unit), having one or more dielectrics disposed between circuit layers (e.g., CMOS layers). Various features described below may be combined to increase heat dissipation from the circuit layers and across one or more dielectrics. Additionally, or alternatively, embodiments of the present technology may be applied to various device applications, such as 3D DRAM, WoW (wafer-on-wafer) 3D NAND memory, heterogeneous devices, etc.

[0012] FIG. 1 is a block diagram of a device (100) according to an embodiment of the present technology. For example, the device (100) may be a DRAM (e.g., DDR4 DRAM, DDR5 DRAM, LP DRAM, HBM DRAM, etc.) or a part thereof comprising one or more dies / chips. In some embodiments, the device (100) may include a DDR type SDRAM (synchronous DRAM) integrated on a single semiconductor chip or on a plurality of semiconductor chips.

[0013] The device (100) may include an array of memory cells, such as a memory array (150). The memory array (150) may include a plurality of banks (e.g., banks 0 to 15), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and bit lines. The memory cells may include any of a plurality of different memory cell media types, such as capacitive, magnetoresistive, ferroelectric, phase change, etc. The selection of the word lines (WL) may be performed by a row decoder (140), and the selection of the bit lines (BL) may be performed by a column decoder (145). Sense amplifiers (SAMPs) may be provided to a corresponding bit line (BL) and connected to at least one individual local I / O line pair (LIOT / B), which in turn may be coupled to at least one main I / O line pair (MIOT / B) through a transfer gate (TG) (which may function as a switch). The memory array (150) may also include plate lines and corresponding circuitry for managing their operation.

[0014] The device (100) may employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus, respectively, to receive command signals (CMD) and address signals (ADDR). The device (100) may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals (CK and CKF), data terminals (DQ, RDQS, DBI, and DMI), and power supply terminals (VDD, VSS, and VDDQ).

[0015] The command terminal and the address terminal may be supplied with an address signal and a bank address signal (not shown in FIG. 1) from the outside. The address signal and bank address signal supplied to the address terminals may be transmitted to the address decoder (110) through a command / address input circuit (105) (e.g., a command circuit). The address decoder (110) may receive the address signal and supply the decoded row address signal (XADD) to the row decoder (140) and the decoded column address signal (YADD) to the column decoder (145). The address decoder (110) may also receive the bank address signal and supply the bank address signal to both the row decoder (140) and the column decoder (145).

[0016] Command signals (CMD), address signals (ADDR), and chip select signals (CS) from a memory controller may be supplied to the command and address terminals. The command signals may represent various memory commands from the memory controller (e.g., access commands, which may include read commands and write commands). The chip select signal may be used to select a device (100) to respond to the commands and addresses provided to the command and address terminals. When an active chip select signal is provided to the device (100), the command and address may be decoded and a memory operation may be performed. The command signals may be provided to the command decoder (115) as internal command signals (ICMD) through the command / address input circuit (105). The command decoder (115) may include circuits for decoding internal command signals (ICMD) to generate various internal signals and commands for performing memory operations, e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line. The command decoder (115) may further include one or more registers for tracking various counts or values ​​(e.g., a count of refresh commands received by the device (100) or a count of a self-refresh operation performed by the device (100) (e.g., a self-refresh entry / exit sequence).

[0017] Read data can be read from memory cells in a memory array (150) specified by row addresses (e.g., active command and provided address) and column addresses (e.g., read and provided address). A read command can be received by a command decoder (115), which can provide internal commands to an input / output circuit (160) so that read data can be output from data terminals (DQ, RDQS, DBI, and DMI) through read / write amplifiers (155) and an input / output circuit (160) according to RDQS clock signals. Read data can be provided at a time limited by read latency information (RL), which can be programmed in the device (100), for example, in a mode register (not shown in FIG. 1). Read latency information (RL) can be defined with respect to the clock pulse of a CK clock signal. For example, the read latency information (RL) may be the number of clock pulses of the CK signal after the read command is received by the device (100) when the associated read data is provided.

[0018] The write data may be supplied to the data terminals (DQ, DBI, and DMI). The write command may be received by the command decoder (115), which may provide internal commands to the input / output circuit (160) so that the write data may be received by data receivers in the input / output circuit (160) and supplied to the memory array (150) through the input / output circuit (160) and read / write amplifiers (155). The write data may be written to memory cells designated by row addresses and column addresses. The write data may be supplied to the data terminals at a time defined by the write latency (WL) information. The write latency (WL) information may be programmed into the device (100), for example, a mode register (not shown in FIG. 1). The write latency (WL) information may be defined with respect to the clock pulse of the CK clock signal. For example, the recording latency information (WL) may be the number of clock pulses of the CK signal after the recording command is received by the device (100) when the associated recording data is received.

[0019] Power supply potentials (VDD and VSS) can be supplied to the power supply terminals. These power supply potentials (VDD and VSS) can be supplied to an internal voltage generator circuit (170). The internal voltage generator circuit (170) can generate various internal potentials (VPP, VOD, VARY, VPERI, etc.) based on the power supply potentials (VDD and VSS). The internal potential VPP can be used in the row decoder (140), the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array (150), and the internal potential VPERI can be used in many other circuit blocks.

[0020] The power supply terminal may also receive a power supply potential (VDDQ). The power supply potential (VDDQ) may be supplied to the input / output circuit (160) together with the power supply potential (VSS). In one embodiment of the present invention, the power supply potential (VDDQ) may be the same potential as the power supply potential (VDD). In another embodiment of the present invention, the power supply potential (VDDQ) may be a different potential from the power supply potential (VDD). However, a dedicated power supply potential (VDDQ) may be used for the input / output circuit (160) to prevent power supply noise generated in the input / output circuit (160) from propagating to other circuit blocks.

[0021] An external clock signal and a complementary external clock signal may be supplied to the clock terminal and the data clock terminal. The external clock signals (CK and CKF) may be supplied to the clock input circuit (120) (e.g., an external clock circuit). The CK and CKF signals may be complementary. The complementary clock signals may have opposite clock levels and may simultaneously have transitions between opposite clock levels. For example, when the clock level of the clock signal is low, the level of the complementary clock signal is high, and when the clock level of the clock signal is high, the clock level of the complementary clock signal is low. Also, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0022] Input buffers included in the clock input circuit (120) can receive external clock signals. For example, when enabled by a clock / enable signal from the command decoder (115), the input buffers can receive clock / enable signals. The clock input circuit (120) can receive external clock signals to generate internal clock signals (ICK). The internal clock signals (ICK) can be supplied to the internal clock circuit (130). The internal clock circuit (130) can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal (ICK) and the clock enable (not shown in FIG. 1) from the command / address input circuit (105). For example, the internal clock circuit (130) may include a clock path (not shown in FIG. 1) that receives an internal clock signal (ICK) and provides various clock signals to the command decoder (115). The internal clock circuit (130) may further provide input / output (IO) clock signals. The IO clock signals may be supplied to the input / output circuit (160) and may be used as timing signals to determine the output timing of read data and the input timing of write data.

[0023] The device (100) may be connected to any of a plurality of electronic devices capable of using memory for temporary or permanent storage of information, or to a component thereof. For example, the host device of the device (100) may be a computing device such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device may be any of a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio and / or video, a vehicle, a home appliance, a toy, or a number of other products. In one embodiment, the host device may be connected directly to the device (100), whereas in another embodiment, the host device may be connected indirectly to the memory device (e.g., via a network connection or through an intermediate device).

[0024] A thermally conductive material may be added at one or more locations within the structure of the device (100). The thermally conductive material may provide a thermal path configured to transfer thermal energy out of the device (100). For example, the thermally conductive material may be located on the same layer as the memory array (150) and adjacent to the memory array (150).

[0025] FIG. 2 illustrates a cross-sectional view of a device (e.g., the device (100) of FIG. 1 or a part thereof) having a thermal path (206) according to one or more embodiments of the present technology. The thermal path (206) may be formed adjacent to a cell structure (202) and may be embedded within a base dielectric layer (204). In some embodiments, the thermal path (206) is located within a non-cell portion of a memory array (e.g., the memory array (150) of FIG. 1). In some embodiments, the thermal path (206) may be placed between a metal layer and a circuit / CMOS layer. For example, the thermal path may be placed within a FEOL (frontend of line) layer. The thermal path (206) may comprise a thermally conductive electrically non-conductive material, such as aluminum oxide or aluminum nitride, which does not interfere with other circuit parts. The thermal path (206) may provide a path for transferring thermal energy out of the base dielectric layer (204) and the memory device structure (200). For example, the thermal path (206) may be located on the CMOS circuit and may provide a path for thermal energy upward from the CMOS circuit. Additionally, the thermal path (206) may provide a path for removing thermal energy from the cell structure (202). In some embodiments, the thermal path may be a connecting material (206). In some other embodiments, the thermal path may be formed to provide maximum heat transfer in the intended direction.

[0026] FIGS. 3a through 6b may illustrate various stages or structures formed during a manufacturing process for the device (100) of FIG. 1. FIG. 3a illustrates a cross-sectional view of the formation of an isolation layer in a memory device structure (300) according to one or more embodiments of the present technology. The isolation layer may include one or more trenches (304) formed on a substrate (302) (e.g., a silicon wafer).

[0027] FIG. 3b illustrates a cross-sectional view of the formation of a CMOS (308), local interconnects (306), and wiring (not shown) in a memory device structure (330) according to one or more embodiments of the present technology. The CMOS (308), local interconnects (306), and wiring may be formed around or across one or more trenches (304). Various circuit components may be formed by depositing or forming components on an isolation layer.

[0028] FIG. 3c illustrates a cross-sectional view of the formation of a base dielectric layer (e.g., base dielectric layer (204)) of a memory device structure (360) according to one or more embodiments of the present technology. The base dielectric layer (204) is formed on a substrate (302) (e.g., on an isolation layer). The base dielectric layer (204) may be formed on and / or surrounding a CMOS (308), a local interconnect (306), and wiring (not shown). The base dielectric layer (204) may comprise an electrically insulating material, such as a silicon oxide material.

[0029] FIG. 4a illustrates a cross-sectional view of the formation of a cell structure (e.g., cell structure (202)) within a base dielectric layer (204) in a memory device structure (400) according to one or more embodiments of the present technology. The cell structure (202) may be formed within the base dielectric layer (204). For example, the cell structure (202) may be formed by removing a portion of the base dielectric layer (204) to form a cavity or base shape, depositing a metallic material, a dopant, and / or circuit component within the cavity, masking, patterning, or a combination thereof. In some embodiments, such as a DRAM, the cell structure (202) may include a capacitor-based circuit portion.

[0030] FIG. 4b illustrates a cross-sectional view of the formation of an isolated region (432) for a thermal path in a memory device structure (430) according to one or more embodiments of the present technology. The isolated region (432) may be formed within the base dielectric layer (204), for example, by removing or etching a target portion of the base dielectric layer (204). Substantially, the isolated region (432) may correspond to a cavity or recess that will subsequently be occupied by the thermal path (206) of FIG. 2. The isolated region (432) may be separated laterally from the cell structure (202) of FIG. 4a. In some embodiments (not shown), the isolated region (432) may be formed over a silicon through-via (TSV) or a thermal via. The isolated region (432) of the thermal path may be isolated within the base dielectric layer (204) from a region designated for other circuit components, such as a contact, via, and / or TSV.

[0031] FIG. 4c illustrates a cross-sectional view of the formation of a thermal path (e.g., a thermal path (206)) within a memory device structure (460) according to one or more embodiments of the present technology. The thermal path (206) may be formed by filling or depositing a thermally conductive material within a base dielectric layer (204) within an isolation region (432) of FIG. 4b. The thermal path (206) may be formed within the base dielectric layer (204) using a highly thermally conductive and / or electrically non-conductive material, such as aluminum oxide, aluminum nitride, etc. In some embodiments, the thermal path (206) may be formed by spin coating, a deposition process, a polishing process, or a combination thereof.

[0032] FIGS. 5A and FIGS. 5B illustrate different embodiments for a thermal path (206). FIGS. 5A illustrates a cross-sectional view of the formation of a thermal path (206a) from a base dielectric layer (204) connected to a substrate (302) within a memory device structure (500) according to one or more embodiments of the present technology. The thermal path (206) may extend from the base dielectric layer (204) to an isolation layer and / or into the isolation layer. For example, the isolation region (432) of FIG. 4B may have an additional extension that exposes a portion of the substrate (302). The additional extension within the cavity may be occupied by a thermally conductive and / or electrically non-conductive material, thereby forming a thermal path (206a) having an extension that extends toward and / or contacts the substrate (302). In some embodiments, the base dielectric layer (204) may be formed or redeposited over the thermal path (206) and thus may surround the top of the thermal path (206a).

[0033] FIG. 5b illustrates a cross-sectional view of the formation of a thermal path (206b) through a base dielectric layer (204) connected to a substrate (302) within a memory device structure (530) according to one or more embodiments of the present technology. The thermal path (206) may extend through part or all of the base dielectric layer (204). For example, the isolation region (432) of FIG. 4b may have an additional extension that exposes part of the substrate (302). The additional extension within the cavity may be occupied by a thermally conductive and / or electrically non-conductive material, thereby forming a thermal path (206b) having an extension that extends toward and / or contacts the substrate (302). In some embodiments, the base dielectric layer (204) may be formed or redeposited over the thermal path (206b) using a cavity that is additionally filled by a thermally conductive and / or electrically non-conductive material. As a result, the thermal path (206b) may have a second extension extending above the base dielectric layer (204) and through it.

[0034] FIG. 5c illustrates a cross-sectional view of a stacked thermal path (206c) in a memory device (560) according to one or more embodiments of the present technology. As an exemplary example, the thermal path (206c) may be connected continuously through memory device structures (562, 564, and 566). For example, the memory device (560) may be formed by a wafer or die (e.g., wafer bonding or a stacked die) having thermal paths (206a and / or 206b) stacked vertically above and below each other. The stacked wafer or stacked die may further include silicon through-vias or corresponding thermal extensions in direct contact with the vertical extension portions of the thermal paths (206a and / or 206b). Thus, the resulting thermal path (206c) may have thermal paths (206a and / or 206b) aligned with each other and directly connected across a plurality of layers. During operation, the thermal path (206) can provide a path for thermal energy to flow between the memory device structures (566, 564, and 562).

[0035] FIG. 6a illustrates a cross-sectional view of the formation of a via (602) of a memory device structure (600) according to one or more embodiments of the present technology. The via (602) may be formed on or thereafter on the memory device structure (460) of FIG. 4c, the memory device structure (500) of FIG. 5a, or the memory device structure (530) of FIG. 5b. The via (602), such as a TSV or a contact, may extend through the substrate (302) and the base dielectric layer (204). As an exemplary example, the via (602) may separate a thermal path (206) from the cell structure (202) within the base dielectric layer (204). The via (602) may be formed by removing or etching to form a cavity extending through the base dielectric layer (204) and / or the substrate (302). The via cavity can be filled using a barrier material, a seed metallic material, a main metallic material (e.g., copper), or a combination thereof.

[0036] FIG. 6b illustrates a cross-sectional view of the formation of a redistribution layer (604) within an EOL layer (606) of a memory device structure (650) according to one or more embodiments of the present technology. The redistribution layer (604) may include lateral electrical connections such as traces, local vias, or a combination thereof. The redistribution layer (604) may be connected to a via (602), a cell structure (202), a CMOS (308), a local interconnect (306), or a combination thereof. Accordingly, the redistribution layer (604)

[0037] FIG. 7 illustrates a cross-sectional view of a thermal path (206c and 206d) on a memory device (704 and 706) connected to a logic circuit (702) of a device (700) (e.g., device (100) of FIG. 1) according to one or more embodiments of the present technology. For example, FIG. 7 may illustrate a portion of a corresponding stacked device having a directly bonded semiconductor wafer or a portion of a memory or data storage circuit (e.g., a memory cell such as a DRAM). For example, the illustrated portion of the memory device (704 and 706) may correspond to the memory array (150) of FIG. 1. The logic circuit (702) may correspond to other circuit portions illustrated in FIG. 1, such as the address command input circuit (105) of FIG. 1, the I / O circuit (160) of FIG. 1, and / or others.

[0038] The memory devices (704 and 706) may include thermal paths, such as thermal paths (206 in FIG. 2, 206a in FIG. 5a, and / or 206B in FIG. 5b), for managing the thermal energy of the device (700). Thermal paths (206c and 206d) provide a thermally conductive route for the flow of thermal energy from the logic circuit (702) to the memory device (704) and may exit the memory device (706). When the manufacturing process for the memory devices (704 and 706) (exemplified in FIG. 3a through 6b) is completed, the memory devices (704 and 706) may be flipped over (e.g. via a carrier wafer) and mounted on the logic circuit (702) to become the device (700). In this way, the active side of the memory device (704 and 706) can be closer to and facing downward from the logic circuit (702) at the bottom of the device (700).

[0039] In some embodiments, the thermal paths (206a and 206b) are connected (as illustrated in FIG. 5c) to provide a directly linked path (e.g., a path to a thermal pillar or a thermal pillar comprising the thermally conductive and / or electrically insulating material described above) so that heat is dissipated out of the device (700). For example, the thermal paths have a quadrilateral cross-sectional shape. However, it is understood that the various embodiments described herein may be implemented in other configurations, such as any dimensions and shapes of the thermal paths within the memory device structure.

[0040] FIG. 8a is a flowchart illustrating an exemplary method (800) for designing a thermal path for a memory device structure according to one or more embodiments of the present technology. The method (800) can determine the arrangement (e.g., size, shape, location, or other) of a thermal path (e.g., the thermal path (206) of FIG. 2 to 7) in a memory device structure as described above.

[0041] In block (802), the method (800) may include the step of determining an operation metric of a device (e.g., device (100) of FIG. 1 and / or device (700) of FIG. 7). The operation metric may include bandwidth requirements, circuit capacity, operating speed, thermal displacement, footprint, or any device design preference or standard. In some embodiments, the operation metric may be determined based on a circuit diagram or requirement related to one provided by another party or entity, such as a circuit designer or a customer.

[0042] In block (804), the method (800) may include the step of computing parameters of a thermal path (e.g., location, size, shape, length, width, depth, and / or number) based on the operation metric of the device. The thermal path may be placed within a memory device structure to provide a path for thermal energy to dissipate out of the memory structure. The method may include the step of determining a location to place the thermal path within the memory device structure. For example, the thermal path may be placed within a base dielectric layer, an isolation layer, or across multiple layers within the memory device structure.

[0043] The method (800) may include the step of computing parameters of a thermal path (e.g., location and / or shape) based on any feature within a cell structure, via, socket, receptacle, solder location, hole, connector, or memory device structure. For example, a manufacturing system may generate a layout for a thermal path that avoids placing the thermal path in a via or cell structure within the memory device structure, underneath, overlapping with, and / or within a critical distance from therefrom.

[0044] A machine learning or artificial intelligence (ML / AI) module may be configured to analyze behavioral metrics of a memory device and compute parameters of thermal path(s) to be added to a memory device structure to remove thermal energy. An ML / AI learning module may be configured to analyze behavioral metrics and compute parameters of thermal paths based on at least one ML / AI model trained on at least one dataset reflecting previous user-determined parameters of thermal paths based on behavioral metrics. The ML / AI algorithms (and models) may be stored locally in a database and / or externally in a database (e.g., a cloud database and / or a cloud server). A client device (e.g., a personal computer, smartphone, tablet, etc.) may be equipped to access these ML / AI algorithms and intelligently compute parameters of thermal paths within a memory device structure based on at least one ML / AI model trained on historical thermal path parameters. For example, the history of column path parameters can be collected to train an ML / AI model to automatically determine the location, size, shape, length, width, depth, and / or number of column paths based on the operation parameters of the memory device.

[0045] As described herein, an ML / AI model may refer to a predictive or statistical utility or program that can be used to determine a probability distribution for one or more character sequences, classes, objects, result sets, or events, and / or to predict response values ​​from one or more predictors. The model may be based on or integrate one or more rule sets, machine learning, neural networks, or others. The ML / AI model may process historical parameters of column paths in memory devices and other data stores (e.g., semiconductor standards, etc.) to analyze memory device structures and design column path locations and sizes in memory device structures. Based on the aggregation of data from memory device design databases, external / internal portals, and other user data stores, at least one ML / AI model may be trained and subsequently deployed to automatically design memory devices with column path(s) inserted within one or more layers of memory device structures.

[0046] In block (806), the method (800) may include the step of calculating the thermal conductivity of the layer(s) within the memory device structure (e.g., using a computing system). The calculation may be based on a simulation test for the layer(s) having added thermal paths to calculate the thermal conductivity for the memory device. For example, by adding thermal paths to the layer(s) of the memory device structure, the thermal conductivity may be improved and the operating temperature may be reduced. The simulation results may show the predicted improvement in thermal conductivity or change in device temperature by adding thermal paths to the layer(s) of the memory device structure.

[0047] In the determination block (808), the method (800) may include the step of determining whether the thermal conductivity for the layer(s) is below a threshold (e.g., 200 W / m K). If the estimated thermal conductivity for the layer(s) is below a predetermined acceptance threshold, the method (800) may include the step of adjusting the parameters of the thermal path inserted within the layer(s) of the memory device structure, as exemplified by the feedback loop to block (804). If the thermal conductivity value for the layer(s) is below the threshold, in block (810), the method (800) enables the design for manufacturing.

[0048] Based on the approval, the device design may be utilized to manufacture a memory device having thermal paths within one or more layers of a memory device structure. For example, the device design may be provided to a memory device manufacturer. When manufacturing a memory device according to the approved design, the thermal paths or materials may be arranged within one or more layers of the memory device structure according to the design.

[0049] FIG. 8b is a flowchart illustrating an exemplary method (850) for manufacturing a thermal path in one or more layers of a memory device structure according to one or more embodiments of the present technology. The method (850) may include the step of adding a thermally conductive material during the FEOL layer manufacturing step. The FEOL layer may include an isolation layer interconnected with a CMOS formation (e.g., the CMOS (308) of FIG. 3 through 7) and local wiring.

[0050] In block (852), the method (850) may include the step of forming a base dielectric layer (e.g., the base dielectric layer (204) of FIGS. 2 to 7) on an isolation layer. The base dielectric layer may be formed to add a thermally conductive material during the FEOL manufacturing step. In block (854), the method (850) may include the step of forming a cell structure (e.g., the cell structure (202) of FIGS. 2 to 7) within the base dielectric layer.

[0051] In block (856), the method (850) may include the step of forming an isolated region for a thermal path (e.g., the isolated region (432) of FIG. 4b) within a base dielectric layer adjacent to a cell structure. The region of the thermal path may be electrically isolated from the region of the surrounding circuit and the region of contacts, vias, and / or TSVs using the base dielectric layer by, for example, by preserving or forming vertical portions or walls surrounding the thermal path portions.

[0052] In block (858), the method (850) may include the step of forming a thermal path (e.g., the thermal path (206) of FIGS. 2 to 7) within a dielectric layer in a region of the thermal path by adding a thermally conductive, electrically non-conductive material such as aluminum oxide, aluminum nitride, etc. The thermal path may be formed by a spin coating process, which contains a thermally conductive material as a filler within a base dielectric layer. In some embodiments, the thermal path is formed by a combination of processes such as physical vapor deposition (PVD), molybdenum (MO), or cut metal dielectric (CMD) to form a thermally conductive layer as a functional film, and is removed by a polishing process. The manufacturing process may be completed by implementing a back end-of-line (BEOL) process to form the wiring of the memory device.

[0053] In block (860), the method (850) may include the step of aligning and bonding wafers and / or dies. For example, the method (850) may include the step of manufacturing one or more wafers / dies, such as a wafer containing the logic circuit (702) of FIG. 7, one or more wafers or dies containing the memory device (704 / 706) of FIG. 7, or a combination thereof, using the process described above for blocks (852-858). The wafers or dies may be aligned using markers. When aligning the wafers or dies, the thermal paths (206) within the wafers or dies may be stacked or aligned vertically along vertical lines.

[0054] Aligned wafers or dies can be attached, for example, through direct wafer-to-wafer bonding. For example, wafers or dies can be arranged or stacked on top of each other so that copper pads on the top and bottom pads are in direct contact with each other. The contact copper pads can be directly bonded to each other (e.g., without adhesive or solder) using diffusion bonding, ultrasonic welding, or other similar direct bonding mechanisms.

[0055] FIG. 9 is a schematic diagram of a system including a device according to an embodiment of the present technology. Any of the aforementioned devices (e.g., memory devices) associated with the memory device described above with reference to FIGS. 1 through 8b may be integrated or implemented in any of a memory (e.g., memory device (900)) or any of a number of larger and / or more complex systems, a representative example of which is the system (980) schematically illustrated in FIG. 9. The system (980) may include a memory device (900), a power supply (982), a driver (984), a processor (986), a placement mechanism (988), and / or other subsystems or components (990). The placement mechanism (988) may use an ML / AI model to determine the location, size, shape, length, width, depth, and / or number of thermal paths to be added to the memory device structure based on the operation metrics of the memory device (as described in FIG. 8a and 8b).

[0056] The memory device (900) may include features generally similar to those of the device described above with reference to FIGS. 1 through 8b, and thus may include various features for performing direct read requests obtained from a host device. The resulting system (980) may perform any of a wide variety of functions, such as memory storage, data processing, and / or other appropriate functions. Accordingly, representative systems (980) may include, without limitation, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, consumer electronics, and other products. Components of the system (980) may be housed in a single unit or distributed across a number of interconnected units (e.g., via a communication network). Components of the system (980) may also include a remote device and any of various computer-readable media.

[0057] As stated above, specific embodiments of the present technology have been described herein for illustrative purposes, but it will be understood that various modifications may be made without departing from the present technology. Additionally, certain forms of the new technology described within the scope of specific embodiments may also be combined or removed in other embodiments. Furthermore, while the advantages associated with specific embodiments of the new technology have been described in the context of these embodiments, other embodiments may also demonstrate these advantages, and not all embodiments are required to demonstrate these advantages to be included within the scope of the present technology. Accordingly, the present technology and related technologies may include other embodiments not explicitly shown or described in this specification.

[0058] In the embodiments described above, the devices were described in the context of DRAM devices. However, devices configured according to other embodiments of the present technology may include other types of suitable storage media, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, etc., in addition to or instead of DRAM devices.

[0059] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transmitting, and / or manipulating data structures. The term "data structure" includes information arranged in bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. Additionally, as used herein, the term "dynamic" describes processes, functions, behaviors, or implementations that occur during the operation, use, or distribution of the device, system, or embodiment, and after or during the execution of manufacturer firmware or third-party firmware. Processes, functions, behaviors, or implementations that occur dynamically may occur after or following design, manufacturing, and initial testing, setup, or configuration.

[0060] The above embodiments are described in sufficient detail to enable those skilled in the art to practice and use the embodiments. However, a person skilled in the art will understand that the present invention may have additional embodiments and that the present invention may be practiced without the various details of the embodiments described above with reference to FIGS. 1 through 9.

Claims

Claim 1 A device comprising: a semiconductor substrate; a memory cell on the semiconductor substrate; a thermal path on the semiconductor substrate and separated from the memory cell along a lateral direction - the thermal path comprises a thermally conductive and electrically insulating material -; and a dielectric material forming a layer on the semiconductor substrate surrounding at least a peripheral portion of the thermal path and the memory cell. Claim 2 A device according to claim 1, wherein the thermal path comprises a material with higher thermal conductivity than the dielectric material, and the thermal path is configured to transfer thermal energy out of or through the device. Claim 3 In claim 1, the thermal path is electrically isolated from the memory cell using the semiconductor substrate. Claim 4 A device according to claim 1, wherein the thermally conductive and electrically insulating material is aluminum oxide or aluminum nitride. Claim 5 A device according to claim 1, wherein the thermal path comprises a top portion, a bottom portion, or both exposed through the semiconductor substrate. Claim 6 A memory device comprising: a semiconductor substrate portion; a dielectric layer on the semiconductor substrate portion; at least one cell structure disposed within the dielectric layer and configured to store charges representing stored data; and a thermal path located adjacent to the at least one cell structure and at least partially embedded within the dielectric layer—the thermal path comprises a thermally conductive and electrically insulating material. Claim 7 A memory device according to claim 6, wherein the thermal path comprises a material having higher thermal conductivity than the dielectric material of the dielectric layer, and the thermal path is configured to transfer thermal energy out of or through the memory device. Claim 8 In claim 6, the above thermal path is electrically isolated from the at least one cell structure using the above dielectric layer, a memory device. Claim 9 In claim 6, the memory device wherein the thermally conductive and electrically insulating material is aluminum oxide or aluminum nitride. Claim 10 A memory device according to claim 6, further comprising: an active circuit portion disposed below at least one cell structure and on or above the semiconductor substrate portion; and a through silicon via (TSV) extending along a vertical direction and through the dielectric layer, the semiconductor substrate portion, or both. Claim 11 A memory device according to claim 6, further comprising a logic device wafer including a logic circuit portion configured to facilitate the storage, access, and maintenance of data stored in the memory device, wherein the semiconductor substrate portion, the dielectric layer, the at least one cell structure, and the thermal path comprise a semiconductor storage device configured to store data, wherein the semiconductor storage device is wafer-bonded to the logic device and on top of the logic device, and the thermal path is configured to allow thermal energy generated by the logic device to move upward and through the semiconductor storage device. Claim 12 In claim 11, the semiconductor storage device is a first storage device having a first column path and directly attached to the logic device, and the memory device comprises a second storage device having a second column path and a wafer directly bonded to the first storage device and on top of the first storage device, wherein the first column path and the second column path are aligned along a vertical line. Claim 13 In paragraph 6, the memory device is a memory device comprising dynamic random access memory (DRAM) cells. Claim 14 A method comprising: providing a semiconductor substrate; forming at least one cell structure on the semiconductor substrate, wherein the at least one cell structure is configured to store data; forming a dielectric layer on the semiconductor substrate and surrounding the at least one cell structure; forming at least one isolated region adjacent to the at least one cell structure by removing a portion of the dielectric layer; and forming a thermal path within the dielectric layer in the at least one isolated region by adding a thermally conductive and electrically insulating material within the at least one isolated region. Claim 15 In claim 14, the step of forming the thermal path comprises spin coating for depositing the thermally conductive and electrically insulating material within the at least one isolated region of the dielectric layer. Claim 16 In claim 14, the step of forming the thermal path comprises a physical vapor deposition (PVD) process, a molybdenum (MO) process, a cut metal dielectric (CMD) process, or a combination thereof for depositing the thermally conductive and electrically insulating material. Claim 17 In claim 14, the thermally conductive and electrically insulating material is added during the FEOL (front-end-of-line) layer manufacturing step, in a method. Claim 18 In claim 14, the thermally conductive and electrically insulating material has higher thermal conductivity than the dielectric material of the dielectric layer, and the thermally conductive and electrically insulating material provides the thermal path to transfer thermal energy out of or through the dielectric layer. Claim 19 The method of claim 14 further comprises the steps of: forming or attaching an active circuit portion on the semiconductor substrate—wherein at least one cell structure is formed on the active circuit portion—; and forming a thermal via or through-silicon via (TSV) extending through the dielectric layer and extending into the semiconductor substrate—wherein the thermal via or the TSV is located between the at least one cell structure and the thermal path—wherein the thermal path is physically separated and electrically isolated from the thermal via or the TSV and the active circuit portion using the dielectric layer. Claim 20 In claim 14, the step of forming the thermal path comprises the step of depositing aluminum oxide or aluminum nitride within the at least one isolated region.

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