Cleaved semiconductor wafer camera systems and methods

Abstract

A semiconductor wafer imaging system for imaging a semiconductor wafer includes shroud panels defining a black box, a camera positioned in the black box to image the semiconductor wafer, and a lighting panel for directing diffused light toward the semiconductor wafer. A portion of the diffused light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffused light.

Description

Technology Field

[0001] The present application claims priority to U.S. Provisional Application No. 62 / 706,894 filed September 16, 2020, U.S. Provisional Application No. 62 / 706,895 filed September 16, 2020, and U.S. Provisional Application No. 62 / 706,897 filed September 16, 2020, by which the entire contents of their disclosures are incorporated by reference.

[0002] The field of the present disclosure is to imaging semiconductor substrates, and in particular, to methods and systems for imaging cleaved wafers. Background Technology

[0003] Generally, semiconductor wafers are used in the production of integrated circuit (IC) chips on which circuits are printed. First, circuits are printed in a miniaturized form onto the surfaces of the wafers, and then the wafers are cut into circuit chips. During the manufacturing process, the wafers are processed and polished so that the front and back surfaces of each wafer have reflective mirror-like surfaces. To reduce manufacturing costs, the wafers are also imaged during the manufacturing process to detect defects on the surfaces of the wafers before they are further processed.

[0004] Some imaging systems used in quality control systems image manufactured articles by reflecting light from the articles and detecting the reflected light with a camera. Typically, cameras image the non-specular surfaces of the manufactured articles. However, because the surfaces of wafers are specular, the light directed toward the wafers must be diffuse, uniform light. Otherwise, the image captured by the imaging system will be a reflected image of the light source rather than the features of the wafers.

[0005] Additionally, while some imaging systems image the reflective surfaces of wafers, these systems typically include large parabolic mirrors that increase the size of the imaging systems and limit the locations where they can be positioned within the manufacturing process. Specifically, parabolic mirrors significantly increase the height and width of the imaging system. The imaging system can only be positioned in locations that have sufficient space to accommodate the large-volume system. Suitable locations for the systems can interfere with the manufacturing process.

[0006] This section is intended to introduce to the reader various aspects of the relevant art, which may relate to the various aspects of the present disclosure described and / or claimed below. This discussion is considered useful for providing background information to facilitate a better understanding of the various aspects of the present disclosure to the reader. Accordingly, these statements should be read in that context and not as an acknowledgment of the prior art.

[0007] One aspect of the present disclosure relates to a semiconductor wafer imaging system for imaging a semiconductor wafer. The system comprises shroud panels defining a black box, a camera positioned in the black box to image the semiconductor wafer, and a lighting panel for directing diffuse light toward the semiconductor wafer. A portion of the diffuse light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0008] Another aspect of the present disclosure relates to a black box for imaging a semiconductor wafer. The black box comprises shroud panels defining an upper chamber and a lower chamber. A support plate separates the upper chamber from the lower chamber. The lowest shroud panel defines at least partially the lower chamber and defines a wafer aperture. The support plate defines a camera aperture. The black box further comprises a camera positioned in the upper chamber to image the semiconductor wafer and a lighting panel for directing diffuse light toward the semiconductor wafer. The diffuse light is transmitted through the wafer aperture toward the semiconductor wafer, and a portion of the diffuse light is reflected from the semiconductor wafer through the wafer aperture and the camera aperture. The camera images the semiconductor wafer by detecting the reflected diffuse light.

[0009] Another aspect of the present disclosure relates to a semiconductor wafer processing system for processing a semiconductor wafer. The system includes a semiconductor wafer processing station for processing a semiconductor wafer, and a semiconductor wafer imaging system for imaging the semiconductor wafer after the semiconductor wafer processing station has processed the semiconductor wafer. The semiconductor wafer imaging system includes shroud panels defining a black box, a camera positioned in the black box to image the semiconductor wafer, and a lighting panel for directing diffuse light toward the semiconductor wafer. A portion of the diffuse light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0010] Another aspect of the present disclosure relates to a semiconductor wafer processing system for processing semiconductor wafers. The system includes a first manufacturing line for processing a first semiconductor wafer, and the first manufacturing line includes a first semiconductor wafer processing station for processing the first semiconductor wafer. The system further includes a second manufacturing line for processing a second semiconductor wafer, and the second manufacturing line includes a second semiconductor wafer processing station for processing the second semiconductor wafer. The second manufacturing line intersects the first manufacturing line at a common location. The system further includes a semiconductor wafer imaging system for imaging the first semiconductor wafer and the second semiconductor wafer, and the semiconductor wafer imaging system is positioned within the common location where the first manufacturing line and the second manufacturing line intersect. The semiconductor wafer imaging system images the first semiconductor wafer and the second semiconductor wafer after the first semiconductor wafer processing station and the second semiconductor wafer processing station have processed the first semiconductor wafer and the second semiconductor wafer. A semiconductor wafer imaging system includes shroud panels defining a black box, a camera positioned in the black box to image the semiconductor wafer, and a lighting panel to direct diffuse light toward the semiconductor wafer. A portion of the diffuse light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffuse light.

[0011] Another aspect of the present disclosure relates to a semiconductor wafer imaging station of a semiconductor wafer processing system for imaging a semiconductor wafer. The station comprises a frame, a locating plate attached to the frame, and a black box movably attached to the locating plate. The black box comprises shroud panels defining the black box, a camera positioned in the black box to image the semiconductor wafer, and a lighting panel for directing diffuse light toward the semiconductor wafer. A portion of the diffuse light is reflected from the semiconductor wafer, and the camera images the semiconductor wafer by detecting the reflected diffuse light. The station further comprises an end effector for positioning the semiconductor wafer within the field of view of the camera.

[0012] Another aspect of the present disclosure relates to a method for detecting defects on a semiconductor wafer. The method comprises the steps of directing diffuse light toward a semiconductor wafer and reflecting the diffuse light from the semiconductor wafer. The method further comprises the steps of detecting the diffuse light with a camera to generate an image of the semiconductor wafer and analyzing the image to detect defects on the semiconductor wafer.

[0013] Another aspect of the present disclosure relates to a method for processing a semiconductor wafer. The method comprises the steps of cleaving a semiconductor wafer at a cleaving station, positioning the semiconductor wafer within the field of view of a camera, and directing diffuse light toward the semiconductor wafer. The method further comprises the steps of reflecting diffuse light from the semiconductor wafer, detecting the diffuse light with a camera to generate an image of the semiconductor wafer, and analyzing the image to detect defects on the semiconductor wafer.

[0014] Another aspect of the present disclosure relates to a method for processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system includes a processing station and a semiconductor wafer imaging station. The method includes the steps of processing a semiconductor wafer at the processing station, positioning the semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station, and directing diffuse light toward the semiconductor wafer. The method further includes the steps of reflecting diffuse light from the semiconductor wafer, detecting the diffuse light with a camera to generate an image of the semiconductor wafer, and analyzing the image to detect defects on the semiconductor wafer.

[0015] Another aspect of the present disclosure relates to a method for processing a semiconductor wafer using a semiconductor wafer processing system. The semiconductor wafer processing system comprises a first manufacturing line, a second manufacturing line, and a semiconductor wafer imaging station positioned within a common location where the first manufacturing line and the second manufacturing line intersect. The first manufacturing line and the second manufacturing line each comprise processing stations for processing a semiconductor wafer. The method comprises: i) processing a first semiconductor wafer at a processing station of the first manufacturing line; ii) positioning the first semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station; and iii) directing diffuse light toward the first semiconductor wafer. The method further comprises: iv) reflecting diffuse light from the first semiconductor wafer; v) detecting diffuse light with a camera to generate an image of the first semiconductor wafer; and vi) analyzing the image to detect defects on the first semiconductor wafer. The method further includes vii) processing a second semiconductor wafer at a processing station of a second manufacturing line, and viii) repeating steps ii through vi to image the second semiconductor wafer.

[0016] Various improvements to the features mentioned in relation to the embodiments mentioned above exist. Additionally, additional features may also be included in the embodiments mentioned above. These improvements and additional features may exist individually or in any combination. For example, various features discussed below in relation to any of the exemplified embodiments may be included in any of the embodiments described above, either alone or in any combination. Brief explanation of the drawing

[0017] Figure 1 is a schematic diagram of a semiconductor wafer processing system. Figure 2 is a schematic diagram of an alternative semiconductor wafer processing system. FIG. 3 is a perspective view of a semiconductor wafer imaging system positioned in a common location within the semiconductor wafer processing systems of FIG. 1 and FIG. 2. FIG. 4 is another perspective view of a semiconductor wafer imaging system positioned in a common location within the semiconductor wafer processing systems of FIG. 1 and FIG. 2. FIG. 5 is a perspective view of the semiconductor wafer imaging system illustrated in FIG. 3 and FIG. 4 having transparent shrouds. Figure 6 is a cross-sectional view of the lighting panel shown in Figure 5. FIG. 7 is a perspective view of the semiconductor wafer imaging system shown in FIG. 5 with the shrouds removed. FIG. 8 is another perspective view of the semiconductor wafer imaging system shown in FIG. 5 with the shrouds and structural members removed. Figure 9 is a cross-sectional view of the semiconductor wafer imaging system illustrated in Figure 5. FIG. 10 is another perspective view of the semiconductor wafer imaging system illustrated in FIG. 5, showing filters with shrouds and structural members removed. FIG. 11 is another perspective view of the semiconductor wafer imaging system illustrated in FIG. 3 and FIG. 4 having an end effector positioner. FIG. 12 is another perspective view of the semiconductor wafer imaging system illustrated in FIG. 3 and FIG. 4 having an end effector positioner and an isolated end effector. FIG. 13 is a schematic diagram of an image of a semiconductor wafer captured by the semiconductor wafer imaging system shown in FIG. 3 and FIG. 4. Figure 14 is an image of a semiconductor wafer captured by the semiconductor wafer imaging system shown in Figures 3 and 4. Figure 15 is a raw Fast Fourier Transform (FFT) image of a semiconductor wafer generated by a controller. Figure 16 is a schematic diagram of an output image of a semiconductor wafer generated by a controller. Figure 17 is an output image of a semiconductor wafer generated by a controller. Figure 18 is a diagram of a computer program for imaging and analyzing a semiconductor wafer. FIGS. 19 to 21 are flowcharts of a method for imaging and analyzing a semiconductor wafer. Figure 22 is a display for use in correcting the position of a wafer by an image analysis process. Certain features of various examples may be shown in some drawings and not in others, but this is merely for convenience. Any feature of any drawing may be referenced and / or claimed in combination with any feature of any other drawing. Unless otherwise indicated, the drawings are intended to illustrate features of the examples of the present disclosure. These features are considered applicable in various systems comprising one or more examples of the present disclosure. The drawings are not intended to include all prior features known to a person skilled in the art as required for carrying out the disclosed examples. Specific details for implementing the invention

[0018] Semiconductor wafers (which may be referred to as semiconductor or silicon "wafers" or "substrates") are generally prepared from a single-crystal ingot (e.g., silicon ingot) formed by a crystal growth process that is sliced ​​into individual wafers. Suitable crystal growth processes include the Czochralski process, the float zone process, the hydrothermal process, the Bridgeman process, the Kyropoulos process, and / or any other crystal growth process. Although semiconductor wafers composed of silicon will be referred to herein, other materials such as germanium, silicon carbide, silicon germanium, gallium arsenide, and other alloys of Group III and V elements, such as gallium nitride or indium phosphide, or alloys of Group II and VI elements, such as cadmium sulfide or zinc oxide, may be used to prepare semiconductor wafers. Each semiconductor wafer comprises a central axis, a front surface, and a back surface parallel to the front surface. The front and rear surfaces are generally perpendicular to the central axis. A circumferential edge connects the front surface and the rear surface.

[0019] Semiconductor wafers can be utilized in the preparation of composite layer structures. A composite layer structure (e.g., semiconductor-on-insulator, more specifically silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, composite layer structures such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz are created by placing two wafers in close proximity to initiate bonding via van der Waals forces, followed by strengthening the bond through thermal treatment. Annealing can strengthen the bond by converting terminal silanol groups into siloxane bonds between the two interfaces.

[0020] After thermal annealing, the bonded structure undergoes additional processing to remove a significant portion of the donor wafer in order to achieve layer transfer. For example, a common method for achieving layer transfer utilizes hydrogen implantation and subsequent thermally induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted to a specified depth below the front surface of the donor wafer. The implanted particles form a cleave plane on the donor wafer at the specified depth in which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds, such as boron compounds, or other contaminants deposited on the wafer during the implantation process.

[0021] Next, the front surface of the donor wafer is bonded to the handle wafer to form a bonded wafer through a hydrophilic bonding process. Before bonding, the donor wafer and / or handle wafer are activated by exposing the surfaces of the wafers, for example, to a plasma containing oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process commonly referred to as surface activation, and this activation process makes the surfaces of one or both of the donor wafer and the handle wafer hydrophilic. The surfaces of the wafers may be further chemically activated by wet treatment such as SC1 cleaning or hydrofluoric acid. Wet treatment and plasma activation may occur in either order, or the wafers may undergo only one treatment. Subsequently, the wafers are pressed together, and a bond is formed between them. This bond is relatively weak due to van der Waals forces and must be strengthened before further processing can occur.

[0022] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding can occur at low temperatures, such as approximately 300°C to 500°C. In some processes, wafer bonding can occur at high temperatures, such as approximately 800°C to 1100°C. The elevated temperatures form covalent bonds between the adjacent surfaces of the donor wafer and the handle wafer, thereby hardening the bond between the donor wafer and the handle wafer. Simultaneously with the heating or annealing of the bonded wafer, particles previously injected into the donor wafer weaken the cleave plane.

[0023] Subsequently, a portion of the donor wafer is separated from the bonded wafer along the cleave plane (i.e., cleaved) to form an SOI wafer. Cleaving can be performed by placing the bonded wafer in a fixture, whereby a mechanical force is applied perpendicular to the opposing faces of the bonded wafer to pull and separate the portion of the donor wafer from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge to the edge of the bonded wafer at the cleave plane to initiate the propagation of a crack along the cleave plane. Subsequently, the mechanical force applied by the suction cups pulls the portion of the donor wafer from the bonded wafer to form an SOI wafer.

[0024] In one example, a semiconductor wafer imaging system images wafers to detect defects within the wafers during the manufacturing process. The imaging system images the wafers after they have been cleaved to detect defects within the wafers formed during any upstream manufacturing process, including a cleaving process. If the semiconductor wafer imaging system detects defects within the wafer, the wafer is removed from the manufacturing process, thereby reducing wafer production costs. The wafers have reflective mirror-like surfaces, and the semiconductor wafer imaging system images the wafer without imaging light sources reflected from the reflective surfaces. Specifically, the semiconductor wafer imaging system includes a black box surrounding a camera and a lighting panel. The black box minimizes reflections in the semiconductor wafer imaging system, and the lighting panel directs diffuse light toward the wafer. The diffuse light is reflected from the wafer toward the camera. The camera detects the reflected diffuse light and does not image the lighting panel because the light generated by the lighting panel is diffused. Therefore, the camera images the wafer rather than the light source, allowing the controller to analyze the wafer for defects and reducing manufacturing costs.

[0025] Referring to FIG. 1, a semiconductor wafer processing system (100) includes a manufacturing line (102) for manufacturing semiconductor wafers (104). The manufacturing line (102) includes semiconductor wafer processing stations (106) for processing the wafers (104). The processing stations (106) include a cleaving station (108) and a semiconductor wafer imaging station or system (110) for imaging the wafers (104). In an illustrated embodiment, the imaging system (110) is positioned over the cleaving station (108) to image the wafers (104) after the wafers (104) have been cleaved by the cleaving station. The imaging system (110) images each wafer (104), and a controller (112) analyzes the images and detects defects within the wafers. If the wafer (104) contains defects, the wafer is discarded before further processing, thereby reducing wafer production costs.

[0026] Referring to FIG. 2, an alternative semiconductor wafer processing system (114) includes two or more manufacturing lines (102) for manufacturing wafers (104). Similar to the processing system (100), each manufacturing line (102) includes processing stations (106) that include cleaving stations (108). The manufacturing lines (102) also include a common location (116) where the manufacturing lines intersect. An imaging system (110) is positioned at the common location (116) and images the wafers (104) manufactured by all manufacturing lines (102) that intersect the common location. In the illustrated embodiment, the processing system (114) includes two manufacturing lines (102). However, in alternative embodiments, the processing system (114) may include any number of manufacturing lines (102) that enable the processing system (114) to operate as described herein. Additionally, in the embodiments illustrated in FIGS. 1 and 2, the imaging system (110) is positioned above or immediately downstream of the cleaving station (108). In alternative embodiments, the imaging system (110) may be positioned at any location within the processing systems (100 and 114) that enable the processing systems to operate as described herein.

[0027] Referring to FIGS. 3 and 4, the imaging system (110) includes a black box (118), an end effector (120), and a locating plate (122). As described below, the black box (118) includes a camera for imaging wafers (104). The locating plate (122) positions the black box (118) at a common position (116), and the end effector (120) positions the wafer (104) under the black box (118) for imaging. The locating plate (122) is attached to a frame (124), and the black box (118) is movably attached to the locating plate. The position of the black box (118) on the locating plate (122) can be adjusted to adjust the position of the black box (118). Additionally, the end effector (120) is movable relative to the black box (118) so that the position of the wafer (104) can be adjusted during imaging.

[0028] Referring to FIG. 5, shroud panels (126) define the black box (118). Specifically, the shroud panels (126) define the upper chamber (128) and the lower chamber (130). A support plate (132) is positioned within the black box (118) and separates the upper chamber (128) from the lower chamber (130). Additionally, a lower shroud (134) defines the lower part (136) of the black box (118). The support plate (132) defines the support plate opening (138), i.e., the camera opening, and the lower shroud (134) defines the lower shroud opening (140), i.e., the wafer opening. In the illustrated embodiment, both the support plate opening (138) and the lower shroud opening (140) are circular, corresponding to the size and shape of the wafer (104). However, in alternative embodiments, the support plate opening (138) and the bottom shroud opening (140) are of any shape that enables the imaging system (110) to operate as described herein. Additionally, the support plate opening (138) is aligned with the bottom shroud opening (140), so that when a wafer is positioned in the bottom shroud opening (140), the wafer (104) can be seen through a direct, unobstructed line of sight (142) from the wafer to the upper chamber (128). The shroud panels (126) are suitably manufactured from black anodized aluminum panels to minimize reflections within the black box (118). In alternative embodiments, the shroud panels (126) are manufactured from any material that enables the black box (118) to operate as described herein.

[0029] The black box (118) includes a lighting panel (144) for directing diffused light toward a wafer (104). The lighting panel (144) is positioned in the lower chamber (130) and directs diffused light toward the wafer (104) positioned in the lower shroud opening through the lower shroud opening (140). Subsequently, the diffused light is reflected from the wafer (104) toward the upper chamber (128) through the support plate opening (138) and the lower shroud opening (140). In the illustrated embodiment, the lighting panel (144) has a rectangular shape, and the shape of the lower chamber (130) matches the shape of the lighting panel. In alternative embodiments, the lighting panel (144) may have any shape including a circular shape and / or a polygonal shape that enables the semiconductor wafer imaging system (110) to operate as described herein.

[0030] Referring to FIG. 6, the lighting panel (144) comprises a frame (186), lights (188), and a transparent plate (190). The frame (186) has a rectangular shape to match the shape of the lower chamber (130). In the illustrated embodiment, the lights (188) are light-emitting diode (LED) lights. In alternative embodiments, the lights (188) may be any type of light that enables the semiconductor wafer imaging system (110) to operate as described herein. The lights (188) are attached to the frame (186) so that the lights direct visible light in a horizontal direction (152) through the transparent plate (190). The transparent plate (190) comprises a first edge (192), a second edge (194), a top surface (196), a bottom surface (198), and reflectors (200).

[0031] The lights (188) direct light into the first edge (192) of the transparent plate (190), and the light exits at the second edge (194) or is directed through the bottom surface (198) by the reflectors (200). The lights (188) substantially surround the transparent plate (190), and accordingly, the visible light emitted by the lights is scattered across the entire transparent plate, traveling and reflecting in all directions parallel to the top and bottom surfaces (196 and 198). The visible light will remain within the transparent plate (190) until it is directed downward by the reflectors (200). The top surface (196) is textured with a regular geometric array of reflectors (200) to direct a portion of the visible light emitted by the lights (188) downward through the bottom surface (198). In the illustrated embodiment, the reflectors (200) include raised and / or recessed features, including holes and / or protrusions formed in the transparent plate (190), which reflect, diffuse, and / or scatter visible light downward. For example, the raised features formed in the transparent plate (190) may include pyramidal or conical protrusions extending from the transparent plate, and the recessed features formed in the transparent plate (190) may include holes that allow a portion of the reflected light to pass through. The raised features and the recessed features are not aligned, and accordingly, reflections from the features do not interfere with each other. When visible light strikes one of the reflectors (200), the visible light is internally reflected and scattered or reflected downward so as not to escape from the transparent plate (190), and intersects the lowest surface (198) at a substantially vertical angle of incidence. The reflectors (200) scatter visible light so that the visible light is directed downward toward the wafer (104) as diffused light.

[0032] The diffused light is reflected back up from the wafer (104) through the transparent plate (190). A portion of the reflected diffused light passes through the transparent plate (190) without colliding with the reflectors (200) and is imaged by a camera as described below. However, the reflected diffused light that collides with the reflectors (200) is scattered or refracted, and accordingly, it is not possible for the camera to image the scattered diffused light, which can create an array of dark spots on the image of the wafer (104).

[0033] The black box (118) also includes a camera (146) for imaging the wafer (104). The camera (146) includes a monochrome digital camera for taking black-and-white digital photographs of the wafer (104). The camera (146) is positioned in the upper chamber (128) and images the wafer (104) through the support plate opening (138) and the lowest shroud opening (140). In the illustrated embodiment and as described below, the camera (146) is positioned near a mirror (148) that reflects light reflected from the wafer (104) to the camera. In alternative embodiments, the black box (118) does not include a mirror (148), and the camera (146) is positioned in the upper chamber (128) to directly image the wafer (104).

[0034] The black box (118) further includes a slide lock (150) attached to the camera (146) to position the camera in the upper chamber (128). The camera (146) is movably attached to the slide lock (150) for positioning and repositioning the camera in the upper chamber (128). Specifically, as illustrated in FIGS. 5 and FIGS. 7 through 10, the slide lock (150) is oriented in a horizontal direction (152) and slides the camera (146) in a horizontal direction to focus the camera on the wafer (104). In an alternative embodiment, the black box (118) does not include a mirror (148), and the slide lock (150) and the camera (146) are oriented in a vertical direction (154). The slide lock (150) slides the camera (146) in a vertical direction (154) to focus the camera on the wafer (104). In alternative embodiments, the camera (146) has an adjustable focus, and the black box (118) does not include a slide lock (150).

[0035] The mirror (148) includes a planar mirror (156) attached to a mirror positioning system (158). The planar mirror (156) reflects diffuse light reflected from the wafer (104) to the camera (146), and the mirror positioning system (158) positions the planar mirror (156) in the upper chamber (128). The mirror (148) redirects the diffuse light reflected from the wafer (104) from the vertical direction (154) to the horizontal direction (152), thereby enabling the camera (146) to be oriented in the horizontal direction and reducing the height (160) of the black box (118). Thus, the mirror (148) enables the semiconductor wafer imaging system (110) to be compact and positioned within the semiconductor wafer processing system (100).

[0036] The mirror positioning system (158) comprises a base (162), a mirror holder (164), and a plurality of mirror screws (166). The mirror holder (164) is rotatably attached to the base (162), and the screws (166) attach a planar mirror (156) to the mirror holder. The screws (166) are rotated to adjust the angle (α) of the planar mirror (156) relative to the camera (146). The rotation of the screws (166) fine-tunes the angle (α). In alternative embodiments, the mirror positioning system (158) includes a slide similar to a slide lock (150).

[0037] The black box (118) may optionally include a filter (168) positioned in the upper chamber (128). The filter (168) may be a polarizing filter, a color filter, a high-pass filter, and / or any other type of filter that enables the imaging system (110) to operate as described herein. The filter (168) is positioned at a first position (170) on the camera (146) or at a second position (172) on the support plate opening (138). The filter (168) creates contrast between the wafer (104) and the surrounding environment, enabling the camera (146) to image the wafer. Specifically, the filter (168) reduces or eliminates reflections, enabling the camera (146) to image the wafer (104) rather than light or objects reflected by the wafer.

[0038] For example, if the filter (168) is a polarizing filter, the filter uses polarization to create contrast between the wafer (104) and the surrounding environment. As described above, the light emitted from the lighting panel (144) is diffuse light that is reflected from the mirror-like surface of the wafer (104) and passes back through the light emitted by the lighting panel. Any light reflected from other surfaces is reflected and scattered. Since the diffused and scattered light is not polarized and the reflected light is polarized, the filter (168) allows only the transmission of diffuse light reflected from the wafer (104). Reflections from surrounding surfaces are reduced or not transmitted to the camera (146). Reducing or eliminating reflections allows the camera (146) to image the wafer (104) rather than the light or objects reflected by the wafer.

[0039] Similarly, if the filter (168) is a color filter, the filter creates contrast between the wafer (104) and the surrounding environment based on the wavelength of light reflected from the mirror-like surface of the wafer (104). The filter (168) selectively transmits light of different wavelengths. For example, the filter (168) may transmit only long wavelengths (long wavelength pass), transmit only short wavelengths (short wavelength pass), or transmit a band of wavelengths to block both longer and shorter wavelengths (band pass). Reflections from surrounding surfaces may have a predetermined wavelength, and the filter (168) reduces or eliminates the reflections by absorbing light within the predetermined wavelength. Reducing or eliminating the reflections allows the camera (146) to image the wafer (104) rather than the light or objects reflected by the wafer.

[0040] Additionally, if the filter (168) is a high-pass filter, the filter creates contrast between the wafer (104) and the surrounding environment based on the wavelength of light reflected from the mirror-like surface of the wafer (104). Specifically, the filter (168) transmits light having a wavelength of 600 nanometers (nm) or greater while absorbing light having wavelengths of less than 600 nm. Reflections from surrounding surfaces may have wavelengths of less than 600 nm, and the filter (168) reduces or eliminates the reflections by absorbing light having wavelengths of less than 600 nm. Reducing or eliminating the reflections allows the camera (146) to image the wafer (104) rather than the light or objects reflected by the wafer.

[0041] The imaging system (110) includes an end effector positioner (174) attached to a black box (118) to correct the position (176) of the end effector (120). The end effector positioner (174) is detached from the black box (118) after the position (176) of the end effector (120) is corrected. The end effector positioner (174) includes a black box brace (178), an arm (180), and a puck (182). The end effector positioner (174) is attached to the black box (118) before the imaging system (110) images the wafer (104). The puck (182) is attached to the arm (180), the arm and the puck are attached to the black box brace (178), and the arm, the puck, and the black box brace are attached to the black box (118). The black box brace (178) and arm (180) are sized and molded to position the puck (182) below the lowest shroud opening (140) within the field of view (184) of the camera (146). The end effector (120) is positioned so that the end effector is attached to the puck (182), and the controller (112) records and corrects the position (176) so that the end effector positions the wafer (104) at the position (176) for each imaging. The end effector positioner (174) is detached from the black box (118) after the position (176) is corrected.

[0042] Before manufacturing the wafer (104), the imaging system (110) is positioned and calibrated within the processing system (100). Specifically, a locating plate (122) is attached to the frame (124), and the imaging system (110) is attached to the locating plate. More specifically, a black box (118) is attached to the locating plate (122).

[0043] The camera (146) and mirror (148) are positioned and calibrated in the black box (118) when the imaging system (110) is positioned and calibrated within the processing system (100). Specifically, the operator uses a mirror positioning system (158) to position the mirror (148) in the upper chamber (128) of the black box (118). More specifically, the operator attaches the flat mirror (148) to a mirror holder (164) and attaches the mirror holder and the flat mirror to a base (162). Additionally, the operator also attaches the camera (146) to a slide lock (150) and positions the camera and the slide lock in the upper chamber (128) of the black box (118). The operator simultaneously adjusts the slide lock (150), the camera (146), and the plane mirror (156) to ensure that the camera's field of view (184) is centered at the lowest shroud opening (140). More specifically, to ensure that the camera's field of view (184) is centered at the lowest shroud opening (140), the operator simultaneously adjusts the screws (166), rotates the mirror holder (164), and slides the camera (146) on the slide lock (150).

[0044] The operator attaches the puck (182) to the arm (180), attaches the puck and the arm to the black box brace (178), and attaches the puck, the arm, and the black box brace to the black box, thereby attaching the end effector positioner (174) to the black box (118). The end effector positioner (174) is attached to the black box (118) so that the puck (182) is centered at the lowest shroud opening (140). The operator positions the end effector (120) so that the end effector is attached directly or indirectly to the puck (182). The controller (112) records and corrects the position (176) of the end effector (120) so that the end effector positions the wafer (104) at the position (176) for each imaging. The operator removes the end effector positioner (174) from the black box (118).

[0045] During operation, the wafer processing system (100) manufactures at least partially the wafer (104). Specifically, in the illustrated embodiment, the cleaving station (108) cleaves the wafer (104) and transmits the wafer to the imaging system (110) for imaging. More specifically, after the cleaving station (108) cleaves the wafer (104), the end effector (120) positions the wafer under the lowest shroud opening (140), and the camera (146) generates an image (202) of the wafer (illustrated in FIG. 14, a schematic representation (203) of the image (202) is illustrated in FIG. 13). The image (202) of the wafer (104) is transmitted to the controller (112) for analysis as described below.

[0046] Referring to FIGS. 13 and 14, as illustrated in image (202) and schematic representation (203) of image (202), a wafer (104) comprises a base (204) and a transfer layer (206) deposited on the base. The base (204) has a wafer boundary (208), and the transfer layer (206) has a transfer layer boundary (210). The wafer boundary (208) and the transfer layer boundary (210) define a terrace width (212) between them. Additionally, the wafer (104) comprises a notch (222). A controller (112) detects the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212) in image (202) and analyzes the detected areas for defects within the wafer (104). Additionally, as discussed above, the arrangement of reflectors (200) on the top surface (196) of the transparent plate (190) can generate a regular geometric array of periodic artifacts (214) in the image (202) (illustrated as a weave pattern in the image (202)). Specifically, the reflectors (200) generate a grid pattern of periodic artifacts (214) in the image (202). The grid pattern of periodic artifacts (214) may include a regularly spaced periodic array of out-of-focus points, slightly in-focus points, and / or dark spots.

[0047] The controller (112) includes a computer program (300) for imaging and analyzing a wafer (104). FIG. 18 is a diagram of the computer program (300) for imaging and analyzing a wafer (104). The computer program (300) includes an image capture module (302), a data management module (304), and a data analysis module (306). The image capture module (302) controls the semiconductor wafer imaging system (110) to position the wafer (104) within the lowest shroud opening (140), capture an image (202) of the wafer, and return the wafer to the semiconductor wafer processing system (100) for further processing. The data management module (304) records identification information for each wafer (104), stores the image (202) for analysis, and notifies the data analysis module (306) that the image (202) is ready for analysis. The data analysis module (306) analyzes the image (202), determines whether the wafer (104) is acceptable for further processing, and, if necessary, removes the wafer from the manufacturing process by controlling the semiconductor wafer processing system (100).

[0048] The computer program (300) may be a single program including all three modules or a plurality of programs interfacing with each other. For example, in the first embodiment, the computer program (300) is a single program including all three modules. In this embodiment, the computer program (300) images and analyzes the wafer (104) before another wafer is imaged and analyzed. The modules (302-306) are executed sequentially before the other wafer (104) is imaged and analyzed.

[0049] In a second embodiment, the computer program (300) comprises a single program that executes the modules (302-306) out of order. For example, in this embodiment, the computer program (300) may execute the image capture module (302) and the data management module (304) sequentially, but may not execute the data analysis module (306) until a number of wafers (104) are imaged, thereby allowing the controller (112) to analyze the wafers in batches. If there is an error in the data analysis module (306), the images (202) are saved by the data management module (304) for subsequent analysis.

[0050] In a third embodiment, the computer program (300) comprises a plurality of programs, each comprising one or more modules (302-306). In this embodiment, the modules (302-306) are separated into distinct programs so that the modules (302-306) can be executed out of sequence. For example, the first computer program may include an image capture module (302) and a data management module (304), while the second computer program may include a data analysis module (306). Additionally, the first and second computer programs may be executed on different controllers (112) or computing devices, thereby allowing the controller not to analyze the images (202) while executing the image capture module (302) and the data management module (304). The third embodiment allows the manufacturing process to continue when the controller or computing device executing the data analysis module (306) and / or the data analysis module is temporarily unable to perform the analysis.

[0051] FIGS. 19 to 21 are flowcharts of a method (400) for imaging and analyzing a wafer (104). Each module (302-306) performs specific steps of the method (400), and the modules may be executed out of order. The method (400) includes a step (402) of imaging the wafer (104) using a semiconductor wafer imaging system (110) as described above. Specifically, the step (402) of imaging a wafer (104) using a semiconductor wafer imaging system (110) includes the step (404) of positioning the wafer (104) within the lowest shroud opening (140) using an end effector (120), the step (406) of directing diffuse light toward the wafer (104) using a lighting panel (144), the step (408) of reflecting diffuse light from the wafer, and the step (410) of detecting diffuse light with a camera (146) to generate an image (202) of the wafer.

[0052] The method (400) also includes the step (412) of storing and transmitting images. Images (202) are transmitted to a controller (112), and the controller analyzes the images before another wafer (104) is imaged. The controller (112) analyzes the images as soon as they are received from the camera (146). However, the controller (112) and / or analysis may create a bottleneck in the manufacturing process. To reduce manufacturing time, the camera (146) may transmit images along with a wafer identification number to the controller (112), and the controller may analyze the images as the wafer (104) proceeds through the manufacturing process.

[0053] The method (400) further includes the step (414) of analyzing the wafer (104) using a controller (112) to detect defects on the wafer. The defects may include voids (missing areas within the transfer layer (206) that do not intersect the transfer layer boundary (210), edge voids (missing areas within the transfer layer (206) that intersect the transfer layer boundary (210), asymmetry of the terrace width (212), oversizing and undersizing of the notch terrace width, alignment of the transfer layer (206) within the wafer (104), symmetry of the terrace width and various metrics of area, stains (darker and / or brighter areas), and / or any other defects within at least one of the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212). As discussed above, the arrangement of reflectors (200) on the top surface (196) of the transparent plate (190) can generate a regular geometric array of periodic artifacts (214) in the image (202). To remove or reduce the periodic artifacts (214), the step (414) of analyzing the wafer (104) using a controller (112) to detect defects on the wafer may include the step (416) of applying a software filter to the image (202) to remove or reduce the periodic artifacts (214).

[0054] The software filter includes a Fast Fourier Transform (FFT) that identifies and removes periodic artifacts (214) from an image (202). Specifically, since the grid pattern of the periodic artifacts (214) is a regularly spaced periodic array, the FFT decomposes the image (202) into its sine and cosine components, and generates an output image (216) (shown in FIG. 17) in the Fourier or frequency domain while the image (202) is in an equivalent spatial domain. The regular spacing of the grid pattern of the periodic artifacts (214) enables the FFT to identify the periodic artifacts (214) from the image (202). In the output image (216), each point represents a specific frequency contained in the spatial domain image or the image (202). Specifically, the controller (112) generates a raw FFT image (218) (illustrated in FIG. 15) (418), detects periodic artifacts (214) in the image (202) (420), removes or reduces periodic artifacts (214) from the image (422), and converts the image into an output image (216) (illustrated in FIG. 17, a schematic representation (217) of the image (216) is illustrated in FIG. 16) (424). The software filter improves the image (202) before analysis of the image (202) to detect defects on the wafer (104), because the software filter is insensitive to translational position variations of the wafer, diffuser plate, and / or camera, and is essentially self-corrected for rotational position variations of the wafer, diffuser plate, or camera.

[0055] At high magnification, periodic artifacts (214) generated by the arrangement of reflectors (200) on the uppermost surface (196) of the transparent plate (190) are visible. The grid pattern of the periodic artifacts (214) can reduce the precision of the results of the analysis (414). When the image (202) is converted to the frequency domain, the periodic artifacts (214) are represented as high-intensity spots (228) on the raw FFT image (218). After removing the high-intensity spots (228) from the raw FFT image (218), if the raw FFT image (218) is converted back to the spatial domain image, the grid pattern of the periodic artifacts (214) can be removed from the image (202).

[0056] A raw FFT image (218) is generated to enable the visualization of FFT analysis, and the modalities of the raw FFT image enable the visualization of specific modalities of FFT analysis. For example, the raw FFT image (218) is generated using conventional FFT methods and includes a pair of center spots (224) and vertical axes (226). The size of the center spot (224) visually represents the period or distance between periodic artifacts (214) within the image (202). Additionally, the raw FFT image (218) also includes high-intensity spots (228), and the vertical axes (226) are aligned with the high-intensity spots (228). As illustrated in FIG. 14, the grid pattern of the periodic artifacts (214) is oriented at an angle. The high-intensity spots (228) are also oriented at the same angle as the orientation angle of the grid pattern of the periodic artifacts (214), and the pair of vertical axes (226) are also oriented at the same angle as the grid pattern of the periodic artifacts (214) and the high-intensity spots (228). Thus, the raw FFT image (218) enables the visualization of the FFT analysis.

[0057] When an output image (216) is generated, the controller (112) analyzes the output image to detect defects within the wafer (104). Specifically, the controller (112) detects the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), terrace width (212), and notch (222) in the output image (216) (426). More specifically, the controller (112) detects the wafer boundary (208) by segmenting and isolating the wafer boundary in the output image (216) (428), and detects the transfer layer boundary (210) by segmenting and isolating the transfer layer boundary in the output image (216) (430). The boundaries of the transfer layer (206), notch (222), and voids within the transfer layer are segmented using various image processing techniques including image blurring, gradient calculation, high gradient edge detection, and contour calculation from edge detection. When the boundaries are ambiguous or faint, additional processing occurs to improve the edge locations, and in some embodiments where the output image (216) has incomplete or missing edges, boundary closure estimates are made where possible. For example, edge boundary extrapolation may be used when small edge segments are missing, and the detected edges may be smoothed to reduce noise introduced by edge detection techniques. When the controller (112) cannot estimate closure, the output image (216) is flagged for manual inspection.

[0058] After the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212) are detected in the output image (216), the controller (112) analyzes the detected regions for defects (432). More specifically, the controller (112) analyzes at least one of the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212) for defects (432). For example, the controller (112) detects at least one feature of the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212) (434), and quantifies the detected features into quantified metrics (436). Next, the controller (112) compares the quantified metrics with predetermined metrics (438) and, based on the comparison, detects defects in at least one of the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212) (440).

[0059] Specifically, detecting (434) at least one feature among the base (204), wafer boundary (208), transfer layer (206), transfer layer boundary (210), and terrace width (212), and quantifying (436) the detected features into quantified metrics, includes detecting the terrace width (212) and quantifying the detected features of the terrace width (212) into various global and local terrace width statistics. For example, in some embodiments, the terrace width (212) is divided into 12 30° segments around the edge of the wafer (104), and the detected features of the terrace width (212) are quantified into local terrace width statistics based on each segment.

[0060] FIG. 22 illustrates a graphical user interface display (500) for use in correcting the position of an end effector (120) (illustrated in FIG. 12) and / or a wafer (104) relative to a camera (146) (illustrated in FIG. 9) by an image analysis process. The user interface display (500) displays a captured image (502) of the wafer (104) and centering meters (504-508). To correct the position of the end effector (120) and / or the wafer (104) by image analysis, the end effector (120) is positioned below the lowest shroud opening (140) (illustrated in FIG. 5) and at least partially within the field of view (184) (illustrated in FIG. 9) of the camera (146). The camera (146) captures an image (502) of the wafer (104), and the image (502) is transmitted to the controller (112). Subsequently, the controller (112) analyzes the captured image (502) of the wafer (104) to determine whether the wafer (104) is within predefined positioning ranges and is properly centered within the field of view (184). If the controller (112) determines that the wafer is not properly centered within the field of view (184), the position of the wafer (104) and / or the end effector (120) is adjusted based on the determination. After adjustment, a new image is captured, and the controller (112) again determines whether the detected position of the wafer (104) is within the predefined positioning ranges. The image analysis process may be used with or as an alternative to the end effector positioner (174) described above in relation to FIG. 12.

[0061] During operation, in order to determine whether the wafer (104) is properly centered within the field of view (184), the controller (112) captures an image (502) of the wafer (104) and detects the boundary (208) of the wafer (104), as described above in relation to FIGS. 14 through 21. Subsequently, the controller (112) measures the distances on the captured image (502) between the edges (510-516) of the image (502) and the wafer boundary (208).

[0062] For example, regarding positioning along the X-axis, the controller (112) measures a first horizontal distance (X1) from the first side edge (510) of the captured image (502) to the wafer boundary (208), and a second horizontal distance (X2) from the second side edge (512) of the image (502) to the wafer boundary (208). Then, the controller (112) determines a delta X value equal to the difference between the first horizontal distance (X1) and the second horizontal distance (X2). Regarding positioning along the Y-axis, the controller (112) measures a first vertical distance (Y1) from the lowest edge (514) of the image (502) to the wafer boundary (208), and a second vertical distance (Y2) from the top edge (516) of the image (502) to the wafer boundary (208). Next, the controller (112) determines a delta Y value equal to the difference between the first vertical distance (Y1) and the second vertical distance (Y2). With respect to positioning along the Z axis, the controller determines minimum distances X1, X2, Y1, and Y2 to determine the minimum gap of the wafer (104) from the edges (510-516) of the image (502). Next, the controller (112) compares the determined delta X, delta Y, and minimum gap values ​​with predefined tolerance ranges (e.g., as illustrated by the centering meters (504-508)) to determine whether further adjustment of the wafer (104) and / or end effector (120) in the X, Y, or Z directions is required. Color-coded indicators (520) are provided on or near an image (502) on a user interface (500) to indicate to a technician whether the wafer (104) is centered within respective ranges along the X, Y, and Z axes. For example, the indicators (520) change colors based on whether each delta X, delta Y, or minimum gap value is within the corresponding ideal range, within an acceptable range, or within an out-of-bounds range.

[0063] In the embodiment of FIG. 22, the centering meters (504-508) include an X-axis centering meter (504), a Y-axis centering meter (506), and a Z-axis or zoom centering meter (508). Each of the centering meters (504-508) indicates an ideal range, an acceptable range, and an out-of-bounds range. The controller (112) maps the determined delta X, delta Y, and minimum gap values ​​onto the X-axis centering meter (504), the Y-axis centering meter (506), and the Z-axis centering meter (507), respectively. As shown in FIG. 22, the delta Y value for the image (502) is equal to -20 and is within the ideal range of -20 to 20 on the Y-axis centering meter (506). The minimum gap value is equal to 25 and is within the ideal range of 20 to 40 on the Z-axis centering meter (508). The delta X value is equal to 130 and is outside both the ideal range and the acceptable range on the X-axis centering meter (504). Subsequently, the positioning of the wafer (104) and / or the end effector (120) is adjusted (e.g., by a technician or by an automated positioning system communicating with the controller (112)). In particular, the wafer positioning is adjusted based on determined values ​​displayed on the centering meters (504-508). For example, based on the results displayed from the centering meters (504-508) as shown in FIG. 22, the technician may move the wafer (104) to the left of the page as shown in FIG. 22 to reduce the displayed delta X value. After adjustment, another image is captured, and the process is repeated until each of the delta X, delta Y, and minimum gap values ​​is within the acceptable range and / or the ideal range.

[0064] The semiconductor wafer imaging systems described herein image wafers to detect defects within the wafers during the manufacturing process. The imaging system images the wafers after they have been cleaved to detect defects within the wafers formed during the cleaving process. When the semiconductor wafer imaging system detects defects within the wafer, the wafer is removed from the manufacturing process, thereby reducing wafer production costs. The wafers have reflective mirror-like surfaces, and the semiconductor wafer imaging system images the wafer without imaging light sources reflected from the reflective surfaces. Specifically, the semiconductor wafer imaging system includes a black box surrounding a camera and a lighting panel. The black box minimizes reflections in the semiconductor wafer imaging system, and the lighting panel directs diffuse light toward the wafer. The diffuse light is reflected from the wafer toward the camera. The camera detects the reflected diffuse light and does not image the lighting panel because the light generated by the lighting panel is diffused. Therefore, the camera images the wafer rather than the light source, allowing the controller to analyze the wafer for defects and reducing manufacturing costs.

[0065] As used herein, the terms “about,” “substantially,” “essentially,” and “approximately,” when used in relation to ranges of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, are intended to cover variations that may exist in the upper and / or lower limits of the ranges of properties or characteristics, including variations resulting from rounding, measurement methods, or other statistical variations.

[0066] When introducing elements of the present disclosure or its embodiments, articles such as "a," "an," "the," and "said" are intended to imply that there is one or more elements. The terms "comprising," "including," "containing," and "having" are intended to be comprehensive and imply that there may be additional elements other than those listed. The use of terms indicating specific orientations (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require any specific orientation of the item being described.

[0067] Since various modifications to the above configurations and methods may be made without departing from the scope of the present disclosure, all matters included in the above description and illustrated in the accompanying drawings are intended to be interpreted as illustrative rather than restrictive.

Claims

Claim 1 A method for detecting defects on a semiconductor wafer comprises: a step of directing diffuse light toward the semiconductor wafer; a step of reflecting the diffuse light from the semiconductor wafer; a step of detecting the diffuse light with a camera to generate an image of the semiconductor wafer; and a step of analyzing the image to detect defects on the semiconductor wafer, wherein the step of analyzing the image to detect defects on the semiconductor wafer comprises: a step of reflecting the diffuse light toward the semiconductor wafer; a step of detecting defects on the semiconductor wafer by analyzing the image. A step of detecting the wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the above image; and A method comprising the step of detecting the transfer layer boundary of the transfer layer on the semiconductor wafer by segmenting and isolating the transfer layer boundary in the above image. Claim 2 A method according to claim 1, wherein the step of analyzing the image to detect defects on the semiconductor wafer further comprises: a step of analyzing the transfer layer of the semiconductor wafer within the image; and a step of detecting defects within the transfer layer of the semiconductor wafer. Claim 3 A method according to claim 1, wherein the wafer boundary and the transfer layer boundary define a terrace width between them, and the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of analyzing the terrace width to generate terrace width statistics. Claim 4 A method according to claim 1, wherein the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of quantifying the detected defects using quantified metrics. Claim 5 A method for processing a semiconductor wafer comprises: cleaving the semiconductor wafer at a cleaving station; positioning the semiconductor wafer within the field of view of a camera; directing diffuse light toward the semiconductor wafer; reflecting the diffuse light from the semiconductor wafer; detecting the diffuse light with the camera to generate an image of the semiconductor wafer; and analyzing the image to detect defects on the semiconductor wafer, wherein the step of analyzing the image to detect defects on the semiconductor wafer comprises: A step of detecting the wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the above image; and A method comprising the step of detecting the transfer layer boundary of the transfer layer on the semiconductor wafer by segmenting and isolating the transfer layer boundary in the above image. Claim 6 A method according to claim 5, wherein the step of analyzing the image to detect defects on the semiconductor wafer further comprises: a step of analyzing the transfer layer of the semiconductor wafer within the image; and a step of detecting defects within the transfer layer of the semiconductor wafer. Claim 7 A method according to claim 5, wherein the wafer boundary and the transfer layer boundary define a terrace width between them, and the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of analyzing the terrace width to generate terrace width statistics. Claim 8 In claim 5, the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of quantifying the detected defects using quantified metrics. Claim 9 A method for processing a semiconductor wafer using a semiconductor wafer processing system, wherein the semiconductor wafer processing system includes a processing station and a semiconductor wafer imaging station, and the method comprises: a step of processing the semiconductor wafer at the processing station; a step of positioning the semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station; a step of directing diffuse light toward the semiconductor wafer; a step of reflecting the diffuse light from the semiconductor wafer; a step of detecting the diffuse light with a camera to generate an image of the semiconductor wafer; and a step of analyzing the image to detect defects on the semiconductor wafer, wherein the step of analyzing the image to detect defects on the semiconductor wafer comprises A step of detecting the wafer boundary of the semiconductor wafer by segmenting and isolating the wafer boundary in the above image; and A method comprising the step of detecting the transfer layer boundary of the transfer layer on the semiconductor wafer by segmenting and isolating the transfer layer boundary in the above image. Claim 10 A method according to claim 9, wherein the step of analyzing the image to detect defects on the semiconductor wafer further comprises: a step of analyzing the transfer layer of the semiconductor wafer within the image; and a step of detecting defects within the transfer layer of the semiconductor wafer. Claim 11 In claim 9, the wafer boundary and the transfer layer boundary define a terrace width between them, and the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of analyzing the terrace width to generate terrace width statistics. Claim 12 In claim 9, the step of analyzing the image to detect defects on the semiconductor wafer further comprises the step of quantifying the detected defects using quantified metrics. Claim 13 A method for processing a semiconductor wafer using a semiconductor wafer processing system, wherein the semiconductor wafer processing system comprises a first manufacturing line, a second manufacturing line, and a semiconductor wafer imaging station positioned within a common location where the first and second manufacturing lines intersect, and wherein the first and second manufacturing lines each comprise processing stations for processing the semiconductor wafer, and the method comprises: i) processing a first semiconductor wafer at a processing station of the first manufacturing line; ii) positioning the first semiconductor wafer within the field of view of a camera of the semiconductor wafer imaging station; iii) directing diffuse light toward the first semiconductor wafer; iv) reflecting the diffuse light from the first semiconductor wafer; v) detecting the diffuse light with a camera to generate an image of the first semiconductor wafer; vi) analyzing the image to detect defects on the first semiconductor wafer; vii) processing a second semiconductor wafer at a processing station of the second manufacturing line; and viii) repeating steps ii) to vi) to image the second semiconductor wafer. Claim 14 In claim 13, the step of detecting defects on the first semiconductor wafer by analyzing the image further comprises: a step of detecting the wafer boundary of the first semiconductor wafer by segmenting and isolating the wafer boundary in the image; and a step of detecting the transfer layer boundary of the transfer layer on the first semiconductor wafer by segmenting and isolating the transfer layer boundary in the image. Claim 15 In claim 14, the step of analyzing the image to detect defects on the first semiconductor wafer further comprises: a step of analyzing the transfer layer of the first semiconductor wafer within the image; and a step of detecting defects within the transfer layer of the first semiconductor wafer. Claim 16 In claim 14, the wafer boundary and the transfer layer boundary define a terrace width between them, and the step of analyzing the image to detect defects on the first semiconductor wafer further comprises the step of analyzing the terrace width to generate terrace width statistics. Claim 17 In claim 14, the step of detecting defects on the first semiconductor wafer by analyzing the image further comprises the step of quantifying the detected defects using quantified metrics.

Images