Semiconductor devices having peripheral circuit regions

Abstract

A semiconductor device according to an embodiment of the present invention comprises a first structure including a first substrate, wherein the first substrate includes a memory cell region and a first peripheral circuit region, and a second structure including a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate includes a core circuit region and a second peripheral circuit region, and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure. The first peripheral circuit region includes peripheral active patterns, a peripheral bit line extending in the vertical direction and contacting the peripheral active patterns, peripheral gate electrodes that overlap the peripheral active patterns in the vertical direction, and a peripheral wiring structure electrically connected to at least one of the peripheral bit line and the peripheral gate electrodes. The peripheral through-vias are electrically connected to the peripheral wiring structure.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device comprising a peripheral circuit region. Background Technology

[0002] As demands for high performance, high speed, and / or multifunctionality in semiconductor devices increase, the integration density of semiconductor devices is rising. In manufacturing semiconductor devices with fine patterns to meet this trend of high integration, it is required to implement patterns with minute widths or minute spacing. Furthermore, it is required to reduce the size of the semiconductor devices. The problem to be solved

[0003] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device including a peripheral wiring structure. means of solving the problem

[0004] A semiconductor device according to exemplary embodiments may include: a first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; a second structure comprising a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate comprises a core circuit region and a second peripheral circuit region; and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure. The memory cell region may include cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; a cell bit line that extends in the vertical direction and contacts the cell active patterns; cell gate electrodes that overlap the cell active patterns in the vertical direction and extend in a second horizontal direction that intersects the first horizontal direction; and a cell wiring structure disposed on the cell active patterns, the cell bit line, and the cell gate electrodes and is electrically connected to at least one of the cell bit line and the cell gate electrodes. The first peripheral circuit region may include peripheral active patterns that extend in the first horizontal direction; a peripheral bit line that extends in the vertical direction and contacts the peripheral active patterns; It may include peripheral gate electrodes that overlap the peripheral active patterns in the vertical direction and extend in the second horizontal direction; and a peripheral wiring structure disposed on the peripheral active patterns, the peripheral bit line and the peripheral gate electrodes and electrically connected to at least one of the peripheral bit line and the peripheral gate electrodes. The peripheral through-vias may be electrically connected to the peripheral wiring structure.

[0005] A semiconductor device according to exemplary embodiments may include: a first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; a second structure comprising a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate comprises a core circuit region and a second peripheral circuit region; and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure. The memory cell region may include cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; a cell bit line that extends in the vertical direction and contacts the cell active patterns; cell gate electrodes that overlap the cell active patterns in the vertical direction and extend in a second horizontal direction that intersects the first horizontal direction; and a cell wiring structure disposed on the cell active patterns, the cell bit line and the cell gate electrodes and electrically connected to at least one of the cell bit line and the cell gate electrodes. The first peripheral circuit region may include a peripheral wiring structure disposed at the same level as the cell wiring structure. The cell wiring structure may include cell wiring layers that are spaced apart and stacked in the vertical direction and cell vias connecting the cell wiring layers. The peripheral wiring structure may include peripheral wiring layers and peripheral vias that are placed at the same level as the cell wiring layers and the cell vias, respectively. The horizontal width of the peripheral wiring layers may be greater than the horizontal width of the cell wiring layers. The peripheral through-vias may be electrically connected to the peripheral wiring structure.

[0006] A semiconductor device according to exemplary embodiments may include: a first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; a second structure comprising a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate comprises a core circuit region and a second peripheral circuit region; and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure. The memory cell region may include cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; a cell bit line that extends in the vertical direction and contacts the cell active patterns; cell gate electrodes that overlap the cell active patterns in the vertical direction and extend in a second horizontal direction that intersects the first horizontal direction; and a cell wiring structure disposed on the cell active patterns, the cell bit line, and the cell gate electrodes and is electrically connected to at least one of the cell bit line and the cell gate electrodes. The first peripheral circuit region may include peripheral active patterns that extend in the first horizontal direction; a peripheral bit line that extends in the vertical direction and contacts the peripheral active patterns; It may include peripheral gate electrodes that overlap the peripheral active patterns in the vertical direction and extend in the second horizontal direction; and a peripheral wiring structure disposed on the peripheral active patterns, the peripheral bit line, and the peripheral gate electrodes and electrically connected to at least one of the peripheral bit line and the peripheral gate electrodes. The second peripheral circuit region may include a peripheral transistor on the second substrate; a lower wiring structure disposed on the peripheral transistor and connected to the peripheral transistor and the peripheral through-via; an upper wiring structure on the lower wiring structure; and an input / output pad on the upper wiring structure.The above peripheral through-vias can be electrically connected to the above peripheral wiring structure.

[0007] A method for manufacturing a semiconductor device according to exemplary embodiments may include forming a first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; bonding a preliminary structure comprising a peripheral transistor on the first structure; forming a cell penetration via and a peripheral penetration via that penetrate a second substrate of the preliminary structure in a vertical direction; forming a lower wiring structure and an upper wiring structure connected to the cell penetration via and the peripheral penetration via on the second substrate; and forming an input / output pad on the lower wiring structure and the upper wiring structure.

[0008] Forming the first structure may include forming a cell transistor on the first substrate; forming an information storage structure connected to the cell transistor on the first substrate; and forming a cell wiring structure and a peripheral wiring structure on the cell transistor and the information storage structure.

[0009] The cell wiring structure is formed on the memory cell region, and the peripheral wiring structure can be formed on the first peripheral circuit region.

[0010] The above peripheral wiring structure is formed simultaneously with the cell wiring structure and can be placed at the same level as the cell wiring structure.

[0011] The cell wiring structure is electrically connected to the cell through-via, and the peripheral wiring structure can be electrically connected to the peripheral through-via.

[0012] The cell transistor may include cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; cell gate electrodes that surround the cell active patterns and extend in a second horizontal direction intersecting the first horizontal direction; and cell gate dielectric layers between the cell active patterns and the cell gate electrodes.

[0013] The above peripheral penetrating via is formed simultaneously with the cell penetrating via and can be placed at the same level as the cell penetrating via.

[0014] The first structure may further include a first bonding layer on the first substrate, and the second structure may further include a second bonding layer disposed below the second substrate and bonded to the first bonding layer.

[0015] The cell-penetrating via and the peripheral-penetrating via can penetrate the bonding surface between the first bonding layer and the second bonding layer.

[0016] The above lower wiring structure can electrically connect the peripheral transistor to the cell through-via and the peripheral through-via. Effects of the invention

[0017] According to embodiments of the technical concept of the present invention, since a peripheral wiring structure is disposed at the same level as a cell wiring structure, the number of wiring layers of a semiconductor device can be reduced and the size of the semiconductor device can be reduced. In addition, since the horizontal width of the peripheral wiring layers of the peripheral wiring structure is formed to be relatively large, the resistance of the peripheral wiring structure can be reduced.

[0018] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0019] FIG. 1 is a conceptual perspective view of a semiconductor device according to an exemplary embodiment. FIG. 2 is a circuit diagram of a memory cell in a memory cell region according to an exemplary embodiment. Figure 3 is a plan view of the first structure. Figure 4 is a plan view of the first memory cell region of the first structure. Figure 5 is a vertical cross-sectional view along line I-I' of the semiconductor device shown in Figure 3. Figure 6 is a partial enlarged view of the semiconductor device shown in Figure 5. Figure 7 is a vertical cross-sectional view along line III-III' of the memory cell region shown in Figure 4. FIG. 8 is a vertical cross-sectional view of a peripheral circuit region of a semiconductor device according to an exemplary embodiment. FIG. 9 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 10a to 16b are plan views and vertical cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 17 and 18 are vertical cross-sectional views of semiconductor devices according to exemplary embodiments. FIGS. 19 and FIGS. 20 are vertical cross-sectional views of semiconductor devices according to exemplary embodiments. Specific details for implementing the invention

[0020] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0021] FIG. 1 is a conceptual perspective view of a semiconductor device according to an exemplary embodiment.

[0022] Referring to FIG. 1, a semiconductor device (1) according to one embodiment may include a first structure (ST1) and a second structure (ST2) that overlaps vertically with the first structure (ST1). The second structure (ST2) may be disposed on the first structure (ST1).

[0023] In one embodiment, the first structure (ST1) may be a first chip structure including memory cells (MC), and the second structure (ST2) may be a second chip structure including peripheral circuits capable of operating the memory cells (MC). The first structure (ST1) and the second structure (ST2) may be formed by bonding through a bonding process such as a wafer bonding process. Accordingly, the first structure (ST1) may be bonded to the second structure (ST2) in contact with it.

[0024] The semiconductor device (1) may include a plurality of banks (BA) and a peripheral circuit region (PERI). The peripheral circuit region (PERI) may include a first peripheral circuit region (PR1) within the first structure (ST1) and a second peripheral circuit region (PR2) within the second structure (ST2). The peripheral circuit region (PERI) may be a peripheral circuit region where peripheral circuits for input / output of data or commands, or input of power / ground, are arranged.

[0025] Each of the plurality of banks (BA) may include a first bank area (BA1) within the first structure (ST1) and a second bank area (BA2) within the second structure (ST2).

[0026] The first bank region (BA1) within the first structure (ST1) may include memory cell regions (MR1, MR2) (see FIG. 5). The memory cell regions (MR1, MR2) may be arranged along the X direction and the Y direction. The X direction and the Y direction may be perpendicular to each other. The X direction and the Y direction may be referred to as horizontal directions, and the Z direction may be referred to as vertical directions.

[0027] The second bank region (BA2) within the second structure (ST2) may include core circuit regions (CR1, CR2) (see FIG. 5). The core circuit regions (CR1, CR2) may be arranged along the X direction and the Y direction. The core circuit regions (CR1, CR2) may overlap with the memory cell regions (MR1, MR2) in the vertical direction (Z). The core circuit regions (CR1, CR2) may include a sense amplifier and a sub-wordline driver, etc.

[0028] The first peripheral circuit area (PR1) and the second peripheral circuit area (PR2) may be peripheral circuit areas where peripheral circuits for input / output of data or commands, or input of power / ground are arranged, and may include a control circuit capable of controlling the sense amplifier and sub-wordline driver.

[0030] FIG. 2 is a circuit diagram of a memory cell in a memory cell region according to an exemplary embodiment.

[0031] Referring to FIG. 2, the memory cell regions (MR1, MR2) may include memory cells (MC) arranged along the X direction and the Y direction, word lines (WL) connected to the memory cells (MC) and extending in the Y direction, and bit lines (BL) connected to the memory cells (MC) and extending in the vertical direction.

[0032] Each of the above memory cells (MC) may include a cell transistor (cTR) and an information storage structure (DS) capable of storing information. In a memory such as a DRAM, the information storage structure (DS) may be a cell capacitor capable of storing information. Adjacent information storage structures (DS) may share a plate electrode (PP). For example, the plate electrode (PP) may extend in a vertical direction and be electrically connected to the information storage structures (DS).

[0034] FIG. 3 is a plan view of a first structure. FIG. 4 is a plan view of a first memory cell region of the first structure. FIG. 4 illustrates a plan view of the first memory cell region (MR1) of the first bank region (BA1) shown in FIG. 3. FIG. 5 is a vertical cross-sectional view along line I-I' of the semiconductor device shown in FIG. 3. FIG. 5 also illustrates a vertical cross-sectional view along line II-II' of the first memory cell region (MR1) shown in FIG. 4. FIG. 6 are enlarged views of a portion of the semiconductor device shown in FIG. 5. FIG. 6 may correspond to regions A and B of FIG. 5. FIG. 7 is a vertical cross-sectional view along line III-III' of the memory cell region shown in FIG. 4. FIG. 8 is a vertical cross-sectional view of a peripheral circuit region of the semiconductor device according to an exemplary embodiment. FIG. 8 illustrates structures corresponding to FIG. 7 that are placed on the peripheral circuit regions (PR1, PR2).

[0035] Referring to FIGS. 3 to 8, the semiconductor device (1) may include a first structure (ST1) and a second structure (ST2) that overlaps vertically with the first structure (ST1). For example, the semiconductor device (1) may have a peri-on-cell (POC) structure, and the second structure (ST2) may be placed on the first structure (ST1).

[0036] The first structure (ST1) may include memory cell regions (MR1, MR2) and a first peripheral circuit region (PR1). The memory cell regions (MR1, MR2) may include a first memory cell region (MR1) and a second memory cell region (MR2). The first peripheral circuit region (PR1) may be spaced horizontally apart from the memory cell regions (MR1, MR2) and may be positioned between the memory cell regions (MR1, MR2). As described below, the components of the first peripheral circuit region (PR1) may be positioned at the same level as the corresponding components of the memory cell regions (MR1, MR2). The first peripheral circuit region (PR1) may have the same or similar structure as the memory cell regions (MR1, MR2).

[0037] Memory cell regions (MR1, MR2) may include a cell transistor (cTR) and an information storage structure (DS) disposed on a substrate (3). The cell transistor (cTR) and the information storage structure (DS) may constitute a memory cell (MC) as described with reference to FIG. 2. The information storage structure (DS) may be a cell capacitor capable of storing information in a memory such as a DRAM.

[0038] The first structure (ST1) may further include a first substrate (3) and cell active patterns (9c) and peripheral active patterns (9p) disposed on the first substrate (3). The disposed cell active patterns (9c) may be disposed on memory cell regions (MR1, MR2), and the peripheral active patterns (9p) may be disposed on a first peripheral circuit region (PR1).

[0039] The cell active patterns (9c) and the peripheral active patterns (9p) may be formed of a semiconductor material that can be used as a channel region of a transistor. For example, each of the cell active patterns (9c) and the peripheral active patterns (9p) may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may comprise silicon, germanium, or silicon-germanium. Each of the cell active patterns (9c) and the peripheral active patterns (9p) may comprise single-crystal silicon.

[0040] In one embodiment, the cell active patterns (9c) and the peripheral active patterns (9p) may include at least one of an oxide semiconductor, for example, hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), and indium-tin-zinc oxide (ITZO).

[0041] In another example, the cell active patterns (9c) and the peripheral active patterns (9p) may comprise a two-dimensional material (2D material) in which atoms form a predetermined crystal structure and can form a channel of a transistor. The two-dimensional material layer may comprise at least one of a TMD material layer (Transition Metal Dichalcogenide material layer), a black phosphorous material layer, and an hBN material layer (hexagonal Boron-Nitride material layer). For example, the two-dimensional material layer may comprise at least one of BiOSe, Crl, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials capable of forming a two-dimensional material.

[0042] Each of the above cell active patterns (9c) may include a first source / drain region (cSD1) and a second source / drain region (cSD2) spaced apart from each other in the X direction, and a cell channel region (cCH) between the first and second source / drain regions (cSD1, cSD2).

[0043] The first structure (ST1) may include cell gate electrodes (18c) that overlap perpendicularly with the cell channel regions (cCH), and cell gate dielectric layers (15c) between the cell gate electrodes (18c) and the cell channel regions (cCH). The cell gate electrodes (18c) may be stacked and spaced apart from each other in the vertical direction (Z). Each of the cell gate electrodes (18c) may extend in the Y direction perpendicular to the X direction, surrounding a corresponding cell channel region (cCH) among the cell channel regions (cCH).

[0044] The cell transistor (cTR) described above may include the cell channel region (cCH), the first and second source / drain regions (cSD1, cSD2), the cell gate dielectric layer (15c), and the cell gate electrode (18c).

[0045] Each of the above peripheral active patterns (9p) may include a first source / drain region (pSD1) and a second source / drain region (pSD2) spaced apart from each other in the X direction, and a peripheral channel region (pCH) between the first and second source / drain regions (pSD1, pSD2). At least one of the above peripheral active patterns (9p) may be placed at the same level as at least one of the cell active patterns (9c).

[0046] The first structure (ST1) may include peripheral gate electrodes (18p) that overlap perpendicularly with the peripheral channel regions (pCH), and peripheral gate dielectric layers (15p) between the peripheral gate electrodes (18p) and the peripheral channel regions (pCH). The peripheral gate electrodes (18p) may be stacked and spaced apart from each other in the vertical direction (Z). Each of the peripheral gate electrodes (18p) may extend in the Y direction perpendicular to the X direction, surrounding a corresponding peripheral channel region (pCH) among the peripheral channel regions (pCH). At least one of the peripheral gate electrodes (18p) may be placed at the same level as at least one of the cell gate electrodes (18c).

[0047] The cell gate electrodes (18c) and the peripheral gate electrodes (18p) may include a conductive material, and the conductive material may include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, cobalt, aluminum, ruthenium, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0048] The cell gate dielectric layer (15c) and the peripheral gate dielectric layer (15p) may comprise at least one of silicon oxide, silicon nitride, a low-dielectric (low-k) material, and a high-dielectric (high-k) material. The high-dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide, and the low-dielectric material may refer to a dielectric material having a dielectric constant lower than that of silicon oxide. The high-dielectric material may be, for example, a metal oxide or a metal oxide nitride. The high dielectric constant material may be, for example, any one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3). The cell gate dielectric layer (140) may be formed as a single layer or multiple layers of the aforementioned materials.

[0049] The information storage structure (DS) described above may be an information storage structure (38c) comprising a first electrode (30c), a dielectric layer (32c), and a second electrode (36c). The first electrode (30c) may be connected to a corresponding second source / drain region (cSD2) among the second source / drain regions (cSD2). The first electrode (30c) may have a columnar shape extending in the X direction. The dielectric layer (32c) may extend between the first electrode (30c) and the second electrode (36c). The second electrode (36c) may cover the dielectric layer (32c). The second electrode (36c) may include a first electrode material layer (34) in contact with the dielectric layer (32c) and a second electrode material layer (35) in contact with the first electrode material layer (34). The second electrodes (36c) of the information storage structures (DS) may be plate electrodes (PP) connected to each other.

[0050] In the information storage structures (DS) above, the lower surface of each of the second electrodes (36c) may be positioned at a level lower than the lowest cell transistor among the cell transistors (cTR), and the upper surface of each of the second electrodes (36c) may be positioned at a level higher than the highest cell transistor among the cell transistors (cTR). Each of the second electrodes (36c) may extend in the Y direction.

[0051] The memory cells (MC), including the cell transistors (cTR) and the information storage structures (DS), can be arranged three-dimensionally along the vertical direction (Z), the X direction, and the Y direction, which are perpendicular to each other.

[0052] The first structure (ST1) may further include structures (30p, 32p, 36p) disposed on the first peripheral circuit region (PR1). The structures (30p, 32p, 36p) may include a first electrode (30p), a dielectric layer (32p), and a second electrode (36p).

[0053] The first electrode (30p) may be connected to a corresponding second source / drain region (pSD2) among the second source / drain regions (pSD2). The first electrode (30p) may have a columnar shape extending in the X direction. The dielectric layer (32p) may extend between the first electrode (30p) and the second electrode (36p). The second electrode (36p) may cover the dielectric layer (32p). The second electrode (36p) may include a first electrode material layer (34) in contact with the dielectric layer (32p) and a second electrode material layer (35) in contact with the first electrode material layer (34).

[0054] In one embodiment, a memory cell (MC) may be disposed on the first peripheral circuit region (PR1). For example, the peripheral channel region (pCH), the first and second source / drain regions (pSD1, pSD2), the peripheral gate dielectric layer (15p), and the peripheral gate electrode (18p) may function as a cell transistor (cTR). The structures (30p, 32p, 36p) may be information storage structures (DS) described with reference to FIG. 2. The second electrodes (36p) of the information storage structures (DS) may be plate electrodes (PP) connected to each other.

[0055] In one embodiment, a CMOS transistor may be placed on the first peripheral circuit region (PR1). For example, the first source / drain regions (pSD1) and the second source / drain regions (pSD2) of the peripheral active patterns (9p) may be doped with N-type impurities or P-type impurities. The CMOS transistor may be used in a peripheral circuit for input / output of data or commands, or for input of power / ground.

[0056] The first structure (ST1) may further include cell bit lines (27c) that are positioned on memory cell regions (MR1, MR2) and are in contact with the cell active patterns (9c). The cell bit lines (27c) may extend in the vertical direction (Z) and may be spaced apart from each other in the X and Y directions. Each of the cell bit lines (27c) may be in contact with the first source / drain regions (cSD1) of the cell active patterns (9c). The cell bit lines (27c) may correspond to the bit lines (BL) described with reference to FIG. 2.

[0057] The first structure (ST1) may further include peripheral bit lines (27p) that are positioned on the first peripheral circuit region (PR1) and are in contact with the peripheral active patterns (9p). The peripheral bit lines (27p) may extend in the vertical direction (Z) and may be spaced apart from each other in the X and Y directions. Each of the peripheral bit lines (27p) may be in contact with the first source / drain regions (pSD1) of the peripheral active patterns (9p).

[0058] Each of the cell bit lines (27c) and the peripheral bit lines (27p) may include a pillar pattern (29) and a conductive liner (28) covering the side and bottom surfaces of the pillar pattern (29). The conductive liner (28) may include at least one of doft polysilicon and metal nitride.

[0059] The first structure (ST1) may further include an insulating layer (4) disposed within the first substrate (3). The cell bit lines (27c) and the peripheral bit lines (27p) may partially penetrate the insulating layer (4), and the lower ends of the cell bit lines (27c) and the peripheral bit lines (27p) may be disposed at a level lower than the upper surface of the insulating layer (4).

[0060] The first structure (ST1) may further include an interlayer insulating layer (21), a first capping insulating layer (24), a first insulating layer (41), a second capping insulating layer (44), a second insulating layer (47), and a third capping insulating layer (50) sequentially disposed on the first substrate (3). The interlayer insulating layer (21) may cover cell transistors (cTR) on memory cell regions (MR1, MR2). The interlayer insulating layer (21) may also be disposed on the first peripheral circuit region (PR1) and may cover components corresponding to the cell transistors (cTR).

[0061] The first capping insulation layer (24) may be disposed on the interlayer insulation layer (21), and a portion of the cell bit line (27c) and the information storage structure (38c) may penetrate the first capping insulation layer (24). For example, the upper surface of the cell bit line (27c) and the upper surface of the information storage structure (38c) may be co-surfaced with the first capping insulation layer (24).

[0062] The interlayer insulation layer (21), the first capping insulation layer (24), the first insulation layer (41), the second capping insulation layer (44), the second insulation layer (47), and the third capping insulation layer (50) may include at least one of an insulating material, for example, silicon nitride, silicon oxynitride, and silicon oxycarbide. The first capping insulation layer (24), the second capping insulation layer (44), and the third capping insulation layer (50) may include silicon nitride.

[0063] The first structure (ST1) may further include a first cell wiring layer (42c), a cell via (46c), and a second cell wiring layer (48c) disposed on the memory cell regions (MR1, MR2). The first cell wiring layer (42c) may be disposed on a first insulating layer (41) and may be covered by a second capping insulating layer (44). The second cell wiring layer (48c) may be disposed on a second insulating layer (47) and may be covered by a third capping insulating layer (50). The cell via (46c) may extend in a vertical direction and may connect at least one of the first cell wiring layers (42c) to the corresponding second cell wiring layer (48c). A first insulating layer (41), a first cell wiring layer (42c), a second capping insulating layer (44), a cell via (46c), a second insulating layer (47), a second cell wiring layer (48c), and a third capping insulating layer (50) can form a cell wiring structure (L1c). The cell wiring structure (L1c) can be electrically connected to at least one of cell gate electrodes (18c) and cell bit lines (27c).

[0064] The first structure (ST1) may further include cell contact structures (39c, 40c) disposed on the memory cell regions (MR1, MR2). The cell contact structures (39c, 40c) may connect the cell transistors (cTR) to the cell wiring structure (L1c). For example, the cell contact structures (39c) may connect at least one of the cell bit lines (27c) to the corresponding first cell wiring layer (42c). The cell contact structures (40c) may connect at least one of the cell gate electrodes (18c) to the corresponding first cell wiring layer (42c).

[0065] The first structure (ST1) may further include a first peripheral wiring layer (42p), a peripheral via (46p), and a second peripheral wiring layer (48p) disposed on the first peripheral circuit area (PR1). The first peripheral wiring layer (42p) may be disposed on a first insulating layer (41) and may be covered by a second capping insulating layer (44). The second peripheral wiring layer (48p) may be disposed on a second insulating layer (47) and may be covered by a third capping insulating layer (50). The peripheral via (46p) may extend in a vertical direction and may connect at least one of the first peripheral wiring layers (42p) to the corresponding second peripheral wiring layer (48p). The first insulating layer (41), the first peripheral wiring layer (42p), the second capping insulating layer (44), the peripheral via (46p), the second insulating layer (47), the second peripheral wiring layer (48p), and the third capping insulating layer (50) can form a peripheral wiring structure (L1p). The peripheral wiring structure (L1p) can be electrically connected to at least one of peripheral gate electrodes (18p) and peripheral bit lines (27p).

[0066] The peripheral wiring structure (L1p) may be placed at the same level as the cell wiring structure (L1c). For example, the first peripheral wiring layer (42p), the peripheral via (46p), and the second peripheral wiring layer (48p) may be placed at the same level as the first cell wiring layer (42c), the cell via (46c), and the second cell wiring layer (48c), respectively. The peripheral wiring structure (L1p) may be used to transmit an input / output signal or a power / ground signal to a transistor composed of the peripheral channel region (pCH), the first and second source / drain regions (pSD1, pSD2), the peripheral gate dielectric layer (15p), and the peripheral gate electrode (18p). In one embodiment, the peripheral wiring structure (L1p) may be electrically connected to the cell wiring structure (L1c) and may be used to transmit an input / output signal or a power / ground signal to a cell transistor (cTR).

[0067] Compared to the case where dummy lines are placed at the same level as the cell wiring structure (L1c) on the first peripheral circuit region (PR1), in the embodiments of the present disclosure where the peripheral wiring structure (L1p) is placed at the same level as the cell wiring structure (L1c), the number of wiring layers of the semiconductor device (1) can be reduced. Accordingly, the size of the semiconductor device (1) can be reduced, and a more miniaturized semiconductor device (1) can be realized.

[0068] Referring to FIGS. 3, 5, and 6, the horizontal widths of the first peripheral wiring layer (42p) and the second peripheral wiring layer (48p) according to embodiments of the present disclosure may each be larger than the horizontal widths of the first cell wiring layer (42c) and the second cell wiring layer (48c). For example, as shown in FIG. 3, the first cell wiring layer (42c) and the second cell wiring layer (48c) may have a first horizontal width (W1), and the first peripheral wiring layer (42p) and the second peripheral wiring layer (48p) may have a second horizontal width (W2) that is larger than the first horizontal width (W1). Thus, the resistance of the peripheral wiring structure (L1p) can be reduced, and the RC delay of the semiconductor device (1) can be reduced. In one embodiment, the horizontal width of the peripheral via (46p) may be larger than the horizontal width of the cell via (46c).

[0069] The first structure (ST1) may further include peripheral contact structures (39p, 40p) disposed on the first peripheral circuit region (PR1). The peripheral contact structures (39p, 40p) may connect a transistor, composed of the peripheral active pattern (9p), the peripheral gate dielectric layer (15p), and the peripheral gate electrode (18p), to the peripheral wiring structure (L1p). For example, the peripheral contact structures (39p) may connect at least one of the peripheral bit lines (27p) to the corresponding first peripheral wiring layer (42p). The peripheral contact structures (40p) may connect at least one of the peripheral gate electrodes (18p) to the corresponding first peripheral wiring layer (42p).

[0070] The first structure (ST1) may further include a first bonding layer (53) disposed on a cell wiring structure (L1c) and a surrounding wiring structure (L1p). The upper surface of the first bonding layer (53) may correspond to a bonding surface (J) between the first structure (ST1) and the second structure (ST2).

[0071] The second structure (ST2) may include core circuit regions (CR1, CR2) and a second peripheral circuit region (PR2). The core circuit regions (CR1, CR2) may include a first core circuit region (CR1) and a second core circuit region (CR2) that are spaced apart from each other in a horizontal direction. The second peripheral circuit region (PR2) may be spaced apart from the core circuit regions (CR1, CR2) in a horizontal direction and may be positioned between the core circuit regions (CR1, CR2). The core circuit regions (CR1, CR2) may overlap vertically with memory cell regions (MR1, MR2), and the second peripheral circuit region (PR2) may overlap vertically with the first peripheral circuit region (PR1).

[0072] The second structure (ST2) may further include a second substrate (102) comprising peripheral channel regions (pCH), and a device isolation region (105) that defines the peripheral channel regions (pCH) on the second substrate (102). The device isolation region (105) may define the sides of the peripheral channel regions (pCH). The device isolation region (105) may be formed of an insulating material.

[0073] The second substrate (102) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate (102) may include single-crystal silicon.

[0074] The second structure (ST2) may further include a peripheral circuit transistor (pTR) disposed on the second substrate (102).

[0075] The peripheral circuit transistor (pTR) may include peripheral source / drain regions (pSD) formed within the peripheral channel region (pCH), a peripheral channel region (pCH) between the peripheral source / drain regions (pSD), and peripheral gates (pGI, pGE) on the peripheral channel region (pCH). The peripheral gates (pGI, pGE) may include a peripheral gate dielectric layer (pGI) and a peripheral gate electrode (pGE) on the peripheral gate dielectric layer (pGI). The peripheral circuit transistors (pTR) may be disposed on core circuit regions (CR1, CR2) and a second peripheral circuit region (PR2).

[0076] As illustrated in FIG. 5, according to embodiments of the present disclosure, a first peripheral circuit region (PR1) may be placed within a first structure (ST1) in which memory cell regions (MR1, MR2) are placed. Accordingly, compared to a semiconductor device in which the first peripheral circuit region (PR1) is not placed in the first structure (ST1), the area of ​​the peripheral circuit regions (PR1, PR2) can be reduced by the area of ​​the first peripheral circuit region (PR1). Therefore, the size of the semiconductor device (1) can be reduced.

[0077] The second structure (ST2) may further include a second bonding layer (110) disposed below the second substrate (102). The lower surface of the second bonding layer (110) may correspond to a bonding surface (J) between the first structure (ST1) and the second structure (ST2). For example, the second bonding layer (110) may be bonded to the first bonding layer (53).

[0078] The second structure (ST2) may include contacts (126), wiring layers (129), vias (132), and wiring layers (135) disposed on the second substrate (102). The contacts (126) may extend in a vertical direction and may be connected to the peripheral source / drain regions (pSD). The wiring layers (129) may be disposed on the peripheral circuit transistor (pTR) and may be electrically connected to the peripheral circuit transistor (pTR). For example, at least one of the wiring layers (129) may be connected to the peripheral source / drain regions (pSD). The wiring layers (135) may be disposed on the wiring layers (129), and the vias (132) may connect the wiring layers (129) and the wiring layers (135).

[0079] Wiring layers (129), vias (132), and wiring layers (135) placed on core circuit regions (CR1, CR2) can form a first lower wiring structure (L2c). Wiring layers (129), vias (132), and wiring layers (135) placed on a second peripheral circuit region (PR2) can form a second lower wiring structure (L2p). For example, the first lower wiring structure (L2c) can be electrically connected to a peripheral circuit transistor (pTR) placed on the core circuit regions (CR1, CR2), and the second lower wiring structure (L2p) can be electrically connected to a peripheral circuit transistor (pTR) placed on the second peripheral circuit region (PR2).

[0080] The semiconductor device (1) may further include a cell through-via (120c) and a peripheral through-via (120p). The cell through-via (120c) penetrates the second substrate (102) in a vertical direction and may be electrically connected to the first lower wiring structure (L2c). The peripheral through-via (120p) penetrates the second substrate (102) in a vertical direction and may be electrically connected to the second lower wiring structure (L2p). The cell through-via (120c) and the peripheral through-via (120p) may have a tapered shape. The horizontal widths of the cell through-via (120c) and the peripheral through-via (120p) may change as they approach the first structure (ST1). For example, the horizontal widths of the cell-penetrating via (120c) and the peripheral-penetrating via (120p) may decrease as they get closer to the first structure (ST1).

[0081] In one embodiment, the cell through-via (120c) and the peripheral through-via (120p) may penetrate the bonding surface (J). For example, the cell through-via (120c) may penetrate the first bonding layer (53) and the second bonding layer (110) in a vertical direction and be electrically connected to the cell wiring structure (L1c). The cell through-via (120c) may come into contact with the second cell wiring layer (48c) of the cell wiring structure (L1c). The peripheral through-via (120p) may penetrate the first bonding layer (53) and the second bonding layer (110) in a vertical direction and be electrically connected to the peripheral wiring structure (L1p). The peripheral through-via (120p) may come into contact with the second peripheral wiring layer (48p) of the peripheral wiring structure (L1p).

[0082] The second structure (ST2) may further include insulating spacers (123) covering the sides of the cell through-via (120c) and the peripheral through-via (120p). The insulating spacers (123) may electrically insulate the cell through-via (120c) and the peripheral through-via (120p) from the second substrate (102).

[0083] The second structure (ST2) may further include connecting vias (138), insulating spacers (141), vias (144), and wiring layers (147) on the first lower wiring structure (L2c) and the second lower wiring structure (L2p). The connecting vias (138) may extend vertically in contact with the first lower wiring structure (L2c) and the second lower wiring structure (L2p). The insulating spacers (141) may cover the sides of the connecting vias (138).

[0084] The wiring layers (147) may be composed of multiple layers, and the vias (144) may electrically connect the wiring layers (147) spaced apart in the vertical direction. The vias (144) and wiring layers (147) placed on the core circuit regions (CR1, CR2) may form a first upper wiring structure (L3c). The vias (144) and wiring layers (147) placed on the second peripheral circuit region (PR2) may form a second upper wiring structure (L3p). The first upper wiring structure (L3c) and the second upper wiring structure (L3p) may be electrically connected to the first lower wiring structure (L2c) and the second lower wiring structure (L2p), respectively, through the connecting vias (138).

[0085] The second structure (ST2) may further include an interlayer insulating layer (150) and vias (153). The interlayer insulating layer (150) may cover the second substrate (102), the peripheral circuit transistor (pTR), the first lower wiring structure (L2c), the second lower wiring structure (L2p), the first upper wiring structure (L3c), and the second upper wiring structure (L3p). The vias (153) may be placed on and in contact with the first upper wiring structure (L3c) and the second upper wiring structure (L3p).

[0086] The second structure (ST2) may further include first input / output pads (156c) and second input / output pads (156p) on the interlayer insulation layer (150). The first input / output pads (156c) may be placed on the core circuit regions (CR1, CR2) and may be electrically connected to the cell wiring structure (L1c) through the first upper wiring structure (L3c), the first lower wiring structure (L2c), and the cell through-via (120c). The second input / output pads (156p) may be placed on the second peripheral circuit region (PR2) and may be electrically connected to the peripheral wiring structure (L1p) through the second upper wiring structure (L3p), the second lower wiring structure (L2p), and the peripheral through-via (120p).

[0087] According to embodiments of the present disclosure, as described above, the peripheral wiring structure (L1p) can be placed at the same level as the cell wiring structure (L1c) on the first peripheral circuit area (PR1). Accordingly, the peripheral wiring structure (L1p) can function as a power delivery network and can reduce the power delivery path from the second input / output pads (156p) to the components (9p, 15p, 18p) on the first peripheral circuit area (PR1).

[0089] FIG. 9 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0090] Referring to FIG. 9, a method for manufacturing a semiconductor device according to an exemplary embodiment may include forming a first structure (S100), bonding a preliminary structure including a peripheral transistor on the first structure (S140), forming a cell through-via and a peripheral through-via penetrating a second substrate of the preliminary structure (S150), forming a lower wiring structure and an upper wiring structure connected to the cell through-via and the peripheral through-via (S160), and forming an input / output pad on the lower wiring structure and the upper wiring structure (S170). Forming the first structure (S100) may include forming a cell transistor on a first substrate (S110), forming an information storage structure connected to the cell transistor on the first substrate (S120), and forming a cell wiring structure and a peripheral wiring structure on the cell transistor and the information storage structure (S130).

[0092] FIGS. 10a to 16b are plan views and vertical cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0093] FIGS. 10a to 11b illustrate forming a cell transistor on a first substrate (S110).

[0094] Referring to FIG. 10a and FIG. 10b, a stack structure (5, 8) may be formed on a first substrate (3). The stack structure (5, 8) may be formed on memory cell regions (MR1, MR2) and a first peripheral circuit region (PR1). The stack structure (5, 8) may include alternately stacked sacrificial semiconductor layers (5) and channel semiconductor layers (8).

[0096] Referring to FIG. 11a and FIG. 11b, the stack structure (5, 8) can be patterned to form lower active patterns (9) in which the channel semiconductor layers (8) are patterned.

[0097] Cell transistors (cTRs) may be formed on memory cell regions (MR1, MR2). For example, a structure may be formed comprising cell gate electrodes (18c) surrounding cell active patterns (9c) and cell gate dielectric layers (15c) between the cell gate electrodes (18c) and the cell active patterns (9c), which are embedded by an interlayer insulating layer (21). The cell gate dielectric layers (15c) surrounding the cell active patterns (9c) and the cell gate electrodes (18c) may constitute cell transistors (cTRs).

[0098] On the first peripheral circuit region (PR1), a structure may be formed comprising peripheral gate electrodes (18p) surrounding the peripheral active patterns (9p) and peripheral gate dielectric layers (15p) between the peripheral gate electrodes (18p) and the peripheral active patterns (9p), which are buried by an interlayer insulating layer (21) at the same level as the cell transistors (cTR). A first capping insulating layer (24) may be formed on the interlayer insulating layer (21).

[0100] Referring to FIG. 12, a cell bit line (27c) connected to a cell transistor (cTR) and an information storage structure (DS) can be formed on the first substrate (3) (S120).

[0101] The information storage structures (DS) may be formed on memory cell regions (MR1, MR2). The information storage structures (DS) may penetrate the first capping insulating layer (24) and the interlayer insulating layer (21). Each of the information storage structures (DS) may be an information storage structure (38c) comprising a first electrode (30c) connected to a corresponding cell active pattern (9c) among the cell active patterns (9c), a second electrode (36c) covering the first electrode (30c), and a dielectric layer (32c) between the first electrode (30c) and the second electrode (36c). The cell transistors (cTR) and the information storage structures (DS) may constitute memory cells (MC).

[0102] The cell bit lines (27c) may be formed on memory cell regions (MR1, MR2). The cell bit lines (27c) may penetrate the first capping insulating layer (24) and the interlayer insulating layer (21). Each of the cell bit lines (27c) may be connected to a corresponding cell active pattern (9c) among the cell active patterns (9c). Each of the cell bit lines (27c) may include a pillar pattern (29) and a conductive liner (28) covering the side and bottom surfaces of the pillar pattern (29).

[0103] According to an embodiment, peripheral bit lines (27p) and information storage structures (DS) may also be formed on the first peripheral circuit area (PR1) as shown in FIG. 8.

[0105] Referring to FIGS. 13a and 13b, a cell wiring structure (L1c) and a peripheral wiring structure (L1p) can be formed on an information storage structure (DS) (S130).

[0106] For example, a first insulating layer (41), a first cell wiring layer (42c), a second capping insulating layer (44), a cell via (46c), a second insulating layer (47), a second cell wiring layer (48c), and a third capping insulating layer (50) may be formed on a first capping insulating layer (24). The first insulating layer (41), the first cell wiring layer (42c), the second capping insulating layer (44), the cell via (46c), the second insulating layer (47), the second cell wiring layer (48c), and the third capping insulating layer (50) may form a cell wiring structure (L1c). Before forming the cell wiring structure (L1c), cell contact structures (39c, 40c) may be formed. The cell contact structures (39c, 40c) may connect the cell transistors (cTR) to the cell wiring structure (L1c).

[0107] In one embodiment, a peripheral wiring structure (L1p) may be formed simultaneously with a cell wiring structure (L1c) on a first peripheral circuit region (PR1). For example, a first peripheral wiring layer (42p), a peripheral via (46p), and a second peripheral wiring layer (48p) may be formed at the same level as the first cell wiring layer (42c), the cell via (46c), and the second cell wiring layer (48c), respectively. A first insulating layer (41), a first peripheral wiring layer (42p), a second capping insulating layer (44), a peripheral via (46p), a second insulating layer (47), a second peripheral wiring layer (48p), and a third capping insulating layer (50) may constitute a peripheral wiring structure (L1p).

[0108] Before forming the first insulating layer (41) and the first cell wiring layer (42c) and the first peripheral wiring layer (42p), cell contact structures (39c, 40c) and peripheral contact structures (39p, 40p) may be formed.

[0109] A first structure (ST1) can be formed by forming a first bonding layer (53) on a third capping insulation layer (50).

[0111] Referring to FIG. 14a and FIG. 14b, a preliminary structure (SUB) including a peripheral transistor (pTR) may be bonded to a first structure (ST1) (S140). The preliminary structure (SUB) may include a second substrate (102), a peripheral transistor (pTR) on the second substrate (102), and a second bonding layer (110) below the second substrate (102). The second bonding layer (110) may be bonded to the first bonding layer (53).

[0112] The peripheral circuit transistor (pTR) may include peripheral source / drain regions (pSD) formed within the peripheral channel region (pCH), a peripheral channel region (pCH) between the peripheral source / drain regions (pSD), and peripheral gates (pGI, pGE) on the peripheral channel region (pCH). The peripheral gates (pGI, pGE) may include a peripheral gate dielectric layer (pGI) and a peripheral gate electrode (pGE) on the peripheral gate dielectric layer (pGI). The second structure (ST2) may further include a device isolation region (105) that defines the peripheral channel regions (pCH) on the second substrate (102).

[0114] Referring to FIGS. 15a and 15b, a cell through-via (120c) and a peripheral through-via (120p) can be formed through the second substrate (102) of the pre-structure (SUB) (S150). The cell through-via (120c) and the peripheral through-via (120p) can be formed on the core circuit area (CR1, CR2) and the second peripheral circuit area (PR2), respectively. The cell through-via (120c) and the peripheral through-via (120p) can penetrate the bonding surface (J) between the second bonding layer (110) and the first bonding layer (53), and the cell through-via (120c) and the peripheral through-via (120p) can be connected to the cell wiring structure (L1c) and the peripheral wiring structure (L1p), respectively. Contacts (126) connected to the peripheral source / drain regions (pSD) of the peripheral circuit transistor (pTR) can be formed simultaneously with the cell through-via (120c) and the peripheral through-via (120p).

[0116] Referring to FIGS. 16a and 16b, a lower wiring structure (L2c, L2p) connected to a cell through-via (120c) and a peripheral through-via (120p) may be formed. A first lower wiring structure (L2c) may be formed on a core circuit region (CR1, CR2) by forming wiring layers (129), vias (132), and wiring layers (135) on the peripheral circuit transistor (pTR). A second lower wiring structure (L2p) including wiring layers (129), vias (132), and wiring layers (135) may be formed on a second peripheral circuit region (PR2).

[0118] Referring again to FIGS. 3 to 8, an upper wiring structure (L3c, L3p) may be formed on a lower wiring structure (L2c, L2p) (S160). The upper wiring structure (L3c, L3p) may be composed of vias (144) and wiring layers (147). A first upper wiring structure (L3c) may be formed on core circuit regions (CR1, CR2), and a second upper wiring structure (L3p) may be formed on a peripheral circuit region (PR2).

[0119] Subsequently, vias (153) on the upper wiring structure (L3c, L3p) and an interlayer insulating layer (150) are formed, and input / output pads (156c, 156p) connected to the upper wiring structure (L3c, L3p) are formed (S170) so that a second structure (ST2) can be formed and a semiconductor device (1) can be manufactured.

[0121] FIGS. 17 and 18 are vertical cross-sectional views of semiconductor devices according to exemplary embodiments.

[0122] Referring to FIG. 17, the semiconductor device (1a) may include a peripheral wiring structure (L1p) placed at the same level as the cell wiring structure (L1c). In one embodiment, unlike the semiconductor device (1), a transistor composed of the peripheral active pattern (9p), the peripheral gate dielectric layer (15p), and the peripheral gate electrode (18p) may be omitted.

[0124] Referring to FIG. 18, the semiconductor device (1b) may include a peripheral wiring structure (L1p) placed at the same level as the cell wiring structure (L1c). In one embodiment, compared to the semiconductor device (1), the first structure (ST1) may further include first bonding pads (BP1), and the second structure (ST2) may further include second bonding pads (BP2) that are bonded to the first bonding pads (BP1). The first bonding pads (BP1) and the second bonding pads (BP2) may form a bonding surface (J). For example, the first bonding layer (53) may be co-plane with the first bonding pads (BP1), and the second bonding layer (110) may be co-plane with the second bonding pads (BP2). Each of the first bonding pads (BP1) can be electrically connected to a cell wiring structure (L1c) or a peripheral wiring structure (L1p).

[0125] In one embodiment, the second structure (ST2) may further include a connection structure (115) that electrically connects the cell-through vias (120c) and peripheral-through vias (120p) to the second bonding pads (BP2). The connection structure (115) may include wiring layers extending in a horizontal direction and vias that connect the wiring layers to the cell-through vias (120c) and peripheral-through vias (120p) or to the second bonding pads (BP2). In one embodiment, the horizontal width of the cell-through vias (120c) and peripheral-through vias (120p) may vary as it approaches the first structure (ST1). For example, the horizontal width of the cell-through vias (120c) and peripheral-through vias (120p) may increase as it approaches the first structure (ST1).

[0126] A semiconductor device (1b) can be formed by separately forming a first structure (ST1) and a second structure (ST2), each comprising first bonding pads (BP1) and second bonding pads (BP2), and then joining the first structure (ST1) and the second structure (ST2).

[0128] FIGS. 19 and FIGS. 20 are vertical cross-sectional views of semiconductor devices according to exemplary embodiments.

[0129] Referring to FIG. 19, the semiconductor device (1c) may include a first structure (ST1) and a second structure (ST2) that overlaps vertically with the first structure (ST1). For example, the semiconductor device (1) may have a COP (cell on peri) structure, and the first structure (ST1) may be placed on the second structure (ST2).

[0130] In one embodiment, the first structure (ST1) may include a first bonding layer (53c) disposed below the first substrate (3), and the second structure (ST2) may include a second bonding layer (110c) disposed on the second substrate (102). The first bonding layer (53c) may be bonded to the second bonding layer (110c). The first structure (ST1) may include a connection structure (115c) within the first bonding layer (53c). The connection structure (115c) may include wiring layers extending in a horizontal direction and vias connecting the wiring layers.

[0131] The first structure (ST1) may include an upper insulating layer (210) on a cell wiring structure (L1c) and a peripheral wiring structure (L1p), and a routing wiring structure (200) within the upper insulating layer (210). The routing wiring structure (200) may include a wiring layer (203) on the cell wiring structure (L1c) and the peripheral wiring structure (L1p), a routing via (209) connecting the wiring layer (203) to the cell wiring structure (L1c) and the peripheral wiring structure (L1p), and a routing via (206) connecting the wiring layer (203) to the connection structure (115c). The routing via (209) may be placed on the cell wiring structure (L1c) and the peripheral wiring structure (L1p) and may extend in a vertical direction. The routing via (209) can penetrate the first substrate (3), the interlayer insulation layer (21), the cell wiring structure (L1c), and the peripheral wiring structure (L1p), and can be extended in a vertical direction.

[0132] In one embodiment, the horizontal widths of the routing vias (206) and routing vias (209) may vary as they approach the second structure (ST2). For example, the horizontal widths of the routing vias (206) and routing vias (209) may decrease as they approach the second structure (ST2).

[0133] The second structure (ST2) may include a cell-through via (120c) and a peripheral-through via (120p). The cell-through via (120c) and the peripheral-through via (120p) penetrate the second substrate (102) and may be electrically connected to the connection structure (115c). For example, the cell-through via (120c) and the peripheral-through via (120p) may penetrate the second bonding layer (110c) and come into contact with the connection structure (115c).

[0134] In one embodiment, the horizontal widths of the cell through-via (120c) and the peripheral through-via (120p) may vary as they approach the first structure (ST1). For example, the horizontal widths of the cell through-via (120c) and the peripheral through-via (120p) may decrease as they approach the first structure (ST1).

[0135] A semiconductor device (1c) can be formed by bonding a preliminary structure (SUB) including a second substrate (102) to a first structure (ST1) using a second bonding layer (110c), and then performing the process of steps S140 to S170 of FIG. 9.

[0137] Referring to FIG. 20, the semiconductor device (1d) may include a first structure (ST1) disposed on a second structure (ST2). In one embodiment, compared to the semiconductor device (1c), the first structure (ST1) may further include first bonding pads (BP1), and the second structure (ST2) may further include second bonding pads (BP2) that are bonded to the first bonding pads (BP1). The first bonding pads (BP1) and the second bonding pads (BP2) may form a bonding surface (J). For example, the first bonding layer (53c) may be co-plane with the first bonding pads (BP1), and the second bonding layer (110c) may be co-plane with the second bonding pads (BP2). Each of the first bonding pads (BP1) may be electrically connected to a connecting structure (115c).

[0138] In one embodiment, the horizontal width of the cell-penetrating vias (120c) and the peripheral penetrating vias (120p) may vary as it approaches the first structure (ST1). For example, the horizontal width of the cell-penetrating vias (120c) and the peripheral penetrating vias (120p) may increase as it approaches the first structure (ST1).

[0139] A semiconductor device (1d) can be formed by separately forming a first structure (ST1) and a second structure (ST2), each comprising first bonding pads (BP1) and second bonding pads (BP2), and then joining the first structure (ST1) and the second structure (ST2).

[0140] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0142] ST1: 1st Structure ST2: 2nd Structure MR: Memory cell area PR1: 1st peripheral circuit area CR: Core Circuit Area PR2: Second peripheral circuit area 3: First substrate 9c: Cell activation pattern 18c: Cell gate electrode 9p: Surrounding active patterns 18p: Peripheral gate electrode 21: Interlayer insulation layer 38: Information storage structures L1c: Cell wiring structure L1p: Peripheral wiring structure 53: First bonding layer 102: Second substrate 110: Second bonding layer 120c: Cell-penetrating via 120p: Peripheral penetrating vias L2c: 1st lower wiring structure L2p: Second lower wiring structure L3c: 1st upper wiring structure L3p: 2nd upper wiring structure 156c: 1st I / O pad 156p: Second I / O Pad

Claims

Claim 1 A first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; a second structure comprising a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate comprises a core circuit region and a second peripheral circuit region; and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure, wherein the memory cell region comprises: cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; a cell bit line that extends in the vertical direction and contacts the cell active patterns; and cell gate electrodes that overlap the cell active patterns in the vertical direction and extend in a second horizontal direction intersecting the first horizontal direction. A semiconductor device comprising a cell wiring structure disposed on the cell active patterns, the cell bit line, and the cell gate electrodes and electrically connected to at least one of the cell bit line and the cell gate electrodes, wherein the first peripheral circuit region comprises: peripheral active patterns extending in the first horizontal direction; a peripheral bit line extending in the vertical direction and contacting the peripheral active patterns; peripheral gate electrodes overlapping the peripheral active patterns in the vertical direction and extending in the second horizontal direction; and a peripheral wiring structure disposed on the peripheral active patterns, the peripheral bit line, and the peripheral gate electrodes and electrically connected to at least one of the peripheral bit line and the peripheral gate electrodes, wherein the peripheral through-vias are electrically connected to the peripheral wiring structure. Claim 2 A semiconductor device according to claim 1, wherein the cell wiring structure comprises cell wiring layers electrically connected to the cell gate electrodes, the peripheral wiring structure comprises peripheral wiring layers electrically connected to the peripheral gate electrodes, and the horizontal width of the peripheral wiring layers is greater than the horizontal width of the cell wiring layers. Claim 3 In claim 2, the semiconductor device wherein the peripheral wiring layers are placed at the same level as the cell wiring layers. Claim 4 A semiconductor device according to claim 2, wherein the cell wiring structure includes cell vias connecting the cell wiring layers, the peripheral wiring structure includes peripheral vias connecting the peripheral wiring layers, and the horizontal width of the peripheral vias is greater than the horizontal width of the cell vias. Claim 5 A semiconductor device according to claim 1, wherein the first peripheral circuit region is spaced horizontally from the memory cell region and overlaps vertically with the second peripheral circuit region. Claim 6 A first structure comprising a first substrate, wherein the first substrate comprises a memory cell region and a first peripheral circuit region; a second structure comprising a second substrate that overlaps the first structure in a vertical direction, wherein the second substrate comprises a core circuit region and a second peripheral circuit region; and peripheral through-vias that penetrate the second substrate in a vertical direction and are electrically connected to the first structure, wherein the memory cell region comprises: cell active patterns that extend in a first horizontal direction and are stacked spaced apart from each other in the vertical direction; a cell bit line that extends in the vertical direction and contacts the cell active patterns; and cell gate electrodes that overlap the cell active patterns in the vertical direction and extend in a second horizontal direction intersecting the first horizontal direction. A semiconductor device comprising a cell wiring structure disposed on the cell active patterns, the cell bit line, and the cell gate electrodes and electrically connected to at least one of the cell bit line and the cell gate electrodes, wherein the first peripheral circuit region comprises a peripheral wiring structure disposed at the same level as the cell wiring structure, wherein the cell wiring structure comprises cell wiring layers that are vertically spaced apart and stacked and cell vias connecting the cell wiring layers, wherein the peripheral wiring structure comprises peripheral wiring layers and peripheral vias disposed at the same level as the cell wiring layers and the cell vias, respectively, wherein the horizontal width of the peripheral wiring layers is greater than the horizontal width of the cell wiring layers, and the peripheral through-vias are electrically connected to the peripheral wiring structure. Claim 7 A semiconductor device according to claim 6, wherein the first structure is disposed on the second structure, the first structure further comprises a first junction layer on the cell wiring structure and the peripheral wiring structure, and the second structure further comprises a second junction layer disposed below the second substrate and bonded to the first junction layer. Claim 8 In claim 7, the peripheral penetrating vias are semiconductor devices penetrating the interface between the first structure and the second structure. Claim 9 A semiconductor device according to claim 7, wherein the first structure further comprises first bonding pads that are co-planar with the first bonding layer, and the second structure further comprises second bonding pads that are co-planar with the second bonding layer and bonded to the first bonding pads. Claim 10 A semiconductor device according to claim 9, wherein the second structure further comprises a connection structure disposed between the peripheral through-vias and the second bonding pads and electrically connecting the peripheral through-vias to the second bonding pads.

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