Capacitor structure and semiconductor device including the same

Abstract

A capacitor structure and a semiconductor device including the same are provided. The capacitor structure comprises an electrode structure including a first electrode and a second electrode on the first electrode, a dielectric film having a first thickness and comprising a rutile phase material between the first electrode and the second electrode, a first interface insulating film having a second thickness smaller than the first thickness between the first electrode and the dielectric film, and a first insertion insulating film having a third thickness smaller than the second thickness between the first electrode and the first interface insulating film.

Description

Technology Field

[0001] The present invention relates to a capacitor structure and a semiconductor device including the same. Background Technology

[0002] In response to the demand for high integration and miniaturization of semiconductor devices, the size of information storage structures within these devices is also becoming finer. Accordingly, various studies are being conducted to optimize the structure of information storage structures capable of storing information in Dynamic Random-Access Memory (DRAM). The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a capacitor structure with improved electrical characteristics and reliability.

[0004] Another technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0006] A capacitor structure according to some embodiments of the present invention for achieving the above technical problem comprises: an electrode structure including a first electrode and a second electrode on the first electrode; a dielectric film having a first thickness and comprising a rutile phase material between the first electrode and the second electrode; a first interface insulating film having a second thickness smaller than the first thickness between the first electrode and the dielectric film; and a first insertion insulating film having a third thickness smaller than the second thickness between the first electrode and the first interface insulating film.

[0007] A capacitor structure according to some other embodiments of the present invention for achieving the above technical problem comprises: an electrode structure including a first electrode and a second electrode on the first electrode; a dielectric film between the first electrode and the second electrode including a first material having a first oxidation number; a first interface insulating film between the first electrode and the dielectric film including a second material having a second oxidation number; and a first insertion insulating film between the first electrode and the first interface insulating film, wherein each of the dielectric film and the first interface insulating film includes a material in the rutile phase, and the first oxidation number is the same as the second oxidation number.

[0008] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises a substrate including a first source / drain region, a second source / drain region, and a word line trench between the first source / drain region and the second source / drain region, a buried word line within the word line trench, a bit line connected to the first source / drain region, and a capacitor structure connected to the second source / drain region, wherein the capacitor structure comprises an electrode structure including a lower electrode and an upper electrode on the lower electrode, and a dielectric film structure between the lower electrode and the upper electrode, and the dielectric film structure comprises a dielectric film having a first thickness and a material in the rutile phase, an interface insulating film having a second thickness smaller than the first thickness between the lower electrode and the dielectric film, and an insertion insulating film having a third thickness smaller than the second thickness between the lower electrode and the interface insulating film.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view along line II' of Figure 1. Figure 3 is a cross-sectional view along the line II-II' of Figure 1. Figure 4 is an enlarged view of area A1 of Figure 3. Figure 5 is an enlarged view of area A2 of Figure 4. FIG. 6 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to FIG. 5. FIG. 7 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to FIG. 5. FIG. 8 is a drawing for explaining a semiconductor device according to some embodiments, and is a drawing corresponding to FIG. 5. FIGS. 9 to 18 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Figure 19 is an enlarged view of area A1' of Figure 18. FIG. 20 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 21 is a cross-sectional view along the X1-X1' and Y1-Y1' lines of FIG. 20. FIG. 22 is a cross-sectional view of a semiconductor device according to some embodiments. FIG. 23 is an exemplary drawing for illustrating a semiconductor device according to some embodiments. FIG. 24 is an exemplary drawing for illustrating a semiconductor device according to some embodiments. Specific details for implementing the invention

[0011] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0012] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is a cross-sectional view along line II' of FIG. 1. FIG. 3 is a cross-sectional view along line II-II' of FIG. 1. FIG. 4 is an enlarged view of region A1 of FIG. 3. FIG. 5 is an enlarged view of region A2 of FIG. 4.

[0013] Referring to FIGS. 1 to 3, a semiconductor device (100) according to some embodiments may include a substrate (101) having active regions (ACT), a device isolation layer (110) defining the active regions (ACT) within the substrate (101), a word line structure (WLS) embedded and extended within the substrate (101) and having a word line (WL), a bit line structure (BLS) extending across the word line structure (WLS) on the substrate (101) and having a bit line (BL), and an information storage structure (CAP) on the bit line structure (BLS).

[0014] The information storage structure (CAP) can store information and may be, for example, a capacitor structure of a DRAM. The semiconductor device (100) may further include a lower conductive pattern (150) on an active region (ACT), an upper conductive pattern (160) on the lower conductive pattern (150), and an insulating pattern (165) penetrating the upper conductive pattern (160).

[0015] The semiconductor device (100) may include, for example, a cell array of a Dynamic Random Access Memory (DRAM). For example, a bit line (BL) may be connected to a first impurity region (105a) of an active region (ACT), and a second impurity region (105b) of an active region (ACT) may be electrically connected to an information storage structure (CAP) on an upper conductive pattern (160) through lower and upper conductive patterns (150, 160).

[0016] The information storage structure (CAP) may be a capacitor capable of storing information in memory such as DRAM. The information storage structure (CAP) may be electrically connected to the conductive region (150, 160) on a substructure including, for example, lower and upper conductive patterns (150, 160). Here, the substructure may include a substrate (101), a word line structure (WLS), and a bit line structure (BLS), etc.

[0017] The information storage structure (CAP) may include first electrode structures (170), a dielectric film structure (180) on the first electrode structures (170), and a second electrode structure (190) on the dielectric film structure (180). The information storage structure (CAP) may further include supporter layers (SP1, SP2, SP3). The first electrode structures (170) may be lower electrodes, and the second electrode structure (190) may be an upper electrode.

[0018] Although not specifically illustrated, the semiconductor device (100) may include a cell array region in which a cell array is placed and a peripheral circuit region in which peripheral circuits for driving memory cells placed in the cell array are placed. The peripheral circuit region may be placed around the cell array region.

[0019] The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may further include impurities. The substrate (101) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0020] Active regions (ACTs) can be defined within the substrate (101) by a device isolation layer (110). The active regions (ACTs) may be in the form of a bar and may be arranged in an island shape extending in one direction within the substrate (101). The one direction may be inclined with respect to the extension direction of the word lines (WL) and bit lines (BL). The active regions (ACTs) may be arranged parallel to each other, such that the end of one active region (ACT) is arranged adjacent to the center of another active region (ACT) adjacent thereto.

[0021] The active region (ACT) may have first and second impurity regions (105a, 105b) at a predetermined depth from the upper surface of the substrate (101). The first and second impurity regions (105a, 105b) may be spaced apart from each other. The first and second impurity regions (105a, 105b) may be provided as source / drain regions of a transistor formed by a word line (WL). The source region and the drain region are formed by the first and second impurity regions (105a, 105b) by doping or ion implanting substantially the same impurities, and may be referred to interchangeably depending on the circuit configuration of the transistor finally formed. The impurities may include impurities having a conductivity type opposite to that of the substrate (101). In exemplary embodiments, the depths of the first and second impurity regions (105a, 105b) in the source region and the drain region may differ from each other.

[0022] The device isolation layer (110) can be formed by a shallow trench isolation (STI) process. The device isolation layer (110) can surround active regions (ACTs) and electrically isolate them from one another. The device isolation layer (110) may be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation layer (110) may include multiple regions having different bottom depths depending on the width of the trench etched in the substrate (101).

[0023] Word line structures (WLS) may be disposed within gate trenches (115) extending within the substrate (101). Each of the word line structures (WLS) may include a gate dielectric layer (120), a word line (WL), and a gate capping layer (125). In this specification, 'gate (120, WL)' may be referred to as a structure comprising a gate dielectric layer (120) and a word line (WL), the word line (WL) may be referred to as a 'gate electrode', and the word line structure (WLS) may be referred to as a 'gate structure'.

[0024] Word lines (WL) may be arranged to extend in a first direction (X) across an active region (ACT). For example, a pair of adjacent word lines (WL) may be arranged to cross one active region (ACT). Word lines (WL) may constitute the gate of a buried channel array transistor (BCAT), but are not limited thereto. In exemplary embodiments, word lines (WL) may be arranged on the upper surface of the substrate (101). Word lines (WL) may be arranged with a predetermined thickness on the lower surface of the gate trench (115). The upper surface of the word lines (WL) may be located at a lower level than the upper surface of the substrate (101). As used herein, the high and low of the term "level" may be defined with respect to the substantially flat upper surface of the substrate (101).

[0025] The word line (WL) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). As an example, the word line (WL) may include a lower pattern and an upper pattern formed of different materials, wherein the lower pattern may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN), and the upper pattern may be a semiconductor pattern comprising polysilicon doped with P-type or N-type impurities.

[0026] The gate dielectric layer (120) may be disposed on the bottom surface and inner surface of the gate trench (115). The gate dielectric layer (120) may conformally cover the inner wall of the gate trench (115). The gate dielectric layer (120) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer (120) may be, for example, a silicon oxide film or an insulating film having a dielectric constant higher than that of a silicon oxide film. In exemplary embodiments, the gate dielectric layer (120) may be a layer formed by oxidizing the active region (ACT) or a layer formed by deposition.

[0027] The gate capping layer (125) may be positioned to fill the gate trench (115) above the word line (WL). The upper surface of the gate capping layer (125) may be located at substantially the same level as the upper surface of the substrate (101). The gate capping layer (125) may be formed of an insulating material, for example, silicon nitride.

[0028] The bit line structure (BLS) may be extended in one direction, for example, in a second direction (Y), perpendicular to the word line (WL). The bit line structure (BLS) may include a bit line (BL) and a bit line capping pattern (BC) on the bit line (BL).

[0029] The bit line (BL) may include a first conductive pattern (141), a second conductive pattern (142), and a third conductive pattern (143) stacked in sequence. A bit line capping pattern (BC) may be placed on the third conductive pattern (143). A buffer insulating layer (128) may be placed between the first conductive pattern (141) and the substrate (101), and a portion of the first conductive pattern (141) (hereinafter, bit line contact pattern (DC)) may be in contact with a first impurity region (105a) of the active region (ACT).

[0030] The bit line (BL) can be electrically connected to the first impurity region (105a) through the bit line contact pattern (DC). The lower surface of the bit line contact pattern (DC) may be located at a lower level than the upper surface of the substrate (101) and may be located at a higher level than the upper surface of the word line (WL). In an exemplary embodiment, the bit line contact pattern (DC) may be formed within the substrate (101) and at least partially disposed within a bit line contact hole that exposes the first impurity region (105a).

[0031] The first conductive pattern (141) may include a semiconductor material such as polycrystalline silicon. The first conductive pattern (141) may be in direct contact with the first impurity region (105a). The second conductive pattern (142) may include a metal-semiconductor compound. The metal-semiconductor compound may be, for example, a layer in which a portion of the first conductive pattern (141) has been silicided.

[0032] For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern (143) may include metallic materials such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The number of conductive patterns forming the bit line (BL), the type of material, and / or the stacking order may vary depending on the embodiments.

[0033] The bit line capping pattern (BC) may include a first capping pattern (146), a second capping pattern (147), and a third capping pattern (148) stacked sequentially on the third conductive pattern (143). The first to third capping patterns (146, 147, 148) may each include an insulating material, for example, a silicon nitride film. The first to third capping patterns (146, 147, 148) may be made of different materials, and even if they include the same material, the boundaries may be distinguished by differences in physical properties.

[0034] The thickness of the second capping pattern (147) may be smaller than the thickness of the first capping pattern (146) and the thickness of the third capping pattern (148), respectively. The number of capping patterns and / or the type of material forming the bit line capping pattern (BC) may vary depending on the embodiments.

[0035] Spacer structures (SS) may be placed on both side walls of each of the bit line structures (BLS) and may extend in one direction, for example, in a second direction (Y). Spacer structures (SS) may be placed between the bit line structure (BLS) and the lower conductive pattern (150). Spacer structures (SS) may be placed to extend along the side walls of the bit line (BL) and the side walls of the bit line capping pattern (BC).

[0036] A pair of spacer structures (SS) disposed on both sides of a single bit line structure (BLS) may have an asymmetric shape with respect to the bit line structure (BLS). Each of the spacer structures (SS) may include a plurality of spacer layers and may further include an air gap according to embodiments.

[0037] The lower conductive pattern (150) may be connected to one region of the active region (ACT), for example, the second impurity region (105b). The lower conductive pattern (150) may be placed between bit lines (BL) and between word lines (WL). The lower conductive pattern (150) may penetrate the buffer insulating layer (128) and be connected to the second impurity region (105b) of the active region (ACT). The lower conductive pattern (150) may be in direct contact with the second impurity region (105b).

[0038] The lower surface of the lower conductive pattern (150) may be located at a lower level than the upper surface of the substrate (101) and at a higher level than the lower surface of the bit line contact pattern (DC). The lower conductive pattern (150) may be insulated from the bit line contact pattern (DC) by a spacer structure (SS).

[0039] The lower conductive pattern (150) may be made of a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In exemplary embodiments, the lower conductive pattern (150) may include a plurality of layers.

[0040] A metal-semiconductor compound layer (155) may be disposed between the lower conductive pattern (150) and the upper conductive pattern (160). The metal-semiconductor compound layer (155) may be, for example, a layer in which a portion of the lower conductive pattern (150) is silicided, where the lower conductive pattern (150) comprises a semiconductor material. The metal-semiconductor compound layer (155) may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. Depending on the embodiments, the metal-semiconductor compound layer (155) may be omitted.

[0041] An upper conductive pattern (160) may be placed on a lower conductive pattern (150). The upper conductive pattern (160) may extend between spacer structures (SS) to cover the upper surface of a metal-semiconductor compound layer (155). The upper conductive pattern (160) may include a barrier layer (162) and a conductive layer (164). The barrier layer (162) may cover the lower surface and sides of the conductive layer (164).

[0042] The barrier layer (162) may include at least one of a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductive layer (164) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0043] Insulating patterns (165) may be positioned to penetrate the upper conductive pattern (160). The upper conductive pattern (160) may be separated into multiple parts by the insulating patterns (165). The insulating patterns (165) may include at least one insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0044] The etch stop layer (168) may cover the insulating patterns (165) between the first electrode structures (170). The etch stop layer (168) may be in contact with the lower regions of the sides of the first electrode structures (170). The etch stop layer (168) may be positioned below the support layers (SP1, SP2, SP3). The upper surface of the etch stop layer (168) may include a portion in direct contact with the dielectric film structure (180). The etch stop layer (168) may include, for example, at least one of silicon nitride and silicon oxynitride.

[0045] The first electrode structures (170) may be disposed on the upper conductive patterns (160). The first electrode structures (170) may penetrate the etching stop layer (168) and come into contact with the upper conductive patterns (160). The first electrode structures (170) may be in the form of pillars, but are not limited thereto. For example, the first electrode structures (170) may each include at least one of Pt, Ir, Ru, Mo, V, TiN, NbN, TiSiN, MoN, VN, and ScN, or a combination thereof, but are not limited thereto.

[0046] The dielectric film structure (180) may cover the side and top surfaces of each of the first electrode structures (170) on the surface of the first electrode structures (170). The dielectric film structure (180) may be disposed between the first electrode structures (170) and the second electrode structure (190). The dielectric film structure (180) may cover the top and bottom surfaces of the support layers (SP1, SP2, SP3). The dielectric film structure (180) may cover the top surface of the etching stop layer (168). The dielectric film structure (180) may include a high dielectric material, silicon oxide, silicon nitride, or a combination thereof. The specific structure and material of the dielectric film structure (180) will be described in detail later with reference to FIGS. 4 and FIGS. 5.

[0047] The second electrode structure (190) can cover the first electrode structures (170), support layers (SP1, SP2, SP3), and dielectric film structure (180). The second electrode structure (190) can extend along the surface of the dielectric film structure (180). The second electrode structure (190) can fill the space between the first electrode structures (170) and the space between the support layers (SP1, SP2, SP3).

[0048] The second electrode structure (190) may include a conductive material. For example, the second electrode structure (190) may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide). However, the technical concept of the present invention is not limited thereto. For example, the second electrode structure (190) may include at least one of Pt, Ir, Ru, Mo, V, TiN, NbN, TiSiN, MoN, VN, and ScN or a combination thereof, but is not limited thereto.

[0049] As another example, the second electrode structure (190) may include a silicon material or a silicon-germanium material. In this case, the second electrode structure (190) may include a doped silicon material or a doped silicon-germanium material.

[0050] The support layers (SP1, SP2, SP3) may include a first support layer (SP1), a second support layer (SP2) on the first support layer (SP1), and a third support layer (SP3) on the second support layer (SP2). The support layers (SP1, SP2, SP3) may be spaced apart from the substrate (101) in a direction perpendicular to the upper surface of the substrate (101), i.e., a third direction (Z). The support layers (SP1, SP2, SP3) may be in contact with the first electrode structures (170) and may extend in a direction parallel to the upper surface of the substrate (101), i.e., a first and second direction (X, Y).

[0051] The support layers (SP1, SP2, SP3) may include a portion that is in direct contact with the first electrode structures (170) and the dielectric film structure (180). The third support layer (SP3) may have a thicker thickness than the first support layer (SP1) and the second support layer (SP2), but is not limited thereto. The support layers (SP1, SP2, SP3) may be layers that support the first electrode structures (170) having a high aspect ratio.

[0052] The support layers (SP1, SP2, SP3) may each include, for example, at least one of silicon nitride and silicon oxynitride. The number, thickness, and / or arrangement relationship of the support layers (SP1, SP2, SP3) are not limited to those illustrated and may vary according to the embodiments.

[0053] At least one support layer (SP1, SP2, SP3) supporting the first electrode structures (170) may be provided between adjacent first electrode structures (170). For example, between adjacent first electrode structures (170), a first support layer (SP1), a second support layer (SP2), and a third support layer (SP3) in contact with the first electrode structures (170) may be provided.

[0054] Referring to FIG. 1, the first electrode structures (170) may have a regular arrangement in the top view. In exemplary embodiments, the first electrode structures (170) may be spaced apart by a predetermined distance along the first direction (X) and arranged in a zigzag pattern along the second direction (Y). However, the arrangement of the first electrode structures (170) is not limited thereto.

[0055] A through-hole pattern may be disposed between a plurality of adjacent first electrode structures (170). In exemplary embodiments, as shown in the semiconductor device (100) of FIG. 1, a single through-hole pattern may be disposed between four adjacent first electrode structures (170). However, the arrangement of the through-hole pattern is not limited thereto.

[0056] Referring to FIGS. 4 and 5, the dielectric film structure (180) may include a first insertion insulating film (181a), a first interface insulating film (182a), a dielectric film (183), a second interface insulating film (182b), and a second insertion insulating film (181b) that are sequentially stacked.

[0057] The first insertion insulating layer (181a) may be disposed between the first electrode structure (170) and the first interface insulating layer (182a). The first insertion insulating layer (181a) may be disposed along the upper surface of the etching stop layer (168), the side surface of the first electrode structure (170), and the upper surface of the first electrode structure (170). The first insertion insulating layer (181a) may be in contact with the upper surface of the etching stop layer (168), the side surface of the first electrode structure (170), and the upper surface of the first electrode structure (170).

[0058] The first insert insulating film (181a) may be disposed on the lower and upper surfaces of the first support layer (SP1), the lower and upper surfaces of the second support layer (SP2), and the lower and upper surfaces of the third support layer (SP3), respectively. The first insert insulating film (181a) may be in contact with the lower and upper surfaces of the first support layer (SP1), the lower and upper surfaces of the second support layer (SP2), and the lower and upper surfaces of the third support layer (SP3), respectively.

[0059] The first interface insulating film (182a) may be disposed between the first insert insulating film (181a) and the dielectric film (183). The first interface insulating film (182a) may be disposed on the first insert insulating film (181a) along the upper surface of the etching stop layer (168), the side of the first electrode structure (170), and the upper surface of the first electrode structure (170). The first interface insulating film (182a) may be disposed on the first insert insulating film (181a) on the lower and upper surfaces of the first supporter layer (SP1), the lower and upper surfaces of the second supporter layer (SP2), and the lower and upper surfaces of the third supporter layer (SP3), respectively.

[0060] The dielectric film (183) may be disposed between the first electrode structure (170) and the second electrode structure (190). The dielectric film (183) may be disposed between the first interface insulating film (182a) and the second interface insulating film (182b). The dielectric film (183) may be disposed on the first interface insulating film (182a) along the upper surface of the etching stop layer (168), the side surface of the first electrode structure (170), and the upper surface of the first electrode structure (170). The dielectric film (183) may be disposed on the first interface insulating film (182a) along the lower and upper surfaces of the first support layer (SP1), the lower and upper surfaces of the second support layer (SP2), and the lower and upper surfaces of the third support layer (SP3), respectively. Although not specifically described, the dielectric film (183) may be formed as a multilayer structure in which different materials are stacked.

[0061] A second interface insulating film (182b) may be disposed between the dielectric film (183) and the second insert insulating film (181b). The second interface insulating film (182b) may be disposed on the dielectric film (183) along the upper surface of the etching stop layer (168), the side of the first electrode structure (170), and the upper surface of the first electrode structure (170). The second interface insulating film (182b) may be disposed on the dielectric film (183) on the lower and upper surfaces of the first support layer (SP1), the lower and upper surfaces of the second support layer (SP2), and the lower and upper surfaces of the third support layer (SP3), respectively.

[0062] The second insertion insulating film (181b) may be disposed between the second interface insulating film (182b) and the second electrode structure (190). The second insertion insulating film (181b) may be disposed on the second interface insulating film (182b) along the upper surface of the etching stop layer (168), the side surface of the first electrode structure (170), and the upper surface of the first electrode structure (170). The second insertion insulating film (181b) may be disposed on the second interface insulating film (182b) on the lower and upper surfaces of the first support layer (SP1), the lower and upper surfaces of the second support layer (SP2), and the lower and upper surfaces of the third support layer (SP3), respectively.

[0063] In a third direction (Z) perpendicular to each of the first and second directions (X, Y), the first insertion insulating film (181a) may have a first thickness (T1), the first interface insulating film (182a) may have a second thickness (T2), and the dielectric film (183) may have a third thickness (T3). The second thickness (T2) may be greater than the first thickness (T1) and smaller than the third thickness (T3). For example, the first thickness (T1) may be within 5 angstroms. More specifically, for example, the first thickness (T1) may be 1 angstrom to 3 angstroms, the second thickness (T2) may be 1 nm to 4 nm, and the third thickness (T3) may be 4 nm to 1 µm, but is not limited thereto.

[0064] In the third direction (Z), the second interface insulating film (182b) may have a fourth thickness (T4), and the second insert insulating film (181b) may have a fifth thickness (T5). The fourth thickness (T4) may be greater than the fifth thickness (T5) and smaller than the third thickness (T3). For example, the fifth thickness (T5) may be within 5 angstroms. More specifically, for example, the fifth thickness (T5) may be 1 angstrom to 3 angstroms, and the fourth thickness (T4) may be 1 nm to 4 nm, but is not limited thereto. For example, the fourth thickness (T4) may be the same as the second thickness (T2), and the fifth thickness (T5) may be the same as the first thickness (T1), but is not limited thereto.

[0065] The dielectric film (183) may contain a material in the rutile phase. The dielectric film (183) may include a metal oxide having a rutile crystal structure. The first interface insulating film (182a) may include a rutile material. The first interface insulating film (182a) may include a metal oxide having a rutile crystal structure. The dielectric film (183) and the first interface insulating film (182a) may include the same metal oxide or different metal oxides.

[0066] For example, the first interface insulating film (182a) may include a rutile-phase material identical to that contained in the dielectric film (183). The first interface insulating film (182a) may include a metal oxide having the same rutile crystal structure as that contained in the dielectric film (183).

[0067] On the other hand, the first insert insulating film (181a) may not contain rutile-phase material contained in the dielectric film (183) and the first interface insulating film (182a). The first insert insulating film (181a) may not contain metal oxide having a rutile crystal structure contained in the dielectric film (183) and the first interface insulating film (182a). The first insert insulating film (181a) may contain an amorphous material.

[0068] The dielectric film (183) may include a first material having a first oxidation state. For example, the first material may be a metal oxide having a first oxidation state. The first interface insulating film (182a) may include a second material having a second oxidation state and may further include a third material having a third oxidation state. For example, the second material may be a metal oxide having the same oxidation state as the first oxidation state, and the third material may be a material having an oxidation state different from the first oxidation state. The content of the second material in the first interface insulating film (182a) may be higher than the content of the third material. As used herein, the term "material content" means the content of the material per unit volume.

[0069] On the other hand, the first insertion insulating film (181a) may include a material having a different oxidation number from the material contained in the dielectric film (183) and the first interface insulating film (182a).

[0070] The second interface insulating film (182b) may include a rutile-phase material identical to that contained in the dielectric film (183). The second interface insulating film (182b) may include a metal oxide having the same rutile crystal structure as that contained in the dielectric film (183). The dielectric film (183) and the second interface insulating film (182b) may include the same metal oxide or different metal oxides.

[0071] On the other hand, the second insertion insulating film (181b) may not contain rutile-like material contained in the dielectric film (183) and the second interface insulating film (182b). The second insertion insulating film (181b) may not contain metal oxide having a rutile crystal structure contained in the dielectric film (183) and the second interface insulating film (182b). The second insertion insulating film (181b) may contain amorphous material.

[0072] The second interface insulating film (182b) comprises a fourth material having a fourth oxidation number and may further comprise a fifth material having a fifth oxidation number. For example, the fourth material may be a metal oxide having the same oxidation number as the first oxidation number, and the fifth material may be a material having an oxidation number different from the first oxidation number. The content of the fourth material in the second interface insulating film (182b) may be higher than the content of the fifth material.

[0073] On the other hand, the second insertion insulating film (181b) may include a material having a different oxidation number from the material contained in the dielectric film (183) and the second interface insulating film (182b).

[0074] Regarding the structure and material of the second interface insulating film (182b), the description of the structure and material of the first interface insulating film (182a) described above may be applied similarly. Regarding the structure and material of the second insert insulating film (181b), the description of the structure and material of the first insert insulating film (181a) described above may be applied similarly.

[0075] For example, the first insertion insulating film (181a) and the second insertion insulating film (181b) may each include at least one of Al2O3, Y2O3, MgO, Sc2O3, and SiO2, but are not limited thereto.

[0076] For example, the first interface insulating film (182a) and the second interface insulating film (182b) may each include at least one of TiO2, NbO, MoO2, VO2, ScO, TaO, Al2O3, and SnO2, but are not limited thereto.

[0077] For example, the dielectric film (183) may include at least one of ZrO2, HfO2, ZrHfO, TiO2, Al2O3, GeO2, Y2O3, MgO, and Sc2O3, but is not limited thereto.

[0078] For example, the oxidation number of the materials contained in each of the first insertion insulating layer (181a), the first interface insulating layer (182a), the dielectric film (183), the second interface insulating layer (182b), and the second insertion insulating layer (181b) can be confirmed through XPS (X-ray photoelectron spectroscopy) analysis. For example, the crystallinity of the materials contained in each of the first insertion insulating layer (181a), the first interface insulating layer (182a), the dielectric film (183), the second interface insulating layer (182b), and the second insertion insulating layer (181b) can be confirmed through XRD (X-ray diffraction) analysis.

[0079] Through high-angle annular fark field image (HAADF) analysis of a capacitor structure according to some embodiments, it can be confirmed that a first insertion insulating film (181a) is interposed between a first interface insulating film (182a) and a first electrode structure (170), and a second insertion insulating film (181b) is interposed between a second interface insulating film (182b) and a second electrode structure (190).

[0080] In addition, through TEM-EDAX (transmission electron microscopy-electron microscopy-energy dispersive X-ray analysis) images, it can be confirmed that a material contained in the first insertion insulating film (181a) exists between the first interface insulating film (182a) and the first electrode structure (170), and that a material contained in the second insertion insulating film (181b) exists between the second interface insulating film (182b) and the second electrode structure (190).

[0081] By forming a first insertion insulating film (181a) between the first interface insulating film (182a) and the first electrode structure (170), and forming a second insertion insulating film (181b) between the second interface insulating film (182b) and the second electrode structure (190), oxidation of each electrode structure (170, 190) can be effectively prevented.

[0082] Accordingly, the oxygen content of the electrode structure (170, 190) according to some embodiments may be smaller compared to the oxygen content of the electrode structure of a comparative example in which an insertion insulating film (181a, 181b) is not interposed between the interface insulating film (182a, 182b) and the electrode structure (170, 190).

[0083] Additionally, according to some embodiments, the oxygen content of the first electrode structure (170) may be smaller than the oxygen content of the first interface insulating film (182a), and according to some embodiments, the oxygen content of the second electrode structure (190) may be smaller than the oxygen content of the second interface insulating film (182b). As used herein, the term "oxygen content" means the content of oxygen per unit volume.

[0084] In some embodiments, the oxygen content of the first electrode structure (170) is smaller than the oxygen content of the first interface insulating film (182a), and the oxygen content of the second electrode structure (190) is smaller than the oxygen content of the second interface insulating film (182b) can be confirmed by analyzing the oxygen concentration profile through TEM-EDAX.

[0085] In some embodiments, an insertion insulating film (181a, 181b) may be introduced to induce an interface insulating film (182a, 182b) having a grid structure that matches the grid structure of the desired high dielectric constant dielectric film (183).

[0086] Through XPS peak analysis of the capacitor structure according to some embodiments, it can be confirmed that, compared to a comparative example in which an insertion insulating film (181a, 181b) is not interposed between the interface insulating film (182a, 182b) and the electrode structure (170, 190), the interface insulating film (182a, 182b) is formed in a direction having a grid structure that matches the grid structure of the high dielectric constant dielectric film (183).

[0087] As a result, in some embodiments, oxidation of the electrode structure (170, 190) is minimized while the dielectric film (183) is secured, thereby providing a capacitor structure with improved capacitance.

[0088] Meanwhile, the thickness of each of the first and second inserted insulating films (181a, 181b) and the concentration of the material included in the first and second inserted insulating films (181a, 181b) are not limited to those described in this specification and may be provided in various forms to secure the desired capacitor characteristics.

[0089] FIG. 6 is a drawing for explaining a semiconductor device according to some embodiments and corresponds to FIG. 5. For convenience of explanation, parts that overlap with those described above using FIG. 1 to FIG. 5 are briefly explained or omitted.

[0090] Referring to FIG. 6, the first interface insulating film (182a) and the second interface insulating film (182b) may have a multilayer structure rather than a single layer structure.

[0091] The first interface insulating film (182a) may include a first metal oxide layer (182a1) and a second metal oxide layer (182a2) sequentially stacked on the first insert insulating film (181a). The first metal oxide layer (182a1) may include a metal material different from that of the second metal oxide layer (182a2).

[0092] The second interface insulating film (182b) may include a third metal oxide layer (182b1) and a fourth metal oxide layer (182b2) sequentially stacked on the second insert insulating film (181b). The third metal oxide layer (182b1) may include a metal material different from that of the fourth metal oxide layer (182b2).

[0093] Meanwhile, the number and thickness of the metal oxide layers included in each interface insulating film (182a, 182b) are not limited to those shown in the drawing.

[0094] Although not specifically illustrated, the dielectric film (183) may also have a multilayer structure rather than a single layer structure. That is, the dielectric film (183), the first interface insulating film (182a), and the second interface insulating film (182b) may each include multiple layers of metal oxide.

[0095] FIG. 7 is a drawing for explaining a semiconductor device according to some embodiments and corresponds to FIG. 5. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 6 are briefly explained or omitted.

[0096] Referring to FIG. 7, an insertion insulating film may not be disposed between the second electrode structure (190) and the second interface insulating film (182b). The second electrode structure (190) may be disposed on the second interface insulating film (182b). The second electrode structure (190) may be in direct contact with the second interface insulating film (182b) on the second interface insulating film (182b).

[0097] FIG. 8 is a drawing for explaining a semiconductor device according to some embodiments and corresponds to FIG. 5. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 7 are briefly explained or omitted.

[0098] Referring to FIG. 8, an insertion insulating film may not be disposed between the first electrode structure (170) and the first interface insulating film (182a). The first interface insulating film (182a) may be disposed on the first electrode structure (170). The first interface insulating film (182a) may be in direct contact with the first electrode structure (170) on the first electrode structure (170).

[0099] FIGS. 9 to 18 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 19 is an enlarged view of area A1' of FIG. 18. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 8 are briefly explained or omitted. FIGS. 9 to 18 are drawings for explaining a method of manufacturing a semiconductor device (100) of FIGS. 2 and FIG. 3, and are drawings corresponding to the cross-sectional view II' of FIG. 2 and the cross-sectional view II-II' of FIG. 3.

[0100] Referring to FIGS. 9 and 10, a lower structure and a mold structure (ST) can be formed on a substrate (101).

[0101] First, an active region (ACT) can be defined by forming a device isolation layer (110) on a substrate (101). A device isolation trench can be formed on the substrate (101), and the device isolation layer (110) can fill the device isolation trench. Planar, the active region (ACT) may be in the shape of an elongated bar extending in an oblique direction to the extension direction of the word line (WL). An ion implantation process can be performed using the device isolation layer (110) as an ion implantation mask to form impurity regions on top of the active region (ACT). A gate trench (115) can be formed by patterning the active region (ACT) and the device isolation layer (110). A pair of gate trenches (115) may cross the active region (ACT), but are not limited thereto. The impurity regions can also be separated by the gate trench (115) to form a first impurity region (105a) and a second impurity region (105b).

[0102] A gate dielectric layer (120) can be formed within the gate trench (115) with a substantially conformal thickness. Subsequently, a word line (WL) can be formed to fill at least a portion of the gate trench (115). The upper surface of the word line (WL) can be recessed so as to be lower than the upper surface of the active region (ACT). An insulating layer can be laminated on the substrate (101) to fill the gate trench (115) and etched to form a gate capping layer (125) on the word line (WL).

[0103] An insulating layer and a conductive layer can be formed sequentially on the front surface of a substrate (101) and patterned to form a buffer insulating layer (128) and a first conductive pattern (141) that are stacked sequentially. The buffer insulating layer (128) can be formed from at least one of silicon oxide, silicon nitride, and silicon oxynitride. A plurality of buffer insulating layers (128) can be formed in a spaced-apart manner. The first conductive pattern (141) can have a shape corresponding to the planar shape of the buffer insulating layer (128). The buffer insulating layer (128) can be formed to simultaneously cover the ends of two adjacent active regions (ACT), that is, adjacent second impurity regions (105b). Bit line contact holes can be formed by etching the upper portions of the device isolation layer (110), the substrate (101), and the gate capping layer (125) using the buffer insulating layer (128) and the first conductive pattern (141) as an etching mask. The bit line contact hole can expose the first impurity region (105a).

[0104] A bit line contact pattern (DC) that fills the bit line contact hole can be formed. Forming the bit line contact pattern (DC) may include forming a conductive layer that fills the bit line contact hole and performing a planarization process. As an example, the bit line contact pattern (DC) may be formed of polysilicon. After forming a second conductive pattern (142), a third conductive pattern (143), and first to third capping patterns (146, 147, 148) in sequence on a first conductive pattern (141), the first to third conductive patterns (141, 142, 143) may be etched in sequence using the first to third capping patterns (146, 147, 148) as an etching mask. As a result, a bit line structure (BLS) can be formed including a bit line (BL) including first to third challenge patterns (141, 142, 143) and a bit line capping pattern (BC) including first to third capping patterns (146, 147, 147).

[0105] Spacer structures (SS) can be formed on the sides of the bit line structure (BLS). The spacer structures (SS) can be formed of multiple layers. Fence insulation patterns (154) can be formed between the spacer structures (SS). The fence insulation patterns (154) may include silicon nitride or silicon oxynitride. An anisotropic etching process can be performed using the fence insulation patterns (154) and the third capping pattern (148) as an etching mask to form an opening that exposes the second impurity region (105b).

[0106] A lower conductive pattern (150) can be formed at the bottom of the opening. The lower conductive pattern (150) can be formed from a semiconductor material such as polysilicon. For example, the lower conductive pattern (150) can be formed by forming a polysilicon layer that fills the opening and then performing an etch-back process.

[0107] A metal-semiconductor compound layer (155) can be formed on the lower conductive pattern (150). The formation of the metal-semiconductor compound layer (155) may include a metal layer deposition process and a heat treatment process.

[0108] An upper conductive pattern (160) can be formed on the upper part of the opening. Forming the upper conductive pattern (160) may include forming a barrier layer (162) and a conductive layer (164) in sequence. Subsequently, a patterning process may be performed on the barrier layer (162) and the conductive layer (164) to form insulating patterns (165) that penetrate therefrom. Accordingly, a lower structure including a substrate (101), a word line structure (WLS), and a bit line structure (BLS), etc., may be formed.

[0109] An etch stop layer (168) may be conformally formed on a substructure, and mold layers (118) and pre-support layers (SP1', SP2', SP3') may be alternately stacked on the etch stop layer (168). The mold layers (118) and pre-support layers (SP1', SP2', SP3') may form a mold structure (ST). The etch stop layer (168) may include at least one insulating material having etch selectivity under specific etching conditions with the mold layers (118), for example, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, and silicon carbonitride. The mold layers (118) may be formed of silicon oxide, and the pre-support layers (SP1', SP2', SP3') may be formed of silicon nitride.

[0110] Referring to FIGS. 11 and 12, a plurality of holes (HL1) can be formed penetrating the mold layers (118) and the pre-support layers (SP1', SP2', SP3'). In the step of forming the plurality of holes (HL1), the etch stop layer (168) can act as a stopper to stop the progress of the etching process. The plurality of holes (HL1) can penetrate the etch stop layer (168) to expose the upper conductive patterns (160). The plurality of holes (HL1) are areas where the first electrode structures (170) are to be formed, and as shown in FIG. 1, they can be formed in a regular arrangement spaced apart at a predetermined interval on a plane.

[0111] Referring to FIGS. 13 and 14, a plurality of holes (HL1) can be filled with a conductive material to form first electrode structures (170).

[0112] The first electrode structures (170) may be formed to be connected to an upper conductive pattern (160) at the bottom of a plurality of holes (HL1). Forming the first electrode structures (170) may include forming a conductive material layer inside and on the plurality of holes (HL1), and performing a planarization process, for example, a chemical mechanical polishing (CMP) process and / or etch back on the conductive material layer. Through this, the first electrode structures (170) may be formed into a plurality of node-separated and spaced-apart patterns. The first electrode structures (170) may be formed from at least one of, for example, polycrystalline silicon (Si), TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN. In exemplary embodiments, the process of forming the first electrode structures (170) may be performed by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), etc.

[0113] Referring to FIGS. 15 and 16, openings (HL2) can be formed by removing at least a portion of the mold structure (ST), namely the mold layers (118 in FIGS. 13 and 14) and / or the pre-support layers (SP1', SP2', SP3' in FIGS. 13 and 14).

[0114] Subsequently, a separate mask is formed on the first electrode structures (170), and at least a portion of the mold layers (118 in FIG. 13 and 14) and / or the preliminary support layers (SP1', SP2', SP3' in FIG. 13 and 14) can be removed using the mask. Accordingly, the preliminary support layers (SP1', SP2', SP3' in FIG. 13 and 14) can be formed into first to third support layers (SP1, SP2, SP3). The first to third support layers (SP1, SP2, SP3) can be patterned according to the structure of the mask to have a shape including a plurality of openings. The plurality of openings can be placed between four adjacent first electrode structures (170), as shown in FIG. 1. The first to third support layers (SP1, SP2, SP3) can connect adjacent first electrode structures (170) to each other. The mold layers (118) can be selectively removed with respect to the support layers (SP1, SP2, SP3). In exemplary embodiments, the process of removing the mold layers (118) can be performed by a wet etching process using an etching solution (e.g., a hydrogen fluoride (HF) solution). The mask can be removed after etching the mold layers (118) or while etching the mold layers (118). Openings (HL2) can be formed in the region where the mold layers (118) have been removed.

[0115] Referring to FIGS. 17 to 19, a dielectric film structure (180) and a second electrode structure (190) covering the first electrode structures (170) can be formed within the openings (HL2).

[0116] The dielectric film structure (180) can be formed on the first electrode structures (170) and the first to third support layers (SP1, SP2, SP3).

[0117] The dielectric film structure (180) may include a first insertion insulating film (181a), a first interface insulating film (182a), a dielectric film (183), a second interface insulating film (182b), and a second insertion insulating film (181b) that are sequentially stacked.

[0118] A first insertion insulating film (181a) may be formed on the first electrode structure (170) and the support layers (SP1, SP2, SP3). Although not specifically illustrated, the first insertion insulating film (181a) may be extended to cover the upper surface of the etching stop layer (168). Subsequently, a first interface insulating film (182a) may be formed on the first insertion insulating film (181a), and subsequently, a dielectric film (183) may be formed on the first interface insulating film (182a).

[0119] A second interface insulating film (182b) may be formed on the dielectric film (183), and a second insert insulating film (181b) may be formed sequentially on the second interface insulating film (182b). The first insert insulating film (181a), the first interface insulating film (182a), the dielectric film (183), the second interface insulating film (182b), and the second insert insulating film (181b) may be formed along the surfaces of the first electrode structure (170), support layers (SP1, SP2, SP3), and etching stop layer (168).

[0120] The process of forming each of the first insertion insulating film (181a), the first interface insulating film (182a), the dielectric film (183), the second interface insulating film (182b), and the second insertion insulating film (181b) can be performed by Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD), etc.

[0121] Subsequently, a second electrode structure (190) covering the dielectric film structure (180) can be formed. The second electrode structure (190) can be formed on the second insertion insulating film (181b) after the second insertion insulating film (181b) is formed. The process of forming the second electrode structure (190) can be performed by ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or PVD (Physical Vapor Deposition), etc.

[0122] Accordingly, an information storage structure (CAP) including first electrode structures (170), dielectric film structures (180), and second electrode structures (190) can be formed. Accordingly, a semiconductor device (100) including an information storage structure (CAP) as illustrated in FIGS. 2 and FIGS. 3 can be manufactured.

[0123] FIG. 20 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 21 is a cross-sectional view along the lines X1-X1' and Y1-Y1' of FIG. 20.

[0124] Referring to FIGS. 20 and 21, the semiconductor device (200) may include a substrate (210), a plurality of first conductive lines (220), a channel layer (230), a gate electrode (240), a gate insulating layer (250), and an information storage structure (280). The integrated circuit device (200) may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (230) extends along a vertical direction from the substrate (210).

[0125] A lower insulating layer (212) may be disposed on a substrate (210), and a plurality of first conductive lines (220) may be spaced apart from each other in a first direction (X) and extended in a second direction (Y) on the lower insulating layer (212). A plurality of first insulating patterns (222) may be disposed on the lower insulating layer (212) to fill the space between the plurality of first conductive lines (220). The plurality of first insulating patterns (222) may be extended in the second direction (Y), and the upper surface of the plurality of first insulating patterns (222) may be disposed at the same level as the upper surface of the plurality of first conductive lines (220). The plurality of first conductive lines (220) may function as bit lines of a semiconductor device (200).

[0126] In exemplary embodiments, a plurality of first conductive lines (220) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (220) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x ..., or a combination thereof, but is not limited thereto. A plurality of first conductive lines (220) may comprise a single layer or a multilayer of the aforementioned materials. In exemplary embodiments, a plurality of first conductive lines (220) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0127] The channel layer (230) may be arranged in a matrix form spaced apart in a first direction (X) and a second direction (Y) on a plurality of first conductive lines (220). The channel layer (230) may have a first width according to the first direction (X) and a first height according to the third direction (Z), and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. The bottom portion of the channel layer (230) functions as a first source / drain region (not shown), the upper portion of the channel layer (230) functions as a second source / drain region (not shown), and a portion of the channel layer (230) between the first and second source / drain regions may function as a channel region (not shown). The first source / drain region and the second source / drain region are vertically spaced apart from each other, and the channel region may be a vertical channel region.

[0128] In exemplary embodiments, the channel layer (230) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Snz O, Yb x Ga y Zn z O, In x Ga y It may include O or a combination thereof. The channel layer (230) may include a single layer or a multilayer of the oxide semiconductor. In some embodiments, the channel layer (230) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (230) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer (230) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer (230) may be polycrystalline or amorphous, but is not limited thereto. In exemplary embodiments, the channel layer (230) may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0129] The gate electrode (240) may extend in a first direction (X) on both sidewalls of the channel layer (230). The gate electrode (240) may include a first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230) and a second sub-gate electrode (240P2) facing the second sidewall opposite the first sidewall of the channel layer (230). As one channel layer (230) is disposed between the first sub-gate electrode (240P1) and the second sub-gate electrode (240P2), the integrated circuit device (200) may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (240P2) and forming only the first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230).

[0130] The gate electrode (240) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode (240) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of , or a combination thereof, but is not limited to these.

[0131] The gate insulating layer (250) surrounds the sidewalls of the channel layer (230) and may be interposed between the channel layer (230) and the gate electrode (240). For example, as shown in FIG. 21, the entire sidewall of the channel layer (230) may be surrounded by the gate insulating layer (250), and a portion of the sidewall of the gate electrode (240) may be in contact with the gate insulating layer (250). In other embodiments, the gate insulating layer (250) may be extended in the extension direction of the gate electrode (240) (i.e., the first direction (X)), and only two sidewalls of the channel layer (230) facing the gate electrode (240) may be in contact with the gate insulating layer (250).

[0132] In exemplary embodiments, the gate insulating layer (250) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. For example, a high dielectric film that can be used as the gate insulating layer (250) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0133] A plurality of second insulation patterns (232) may be extended along a second direction (Y) on a plurality of first insulation patterns (222), and a channel layer (230) may be disposed between two adjacent second insulation patterns (232). Additionally, between two adjacent second insulation patterns (232), a first filling layer (234) and a second filling layer (236) may be disposed in the space between two adjacent channel layers (230). The first filling layer (234) may be disposed at the bottom of the space between two adjacent channel layers (230), and the second filling layer (236) may be formed to fill the remainder of the space between two adjacent channel layers (230) on the first filling layer (234). The upper surface of the second buried layer (236) is positioned at the same level as the upper surface of the channel layer (230), and the second buried layer (236) can cover the upper surface of the gate electrode (240). Alternatively, a plurality of second insulating patterns (232) may be formed as a material layer continuous with a plurality of first insulating patterns (222), or the second buried layer (236) may be formed as a material layer continuous with the first buried layer (234).

[0134] Storage contacts (260) may be disposed on the channel layer (230). The storage contacts (260) may be arranged in a matrix form that is spaced apart in a first direction (X) and a second direction (Y) and positioned so as to overlap vertically with the channel layer (230). The storage contacts (260) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x , or a combination thereof, but is not limited thereto. The upper insulating layer (262) may surround the side wall of the storage contact (260) on a plurality of second insulating patterns (232) and a second embedded layer (236).

[0135] An etch stop layer (270) is disposed on the upper insulating layer (262), and an information storage structure (280) may be disposed on the etch stop layer (270). The information storage structure (280) may include a first electrode structure (282), a dielectric layer (284), and a plate electrode (286).

[0136] The first electrode structure (282) can be electrically connected to the upper surface of the storage contact (260) by penetrating the etch stop layer (270). The first electrode structure (282) may be formed as a pillar type extending in the third direction (Z), but is not limited thereto. In exemplary embodiments, the first electrode structure (282) may be arranged in a matrix form that is positioned to overlap vertically with the storage contact (260) and spaced apart in the first direction (X) and the second direction (Y). Alternatively, a landing pad (not shown) may be further positioned between the storage contact (260) and the first electrode structure (282), so that the first electrode structure (282) may be arranged in a hexagonal shape.

[0137] In the semiconductor device (200), the first electrode structure (282) of the information storage structure (280) may be the first electrode structure (170) described using FIGS. 1 to 19. The plate electrode (286) of the information storage structure (280) may be the second electrode structure (190) described using FIGS. 1 to 19.

[0138] In a semiconductor device (200), the dielectric layer (284) of an information storage structure (280) may include a first insertion insulating film (181a), a first interface insulating film (182a), a dielectric film (183), a second interface insulating film (182b), and a second insertion insulating film (181b) as described using FIGS. 1 to 19.

[0139] FIG. 22 is a cross-sectional view of a semiconductor device according to some embodiments.

[0140] Referring to FIG. 22, the semiconductor device (300) may include a substrate (301), a lower structure (310) on the substrate (301), a plurality of structures (LS) alternately stacked on the substrate (301), a plurality of first insulating layers (321), and a second conductive pattern (350).

[0141] Each of the plurality of structures (LS) may include an active layer (330) extending in a first direction (X), a first conductive pattern (340) extending in a second direction (Y) perpendicular to the first direction (X) and intersecting the active layer (330), a gate dielectric layer (342) between the active layer (330) and the first conductive pattern (340), a gate capping layer (344) between the first conductive pattern (340) and the second conductive pattern (350), a first electrode (361) of an information storage structure (DS), and a second insulating layer (322) between the first conductive pattern (340) and the first electrode (361).

[0142] The information storage structure (DS) may further include a dielectric layer (365) on the first electrode (361) and a second electrode (362) on the dielectric layer (265).

[0143] In the semiconductor device (300), the first electrode (361) of the information storage structure (DS) may be the first electrode structure (170) described using FIGS. 1 to 19. The second electrode (362) of the information storage structure (280) may be the second electrode structure (190) described using FIGS. 1 to 19.

[0144] In a semiconductor device (300), the dielectric layer (365) of an information storage structure (DS) may include a first insertion insulating film (181a), a first interface insulating film (182a), a dielectric film (183), a second interface insulating film (182b), and a second insertion insulating film (181b) as described using FIGS. 1 to 19.

[0145] The first direction (X) and the second direction (Y) are perpendicular to each other and may be parallel to the upper surface of the substrate (301). The third direction (Z) is perpendicular to the first direction (X) and the second direction (Y) and may be perpendicular to the upper surface of the substrate (301).

[0146] A lower structure (310) may be disposed on a substrate (301). A plurality of structures (LS) and a plurality of first insulating layers (321) may be laminated on the lower structure (310). The lower structure (310) may include an element region on the substrate (301) and an insulating region covering the element region. The insulating region may be formed of insulating layers comprising at least one of an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0147] A plurality of structures (LS) and a plurality of first insulating layers (321) may form a molded structure on a substrate (301). A plurality of structures (LS) may be disposed between a plurality of first insulating layers (321) and may be spaced apart from each other in a third direction (Z) by a plurality of first insulating layers (321). A first insulating layer (321) may extend along a first direction (X), and its end may extend into a second conductive pattern (350). A second insulating layer (322) may be disposed between the first insulating layer (321) and the active layer (330), and between the first conductive pattern (340) and the information storage structure (DS). A first insulating layer (321) and a second insulating layer (322) may each include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The first insulating layer (321) may be extended horizontally longer than the second insulating layer (322). The thickness of the second insulating layer (322) may be thicker than the thickness of the first insulating layer (321).

[0148] The active layer (330) is disposed on the substrate (301) and may extend horizontally in the first direction (X). The active layer (330) may be stacked in a plurality spaced apart from each other in the third direction (Z) and arranged in a plurality in the second direction (Y). The active layer (330) arranged in a plurality in the third direction (Z) may be disposed between a plurality of first insulating layers (321). The active layer (330) may have a line shape, a bar shape, or a pillar shape extending in the first direction (X) while intersecting the first conductive pattern (340). The active layer (330) may include a semiconductor material, for example, silicon, germanium, or silicon-germanium.

[0149] The active layer (330) may include a first impurity region (330a), a second impurity region (330b), and a channel region (330c). The first impurity region (330a) may be electrically connected to the second conductivity pattern (350). The second impurity region (330b) may be electrically connected to the first electrode (361) of the information storage structure (DS). The length in the first direction (X) of the second impurity region (330b) may be longer than the length in the first direction (X) of the first impurity region (330a), but is not limited thereto. The channel region (330c) may be disposed between the first impurity region (330a) and the second impurity region (330b). The channel region (330c) may overlap with the first conductivity pattern (340). The first impurity region (330a) and the second impurity region (330b) are spaced apart from each other in the horizontal direction and are placed at the same level, and the channel region (330c) may be a horizontal channel region (330c).

[0150] The first impurity region (330a) and the second impurity region (330b) can be formed by performing a doping or ion implantation process of impurities on the active layer (330). The first impurity region (330a) and the second impurity region (330b) may have an n-type or p-type conductivity type.

[0151] A portion of the first impurity region (330a) may correspond to the source region of the transistor, a portion of the second impurity region (330b) may correspond to the drain region of the transistor, and a channel region (330c) may correspond to the channel of the transistor. A portion of the first impurity region (330a) may provide a first contact region for directly connecting the source region of the transistor to the second conduction pattern (350), i.e., the bit line (BL), and a portion of the second impurity region (330b) may provide a second contact region for directly connecting the drain region of the transistor to the information storage structure (DS).

[0152] In another example, the active layers (330) may comprise at least one of an oxide semiconductor, for example, hafnium-silicon oxide (HSO), hafnium-zinc oxide (HZO), indium-zinc oxide (IZO), indium-gallium oxide (IGO), indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), and indium-tin-zinc oxide (ITZO).

[0153] In another example, the active layers (330) may include a two-dimensional material (2D material) in which atoms form a predetermined crystal structure and can form a channel of a transistor. The two-dimensional material layer may include at least one of a TMD material layer (Transition Metal Dichalcogenide material layer), a black phosphorous material layer, and an hBN material layer (hexagonal Boron-Nitride material layer). For example, the two-dimensional material layer may include at least one of BiOSe, Crl, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials capable of forming a two-dimensional material.

[0154] The first conductive pattern (340) is placed on the substrate (301) and may extend horizontally in the second direction (Y). The first conductive pattern (340) may be stacked in multiple numbers spaced apart from each other in the third direction (Z) and arranged in multiple numbers in the first direction (X). The first conductive pattern (340) may be placed between the channel region (330c) of the active layer (330) and the first insulating layer (321). The first conductive pattern (340) may be placed on the upper and lower surfaces of the active layer (330). The first conductive pattern (340) may have a line shape, a bar shape, or a column shape that intersects the second conductive pattern (350) and extends in the second direction (Y). Although not illustrated, a plurality of first conductive patterns (340) stacked in a third direction (Z) within a single memory cell may be extended to different lengths in a second direction (Y) to provide a contact area in which each upper surface is exposed.

[0155] The first conductive pattern (340) may include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. The first conductive pattern (340) may be a word line (WL) and may be referred to as a 'gate electrode'.

[0156] The gate dielectric layer (342) may be disposed between the first conductive pattern (340) and the active layer (330). The gate dielectric layer (342) may be formed to have a thickness substantially conformal to the inner space of the gap region formed by etching the second insulating layer (322) from the side between adjacent first insulating layers (321). The gate dielectric layer (342) may comprise silicon oxide, silicon nitride, or a high-dielectric constant (high-k) material.

[0157] The gate capping layer (344) may be positioned to fill an area where the first conductive pattern (340) is partially removed from the side. For example, the side of the gate capping layer (344) may be in contact with the side of the first conductive pattern (340), and the upper and lower surfaces may be covered by the gate dielectric layer (342). The gate capping layer (344) may electrically insulate the first conductive pattern (340) and the second conductive pattern (350).

[0158] The second conductive pattern (350) may be extended vertically in the third direction (Z) on the substrate (301). The second conductive pattern (350) may be arranged in multiple numbers in the second direction (Y). The second conductive pattern (350) may be positioned adjacent to the first impurity region (330a) and the first end surface of the active layer (330). The second conductive pattern (350) may have an inclined inner surface facing the inclined sides of the first epitaxial layer (335a). Multiple active layers (330) stacked in the third direction (Z) may be electrically connected to a single second conductive pattern (350). The second conductive pattern (350) may have a line shape, a bar shape, or a column shape extending in the third direction (Z). Although not illustrated, the semiconductor device may further include upper wiring that is disposed on the second conductive pattern (350), connected to the second conductive pattern (350), and extends in the first direction (X). The second conductive pattern (350) may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0159] The information storage structure (DS) may be disposed adjacent to the second impurity region (330b) and the second end surface of the active layer (330). The information storage structure (DS) may be electrically connected to the active layer (330). The information storage structure (DS) may include a first electrode (361), a dielectric layer (365) on the first electrode (361), and a second electrode (362) on the dielectric layer (365). The first electrode (361) of the information storage structure (DS) may have a cylinder shape, but is not limited thereto, and in the embodiments, may have a pillar shape.

[0160] The first electrode (361) may be formed to have a substantially conformal thickness in the inner space of the gap region formed by etching the second insulating layer (322) from the side. The first electrode (361) may be in a state where nodes are separated by structures (LS) by removing a portion on the side of the first insulating layer (321) after depositing a conductive material. The first electrode (361) may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a conductive metal oxide.

[0161] The dielectric layer (365) may conformally cover the first electrode (361). The dielectric layer (365) covers a protruding portion of the first electrode (361) and may include a portion protruding toward the second electrode (362). The dielectric layer (365) may include a high dielectric material or silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, depending on the embodiments, the dielectric layer (365) may include an oxide, nitride, silicide, oxynitride, or silicide-oxynitride comprising at least one of Hf, Al, Zr, and La.

[0162] The second electrode (362) can cover the dielectric layer (365). The second electrode (362) can fill the internal space of the first electrode (361) having a cylinder shape. The second electrode (362) may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0163] FIG. 23 is an exemplary drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 22 are briefly explained or omitted.

[0164] Referring to FIG. 23, a semiconductor device according to some embodiments comprises a cell structure (CST), a ferri structure (PST), and a bonding structure (BST) between the cell structure (CST) and the ferri structure (PST), and may include word lines (WL1, WL2) each extending in a second direction (Y), a bit line (BL) extending in a first direction (X) intersecting the second direction (Y), and active patterns (AP1, AP2) connected to the bit line (BL). In a direction parallel to the third direction (Z), the ferri structure (PST) may be disposed on the cell structure (CST).

[0165] The cell structure (CST) may include word lines (WL1, WL2), bit lines (BL), active patterns (AP1, AP2), back gate electrodes (BG), and data storage patterns (DSP), etc. The ferri structure (PST) may include a ferri active substrate (400) and a ferri gate structure (PG), etc.

[0166] The substrate (500) may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0167] A data storage pattern (DSP) can be placed on a substrate (500). Although not illustrated, the data storage pattern (DSP) can be arranged in a matrix form along a first direction (X) and a second direction (Y).

[0168] For example, the third direction (Z) may be the thickness direction of the substrate (500). The first direction (X) and the second direction (Y) may be parallel to the upper surface of the substrate (500).

[0169] For example, data storage patterns (DSPs) may be capacitors. Data storage patterns (DSPs) may include a capacitor dielectric film (453) interposed between storage electrodes (451) and plate electrodes (455). In a planar view, the storage electrodes (451) may have various shapes such as circular, elliptical, rectangular, square, rhombus, hexagonal, etc.

[0170] The storage electrode (451) and the plate electrode (455) may each include, for example, at least one of a conductive semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, and a metal. The capacitor dielectric film (453) may include at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, it may include one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, or a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0171] In contrast, data storage patterns (DSPs) may be variable resistance patterns that can be switched between two resistance states by an electrical pulse applied to a memory element. For example, data storage patterns (DSPs) may include phase-change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystal state changes depending on the amount of current.

[0172] Contact patterns (BC) can be placed on the storage electrode (451). The contact patterns (BC) can be connected to the first active pattern (AP1) and the second active pattern (AP2), respectively. Each contact pattern (BC) can have various shapes, such as circular, elliptical, rectangular, square, rhombus, or hexagonal, in a planar view.

[0173] The contact pattern (BC) may include a conductive material. The contact pattern (BC) may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material and metal.

[0174] The first active patterns (AP1) and the second active patterns (AP2) may be placed on the data storage patterns (DSP). The data storage patterns (DSP) may be placed between the first active pattern (AP1) and the substrate (500). The data storage patterns (DSP) may be placed between the second active pattern (AP1) and the substrate (500). The first active patterns (AP1) and the second active patterns (AP2) may be placed alternately along the first direction (X). Although not illustrated, the first and second active patterns (AP1, AP2) may be arranged two-dimensionally along the first direction (X) and the second direction (Y).

[0175] For example, the first active pattern (AP1) and the second active pattern (AP2) may each be made of a single-crystal semiconductor material. As an example, the first active pattern (AP1) and the second active pattern (AP2) may each be made of single-crystal silicon.

[0176] The back gate electrode (BG) can be placed on the data storage pattern (DSP). The back gate electrode (BG) can be placed on the contact pattern (BC). The back gate electrode (BG) can be extended in a second direction (Y). The back gate electrodes (BG) can be spaced apart from each other in a first direction (X). The back gate electrodes (BG) can be spaced apart at a certain interval.

[0177] Each back gate electrode (BG) can be positioned between a first active pattern (AP1) and a second active pattern (AP2) that are adjacent to each other in a first direction (X). In other words, the first active pattern (AP1) can be positioned on one side of each back gate electrode (BG), and the second active pattern (AP2) can be positioned on the other side of each back gate electrode (BG).

[0178] A first active pattern (AP1) may be placed between a first word line (WL1) and a back gate electrode (BG). A second active pattern (AP2) may be placed between a second word line (WL2) and a back gate electrode (BG). A pair of first word lines (WL1) and second word lines (WL2) may be placed between back gate electrodes (BG) adjacent in a first direction (X).

[0179] The back gate electrode (BG) comprises a conductive material and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material and metal.

[0180] Although not shown, a back gate insulating film may be placed between the back gate electrode (BG) and the first active pattern (AP1), and between the back gate electrode (BG) and the second active pattern (AP2).

[0181] The first word line (WL1) and the second word line (WL2) may be placed on the data storage pattern (DSP). The first word line (WL1) and the second word line (WL2) may be placed on the contact patterns (BC). The data storage patterns (DSP) may be placed between the first word line (WL1) and the substrate (500). The data storage patterns (DSP) may be placed between the second word line (WL2) and the substrate (500).

[0182] Each of the first word line (WL1) and the second word line (WL2) may be extended in the second direction (Y). The first word line (WL1) and the second word line (WL2) may be arranged alternately in the first direction (X).

[0183] The first word line (WL1) and the second word line (WL2) may be spaced apart from the bit line (BL) and the contact pattern (BC) in a third direction (Z). The first word line (WL1) and the second word line (WL2) may be located between the bit line (BL) and the contact pattern (BC).

[0184] The first word line (WL1) and the second word line (WL2) may include a conductive material. The first word line (WL1) and the second word line (WL2) may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal.

[0185] Although not shown, a gate insulating film may be placed between the first word line (WL1) and the first active pattern (AP1), and between the second word line (WL2) and the second active pattern (AP2).

[0186] A bit line (BL) can be placed on a first active pattern (AP1) and a second active pattern (AP2). A bit line (BL) can be connected to the first active pattern (AP1) and the second active pattern (AP2).

[0187] A bit line (BL) can be placed on a back gate electrode (BG), a first word line (WL1), and a second word line (WL2). The bit line (BL) can be extended in a first direction (X) across the back gate electrode (BG).

[0188] The bit line (BL) includes a conductive material and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material and metal.

[0189] A shielding conduction pattern (SL) may be placed on a bit line (BL). The bit line (BL) may be placed between the shielding conduction pattern (SL) and a first word line (WL1). The bit line (BL) may be placed between the shielding conduction pattern (SL) and a second word line (WL2).

[0190] For example, the shielding conductive pattern (SL) may include a shielding conductive plate and a plurality of shielding conductive protrusions. The shielding conductive plate may have a flat shape. The plurality of shielding conductive protrusions may protrude from the shielding conductive plate in a third direction (Z). The shielding conductive protrusions may be positioned between adjacent first bit lines (BL1) in a second direction (Y).

[0191] The shielding conductive pattern (SL) includes a conductive material and may include, for example, at least one of a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material and a metal.

[0192] Unlike what is described, the shielding conductive pattern (SL) may not include a flat shielding conductive plate. In such a case, the shielding conductive pattern (SL) may include a plurality of shielding conductive protrusions having a line shape.

[0193] The data storage pattern (DSP) is depicted as being placed between the substrate (500) and the bit line (BL), but is not limited thereto. In a semiconductor device according to some embodiments, the bit line (BL), the first word line (WL1) and the second word line (WL2) may be placed between the substrate (500) and the ferriactive substrate (400).

[0194] The first lower insulating layer (471), the second lower insulating layer (472), and the third lower insulating layer (473) may be sequentially disposed on the substrate (500). A data storage pattern (DSP) may be disposed within the first lower insulating layer (471). A contact pattern (BC) may be disposed within the second lower insulating layer (472). The first and second word lines (WL1, WL2), the bit line (BL), and the shielding conductive pattern (SL) may be disposed within the third lower insulating layer (473).

[0195] The first lower insulating film (471), the second lower insulating film (472), and the third lower insulating film (473) may include an insulating material. Although the first lower insulating film (471), the second lower insulating film (472), and the third lower insulating film (473) are depicted as single films, this is for convenience of explanation only and is not limited thereto.

[0196] The lower contact plug (443a) and the lower wiring line (443b) may be placed within the third lower insulating film (473). The lower wiring line (443b) may be placed on the data storage pattern (DSP), bit line (BL), first word line (WL1), and second word line (WL2).

[0197] The lower contact plug (443a) can connect the lower wiring line (443b) and the word lines (WL1, WL2). The lower contact plug (443a) can connect the lower wiring line (443b) and the shielding conductive pattern (SL). Although not shown, the lower contact plug (443a) can connect the lower wiring line (443b) and the bit line (BL). Additionally, the lower contact plug (443a) can connect the lower wiring line (443b) and the plate electrode (455) of the data storage pattern (DSP).

[0198] The lower contact plug (443a) and the lower wiring line (443b) are depicted as having different membranes, but are not limited thereto. The boundary between the lower contact plug (443a) and the lower wiring line (443b) may not be distinct. The lower contact plug (443a) and the lower wiring line (443b) each contain a conductive material.

[0199] The first connecting wiring structure (461) may be placed on the lower wiring line (443b). The first connecting wiring structure (461) may be connected to the lower wiring line (443b). The first connecting wiring structure (461) may be placed within the third lower insulating film (473).

[0200] The first connecting wiring structure (461) may include a first connecting wiring (461b) and a first connecting via (461a). Although the first connecting wiring structure (461) is illustrated as including a first connecting wiring (461b) placed on a single metal level, this is for convenience of explanation only and is not limited thereto. Unlike illustrated, the first connecting wiring structure (461) may include a plurality of first connecting wirings (461b) placed on different metal levels.

[0201] The first connecting wire (461b) and the first connecting via (461a) may each include a conductive material. Although the first connecting wire (461b) and the first connecting via (461a) are depicted as having different films, they are not limited thereto.

[0202] The ferriactive substrate (400) may be placed on the first connecting wiring structure (461). The ferriactive substrate (400) may be spaced apart from the substrate (500) in a third direction (Z). The first connecting wiring structure (461) may be placed between the substrate (500) and the ferriactive substrate (400).

[0203] The ferriactive substrate (400) may include silicon, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0204] An interlayer insulating film (401) may be disposed on the lower portion of the ferriactive substrate (400). The interlayer insulating film (401) may include an insulating material, for example, silicon oxide and / or silicon nitride.

[0205] A perigate structure (PG) may be disposed on a perigate active substrate (400). The perigate structure (PG) may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. The perigate structure (PG) may include a perigate insulating film, a perigate conductive film, and a perisource / drain region.

[0206] The upper insulating film (481) is disposed on the ferriactive substrate (400). The upper insulating film (481) may include an insulating material. Although the upper insulating film (481) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0207] The ferry contact plug (441a) and ferry wiring line (441b) can be placed within the upper interlayer insulating film (481).

[0208] The ferri contact plug (441a) can be connected to the ferri gate structure (PG). For example, the ferri contact plug (441a) can be connected to the ferri source / drain region and / or the ferri gate conductive film.

[0209] The ferry wiring line (441b) may be placed on the ferry contact plug (441a) and the ferry gate structure (PG). The ferry wiring line (441b) may be placed on the ferry active substrate (400). The ferry wiring line (441b) is connected to the ferry contact plug (441a). For example, the ferry wiring line (441b) may be the wiring line closest to the ferry gate structure (PG) in the third direction (Z).

[0210] The ferry contact plug (441a) and the ferry wiring line (441b) are depicted as having different membranes, but are not limited thereto. The boundary between the ferry contact plug (441a) and the ferry wiring line (441b) may not be distinct. The ferry contact plug (441a) and the ferry wiring line (441b) each contain a conductive material.

[0211] A bonding structure (BST) may include a first bonding pad (491a) and a first bonding insulating layer (491b) adjacent to a cell structure (CST), and a second bonding pad (492a) and a second bonding insulating layer (492b) adjacent to a ferri structure (PST). The first bonding pad (491a) may be disposed within the first bonding insulating layer (491b), and the second bonding pad (492a) may be disposed within the second bonding insulating layer (492b).

[0212] For example, the first bonding pad (491a) and the second bonding pad (492a) may each include a conductive material such as copper (Cu), and the first bonding insulating layer (491b) and the second bonding insulating layer (492b) may each include an insulating material such as silicon carbonitride, but are not limited thereto.

[0213] The first bonding pad (491a) can be directly bonded to the second bonding pad (492a) by a Cu-Cu junction. The cell structure (CST) and the ferri structure (PST) can be bonded by hybrid bonding by a Cu-Cu junction and an insulating material.

[0214] A second connecting wiring structure (442) may be positioned between the ferry wiring line (441b) and the bonding structure (BST). The second connecting wiring structure (442) may connect the ferry wiring line (441b) and the bonding structure (BST). For example, the ferry wiring line (441b) may be connected to the second bonding pad (492a) through the wiring within the second connecting wiring structure (442) and the interlayer insulating film (401). The second connecting wiring structure (442) may extend in a third direction (Z). The second connecting wiring structure (442) includes a conductive material.

[0215] FIG. 24 is an exemplary drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 23 are briefly explained or omitted.

[0216] Referring to FIG. 24, a semiconductor device according to some embodiments includes a cell structure (CST), a ferri structure (PST), and a bonding structure (BST) between the cell structure (CST) and the ferri structure (PST). In a direction parallel to the third direction (Z), the cell structure (CST) may be disposed on the ferri structure (PST). Unlike FIG. 23, the semiconductor device illustrated in FIG. 24 may not include an interlayer insulating film (401) and a substrate (500).

[0217] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0218] 100: Semiconductor device 101: Board 105a, 105b: Impurity regions 110: Device isolation layer 115: Gate Trench 120: Gated Dielectric 125: Gate capping layer 141, 142, 143: Challenge Patterns 146, 147, 148: Capping pattern 150: Lower challenge pattern 155: Metal-semiconductor compound layer 160: Upper challenge pattern 162: Barrier layer 164: Challenge Floor 165: Insulation pattern 170: First electrode structure 180: Dielectric membrane structure 190: Second electrode structure 181a: First inserted insulating film 181b: Second insert insulating film 1812a: First interface insulating film 182b: Second interface insulating film 183: Genetic membrane ACT: Active area BL: Beat Line WL: Word Line 100, 200, 300: Semiconductor device

Claims

Claim 1 An electrode structure comprising a first electrode and a second electrode on the first electrode; a dielectric film having a first thickness and comprising a rutile phase material between the first electrode and the second electrode; a first interface insulating film having a second thickness smaller than the first thickness between the first electrode and the dielectric film; and a first insertion insulating film having a third thickness smaller than the second thickness between the first electrode and the first interface insulating film. Claim 2 In claim 1, the first interface insulating film comprises a capacitor structure including a rutile-phase material. Claim 3 In claim 1, the first inserted insulating film is a capacitor structure that does not contain a rutile-phase material. Claim 4 A capacitor structure according to claim 1, wherein the first interface insulating film comprises a first metal oxide layer and a second metal oxide layer sequentially stacked on the first insert insulating film, and the first metal oxide layer comprises a metal material different from the second metal oxide layer. Claim 5 A capacitor structure according to claim 1, further comprising: a second interface insulating film having a fourth thickness smaller than the first thickness between the second electrode and the dielectric film; and a second insertion insulating film having a fifth thickness smaller than the fourth thickness between the second electrode and the second interface insulating film. Claim 6 In claim 5, the second interface insulating film comprises a third metal oxide layer and a fourth metal oxide layer sequentially stacked on the second insert insulating film, and the third metal oxide layer comprises a metal material different from the fourth metal oxide layer, forming a capacitor structure. Claim 7 A capacitor structure comprising: an electrode structure including a first electrode and a second electrode on the first electrode; a dielectric film including a first material having a first oxidation number between the first electrode and the second electrode; a first interface insulating film including a second material having a second oxidation number between the first electrode and the dielectric film; and a first insertion insulating film between the first electrode and the first interface insulating film, wherein each of the dielectric film and the first interface insulating film comprises a material in the rutile phase, and the first oxidation number is the same as the second oxidation number. Claim 8 In claim 7, the first interface insulating film further comprises a third material having a third oxidation state different from the first oxidation state, and the capacitor structure in which the content of the second material within the first interface insulating film is higher than the content of the third material. Claim 9 In claim 7, the first insertion insulating film comprises a capacitor structure having a material having an oxidation number different from that of the dielectric film and the first interface insulating film. Claim 10 A semiconductor device comprising: a substrate including a first source / drain region, a second source / drain region, and a word line trench between the first source / drain region and the second source / drain region; a buried word line within the word line trench; a bit line connected to the first source / drain region; and a capacitor structure connected to the second source / drain region, wherein the capacitor structure comprises an electrode structure including a lower electrode and an upper electrode on the lower electrode, and a dielectric film structure between the lower electrode and the upper electrode, wherein the dielectric film structure comprises a dielectric film having a first thickness and a material in the rutile phase, an interface insulating film having a second thickness smaller than the first thickness between the lower electrode and the dielectric film, and an insertion insulating film having a third thickness smaller than the second thickness between the lower electrode and the interface insulating film.

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