Semiconductor device including memory cells and global bit lines

Abstract

A semiconductor device is provided. The semiconductor device comprises memory cells; local bit lines connected to the memory cells and positioned at the same level as each other; and global bit lines positioned at a higher level than the local bit lines and connected to the local bit lines. Each of the memory cells comprises a cell transistor and an information storage structure. Each of the first global bit lines comprises a first bit line portion, and each of the second global bit lines comprises a second bit line portion positioned at a higher level than the first bit line portions of the first global bit lines, and three local bit lines arranged sequentially in a first horizontal direction among the local bit lines are each connected to three global bit lines spaced apart from each other among the global bit lines.

Description

Technology Field

[0001] The present invention relates to a semiconductor device comprising memory cells and global bitlines and a method for manufacturing a semiconductor device. Background Technology

[0003] Research is underway to reduce the size of the components constituting semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form reduced-size components; however, as the size of the components decreases, the dispersion characteristics of the semiconductor device are deteriorating. The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device capable of increasing integration density.

[0006] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device capable of improving performance.

[0007] One of the technical problems that the technical concept of the present invention aims to solve is to provide a method for manufacturing the semiconductor device. means of solving the problem

[0009] A semiconductor device according to one embodiment is provided. The semiconductor device comprises memory cells arranged three-dimensionally along a vertical direction perpendicular to each other, a first horizontal direction, and a second horizontal direction; local bit lines connected to the memory cells and positioned at the same level as each other; and global bit lines positioned at a higher level than the local bit lines and connected to the local bit lines. Each of the memory cells comprises a cell transistor including a cell gate electrode extending in the second horizontal direction, and an information storage structure. The global bit lines include first global bit lines connected to N first local bit lines among the local bit lines; The above includes second global bitlines connected to N second local bitlines among the above local bitlines, wherein N is a natural number greater than or equal to 2, each of the first global bitlines includes a first bitline portion, and each of the second global bitlines includes a second bitline portion positioned at a higher level than the first bitline portions of the first global bitlines, and three local bitlines arranged in order in the first horizontal direction among the above local bitlines are each connected to three global bitlines spaced apart from each other among the global bitlines.

[0010] A semiconductor device according to one embodiment is provided. The semiconductor device comprises: memory cells arranged three-dimensionally along a vertical direction, a first horizontal direction, and a second horizontal direction that intersect each other; local bit lines connected to the memory cells and positioned at the same level as each other; global bit lines positioned at a level higher than the local bit lines and connected to the local bit lines; bit line sense amplifiers positioned at a level higher than the global bit lines; and global bit line selection circuits connected to the bit line sense amplifiers and the global bit lines. Each of the above global bitlines is connected to N local bitlines among the above local bitlines, and N is a natural number greater than or equal to 2, and among the above global bitlines, the first global bitline includes a first bitline portion, and among the above global bitlines, the second global bitline includes a second bitline portion placed at a higher level than the first bitline portion, and the above global bitline selection circuits include a first global bitline selection circuit connected to a first bitline sense amplifier among the above bitline sense amplifiers, and the above global bitlines include M global bitlines connected to the first global bitline selection circuit, and M is a natural number greater than or equal to 4.

[0011] A semiconductor device according to one embodiment is provided. The semiconductor device comprises a first structure and a second structure disposed on the first structure and bonded to the first structure. The first structure comprises memory cells arranged three-dimensionally along a vertical direction perpendicular to each other, a first horizontal direction, and a second horizontal direction; local bit lines connected to the memory cells and disposed at the same level; and global bit lines disposed at a level higher than the local bit lines and connected to the local bit lines. Each of the memory cells comprises a cell transistor including a cell gate electrode extending in the second horizontal direction, and an information storage structure. The global bit lines include first global bit lines connected to N first local bit lines among the local bit lines; and second global bit lines connected to N second local bit lines among the local bit lines. The above N is a natural number greater than or equal to 2, each of the first global bitlines includes a first-1 bitline portion, each of the second global bitlines includes a second-1 bitline portion placed at a higher level than the first-1 bitline portions of the first global bitlines, and three local bitlines arranged in order in the first horizontal direction among the local bitlines are each connected to three global bitlines spaced apart from each other among the global bitlines.

[0012] A method for manufacturing a semiconductor device according to one embodiment is provided. The semiconductor device manufacturing method comprises forming a first structure including memory cells, local bit lines, and global bit lines, forming a second preliminary structure including peripheral circuits, forming a bonded structure by bonding the first structure and the second preliminary structure through a wafer bonding process, and performing a wiring process. The global bit lines include first global bit lines connected to N first local bit lines among the local bit lines, and second global bit lines connected to N second local bit lines among the local bit lines, wherein N is a natural number greater than or equal to 2, each of the first global bit lines includes a first bit line portion, and each of the second global bit lines includes a second bit line portion disposed at a higher level than the first bit line portions of the first global bit lines.

[0013] The memory cells may be arranged three-dimensionally along a vertical direction, a first horizontal direction, and a second horizontal direction that intersect each other. Each of the memory cells includes a cell transistor including a cell gate electrode extending in the second horizontal direction, and an information storage structure.

[0014] The above local bitlines are connected to the memory cells and can be placed at the same level as each other.

[0015] The above global bitlines are placed at a higher level than the above local bitlines and can be connected to the above local bitlines.

[0016] Among the above local bit lines, the three local bit lines arranged in order in the first horizontal direction can each be connected to three global bit lines spaced apart from each other among the above global bit lines.

[0017] The above peripheral circuit may include bitline sense amplifiers.

[0018] The above peripheral circuit may further include global bitline selection circuits connected to the bitline sense amplifiers and the global bitlines.

[0019] The global bitline selection circuits include a first global bitline selection circuit connected to a first bitline sense amplifier among the bitline sense amplifiers, and the global bitlines may include M global bitlines connected to the first global bitline selection circuit. M may be a natural number greater than or equal to 4.

[0020] The above bitline sense amplifiers may include sense amplifier transistors.

[0021] The above global bitline selection circuits may include select transistors placed at the same level as the sense amplifier transistors. Effects of the invention

[0023] According to embodiments, local bitlines connected to memory cells, global bitlines connected to the local bitlines, and bitline sense amplifiers connected to the global bitlines may be provided. Each of the global bitlines may be connected to N local bitlines. N may be a natural number greater than or equal to 2. Thus, the integration density of the semiconductor device can be increased.

[0024] According to embodiments, the global bitlines may include global bitlines positioned at different levels to reduce parasitic capacitance between the global bitlines. Thus, since parasitic capacitance between the global bitlines can be reduced, the performance of the semiconductor device can be improved.

[0025] According to embodiments, global bitline selection circuits connected to the bitline sense amplifiers and global bitlines can be provided. Since the global bitline selection circuits can increase the number of global bitlines connected to each bitline sense amplifier, the total number of bitline sense amplifiers required in the semiconductor device can be reduced. Therefore, since more area can be secured for forming the bitline sense amplifiers, the performance of the peripheral circuit including the bitline sense amplifiers can be improved.

[0026] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0028] FIGS. 1, FIGS. 2a, and FIGS. 2b are drawings showing a semiconductor device according to one embodiment. FIG. 3 is a drawing including a circuit of an exemplary example of a semiconductor device according to one embodiment. FIGS. 4a and FIGS. 4b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 5A and FIGS. 5B are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 6a and FIGS. 6b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 7a and FIGS. 7b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 8a and FIGS. 8b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 9a and 9b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 10a and FIGS. 10b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 11a and FIGS. 11b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 12, FIGS. 13a, FIGS. 13b, and FIGS. 14 are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 15, 16, and 17 are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 18a and FIGS. 18b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 19a and FIGS. 19b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIGS. 20a and FIGS. 20b are drawings illustrating exemplary examples of a semiconductor device according to one embodiment. FIG. 21 is a drawing showing an exemplary example of a semiconductor device according to one embodiment. FIG. 22 is a drawing showing an exemplary example of a semiconductor device according to one embodiment. FIGS. 23 to 28 are drawings illustrating exemplary examples of a method for manufacturing a semiconductor device according to one embodiment. Specific details for implementing the invention

[0029] In the following, terms such as "upper," "middle," and "lower," etc., may be replaced with other terms, such as "first," "second," and "third," etc., to describe the components of the specification. While terms such as "first," "second," and "third," etc., may be used to describe various components, said components are not limited by said terms, and "first component" may be named "second component." In the specification, terms such as "lower," "upper," "top," and "bottom," etc., may be terms described based on the drawings.

[0030] First, a semiconductor device according to one embodiment will be described with reference to FIGS. 1, FIGS. 2a, and FIGS. 2b. In FIGS. 1, FIGS. 2a, and FIGS. 2b, FIG. 1 is a conceptual perspective view showing a semiconductor device according to one embodiment, FIG. 2a is a drawing showing a semiconductor device according to one embodiment of the present invention, and FIG. 2b is a drawing including an exemplary circuit of a semiconductor device according to one embodiment. Here, while describing a semiconductor device according to one embodiment with reference to FIGS. 1, FIGS. 2a, and FIGS. 2b, other drawings may also be cited for description.

[0031] Referring to FIGS. 1, FIGS. 2a, and FIGS. 2b, a semiconductor device (1) according to one embodiment may include a first structure (STC1) and a second structure (STC2) on the first structure (STC1). The first structure (STC1) and the second structure (STC2) may be structures joined by a wafer bonding process.

[0032] In one example, the first structure (STC1) and the second structure (STC2) may be structures in which the insulating layer of the first structure (STC1) and the insulating layer of the second structure (STC2) are joined.

[0033] In one example, the first structure (STC1) and the second structure (STC2) may be structures formed by joining the insulating layer of the first structure (STC1) and the insulating layer of the second structure (STC2), and joining the metal layer (e.g., copper layer) of the first structure (STC1) and the metal layer (e.g., copper layer) of the second structure (STC2).

[0034] The semiconductor device (1) may include a plurality of banks (BA) and an outer peripheral region (PERI). The outer peripheral region (PERI) may include a first peripheral region (PERI1) within the first structure (STC1) and a second peripheral region (PERI2) within the second structure (STC2). The outer peripheral region (PERI) may be a peripheral circuit region where peripheral circuits for input / output of data or commands, or input of power / ground, are arranged.

[0035] Each of the plurality of banks (BA) may include a first bank area (BA1) within the first structure (STC1) and a second bank area (BA2) within the second structure (STC2).

[0036] The first bank region (BA1) of the first structure (STC1) may include memory cells arranged in three dimensions (e.g., MC in FIG. 4a), local bit lines (e.g., LBL in FIG. 4a) connected to the memory cells (e.g., MC in FIG. 4a), and global bit lines (GBL) connected to the local bit lines (e.g., LBL in FIG. 4a).

[0037] Each of the global bitlines (GBL) may be connected to N local bitlines among the local bitlines (e.g., LBL in FIG. 4a). "N" may be a natural number greater than or equal to 2. For example, each of the global bitlines (GBL) may be connected to 2 local bitlines (LBL in FIG. 4a and 4b), 3 local bitlines (LBL in FIG. 5a and 5b), or 4 local bitlines (LBL in FIG. 6a and 6b), but the embodiments are not limited thereto. For example, each of the global bitlines (GBL) may be connected to 5 or more local bitlines.

[0038] The second bank region (BA2) of the second structure (STC2) may include bitline sense amplifiers (BLSA) and bitline select circuits (BLSC) connected to the bitline sense amplifiers (BLSA).

[0039] The first and second structures (STC1, STC2) may further include routing wiring structures (RI) configured to electrically connect the bitline selection circuits (BLSC) and the global bitlines (GBL).

[0040] The bitline sense amplifiers (BLSA) can be connected to the global bitlines (GBL) through the routing wiring structures (RI). The routing wiring structures (RI) can be configured to electrically connect the global bitlines (GBL) and the bitline sense amplifiers (BLSA).

[0041] Each of the bitline sense amplifiers (BLSA) may be electrically connected to a pair of global bitlines selected by the bitline selection circuit (BLSC) among the global bitlines (GBL) connected to the bitline sense amplifier (BLSA) according to the operation of the corresponding bitline selection circuit (BLSC) among the bitline selection circuits (BLSC), and may not be electrically connected to a pair of global bitlines not selected by the bitline selection circuit (BLSC).

[0042] Each of the bitline sense amplifiers (BLSA) can be connected to M global bitlines (GBL). In one example, "M" can be a natural number greater than or equal to 4.

[0043] Each of the bitline sense amplifiers (BLSA) may include a plurality of sense amplifier transistors (P1_a, P1_b, N1_a, N1_b). The sense amplifier transistors (P1_a, P1_b, N1_a, N1_b) may include a first PMOS transistor (P1_a) and a second PMOS transistor (P1_b), and a first NMOS transistor (N1_a) and a second NMOS transistor (N1_b).

[0044] Each of the bitline selection circuits (BLSC) above may include selection transistors (ST).

[0045] Each of the bitline selection circuits (BLSC) may include a first selection circuit (SC1) and a second selection circuit (SC2). In each of the bitline selection circuits (BLSC), the first selection circuit (SC1) may include a first selection transistor (ST1) connected to a first global bitline (GBL_1) among the global bitlines (GBL) and a second selection transistor (ST2) connected to a second global bitline (GBL_2) among the global bitlines (GBL).

[0046] In each of the bitline selection circuits (BLSC), the second selection circuit (SC2) may include a third selection transistor (ST3) connected to a third global bitline (GBL_3) among the global bitlines (GBL) and a fourth selection transistor (ST4) connected to a fourth global bitline (GBL_4) among the global bitlines (GBL).

[0047] In the following, we will focus on explaining the first bitline sense amplifier (BLSA1) and the first bitline selection circuit (BLSC1) that are connected to each other among the bitline sense amplifiers (BLSA) and the bitline selection circuits (BLSC).

[0048] The first PMOS transistor (P1_a) and the second PMOS transistor (P1_b) may be referred to as a PMOS transistor pair, and the first NMOS transistor (N1_a) and the second NMOS transistor (N1_b) may be referred to as a NMOS transistor pair.

[0049] The source of the first PMOS transistor (P1_a) and the source of the second PMOS transistor (P1_b) can be connected to the first control line (LA) through the first node (ND1_a). The source of the first NMOS transistor (N1_a) and the source of the second NMOS transistor (N1_b) can be connected to the second control line (LAB) through the second node (ND1_b). The first node (ND1_a) and the second node (ND1_b) can be referred to as the first source node and the second source node, respectively.

[0050] Depending on the operation of the first bitline selection circuit (BLSC1), the drain of the first PMOS transistor (P1_a) and the drain of the first NMOS transistor (N1_a) can be connected to the first global bitline (GBL_1) or the third global bitline (GBL_3) through the first drain node (ND1_c).

[0051] Depending on the operation of the first bitline selection circuit (BLSC1), the drain of the second p-MOS transistor (P1_b) and the drain of the second NMOS transistor (N1_b) can be connected to the second global bitline (GBL_2) or the fourth global bitline (GBL_4), which may be a complementary bitline among the global bitlines (GBL), through the second drain node (ND1_d).

[0052] When the third selection transistor (ST3) and the fourth selection transistor (ST4) of the second selection circuit (SC2) are in the off state and the first selection transistor (ST1) and the second selection transistor (ST2) of the first selection circuit (SC1) are in the on state, the first and second global bitlines (GBL_1, GBL_2) may be a pair of global bitlines selected by the first bitline selection circuit (BLSC1) and electrically connected to the first bitline sense amplifier (BLSA1), and the third and fourth global bitlines (GBL_3, GBL_4) may be a pair of global bitlines unselected by the first bitline selection circuit (BLSC1) and electrically isolated from the first bitline sense amplifier (BLSA1). For example, when the third selection transistor (ST3) and the fourth selection transistor (ST4) of the second selection circuit (SC2) are off, and the first selection transistor (ST1) and the second selection transistor (ST2) of the first selection circuit (SC1) are on, the drain of the first PMOS transistor (P1_a) and the drain of the first NMOS transistor (N1_a) can be connected to the first global bitline (GBL_1) through the first drain node (ND1_c), and the drain of the second PMOS transistor (P1_b) and the drain of the second NMOS transistor (N1_b) can be connected to the second global bitline (GBL_2), which may be a complementary bitline, through the second drain node (ND1_d).

[0053] When the third selection transistor (ST3) and the fourth selection transistor (ST4) of the second selection circuit (SC2) are in the ON state and the first selection transistor (ST1) and the second selection transistor (ST2) of the first selection circuit (SC1) are in the OFF state, the first and second global bitlines (GBL_1, GBL_2) may be a pair of global bitlines that are not selected by the first bitline selection circuit (BLSC1) and are electrically isolated from the first bitline sense amplifier (BLSA1), and the third and fourth global bitlines (GBL_3, GBL_4) may be a pair of global bitlines that are selected by the first bitline selection circuit (BLSC1) and are electrically connected to the first bitline sense amplifier (BLSA1). For example, when the third selection transistor (ST3) and the fourth selection transistor (ST4) of the second selection circuit (SC2) are in the ON state and the first selection transistor (ST1) and the second selection transistor (ST2) of the first selection circuit (SC1) are in the OFF state, the drain of the first PMOS transistor (P1_a) and the drain of the first NMOS transistor (N1_a) can be connected to the third global bit line (GBL_3) through the first drain node (ND1_c), and the drain of the second PMOS transistor (P1_b) and the drain of the second NMOS transistor (N1_b) can be connected to the fourth global bit line (GBL_4), which may be a complementary bit line, through the second drain node (ND1_d).

[0054] When the first bitline sense amplifier (BLSA1) is electrically connected to the first and second global bitlines (GBL_1, GBL_2) by the first bitline selection circuit (BLSC1) and is not electrically connected to the third and fourth global bitlines (GBL_3, GBL_4) by the first bitline selection circuit (BLSC1), the first bitline sense amplifier (BLSA1) can sense the voltage change amount of the first global bitline (GBL_1) and amplify it.

[0055] In the case where the first bitline sense amplifier (BLSA1) is not electrically connected to the first and second global bitlines (GBL_1, GBL_2) by the first bitline selection circuit (BLSC1) and is electrically connected to the third and fourth global bitlines (GBL_3, GBL_4) by the first bitline selection circuit (BLSC1), the first bitline sense amplifier (BLSA1) can sense the voltage change amount of the third global bitline (GBL_3) and amplify it.

[0056] When the first bitline sense amplifier (BLSA1) performs sensing and amplification operations, an internal power supply voltage may be applied to the first node (ND1_a) through the first control line (LA), and the second node (ND1_b) may be connected to a ground terminal through the second control line (LAB). The first bitline sense amplifier (BLSA1) includes a pair of PMOS transistors and a pair of NMOS transistors and is implemented in a circuit configuration in which the transistors are cross-coupled, but this is an exemplary embodiment and the embodiments are not limited thereto. For example, the circuit of the first bitline sense amplifier (BLSA1) may be implemented in various circuit configurations.

[0057] As described above, the first bitline sense amplifier (BLSA1) may not be connected to the third and fourth global bitlines (GBL_3, GBL_4) when connected to the first and second global bitlines (GBL_1, GBL_2) depending on the operation of the first bitline selection circuit (BLSC1), and may be connected to the third and fourth global bitlines (GBL_3, GBL_4) when not connected to the first and second global bitlines (GBL_1, GBL_2). Therefore, since the area occupied by the bitline sense amplifiers (BLSA) can be reduced, the integration density of the semiconductor device (1) can be increased.

[0058] In one example, the first and second selection transistors (ST1, ST2) may be placed on the first side of the first bitline sense amplifier (BLSA1), and the third and fourth selection transistors (ST3, ST4) may be placed on the second side of the first bitline sense amplifier (BLSA1) opposite to the first side of the first bitline sense amplifier (BLSA1).

[0059] In one example, the first selection circuit (SC1) may include the first and second selection transistors (ST1, ST2), and the second selection circuit (SC2) may include the third and fourth selection transistors (ST3, ST4). Accordingly, the first selection circuit (SC1) may be placed on the first side of the first bitline sense amplifier (BLSA1), and the second selection circuit (SC2) may be placed on the second side of the first bitline sense amplifier (BLSA1) opposite to the first side of the first bitline sense amplifier (BLSA1).

[0061] Hereinafter, exemplary embodiments of the semiconductor device (1) described above will be explained. Various exemplary embodiments described below and the embodiments described above may be combined to form a single exemplary embodiment. Hereinafter, the components described above may be directly cited without separate detailed explanation, or the explanation may be omitted. In addition, the components that can be modified or substituted described below are described with reference to the drawings below, but the components that can be modified, substituted, or added may be combined with each other or combined with the components described above to form a semiconductor device according to an embodiment of the present invention. In addition, in cases where the components described above are composed of multiple parts, the description below will focus on the case where there is only one component described above.

[0062] Referring to FIG. 3, exemplary examples of the first selection circuit (SC1) and the second selection circuit (SC2) will be described. FIG. 3 is a circuit diagram for describing exemplary examples of the first selection circuit (SC1) and the second selection circuit (SC2) in the first bitline selection circuit (BLSC1) of FIG. 2b.

[0063] In one embodiment, referring to FIG. 3, the first selection circuit (SC1) described in FIG. 2b may be replaced with a first selection circuit (SC1') comprising the first selection transistor (ST1) and the fourth selection transistor (ST4), and the second selection circuit (SC2) described in FIG. 2b may be replaced with a second selection circuit (SC2') comprising the second selection transistor and the third selection transistor (ST3).

[0064] The first selection circuit (SC1') may include the first selection transistor (ST1) and the fourth selection transistor (ST4) disposed on both sides of the first bitline sense amplifier (BLSA1). The second selection circuit (SC2) may include the third selection transistor (ST3) and the second selection transistor (ST2) disposed on both sides of the first bitline sense amplifier (BLSA1).

[0065] When the first bitline sense amplifier (BLSA1) is electrically connected to the first and fourth global bitlines (GBL_1, GBL_4) by the first bitline selection circuit (BLSC1) and is not electrically connected to the second and third global bitlines (GBL_2, GBL_3) by the first bitline selection circuit (BLSC1), the first bitline sense amplifier (BLSA1) can sense the voltage change amount of the first global bitline (GBL_1) and amplify it.

[0066] In the case where the first bitline sense amplifier (BLSA1) is not electrically connected to the first and fourth global bitlines (GBL_1, GBL_4) by the first bitline selection circuit (BLSC1) and is electrically connected to the second and third global bitlines (GBL_2, GBL_3) by the first bitline selection circuit (BLSC1), the first bitline sense amplifier (BLSA1) can sense the voltage change amount of the third global bitline (GBL_3) and amplify it.

[0068] An exemplary example in which each of the global bitlines (GBL) described above is connected to two local bitlines (LBL) will be explained with reference to FIGS. 4a and 4b. FIG. 4a is a conceptual diagram of a semiconductor device according to one embodiment, and FIG. 4b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0069] In one embodiment, referring to FIGS. 4a and 4b, each of the local bit lines (LBL) may be connected to memory cells (MC) arranged in the vertical direction (Z) among the memory cells (MC). Each of the local bit lines (LBL) may be in the shape of a pillar extending in the vertical direction (Z).

[0070] The above global bitlines (GBL) may include first global bitlines (GBL1a) and second global bitlines (GBL2a).

[0071] Each of the first global bitlines (GBL1a) may include a first bitline portion, and each of the second global bitlines (GBL2a) may include a second bitline portion positioned at a higher level than the first bitline portions of the first global bitlines (GBL1a). Each of the first global bitlines (GBL1a) may include a line portion positioned at a different level from the line portion of each of the second global bitlines (GBL2a). For example, the first global bitlines (GBL1a) may be positioned at a different level from the second global bitlines (GBL2a).

[0072] The second global bitlines (GBL2a) can be placed at a higher level than the first global bitlines (GBL1a).

[0073] Each of the first global bitlines (GBL1a) can be connected to two first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2a) can be connected to two second local bitlines (LBL2) among the local bitlines (LBL).

[0074] In one example, the semiconductor device (1) may further include bitline contact plugs (BLC1) and bitline contact structures (BLC2).

[0075] The bitline contact plugs (BLC1) may be positioned between the first local bitlines (LBL1) and the first global bitlines (GBL1a). Each of the first global bitlines (GBL1a) may be connected to the first local bitlines (LBL1) by the bitline contact plugs (BLC1). The bitline contact plugs (BLC1) may have a lower surface connected to the first local bitlines (LBL1) and an upper surface connected to the first global bitlines (GBL1a).

[0076] The bitline contact structures (BLC2) may be positioned between the second local bitlines (LBL2) and the second global bitlines (GBL2a). Each of the second global bitlines (GBL2a) may be connected to the second local bitlines (LBL2) by the bitline contact structures (BLC2).

[0077] Each of the bitline contact structures (BLC2) may include a lower contact plug (LLC), an intermediate contact plug (LMC) on the lower contact plug (LLC), and an upper contact plug (LUC) on the intermediate contact plug (LMC).

[0078] The lower contact plugs (LLC) may be positioned at the same level as the bitline contact plugs (BLC1). The lower contact plugs (LLC) may be formed of the same material as the bitline contact plugs (BLC1). The lower contact plugs (LLC) may be connected to the second local bitlines (LBL2).

[0079] The intermediate contact plugs (LMC) may be positioned at the same level as the first global bitlines (GBL1a). The intermediate contact plugs (LMC) may be formed of the same material as the first global bitlines (GBL1a). The intermediate contact plugs (LMC) may be connected to the lower contact plugs (LLC). The upper contact plugs (LUC) may be positioned between the second global bitlines (GBL2a) and the intermediate contact plugs (LMC). The upper contact plugs (LUC) may be connected to the second global bitlines (GBL2a) and the intermediate contact plugs (LMC).

[0080] The above routing wiring structures (RI) may include first routing wiring structures (RI1) each connected to the first global bitlines (GBL1a) and second routing wiring structures (RI2) each connected to the second global bitlines (GBL2a).

[0081] Each of the first routing wiring structures (RI1) may include a first lower routing wiring portion (RI1a). Each of the first lower routing wiring portions (RI1a) of the first routing wiring structures (RI1) may include a first plug pattern (BUC1) connected to a corresponding first global bit line among the first global bit lines (GBL1a), and a first pad pattern (PD1) positioned at a higher level than the global bit lines (GBL) and connected to the first plug pattern (BUC1).

[0082] Each of the first plug patterns (BUC1) may include a lower plug pattern (ULC), an intermediate plug pattern (UMC) disposed on the lower plug pattern (ULC) and connected to the lower plug pattern (ULC), and an upper plug pattern (UUC) disposed on the intermediate plug pattern (UMC) and connected to the intermediate plug pattern (UMC).

[0083] In each of the first plug patterns (BUC1), the lower plug pattern (ULC) may be connected to the corresponding first global bit line (GBL1a) among the first global bit lines (GBL1a), and the intermediate plug pattern (UMC) may be positioned at the same level as the second global bit lines (GBL2a). The intermediate plug patterns (UMC) may be formed of the same material as the second global bit lines (GBL2a).

[0084] Each of the first pad patterns (PD1) may include a first pad portion (PD1a) connected to a corresponding first plug pattern (BUC1) among the first plug patterns (BUC1) by overlapping it perpendicularly, a second pad portion (PD1b) extending from the first pad portion (PD1a), and a third pad portion (PD1c) extending from the second pad portion (PD1b). In each of the first pad patterns (PD1), the width of the third pad portion (PD1c) may be greater than the width of the second pad portion (PD1b). The third pad portions (PD1c) may not overlap perpendicularly with the first global bitlines (GBL1a).

[0085] Each of the second routing wiring structures (RI2) may include a second lower routing wiring portion (RI2a). Each of the second lower routing wiring portions (RI2a) of the second routing wiring structures (RI2) may include a second plug pattern (BUC2) connected to a corresponding second global bit line (GBL2a) among the second global bit lines (GBL2a), and a second pad pattern (PD2) positioned at a higher level than the global bit lines (GBL) and connected to the second plug pattern (BUC2).

[0086] The second plug patterns (BUC2) may be placed at the same level as the upper plug patterns (UUC). The second plug patterns (BUC2) may be formed of the same material as the upper plug patterns (UUC).

[0087] Each of the second pad patterns (PD2) may include a fourth pad portion (PD2a) connected by vertically overlapping with the corresponding second plug pattern (BUC2) among the second plug patterns (BUC2), a fifth pad portion (PD2b) extending from the fourth pad portion (PD2a), and a sixth pad portion (PD2c) extending from the fifth pad portion (PD2b). In each of the second pad patterns (PD2), the width of the sixth pad portion (PD2c) may be greater than the width of the fifth pad portion (PD2b). The sixth pad portions (PD2c) may not overlap vertically with the second global bitlines (GBL2a).

[0088] In one example, the first global bitlines (GBL1a) may include the first global bitline (GBL_1 in FIG. 2b) or the third global bitline (GBL_3 in FIG. 2b) described above. For example, the first global bitline (GBL_1 in FIG. 2b) and / or the third global bitline (GBL_3 in FIG. 2b) described above may be formed from the first global bitlines (GBL1a) as in FIG. 4a and FIG. 4b.

[0089] In one example, the second global bitlines (GBL2a) may comprise the second global bitline (GBL_2 in FIG. 2b) described above or the fourth global bitline (GBL_4 in FIG. 2b). For example, the second global bitline (GBL_2 in FIG. 2b) and / or the fourth global bitline (GBL_4 in FIG. 2b) described above may be formed from the second global bitlines (GBL2a) as in FIG. 4a and FIG. 4b.

[0091] An exemplary example in which each of the global bitlines (GBL) described above is connected to three local bitlines (LBL) will be explained with reference to FIGS. 5a and 5b. FIG. 5a is a conceptual drawing of a semiconductor device according to one embodiment, and FIG. 5b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0092] In one embodiment, with reference to FIGS. 5a and 5b, the first global bitlines (GBL1a) described in FIGS. 4a and 4b may be replaced with first global bitlines (GBL1b) as in FIGS. 5a and 5b, and the second global bitlines (GBL2a) described in FIGS. 4a and 4b may be replaced with second global bitlines (GBL2b) as in FIGS. 5a and 5b.

[0093] The first global bitlines (GBL1b) may be placed at a different level from the second global bitlines (GBL2b). The second global bitlines (GBL2b) may be placed at a higher level than the first global bitlines (GBL1b).

[0094] Each of the first global bitlines (GBL1b) can be connected to three first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2b) can be connected to three second local bitlines (LBL2) among the local bitlines (LBL).

[0095] Each of the first global bitlines (GBL1b) can be connected to the first local bitlines (LBL1) by the bitline contact plugs (BLC1) as described in FIGS. 4a and 4b.

[0096] Each of the second global bitlines (GBL2b) may be connected to the second local bitlines (LBL2) by bitline contact structures (BLC2) as described in FIGS. 4a and 4b. For example, as described in FIGS. 4a and 4b, each of the bitline contact structures (BLC2) may include the lower contact plug (LLC), the middle contact plug (LMC), and the upper contact plug (LUC). The first and second global bitlines (GBL1b, GBL2b) may be connected to the routing wiring structures (RI) as described in FIG. 4b.

[0098] An exemplary example in which each of the aforementioned global bitlines (GBL) described above is connected to four local bitlines (LBL) will be explained with reference to FIGS. 6a and 6b. FIG. 6a is a conceptual diagram of a semiconductor device according to one embodiment, and FIG. 6b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0099] In one embodiment, with reference to FIGS. 6a and 6b, the first global bitlines (GBL1a) described in FIGS. 4a and 4b may be replaced with first global bitlines (GBL1c) as in FIGS. 6a and 6b, and the second global bitlines (GBL2a) described in FIGS. 4a and 4b may be replaced with second global bitlines (GBL2c) as in FIGS. 6a and 6b.

[0100] The first global bitlines (GBL1c) may be placed at a different level from the second global bitlines (GBL2c). The second global bitlines (GBL2c) may be placed at a higher level than the first global bitlines (GBL1c).

[0101] Each of the first global bitlines (GBL1c) can be connected to four first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2c) can be connected to four second local bitlines (LBL2) among the local bitlines (LBL).

[0102] Each of the first global bitlines (GBL1c) can be connected to the first local bitlines (LBL1) by the bitline contact plugs (BLC1) as described in FIGS. 4a and 4b.

[0103] Each of the second global bitlines (GBL2c) may be connected to the second local bitlines (LBL2) by bitline contact structures (BLC2) as described in FIGS. 4a and 4b. For example, as described in FIGS. 4a and 4b, each of the bitline contact structures (BLC2) may include the lower contact plug (LLC), the middle contact plug (LMC), and the upper contact plug (LUC).

[0104] The first and second global bitlines (GBL1c, GBL2c) can be connected to the routing wiring structures (RI) as described in FIG. 4b.

[0106] An exemplary example in which the above global bitlines (GBL) are connected to three local bitlines (LBL) will be described with reference to FIGS. 7a and 7b. FIG. 7a is a conceptual diagram of a semiconductor device according to one embodiment, and FIG. 7b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0107] In one embodiment, with reference to FIGS. 7a and 7b, the first global bitlines (GBL1b) described in FIGS. 5a and 5b may be replaced with first global bitlines (GBL1d) as in FIGS. 7a and 7b, and the second global bitlines (GBL2b) described in FIGS. 5a and 5b may be replaced with second global bitlines (GBL2d) as in FIGS. 7a and 7b.

[0108] Each of the first global bitlines (GBL1d) can be connected to three first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2d) can be connected to three second local bitlines (LBL2) among the local bitlines (LBL).

[0109] Each of the above first global bitlines (GBL1d) may include a first-1 global bitline (GBL1d_1) and a first-2 global bitline (GBL1d_2) placed at different levels.

[0110] In each of the above first global bitlines (GBL1d), the first-1 global bitline (GBL1d_1) may be referred to as the first-1 bitline portion (GBL1d_1), and the first-2 global bitline (GBL1d_2) may be referred to as the first-2 bitline portion (GBL1d_2).

[0111] In each of the above first global bitlines (GBL1d), the first-2 bitline portion (GBL1d_2) may be placed at a higher level than the first-1 bitline portion (GBL1d_1).

[0112] In each of the above first global bitlines (GBL1d), the first-2 bitline portion (GBL1d_2) may have substantially the same length as the first-1 bitline portion (GBL1d_1).

[0113] In each of the first global bitlines (GBL1d), the first-1 bitline portion (GBL1d_1) and the first-2 bitline portion (GBL1d_2) can be vertically superimposed on the first local bitline (LBL1) located in the middle of the first local bitlines (LBL1) connected to the first global bitline (GBL1d), and can be electrically connected by the first intermediate contact plug (BLC3a).

[0114] In each of the first global bitlines (GBL1d), the first-1 bitline portion (GBL1d_1) may be connected to x first local bitlines (LBL1) among the first local bitlines (LBL1) by first bitline contact plugs (BLC1a), and the first-2 bitline portion (GBL1d_2) may be connected to y first local bitlines (LBL1) among the first local bitlines (LBL1) by first bitline contact structures (BLC2a). In one example, x and y may be different natural numbers. In one example, x may be 2 and y may be 1.

[0115] The first bitline contact plugs (BLC1a) may have the same shape and the same structure as the bitline contact plugs (BLC1) described in FIG. 4b. The first bitline contact structure (BLC2a) may have the same shape and the same structure as each of the bitline contact structures (BLC2) described in FIG. 4b.

[0116] Each of the above second global bitlines (GBL2d) may include a second-1 global bitline (GBL2d_1) and a second-2 global bitline (GBL2d_2) placed at different levels.

[0117] In each of the above-mentioned second global bitlines (GBL2d), the second-1 global bitline (GBL2d_1) may be referred to as the second-1 bitline portion (GBL2d_1), and the second-2 global bitline (GBL2d_2) may be referred to as the second-2 bitline portion (GBL2d_2).

[0118] In each of the above-mentioned second global bitlines (GBL2d), the second-1 bitline portion (GBL2d_1) may be placed at a higher level than the second-2 bitline portion (GBL2d_2).

[0119] In each of the above-mentioned second global bitlines (GBL2d), the second-1 bitline portion (GBL2d_1) may have substantially the same length as the second-2 bitline portion (GBL2d_2).

[0120] In each of the above-mentioned second global bitlines (GBL2d), the second-1 bitline portion (GBL2d_1) and the second-2 bitline portion (GBL2d_2) can be vertically superimposed on the second local bitline (LBL2) located in the middle of the second local bitlines (LBL2) connected to the second global bitline (GBL2d), and can be electrically connected by a second intermediate contact plug (BLC3b).

[0121] In each of the above-mentioned second global bitlines (GBL2d), the second-1 bitline portion (GBL2d_1) may be connected to the y first local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact structure (BLC2b), and the second-2 bitline portion (GBL2d_2) may be connected to the x second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact plugs (BLC1b). As previously explained, x may be 2 and y may be 1.

[0122] The second bitline contact plugs (BLC1b) may have the same shape and the same structure as the bitline contact plugs (BLC1) described in FIG. 4b. The second bitline contact structure (BLC2b) may have the same shape and the same structure as each of the bitline contact structures (BLC2) described in FIG. 4b.

[0123] The first and second global bitlines (GBL1d, GBL2d) can be connected to the routing wiring structures (RI).

[0124] Each of the first routing wiring structures (RI1) of the above routing wiring structures (RI) may include a third lower routing wiring portion (RI1aa). The third lower routing wiring portion (RI1aa) may be connected to the first-second bitline portion (GBL1d_2) of the first global bitline (GBL1d).

[0125] Each of the second routing wiring structures (RI2) of the routing wiring structures (RI) may include a fourth lower routing wiring portion (RI2aa). The fourth lower routing wiring portion (RI2aa) may be connected to the second-2 bitline portion (GBL2d_2) of the second global bitline (GBL2d).

[0126] The third lower routing wiring portion (RI1aa) may include a first plug pattern (BUC1a) connected to the first-2 bitline portion (GBL1d_2) of the first global bitline (GBL1d), and a first pad pattern (PD1) positioned at a higher level than the global bitlines (GBL) and connected to the first plug pattern (BUC1a) as described in FIG. 4b. The fourth lower routing wiring portion (RI2aa) may include a second plug pattern (BUC2a) connected to the second-2 bitline portion (GBL2d_2) of the second global bitline (GBL2d), and a second pad pattern (PD2) positioned at a higher level than the global bitlines (GBL) and connected to the second plug pattern (BUC2a) as described in FIG. 4b.

[0127] The first plug pattern (BUC1a) may have substantially the same shape and structure as the second plug pattern (BUC2) in FIG. 4b. The second plug pattern (BUC2a) may have substantially the same shape and structure as the first plug pattern (BUC1) in FIG. 4b.

[0129] An exemplary example in which the above global bitlines (GBL) are connected to four local bitlines (LBL) will be described with reference to FIGS. 8a and 8b. FIG. 8a is a conceptual drawing of a semiconductor device according to one embodiment, and FIG. 8b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0130] In one embodiment, with reference to FIGS. 8a and 8b, the first global bitlines (GBL1c) described in FIGS. 6a and 6b may be replaced with first global bitlines (GBL1e) as in FIGS. 8a and 8b, and the second global bitlines (GBL2c) described in FIGS. 6a and 6b may be replaced with second global bitlines (GBL2e) as in FIGS. 8a and 8b.

[0131] Each of the first global bitlines (GBL1e) can be connected to four first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2e) can be connected to four second local bitlines (LBL2) among the local bitlines (LBL).

[0132] Each of the above first global bitlines (GBL1e) may include a first-1 global bitline (GBL1e_1) and a first-2 global bitline (GBL1e_2) placed at different levels.

[0133] In each of the above first global bitlines (GBL1e), the first-1 global bitline (GBL1e_1) may be referred to as the first-1 bitline portion (GBL1e_1), and the first-2 global bitline (GBL1e_2) may be referred to as the first-2 bitline portion (GBL1e_2).

[0134] In each of the above first global bitlines (GBL1e), the first-2 bitline portion (GBL1e_2) may be placed at a higher level than the first-1 bitline portion (GBL1e_1).

[0135] In each of the above first global bitlines (GBL1e), the first-2 bitline portion (GBL1e_2) may have a length greater than the length of the first-1 bitline portion (GBL1e_1).

[0136] In each of the first global bitlines (GBL1e), the first-1 bitline portion (GBL1e_1) and the first-2 bitline portion (GBL1e_2) can be vertically superimposed on one first local bitline (LBL1) and can be electrically connected by a first intermediate contact plug (BLC3a).

[0137] In each of the first global bitlines (GBL1e), the first-1 bitline portion (GBL1e_1) may be connected to xa first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact plugs (BLC1a) as described in FIG. 7b, and the first-2 bitline portion (GBL1e_2) may be connected to ya first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact structures (BLC2a) as described in FIG. 7b. In one example, xa and ya may be the same natural number. In one example, xa and ya may each be 2.

[0138] Each of the above second global bitlines (GBL2e) may include a second-1 global bitline (GBL2e_1) and a second-2 global bitline (GBL2e_2) positioned at different levels.

[0139] In each of the above-mentioned second global bitlines (GBL2e), the second-1 global bitline (GBL2e_1) may be referred to as the second-1 bitline portion (GBL2e_1), and the second-2 global bitline (GBL2e_2) may be referred to as the second-2 bitline portion (GBL2e_2).

[0140] In each of the above-mentioned second global bitlines (GBL2e), the second-1 bitline portion (GBL2e_1) may be placed at a higher level than the second-2 bitline portion (GBL2e_2).

[0141] In each of the above-mentioned second global bitlines (GBL2e), the length of the second-1 bitline portion (GBL2e_1) may have a length smaller than the length of the second-2 bitline portion (GBL2e_2).

[0142] In each of the above-mentioned second global bitlines (GBL2e), the second-1 bitline portion (GBL2e_1) and the second-2 bitline portion (GBL2e_2) can be vertically superimposed on one second local bitline (LBL2) and can be electrically connected by a second intermediate contact plug (BLC3b).

[0143] In each of the above-mentioned second global bitlines (GBL2e), the second-1 bitline portion (GBL2e_1) may be connected to xb second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact structure (BLC2b) as described in FIG. 7b, and the second-2 bitline portion (GBL2e_2) may be connected to yb second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact plugs (BLC1b) as described in FIG. 7b. xb and yb may be different natural numbers. yb may be greater than xb. For example, yb may be 3 and xb may be 1.

[0144] The first and second global bitlines (GBL1e, GBL2e) may be connected to the routing wiring structures (RI). Each of the first routing wiring structures (RI1) of the routing wiring structures (RI) may include the third lower routing wiring portion (RI1aa) as described in FIG. 7b. The third lower routing wiring portion (RI1aa) may be connected to the first-2 bitline portion (GBL1e_2) of the first global bitline (GBL1e). The second routing wiring structures (RI2) of the routing wiring structures (RI) may include the fourth lower routing wiring portion (RI2aa) as described in FIG. 7b. The fourth lower routing wiring portion (RI2aa) may be connected to the second-2 bitline portion (GBL2e_2) of the second global bitline (GBL2e).

[0146] An exemplary example in which the above global bitlines (GBL) are connected to four local bitlines (LBL) will be described with reference to FIGS. 9a and 9b. FIG. 9a is a conceptual diagram of a semiconductor device according to one embodiment, and FIG. 9b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0147] In one embodiment, with reference to FIGS. 9a and 9b, the first global bitlines (GBL1c) described in FIGS. 6a and 6b may be replaced with first global bitlines (GBL1f) as in FIGS. 9a and 9b, and the second global bitlines (GBL2c) described in FIGS. 6a and 6b may be replaced with second global bitlines (GBL2f) as in FIGS. 9a and 9b.

[0148] Each of the first global bitlines (GBL1f) can be connected to four first local bitlines (LBL1) among the local bitlines (LBL), and each of the second global bitlines (GBL2f) can be connected to four second local bitlines (LBL2) among the local bitlines (LBL).

[0149] Each of the above first global bitlines (GBL1f) may include a first-1 global bitline (GBL1f_1) and a first-2 global bitline (GBL1f_2) placed at different levels.

[0150] In each of the above first global bitlines (GBL1f), the first-1 global bitline (GBL1f_1) may be referred to as the first-1 bitline portion (GBL1f_1), and the first-2 global bitline (GBL1f_2) may be referred to as the first-2 bitline portion (GBL1f_2).

[0151] In each of the above first global bitlines (GBL1f), the first-2 bitline portion (GBL1f_2) may be placed at a lower level than the first-1 bitline portion (GBL1f_1).

[0152] In each of the first global bitlines (GBL1f), the first-1 bitline portion (GBL1f_1) and the first-2 bitline portion (GBL1f_2) can be vertically superimposed on one first local bitline (LBL1) and can be electrically connected by a first intermediate contact plug (BLC3a).

[0153] In each of the first global bitlines (GBL1f), the first-1 bitline portion (GBL1f_1) may be connected to xc first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact structure (BLC2a) as described in FIG. 7b, and the first-2 bitline portion (GBL1f_2) may be connected to yc first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact plugs (BLC1a) as described in FIG. 7b. In one example, xc and yc may be different natural numbers. yc may be greater than xc. In one example, xc may be 1 and yc may be 3.

[0154] Each of the above second global bitlines (GBL2f) may include a second-1 global bitline (GBL2f_1) and a second-2 global bitline (GBL2f_2) placed at different levels.

[0155] In each of the above-mentioned second global bitlines (GBL2f), the second-1 global bitline (GBL2f_1) may be referred to as the second-1 bitline portion (GBL2f_1), and the second-2 global bitline (GBL2f_2) may be referred to as the second-2 bitline portion (GBL2f_2).

[0156] In each of the above-mentioned second global bitlines (GBL2f), the second-1 bitline portion (GBL2f_1) may be placed at a lower level than the second-2 bitline portion (GBL2f_2).

[0157] In each of the above-mentioned second global bitlines (GBL2f), the second-1 bitline portion (GBL2f_1) and the second-2 bitline portion (GBL2f_2) can be vertically superimposed on one second local bitline (LBL2) and can be electrically connected by a second intermediate contact plug (BLC3b).

[0158] In each of the above-mentioned second global bitlines (GBL2f), the second-1 bitline portion (GBL2f_1) may be connected to xd second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact plugs (BLC1b) as described in FIG. 7b, and the second-2 bitline portion (GBL2f_2) may be connected to yd second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact structures (BLC2b) as described in FIG. 7b. xd and yd may be the same natural number. For example, xd and yd may be 2.

[0159] The first and second global bitlines (GBL1f, GBL2f) may be connected to the routing wiring structures (RI). The first routing wiring structures (RI1) of the routing wiring structures (RI) may include the first lower routing wiring portion (RI1a) as described in FIG. 6b. The first lower routing wiring portion (RI1a) may be connected to the first-2 bitline portion (GBL1f_2) of the first global bitline (GBL1f). The second routing wiring structures (RI2) of the routing wiring structures (RI) may include the second lower routing wiring portion (RI2a) as described in FIG. 6b. The second lower routing wiring portion (RI2a) may be connected to the second-2 bitline portion (GBL2f_2) of the second global bitline (GBL2f).

[0161] An exemplary example in which the above global bitlines (GBL) are connected to four local bitlines (LBL) will be described with reference to FIGS. 10a and 10b. FIG. 10a is a conceptual drawing of a semiconductor device according to one embodiment, and FIG. 10b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0162] In one embodiment, with reference to FIGS. 10a and 10b, the first global bitlines (GBL1e) described in FIGS. 8a and 8b may be replaced with first global bitlines (GBL1g) as in FIGS. 10a and 10b, and the second global bitlines (GBL2e) described in FIGS. 8a and 8b may be replaced with second global bitlines (GBL2g) as in FIGS. 10a and 10b.

[0163] The first-1 bitline portion (GBL1e_1) described in FIGS. 8a and 8b may be replaced with a first-1 bitline portion (GBL1g_1) with increased length, and the first-2 bitline portion (GBL1e_2) described in FIGS. 8a and 8b may be replaced with a first-2 bitline portion (GBL1g_2) with decreased length. The length of the first-1 bitline portion (GBL1g_1) may be greater than the length of the first-2 bitline portion (GBL1g_2). Accordingly, each of the first global bitlines (GBL1g) may include the first-1 bitline portion (GBL1g_1) and the first-2 bitline portion (GBL1g_2).

[0165] In each of the first global bitlines (GBL1g), the first-1 bitline portion (GBL1g_1) and the first-2 bitline portion (GBL1g_2) can be vertically superimposed on one first local bitline (LBL1) and can be electrically connected by a first intermediate contact plug (BLC3a).

[0166] In each of the first global bitlines (GBL1g), the first-1 bitline portion (GBL1g_1) may be connected to xe first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact plugs (BLC1a) as described in FIG. 7b, and the first-2 bitline portion (GBL1g_2) may be connected to ye first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact structure (BLC2a) as described in FIG. 7b. xe may be greater than ye. In one example, xe may be 3 and ye may be 1.

[0168] The second-1 bitline portion (GBL2e_1) described in FIGS. 8a and 8b may be replaced with a second-1 bitline portion (GBL2g_1) with increased length, and the second-2 bitline portion (GBL2e_2) described in FIGS. 8a and 8b may be replaced with a second-2 bitline portion (GBL2g_2) with decreased length. The length of the second-1 bitline portion (GBL2g_1) may be greater than the length of the second-2 bitline portion (GBL2g_2). Accordingly, each of the second global bitlines (GBL2g) may include the second-1 bitline portion (GBL2g_1) and the second-2 bitline portion (GBL2g_2).

[0169] In each of the above-mentioned second global bitlines (GBL2g), the second-1 bitline portion (GBL2g_1) and the second-2 bitline portion (GBL2g_2) can be vertically superimposed on one second local bitline (LBL2) and can be electrically connected by a second intermediate contact plug (BLC3b).

[0170] In each of the above-mentioned second global bitlines (GBL2g), the second-1 bitline portion (GBL2g_1) may be connected to xf second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact structures (BLC2b) as described in FIG. 7b, and the second-2 bitline portion (GBL2g_2) may be connected to yf second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact plugs (BLC1b) as described in FIG. 7b. xf and yf may be the same natural number. For example, xf and yf may be 2.

[0171] The first and second global bitlines (GBL1g, GBL2g) may be connected to the routing wiring structures (RI). The first routing wiring structures (RI1) of the routing wiring structures (RI) may include the third lower routing wiring portion (RI1aa) as described in FIG. 8b. The third lower routing wiring portion (RI1aa) may be connected to the first-2 bitline portion (GBL1g_2) of the first global bitline (GBL1g). The second routing wiring structures (RI2) of the routing wiring structures (RI) may include the fourth lower routing wiring portion (RI2aa) as described in FIG. 8b. The fourth lower routing wiring portion (RI2aa) may be connected to the second-2 bitline portion (GBL2g_2) of the second global bitline (GBL2g).

[0173] An exemplary example in which the above global bitlines (GBL) are connected to four local bitlines (LBL) will be described with reference to FIGS. 11a and 11b. FIG. 11a is a conceptual drawing of a semiconductor device according to one embodiment, and FIG. 11b is a conceptual perspective view of a semiconductor device according to one embodiment.

[0174] In one embodiment, with reference to FIGS. 11a and 11b, the first global bitlines (GBL1f) described in FIGS. 9a and 9b may be replaced with first global bitlines (GBL1h) as in FIGS. 11a and 11b, and the second global bitlines (GBL2f) described in FIGS. 9a and 9b may be replaced with second global bitlines (GBL2h) as in FIGS. 11a and 11b.

[0175] The first-1 bitline portion (GBL1f_1) described in FIGS. 9a and 9b may be replaced with a first-1 bitline portion (GBL1h_1) with increased length, and the first-2 bitline portion (GBL1f_2) described in FIGS. 9a and 9b may be replaced with a first-2 bitline portion (GBL1h_2) with decreased length. The length of the first-1 bitline portion (GBL1h_1) may be greater than the length of the first-2 bitline portion (GBL1h_2). Accordingly, each of the first global bitlines (GBL1h) may include the first-1 bitline portion (GBL1h_1) and the first-2 bitline portion (GBL1h_2).

[0176] In each of the first global bitlines (GBL1h), the first-1 bitline portion (GBL1h_1) and the first-2 bitline portion (GBL1h_2) can be vertically superimposed on a first local bitline (LBL1) and can be electrically connected by a first intermediate contact plug (BLC3a).

[0177] In each of the first global bitlines (GBL1h), the first-1 bitline portion (GBL1h_1) may be connected to xg first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact structure (BLC2a) as described in FIG. 7b, and the first-2 bitline portion (GBL1h_2) may be connected to yg first local bitlines (LBL1) among the first local bitlines (LBL1) by the first bitline contact plugs (BLC1a) as described in FIG. 7b. In one example, xg and yg may be 2.

[0178] The second-1 bitline portion (GBL2f_1) described in FIGS. 9a and 9b may be replaced with a second-1 bitline portion (GBL2h_1) with increased length, and the second-2 bitline portion (GBL2f_2) described in FIGS. 9a and 9b may be replaced with a second-2 bitline portion (GBL2h_2) with decreased length. The length of the second-1 bitline portion (GBL2h_1) may be greater than the length of the second-2 bitline portion (GBL2h_2). Accordingly, each of the second global bitlines (GBL2h) may include the second-1 bitline portion (GBL2h_1) and the second-2 bitline portion (GBL2h_2).

[0179] In each of the above-mentioned second global bitlines (GBL2h), the second-1 bitline portion (GBL2h_1) and the second-2 bitline portion (GBL1h_2) can be vertically superimposed on one second local bitline (LBL2) and can be electrically connected by a second intermediate contact plug (BLC3b).

[0180] In each of the above-mentioned second global bitlines (GBL2h), the second-1 bitline portion (GBL2h_1) may be connected to xh second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact plugs (BLC1b) as described in FIG. 7b, and the second-2 bitline portion (GBL2h_2) may be connected to yh second local bitlines (LBL2) among the second local bitlines (LBL2) by the second bitline contact structure (BLC2b) as described in FIG. 7b. In one example, xh may be 3 and yh may be 1.

[0181] The first and second global bitlines (GBL1h, GBL2h) may be connected to the routing wiring structures (RI). The first routing wiring structures (RI1) of the routing wiring structures (RI) may include the first lower routing wiring portion (RI1a) as described in FIG. 6b. The first lower routing wiring portion (RI1a) may be connected to the first-2 bitline portion (GBL1h_2) of the first global bitline (GBL1h). The second routing wiring structures (RI2) of the routing wiring structures (RI) may include the second lower routing wiring portion (RI2a) as described in FIG. 6b. The second lower routing wiring portion (RI2a) may be connected to the second-2 bitline portion (GBL2h_2) of the second global bitline (GBL2h).

[0183] Next, with reference to FIGS. 12, FIGS. 13a, FIGS. 13b, and FIGS. 14, a structure including the local bit lines (LBL) and the memory cells (MC) in a semiconductor device (1) according to the embodiments described above will be described. In FIGS. 12, FIGS. 13a, FIGS. 13b, and FIGS. 14, FIGS. 12 is a plan view showing the local bit lines (LBL) described above, FIGS. 13a is a cross-sectional view showing an area taken along the line I-I' of FIGS. 12, FIGS. 13b is a partial enlarged view showing an area marked 'A' in FIGS. 13a, and FIGS. 14 is a perspective view showing a part of the structure including the local bit lines (LBL) and the memory cells (MC).

[0184] Referring to FIGS. 12, FIGS. 13a, FIGS. 13b, and FIGS. 14, the first structure (ST1 in FIG. 1) of the semiconductor device (1) described above may include a lower structure (LS).

[0185] The above substructure (LS) may include the local bitlines (LBL) and memory cells (MC) described in the preceding embodiments.

[0186] The above-described substructure (LS) may include a base (3) and active patterns (9) disposed on the base (3). The base (3) may be a semiconductor substrate, but embodiments are not limited thereto. For example, the base (3) may be an insulating substrate.

[0187] The active patterns (9) may be formed of a semiconductor material that can be used as a channel region of a transistor. For example, each of the active patterns (9) may include a single-crystal silicon semiconductor, an oxide semiconductor, or a two-dimensional material having semiconductor properties. Each of the active patterns (9) may be bar-shaped extending in a first horizontal direction (X). Each of the active patterns (9) may include a first source / drain region (SD1) and a second source / drain region (SD2) spaced apart from each other in the first horizontal direction (X), and a channel region (cCH) between the first and second source / drain regions (SD1, SD2).

[0188] The above substructure (LS) may include cell gate electrodes (GE) that overlap perpendicularly with the channel regions (cCH), and cell gate dielectric layers (15) between the cell gate electrodes (GE) and the channel regions (cCH). The cell gate electrodes (GE) may be stacked and spaced apart from each other in the vertical direction (Z). Each of the cell gate electrodes (GE) may extend in the second horizontal direction (Y) perpendicular to the first horizontal direction (X), surrounding a corresponding channel region (cCH) among the channel regions (cCH). The cell gate electrodes (GE) may be word lines.

[0189] The first and second horizontal directions (X, Y) may be parallel to the upper surface of the base (3). The vertical direction (Z) may be perpendicular to the upper surface of the base (3).

[0190] In the embodiments, each of the memory cells (MC) described above may include a cell transistor (cTR) and an information storage structure (DS). The information storage structure (DS) may be a cell capacitor capable of storing information in a memory such as a DRAM.

[0191] In the embodiments, each of the cell transistors (cTR) may include the channel region (cCH), the first and second source / drain regions (SD1, SD2), the cell gate dielectric layer (15), and the cell gate electrode (GE).

[0192] In the embodiments, each of the information storage structures (DS) may include a first electrode (30) connected to a corresponding second source / drain region (SD2) among the second lower source / drain regions (SD2), a second electrode (36) covering the first electrode (30), and a dielectric layer (32) between the first electrode (30) and the second electrode (36). The second electrodes (36) may be plate electrodes.

[0193] In each of the above information storage structures (DS), the first electrode (30) may be in the shape of a column extending in the first horizontal direction (X), and the second electrode (36) may include a first electrode material layer (34) in contact with the dielectric layer (32) and a second electrode material layer (35) in contact with the first electrode material layer (34). In an embodiment, the first electrode (30) is not limited to the shape of a column. For example, the first electrode (30) may be in the shape of a cylinder.

[0194] In the information storage structures (DS) above, the lower surface of each of the second electrodes (36) may be positioned at a level lower than the lowest cell transistor among the cell transistors (cTR), and the upper surface of each of the second electrodes (36) may be positioned at a level higher than the highest cell transistor among the cell transistors (cTR). Each of the second electrodes (36) may extend in the second horizontal direction (Y).

[0195] The memory cells (MC), including the cell transistors (cTR) and the information storage structures (DS), can be arranged three-dimensionally along the vertical direction (Z), the first horizontal direction (X), and the second horizontal direction (Y) which are perpendicular to each other.

[0196] The lower structure (LS) may include a lower insulating structure (21) disposed on the base (3) and on the sides of the second electrodes (36). The cell transistors (cTR) may be embedded within the lower insulating structure (21).

[0197] The above substructure (LS) may include a capping insulating layer (24) disposed on the insulating structure (21) and between the second electrodes (36). The above substructure (LS) may include an insulating layer (4) between the local bit lines (LBL) and the base (3).

[0198] Each of the above local bitlines (LBL) may extend in the vertical direction (Z). For example, each of the above local bitlines (LBL) may be in the shape of a column extending in the vertical direction (Z).

[0199] In a plane, the local bit lines (LBL) can be arranged along the first horizontal direction (X) and the second horizontal direction (Y) which are perpendicular to each other.

[0200] The sides of the above local bitlines (LBL) can be connected to the memory cells (MC).

[0201] The sides of the above local bitlines (LBL) can be connected to the first source / drain regions (cSD1) of the cell transistors (cTR) of the first memory cells (MC).

[0202] The above local bitlines (LBL) may have recessed sides in contact with the memory cells (MC).

[0203] Each of the above local bitlines (LBL) may be pillar-shaped, extending from a level lower than the channel region (cCH) of the cell transistor (cTR) of the lowest memory cell (MC) to a level higher than the channel region (cCH) of the cell transistor (cTR) of the highest memory cell (MC).

[0204] Each of the above local bitlines (LBL) may include a pillar pattern (107b) and a conductive liner (107a) covering the side and bottom surfaces of the pillar pattern (107b). The conductive liner (107a) may include at least one of doft polysilicon, a metal-semiconductor compound, and a metal nitride. For example, the conductive liner (107a) may include at least one of Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, and CoSi, and the pillar pattern (107b) may include a material different from the material of the conductive liner (107a) and may include at least one of Dought polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, and CoSi.

[0206] Next, with reference to FIGS. 15, 16, and 17, a structure further comprising global bitlines (GBL) and peripheral circuits in the structure previously described with reference to FIGS. 12, 13a, 13b, and 14 will be described. In FIGS. 15, 16, and 17, FIG. 15 is a plan view showing the planar shape of local bitlines (LBL) and global bitlines (GBL) according to one embodiment, FIG. 16 is a partial enlarged view of the area marked 'B' in FIG. 15, and FIG. 17 is a cross-sectional view showing the area taken along the line I-I' in FIG. 16, which is a cross-sectional view further comprising global bitlines (GBL) and peripheral circuits in the cross-sectional structure of FIG. 13a. The planar shape of the first global bitlines (GBL1a) and the second global bitlines (GBL2a) described in FIGS. 4a and 4b may be the same as the planar shape of the global bitlines (GBL) in FIGS. 15 and 16. Here, the components described in FIGS. 4a and 4b, FIG. 12, FIG. 13a, FIG. 13b, and FIG. 14 are described by omitting separate descriptions or by direct citation, and the description will focus on the planar shape of the first global bitlines (GBL1a) and the second global bitlines (GBL2a) and an exemplary example of the second structure (STC2).

[0207] With reference to FIGS. 15 through 17, together with FIGS. 4a and 4b, FIGS. 12, FIGS. 13a, FIGS. 13b, and FIGS. 14, each of the first global bitlines (GBL1a) described in FIGS. 4a and 4b may extend in a first direction (D1). For example, each of the first global bitlines (GBL1a) may be in the shape of a line or a bar extending in the first direction (D1). Each of the second global bitlines (GBL2a) described in FIGS. 4a and 4b may extend in a second direction (D2). For example, each of the second global bitlines (GBL2a) may be in the shape of a line or a bar extending in the second direction (D1).

[0208] The first direction (D1) may be parallel to the upper surface of the base (3). The first direction (D1) may intersect the first horizontal direction (X) and the second horizontal direction (Y).

[0209] The second direction (D2) may be parallel to the upper surface of the base (3). The second direction (D2) may intersect the first direction (D1), the first horizontal direction (X), and the second horizontal direction (Y).

[0210] In a plane, the first global bitlines (GBL1a) may intersect with the second global bitlines (GBL2a). For example, among the first global bitlines (GBL1a) and the second global bitlines (GBL2a), the first global bitline (GBL1a) and the second global bitline (GBL2a) that are adjacent to each other in the vertical direction (Z) may intersect each other when viewed in a planar view such as FIGS. 15 and FIGS. 16.

[0211] The first structure (STC1) may further include a lower insulating structure (118) disposed on the lower structure (LS). The bitline contact plugs (BLC1), bitline contact structures (BLC2), global bitlines (GBL), the first lower routing wiring portions (RI1a), and the second lower routing wiring portions (RI2a) described in FIGS. 4a and 4b may be embedded within the lower insulating structure (118).

[0212] As described in FIGS. 4a and 4b, the third pad portions (PD1c) and the sixth pad portions (PD2c) may not overlap perpendicularly with the global bitlines (GBL).

[0213] In the embodiments, the three local bit lines (LBL) arranged sequentially in the first horizontal direction (X) may each be connected to three spaced-apart global bit lines (GBL) among the global bit lines (GBL). For example, as shown in FIG. 16, among the three local bit lines (LBL) arranged sequentially in the first horizontal direction (X), the first local bit line (LBL) may be a second local bit line (LBL2) connected to a second global bit line (GBL2a), the second local bit line (LBL) may be a first local bit line (LBL1) connected to a first global bit line (GBL1a), and the third local bit line (LBL) may be a second local bit line (LBL2) connected to a second global bit line (GBL2a).

[0214] The above local bitlines (LBL) may include a second local bitline (LBL2), a first local bitline (LBL1), a second local bitline (LBL2), and a first local bitline (LBL1) arranged in sequence in the first horizontal direction (X).

[0215] In the embodiments, the four local bitlines (LBL) arranged in sequence in the first horizontal direction (X) can each be connected to four spaced-apart global bitlines (GBL) among the global bitlines (GBL).

[0216] The second structure (STC2) may include a rear insulating layer (133), a substrate (121) on the rear insulating layer (133), peripheral circuits (BLSA, BLSC) disposed on the substrate (121), and an upper insulating structure (150) covering the peripheral circuits (BLSA, BLSC) on the substrate (121). The substrate (121) may be a semiconductor substrate or a semiconductor body.

[0217] The lower insulating structure (118) of the first structure (STC1) and the rear insulating layer (133) of the second structure (STC2) are joined, so that a joining region (JUN) can be formed between the first structure (STC1) and the second structure (STC2).

[0218] The second structure (STC2) may include a plurality of peripheral active regions (124a) that can be defined by device isolation regions (124s) on the substrate (121).

[0219] The above peripheral circuits (BLSA, BLSC) may include the bitline sense amplifiers (BLSA) and bitline select circuits (BLSC) described in FIG. 2a and 2b.

[0220] Each of the sense amplifier transistors (P1_a, P1_b, N1_a, N1_b) constituting the bitline sense amplifiers (BLSA) described in FIG. 2b may include a peripheral source / drain region (pSDa) disposed within the peripheral active region (124a), a peripheral channel region (pCHa) between the peripheral source / drain region (pSDa), a peripheral gate electrode (pGEa) on the peripheral channel region (pCHa), and a peripheral gate dielectric layer (pGoxa) between the peripheral gate electrode (pGEa) and the peripheral channel region (pCHa). The peripheral source / drain regions (pSDa) of the first NMOS transistor (N1_a) and the second NMOS transistor (N1_b) described in FIG. 2b may have an N-type conductivity, and the peripheral source / drain regions (pSDa) of the first P-MOS transistor (P1_a) and the second P-MOS transistor (P1_b) may have a P-type conductivity.

[0221] Each of the selection transistors (ST) constituting the bitline selection circuits (BLSC) described in FIG. 2b may include peripheral source / drain regions (pSDb) disposed within the peripheral active region (124a), a peripheral channel region (pCHb) between the peripheral source / drain regions (pSDb), a peripheral gate electrode (pGEb) on the peripheral channel region (pCHb), and a peripheral gate dielectric layer (pGoxb) between the peripheral gate electrode (pGEb) and the peripheral channel region (pCHb).

[0222] The above second structure (STC2) may include upper routing wiring portions (140). Among the upper routing wiring portions (140), the upper routing wiring portion connected to the first lower routing wiring portion (RI1a) may constitute the first routing wiring structure (RI1). Among the upper routing wiring portions (140), the upper routing wiring portion connected to the second lower routing wiring portion (RI2a) may constitute the second routing wiring structure (RI2).

[0223] Each of the upper routing wiring portions (140) may include a through electrode (143) penetrating the substrate (121) and a connecting wire (146) electrically connecting the through electrode (143) and the selection transistor (ST) of the bitline selection circuit (BLSC) on the substrate (121). The through electrode (143) may be spaced apart from the substrate (121) by an insulating spacer (138) on the side of the through electrode (143).

[0224] The through electrode (143) of the upper routing wiring portion (140) constituting the first routing wiring structure (RI1) can be connected to the third pad portion (PD1c), and the through electrode (143) of the upper routing wiring portion (140) constituting the second routing wiring structure (RI2) can be connected to the sixth pad portion (PD2c).

[0225] The global bitlines (GBL) can be electrically connected to the bitline selection circuits (BLSC) by routing wiring structures (RI) including the first and second routing wiring structures (RI1, RI2).

[0227] Next, with reference to FIGS. 18a and 18b, an exemplary example of the planar shape of the first global bitlines (GBL1b) and the second global bitlines (GBL2b) described in FIGS. 5a and 5b above will be described. FIG. 18a is a plan view showing the planar shape of local bitlines (LBL) and global bitlines (GBL) according to one embodiment, and FIG. 18b is a partial enlarged view of the area marked 'C' in FIG. 18a. Hereinafter, the components indicating directions, such as the first direction (D1), the second direction (D2), the vertical direction (Z), the first horizontal direction (X), and the second horizontal direction (Y) described in FIGS. 15 and 16, will be cited directly without further explanation.

[0228] With reference to FIGS. 18a and FIGS. 18b together with FIGS. 5a and 5b, each of the first global bitlines (GBL1b) described in FIGS. 5a and 5b may include a first-1 bitline portion (GBL1b_1) extending in the first direction (D1) and a first-2 bitline portion (GBL1b_2) extending from the first-1 bitline portion (GBL1b_1) to the second direction (D2). Each of the second global bitlines (GBL2b) described in FIGS. 5a and 5b may include a second-1 bitline portion (GBL2b_1) extending in the first direction (D1) and a second-2 bitline portion (GBL2b_2) extending from the second-1 bitline portion (GBL2b_1) to the second direction (D2).

[0229] In a plane, the first global bitlines (GBL1b) may intersect with the second global bitlines (GBL2b). For example, among the first global bitlines (GBL1b) and the second global bitlines (GBL2b), the first global bitline (GBL1b) and the second global bitline (GBL2b) that are adjacent to each other in the vertical direction (Z) may intersect each other when viewed in a planar view such as FIG. 18a and FIG. 18b. For example, among the first global bitline (GBL1b) and the second global bitline (GBL2b), the first-1 bitline portion (GBL1b_1) and the second-2 bitline portion (GBL2b_2) may intersect each other. Hereinafter, the first global bitline (GBL1b) and the second global bitline (GBL2b) that are adjacent to each other in the vertical direction (Z) will be described with an emphasis on them.

[0230] The three first local bitlines (LBL1) connected to the first global bitline (GBL1b) may include a first-1 local bitline (LBL1_1), a first-2 local bitline (LBL1_2), and a first-3 local bitline (LBL1_3). The first-1 local bitline (LBL1_1) and the first-3 local bitline (LBL1_3) may be connected to both ends of the first global bitline (GBL1b), and the first-2 local bitline (LBL1_2) may be connected to the middle part of the first global bitline (GBL1b). The first-2 local bitline (LBL1_2) may be connected to the first global bitline (GBL1b) in the area between the first-1 bitline portion (GBL1b_1) and the first-2 bitline portion (GBL1b_2). The first global bitline (GBL1b) may have a bent portion between the first-1 bitline portion (GBL1b_1) and the first-2 bitline portion (GBL1b_2).

[0231] The three second local bitlines (LBL2) connected to the second global bitline (GBL2b) may include a second-1 local bitline (LBL2_1), a second-2 local bitline (LBL2_2), and a second-3 local bitline (LBL2_3). The second-1 local bitline (LBL2_1) and the second-3 local bitline (LBL2_3) may be connected to both ends of the second global bitline (GBL2b), and the second-2 local bitline (LBL2_2) may be connected to the middle part of the second global bitline (GBL2b). The second-2 local bitline (LBL2_2) may be connected to the second global bitline (GBL2b) in the area between the second-1 bitline portion (GBL2b_1) and the second-2 bitline portion (GBL2b_2). The above second global bit line (GBL2b) may have a bent portion between the above second-1 bit line portion (GBL2b_1) and the above second-2 bit line portion (GBL2b_2).

[0232] In the embodiments, the three local bitlines (LBL) arranged in sequence in the first horizontal direction (X) can each be connected to three spaced-apart global bitlines (GBL) among the global bitlines (GBL).

[0233] In the embodiments, the four local bitlines (LBL) arranged in sequence in the first horizontal direction (X) can each be connected to four spaced-apart global bitlines (GBL) among the global bitlines (GBL).

[0234] In the embodiments, among the five local bit lines (LBL) arranged in order in the first horizontal direction (X), the first local bit line (LBL) and the fifth local bit line (LBL) can be connected to one global bit line (GBL), and the remaining local bit lines (LBL) can each be connected to three different global bit lines (GBL).

[0236] Next, with reference to FIGS. 19a and 19b, an exemplary example of the planar shape of the first global bitlines (GBL1d) and the second global bitlines (GBL2d) described in FIGS. 7a and 7b above will be described. FIG. 19a is a plan view showing the planar shape of local bitlines (LBL) and global bitlines (GBL) according to one embodiment, and FIG. 19b is a partial enlarged view of the area marked 'D' in FIG. 19a.

[0237] With reference to FIGS. 19a and FIGS. 19b together with FIGS. 7a and 7b, the first-1 bitline portion (GBL1d_1) described in FIG. 7b may have substantially the same planar shape as the first-1 bitline portion (GBL1b_1) described in FIGS. 18a and 18b, and the first-2 bitline portion (GBL1d_2) described in FIG. 7b may have substantially the same planar shape as the first-2 bitline portion (GBL1b_2) described in FIGS. 18a and 18b. The second-1 bitline portion (GBL2d_1) described in FIG. 7b may have substantially the same planar shape as the second-1 bitline portion (GBL2b_1) described in FIG. 18a and FIG. 18b, and the second-2 bitline portion (GBL2d_2) described in FIG. 7b may have substantially the same planar shape as the second-2 bitline portion (GBL1b_2) described in FIG. 18a and FIG. 18b.

[0239] Next, with reference to FIGS. 20a and 20b, an exemplary example of the planar shape of the first global bitlines (GBL1c) and the second global bitlines (GBL2c) described in FIGS. 6a and 6b above will be described. FIG. 20a is a plan view showing the planar shape of local bitlines (LBL) and global bitlines (GBL) according to one embodiment, and FIG. 20b is a partial enlarged view of the area marked 'E' in FIG. 20a.

[0240] Referring to FIGS. 20a and FIGS. 20b together with FIGS. 6a and 6b, each of the first global bitlines (GBL1c) described in FIGS. 6a and 6b may include a first-1 bitline portion (GBL1c_1) and a first-2 bitline portion (GBL1c_2) having the same planar shape as the first-1 bitline portion (GBL1b_1) and the first-2 bitline portion (GBL1b_1) described in FIGS. 18a and 18b, and may include a first-3 bitline portion (GBL1c_3) extending from the first-2 bitline portion (GBL1c_2) in the second direction (D2) as in FIG. 20b. The first-1 bitline portion (GBL1c_1) and the first-3 bitline portion (GBL1c_3) may be parallel to each other.

[0241] Each of the second global bitlines (GBL2c) described in FIGS. 6a and 6b may include a second-1 bitline portion (GBL2c_1) and a second-2 bitline portion (GBL2c_2) having the same planar shape as the second-1 bitline portion (GBL2b_1) and the second-2 bitline portion (GBL2b_1) described in FIGS. 18a and 18b, and may include a second-3 bitline portion (GBL2c_3) extending from the second-2 bitline portion (GBL2c_2) in the second direction (D2) as in FIG. 20b. The second-1 bitline portion (GBL2c_1) and the second-3 bitline portion (GBL2c_3) may be parallel to each other.

[0242] In a plane, the first global bitlines (GBL1c) may intersect with the second global bitlines (GBL2c). For example, among the first global bitlines (GBL1c) and the second global bitlines (GBL2c), the first global bitline (GBL1c) and the second global bitline (GBL2c) that are adjacent to each other in the vertical direction (Z) may intersect each other when viewed in a planar view such as FIG. 20a and FIG. 20b. For example, in the first global bitline (GBL1c) and the second global bitline (GBL2c), the first-1 bitline portion (GBL1c_1) and the second-2 bitline portion (GBL2c_2) may intersect each other, and the first-2 bitline portion (GBL1c_2) may intersect with the second-3 bitline portion (GBL2c_3).

[0243] The four first local bitlines (LBL1) connected to the first global bitline (GBL1c) may include a first-1 local bitline (LBL1_1), a first-2 local bitline (LBL1_2), a first-3 local bitline (LBL1_3), and a first-4 local bitline (LBL1_4).

[0244] The first global bit line (GBL1c) may have a folded portion between the first-1 bit line portion (GBL1c_1) and the first-2 bit line portion (GBL1c_2), and may have a folded portion between the first-2 bit line portion (GBL1c_2) and the first-3 bit line portion (GBL1c_3).

[0245] The four second local bitlines (LBL2) connected to the second global bitline (GBL2c) may include a second-1 local bitline (LBL2_1), a second-2 local bitline (LBL2_2), a second-3 local bitline (LBL2_3), and a second-4 local bitline (LBL2_4). The second global bitline (GBL2c) may have a bend portion between the second-1 bitline portion (GBL2c_1) and the second-2 bitline portion (GBL2c_2), and may have a bend portion between the second-2 bitline portion (GBL2c_2) and the second-3 bitline portion (GBL2c_3).

[0246] With reference to FIGS. 8a, 8b, 9a, 9b, 10a, 10b, 11a, and 11b, the planar shape of the global bitlines (GBL) described above may be substantially the same as the planar shape of the global bitlines (GBL) described in FIGS. 20a and 20b.

[0248] In the embodiments described above, the bitline sense amplifiers (BLSA) and the bitline select circuits (BLSC) may be placed at the same level, but the embodiments are not limited thereto. An exemplary example in which the bitline sense amplifiers (BLSA) and the bitline select circuits (BLSC) are placed at different levels will be described with reference to FIG. 21. FIG. 21 is a diagram illustrating an exemplary example in which the bitline sense amplifiers (BLSA) and the bitline select circuits (BLSC) are placed at different levels.

[0249] Referring to FIG. 21, a first structure (S1) including the memory cells (MC), local bitlines (LBL), and global bitlines (GBL) described above may be disposed. A second structure (S2) including the bitline selection circuits (BLSC) described above may be disposed on the first structure (S1). A third structure (S3) including the bitline sense amplifiers (BLSA) described above may be disposed on the second structure (S2). Accordingly, the bitline selection circuits (BLSC) may be disposed at a higher level than the first structure (S1), and the bitline sense amplifiers (BLSA) may be disposed at a higher level than the bitline selection circuits (BLSC).

[0251] In the embodiments described above, the bitline selection circuits (BLSC) may be omitted. An exemplary example in which the bitline selection circuits (BLSC) are omitted will be described with reference to FIG. 22. FIG. 22 is a diagram showing an exemplary example in which the bitline selection circuits (BLSC) in FIG. 2a are omitted.

[0252] Referring to FIG. 22, the bitline selection circuits (BLSC) in FIG. 2a are omitted, and each of the bitline sense amplifiers (BLSA) can be connected to a pair of global bitlines (GBL).

[0254] Next, a method for manufacturing a semiconductor device according to embodiments will be described with reference to FIGS. 23 to 28. In FIGS. 23 to 28, FIGS. 23 and 24 are process flow diagrams for describing a method for manufacturing a semiconductor device according to embodiments, and FIGS. 25 to 28 are cross-sectional views showing a region taken along the line I-I' of FIG. 16.

[0255] Referring to FIGS. 23, 24, and FIGS. 25 through 27, a first structure (STC1) including memory cells (MC), local bit lines (LBL), and global bit lines (GBL) can be formed (S100). Forming the first structure (STC1) (S100) may include forming a lower structure (LS) including the memory cells (MC) and the local bit lines (LBL) (S10), forming first global bit lines (GBL1a) (S20), forming second global bit lines (GBL2a) positioned at a higher level than the first global bit lines (GBL1a) (S30), and forming lower routing wiring portions (RI1a, RI2a) (S40).

[0256] The above-mentioned substructure (LS) may be substantially the same as described in FIG. 13a and FIG. 13b. For example, the memory cells (MC) may be connected to the local bit lines (LBL), and each of the memory cells (MC) may include the cell transistor (cTR) and the information storage structure (DS) as described in FIG. 13b. Accordingly, the components illustrated in FIG. 25 through 27 may be described as the components described in FIG. 13a and FIG. 13b.

[0257] The first global bitlines (GBL1a) may be formed within a lower insulating structure (118) formed on the lower structure (LS). The second global bitlines (GBL2a) may be formed at a higher level than the first global bitlines (GBL1a) after the first global bitlines (GBL1a) have been formed.

[0258] The above lower routing wiring portions (RI1a, RI2a) may include a first lower routing wiring portion (RI1a) connected to the first global bitlines (GBL1a) and a second lower routing wiring portion (RI2a) connected to the second global bitlines (GBL2a).

[0259] On the above substructure (LS), the first and second global bit lines (GBL1a, GBL2a) and the lower routing wiring parts (RI1a, RI2a) that are placed at the same level can be formed simultaneously by the same process.

[0260] The first and second global bit lines (GBL1a, GBL2a) and the lower routing wiring portions (RI1a, RI2a) may be formed within a lower insulating structure (118) formed on the lower structure (LS).

[0261] Referring to FIGS. 23 and 28, a second preliminary structure (STC2a) including peripheral circuits can be formed (S200). The second preliminary structure (STC2a) may include peripheral transistors (pTRa, pTRb) formed on a substrate (121), an insulating layer (150a) covering the peripheral transistors (pTRa, pTRb) on the substrate (121), and a rear insulating layer (133) on the lower part of the substrate (121). The peripheral transistors (pTRa, pTRb) may be transistors for forming the peripheral circuits (BLSA, BLSC) described in FIG. 17.

[0262] A bonded structure (STC1, ST2a) can be formed by bonding the first structure (STC1) and the second prefabricated structure (STC2a) through a wafer bonding process (S300). The lower insulating structure (118) of the first structure (STC1) and the rear insulating layer (133) of the second prefabricated structure (STC2a) can be bonded to form a bonded region (JUN).

[0263] A wiring process can be performed (S400). Performing the wiring process may include forming the upper routing wiring portions (140) described in FIG. 17 and forming connecting wirings (146) for circuit connection. Thus, the second structure (STC2) described in FIG. 17 can be formed. Thus, the first and second structures (STC1, STC2) joined together as described in FIG. 17 can be formed.

[0264] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 Memory cells arranged three-dimensionally along mutually perpendicular vertical directions, a first horizontal direction, and a second horizontal direction; local bit lines connected to the memory cells and positioned at the same level as each other; and global bit lines positioned at a level higher than the local bit lines and connected to the local bit lines, wherein each of the memory cells includes a cell transistor having a cell gate electrode extending in the second horizontal direction, and an information storage structure, and the global bit lines include first global bit lines connected to N first local bit lines among the local bit lines; A semiconductor device comprising: second global bitlines connected to N second local bitlines among the local bitlines, wherein N is a natural number greater than or equal to 2, each of the first global bitlines includes a first bitline portion, each of the second global bitlines includes a second bitline portion positioned at a higher level than the first bitline portions of the first global bitlines, and three local bitlines arranged sequentially in the first horizontal direction among the local bitlines are each connected to three global bitlines spaced apart from each other among the global bitlines. Claim 2 A semiconductor device according to claim 1, further comprising: bitline contact plugs disposed between the first global bitlines and the first local bitlines and electrically connecting the first global bitlines and the first local bitlines; and bitline contact structures disposed between the second global bitlines and the second local bitlines and electrically connecting the second global bitlines and the second local bitlines. Claim 3 A semiconductor device according to claim 2, wherein each of the bitline contact structures comprises: a lower contact plug disposed at the same level as the bitline contact plugs and connected to a corresponding second local bitline among the second local bitlines; an intermediate contact plug disposed at the same level as the first global bitlines and connected to the lower contact plug; and an upper contact plug disposed between a corresponding second global bitline among the second global bitlines and the intermediate contact plug. Claim 4 A semiconductor device according to claim 1, further comprising: bitline sense amplifiers positioned at a higher level than the global bitlines; routing wiring structures configured to electrically connect the global bitlines and the bitline sense amplifiers; and global bitline select circuits connected to the bitline sense amplifiers, wherein the bitline sense amplifiers include sense amplifier transistors, and the global bitline select circuits include select transistors positioned at the same level as the sense amplifier transistors. Claim 5 Memory cells arranged three-dimensionally along mutually intersecting vertical directions, a first horizontal direction, and a second horizontal direction; local bitlines connected to the memory cells and positioned at the same level; global bitlines positioned at a level higher than the local bitlines and connected to the local bitlines; bitline sense amplifiers positioned at a level higher than the global bitlines; A semiconductor device comprising bitline sense amplifiers and global bitline selection circuits connected to the global bitlines, wherein each of the global bitlines is connected to N local bitlines among the local bitlines, and N is a natural number greater than or equal to 2, wherein the first global bitline among the global bitlines includes a first bitline portion, and the second global bitline among the global bitlines includes a second bitline portion placed at a higher level than the first bitline portion, and the global bitline selection circuits include a first global bitline selection circuit connected to the first bitline sense amplifier among the bitline sense amplifiers, and the global bitlines include M global bitlines connected to the first global bitline selection circuit, and M is a natural number greater than or equal to 4. Claim 6 In claim 5, the semiconductor device comprises: a first global bitline selection circuit connected to the first global bitline and the second global bitline; and a second selection circuit connected to the third global bitline and the fourth global bitline among the global bitlines. Claim 7 A semiconductor device according to claim 6, wherein the first selection circuit comprises a first selection transistor connected to the first global bit line; and a second selection transistor connected to the second global bit line, and the second selection circuit comprises a third selection transistor connected to the third global bit line; and a fourth selection transistor connected to the fourth global bit line. Claim 8 A semiconductor device according to claim 7, wherein the first global bitline and the third global bitline are placed at the same level as each other, and the second global bitline and the fourth global bitline are placed at a different level from the first global bitline and the third global bitline. Claim 9 A first structure; and a second structure disposed on the first structure and joined to the first structure, wherein the first structure comprises memory cells arranged three-dimensionally along a vertical direction perpendicular to each other, a first horizontal direction, and a second horizontal direction; local bit lines connected to the memory cells and disposed at the same level; and global bit lines disposed at a higher level than the local bit lines and connected to the local bit lines, wherein the global bit lines include first global bit lines connected to N first local bit lines among the local bit lines. A semiconductor device comprising: second global bit lines connected to N second local bit lines among the local bit lines, wherein N is a natural number greater than or equal to 2; each of the memory cells comprises a cell transistor including a cell gate electrode extending in the second horizontal direction; and an information storage structure, wherein each of the first global bit lines comprises a first-1 bit line portion, and each of the second global bit lines comprises a second-1 bit line portion disposed at a higher level than the first-1 bit line portions of the first global bit lines, and three local bit lines arranged sequentially in the first horizontal direction among the local bit lines are each connected to three global bit lines spaced apart from each other among the global bit lines. Claim 10 A semiconductor device according to claim 9, wherein among the first global bitlines and the second global bitlines, the first global bitline and the second global bitline that are adjacent to each other in the vertical direction, the first-1 bitline portion of the first global bitline extends in a first direction intersecting the first horizontal direction and the second horizontal direction, and the second-1 bitline portion of the second global bitline extends in a second direction intersecting the first horizontal direction, the second horizontal direction and the first direction, and each of the first global bitlines further includes a first-2 bitline portion extending from the first-1 bitline portion in the second direction, and each of the second global bitlines further includes a second-2 bitline portion extending from the second-1 bitline portion in the first direction.

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