Image sensor device

Abstract

An image sensor device according to the present invention comprises: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to a ramp signal and a first control signal; a second variable ramp buffer configured to output a second output voltage in response to a ramp signal and a second control signal; a first analog-to-digital converting (ADC) circuit configured to sample a first digital signal based on a first pixel voltage and a first output voltage received through a first column line; and a second ADC circuit configured to sample a second digital signal based on a second pixel voltage and a second output voltage received through a second column line, wherein the first variable ramp buffer is further configured to vary the first output voltage to a first level during the auto-zero operation of the first and second ADC circuits and to vary the first output voltage to a reference level after the auto-zero operation, and the second variable ramp buffer is further configured to vary the second output voltage to a second level different from the first level during the auto-zero operation and to vary the second output voltage to a reference level after the auto-zero operation.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to an image sensor device. Background Technology

[0002] An image sensor acquires image information about an external object by converting light reflected from the external object into an electrical signal. An electronic device including an image sensor can display an image on a display panel using the acquired image information.

[0003] As the performance of an image sensor improves or its size decreases, various types of noise may occur in the image data acquired by the image sensor. For example, as the performance of the image sensor improves (e.g., as the resolution or frame rate increases), the sampling time required to acquire image data may decrease. In this case, multiple samples may be performed at the same point in time or within a specific time interval, which can cause abrupt fluctuations in the power supply voltage or ground voltage used by the image sensor. Abrupt fluctuations in the power supply voltage or ground voltage act as noise for the image data and degrade its quality. The problem to be solved

[0004] The objective of the present invention is to provide an image sensor device having improved performance and improved reliability. means of solving the problem

[0005] According to one embodiment of the present invention, an image sensor device comprises: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to the ramp signal and a first control signal; a second variable ramp buffer configured to output a second output voltage in response to the ramp signal and a second control signal; and a first analog-to-digital converting (ADC) circuit configured to sample a first digital signal based on a first pixel voltage received through a first column line and the first output voltage. It includes a second ADC circuit configured to sample a second digital signal based on a second pixel voltage received through a second column line and the second output voltage, and the first variable ramp buffer is further configured to vary the first output voltage to a first level during the auto-zero operation of the first and second ADC circuits and to vary the first output voltage to a reference level after the auto-zero operation, and the second variable ramp buffer is further configured to vary the second output voltage to a second level different from the first level during the auto-zero operation and to vary the second output voltage to the reference level after the auto-zero operation.

[0006] According to one embodiment of the present invention, an image sensor device comprises: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to the ramp signal and a first control signal; and a first analog-to-digital converting (ADC) circuit configured to output a first digital signal based on a first pixel voltage received through a first column line and the first output voltage, wherein the first variable ramp buffer comprises: a first driving transistor connected between a first node where the first output voltage is output and a ground voltage and configured to operate in response to the ramp signal; and a first variable current bias circuit connected between the first node and a power supply voltage and configured to control a first bias current provided to the first node in response to the first control signal, wherein the first variable current bias circuit may be further configured to drive the first bias current to a first magnitude during the auto-zero operation of the first ADC circuit and to drive the first bias current to a reference magnitude after the auto-zero operation.

[0007] According to one embodiment of the present invention, an image sensor device comprises: a ramp generator configured to generate a ramp signal; a variable ramp buffer block configured to buffer the ramp signal and output a plurality of output voltages; and an analog to digital converting (ADC) block configured to compare a plurality of pixel voltages received through a plurality of column lines and the plurality of output voltages, respectively, and to sample a plurality of digital signals corresponding to each of the plurality of pixel voltages, wherein while the ADC block performs an auto-zero operation, at least two of the plurality of output voltages have different levels, and after the auto-zero operation, the plurality of output voltages may have the same level.

[0008] According to one embodiment of the present invention, an image sensor device comprises: a first pixel configured to output a first pixel voltage through a first column line; a ramp generator configured to generate a ramp signal; a first variable pixel load circuit connected to the first column line and configured to generate a first pixel bias current in response to a first control signal; and a first analog to digital converting (ADC) circuit configured to sample a first digital signal based on the ramp signal and the first pixel output voltage, wherein the first variable pixel load circuit may be further configured to vary the first pixel bias current to a first level during the auto-zero operation of the first ADC circuit, and to vary the first pixel bias current to a reference level after the auto-zero operation.

[0009] According to one embodiment of the present invention, an image sensor device comprises: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to the ramp signal and a first control signal; a second variable ramp buffer configured to output a second output voltage in response to the ramp signal and a second control signal; a first control switch connected between the first variable ramp buffer and the second variable ramp buffer; a first analog to digital converting (ADC) circuit configured to sample a first digital signal based on a first pixel voltage received through a first column line and the first output voltage; and a second ADC circuit configured to sample a second digital signal based on a second pixel voltage received through a second column line and the second output voltage, wherein during the auto-zero operation of the first and second ADC circuits, the first control switch is turned on, and after the auto-zero operation, the first control switch can be turned off.

[0010] According to one embodiment of the present invention, a method of operating an image sensor device may include: performing an auto-zero operation of first and second analog-to-digital converting (ADC) circuits of the image sensor device; controlling a first output voltage of a first variable ramp buffer and a second output voltage of a second variable ramp buffer differently while the auto-zero operation is performed; controlling the first output voltage of the first variable ramp buffer and the second output voltage of the second variable ramp buffer equally after the auto-zero operation; controlling the first output voltage based on a ramp signal by the first variable ramp buffer and controlling the second output voltage based on the ramp signal by the second variable ramp buffer; and sampling a first digital signal based on the first output voltage and a first pixel voltage by the first ADC circuit and sampling a second digital signal based on the second output voltage and a second pixel voltage by the second ADC circuit.

[0011] According to one embodiment of the present invention, an image sensor device comprises: a first pixel configured to output a first pixel voltage through a first column line; a ramp generator configured to generate a ramp signal; a first variable pixel buffer configured to receive the first pixel voltage through the first column line and output a first pixel output voltage in response to the first pixel voltage and a first control signal; and a first analog to digital converting (ADC) circuit configured to sample a first digital signal based on the ramp signal and the first pixel output voltage, wherein the first variable pixel buffer is further configured to vary the first pixel output voltage to a first level during the auto-zero operation of the first ADC circuit, and to vary the first pixel output voltage to a reference level corresponding to the first pixel voltage after the auto-zero operation. Effects of the invention

[0012] According to the present invention, an image sensor device having improved performance and improved reliability is provided. Brief explanation of the drawing

[0013] FIG. 1 is a drawing showing an image system according to an embodiment of the present invention. Figure 2 is a block diagram showing the image sensor device of Figure 1. Figure 3a is a circuit diagram showing some examples of pixels included in the pixel array of Figure 2. FIG. 3b is a timing diagram to explain the operation of the first ADC circuit of FIG. 2. FIGS. 4a to 4d are drawings for explaining the ramp buffer and ADC circuit. Figure 5 is a block diagram showing the variable ramp buffer and ADC circuit of the image sensor device of Figure 1. Figure 6 is a circuit diagram showing the variable lamp buffers of Figure 5. FIGS. 7a and 7b are diagrams for explaining the operation of applying an offset to the inverting input terminal of the first amplifier by the operation of the A variable ramp buffer of FIG. 6. Figure 8 is a timing diagram showing the operation of the variable ramp buffers and ADC circuits of Figure 5. FIGS. 9A and 9B are drawings for explaining the operation of variable ramp buffers according to the flowchart of FIG. 8. Figure 10 is a circuit diagram showing the variable lamp buffer of Figure 1. Figure 11 is a circuit diagram showing the variable lamp buffer of Figure 1. FIGS. 12a and FIGS. 12b are drawings for explaining the operation of the variable ramp buffer of FIG. 11. Figure 13 is a circuit diagram showing the variable lamp buffer of Figure 1. FIGS. 14a and FIGS. 14b are drawings for explaining the operation of the variable ramp buffer of FIG. 13. Figure 15 is a circuit diagram showing the variable lamp buffer of Figure 1. Figure 16 is a circuit diagram showing the variable lamp buffer of Figure 15. FIG. 17 is a timing diagram to explain the operation of the variable ramp buffer of FIG. 16. FIGS. 18 to 20 are circuit diagrams showing the variable lamp buffer of FIG. 1. FIG. 21 is a flowchart showing the operation of the image sensor device of FIG. 1. FIGS. 22 to 26 are circuit diagrams showing the variable lamp buffer of FIG. 1. FIG. 27 is a block diagram showing a part of the configuration of an image sensor device according to an embodiment of the present invention. FIG. 28 is a block diagram showing an image sensor device according to an embodiment of the present invention. FIG. 29 is a block diagram showing an image sensor device according to an embodiment of the present invention. FIG. 30 is a block diagram showing the variable pixel load circuit and ADC circuit of FIG. 29. FIG. 31 is a timing diagram to explain the operation of the variable pixel load circuit of FIG. 30. FIG. 32 is a block diagram showing an image sensor device according to one embodiment of the present invention. FIG. 33 is a block diagram showing the variable ramp buffer, variable pixel load circuit, and ADC circuit of FIG. 32. FIG. 34 is a block diagram showing an image sensor device according to one embodiment of the present invention. FIG. 35 is a block diagram showing the ramp buffer, variable pixel buffer, and ADC circuit of FIG. 34. FIG. 36 is a block diagram showing an image sensor device according to one embodiment of the present invention. FIG. 37 is a block diagram showing the variable ramp buffer, variable pixel buffer, and ADC circuit of FIG. 36. FIGS. 38 and FIGS. 39 are drawings showing the stacked structure of an image sensor device according to an embodiment of the present invention. Specific details for implementing the invention

[0014] In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention.

[0015] Terms such as "block," "unit or part," "module," etc., used below, or corresponding configurations, or functional blocks of the drawings, or circuits, may be implemented in the form of software, hardware, or a combination thereof configured to perform or process the various functions, operations, and features described in the detailed description.

[0016] In the following, where various components are listed via the conjunction "or," this may refer to each of the listed components or at least a combination of some of them. For example, "A, B, or C" may mean A, B, and C respectively, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C.

[0017] FIG. 1 is a drawing showing an image system according to an embodiment of the present invention. Referring to FIG. 1, the image system (10) may include a lens (11), an image sensor device (100), and an image signal processor (12). In one embodiment, the image system (10) may be implemented as part of various electronic devices such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet PC (Personal Computer), a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a navigation system, a drone, an Advanced Driver Assistance System (ADAS), a traffic surveillance camera, a CCTV, etc. Additionally, the image system (10) may be mounted on an electronic device equipped as a component in a vehicle, furniture, manufacturing equipment, a door, various measuring instruments, etc.

[0018] The lens (11) can receive light reflected from an external object. The image sensor device (100) can generate an image electrical signal based on the light received through the lens (11). For example, the image sensor device (100) can be implemented as a CMOS (Complementary Metal Oxide Semiconductor) image sensor, etc. However, the scope of the present invention is not limited thereto, and the image sensor device (100) can be implemented based on various image sensors such as a DVS (dynamic vision sensor), a DPS (digital pixel sensor), etc.

[0019] An image signal processor (12) receives an electrical signal (e.g., image data or output data including information about an external object or foreground) received from an image sensor (100) and can perform various image signal processing operations on the received signals. In one embodiment, the image signal processing operations may include various signal processing operations to improve image quality, such as de-noising operations, tone-mapping operations, detail enhancing operations, white balancing operations, gamma correction operations, de-mosaic operations, sharpening operations, color conversion operations, etc.

[0020] FIG. 2 is a block diagram showing an image sensor device of FIG. 1. Referring to FIG. 1 and FIG. 2, the image sensor device (100) may include a pixel array (110), a row driver (120), a pixel load block (130), a ramp generator (140), a ramp buffer controller (150), a variable ramp buffer block (160), an analog to digital converting (ADC) block (170), and an input / output circuit (180).

[0021] A pixel array (110) may include a plurality of pixels. Each of the plurality of pixels may be configured to convert light incident through a lens (11) into an electrical signal. Each of the plurality of pixels may output a plurality of pixel voltages (VPIX[A]–VPIX[n]) through a plurality of column lines (CL[A]–CL[n]). In one embodiment, each of the plurality of pixel voltages (VPIX[A]–VPIX[n]) may correspond to a reset level or signal level of a corresponding pixel.

[0022] In the following, for convenience of explanation, the reference symbol "[X]" is used. "[X]" may be used in combination with other reference symbols, and the combined reference symbol may indicate that the component of the combined reference symbol corresponds to column X among multiple pixels. For example, the symbol CL[A] may refer to a column line (CL) corresponding to column A among multiple pixels of a pixel array. VPIX[B] may refer to pixel voltages output from pixels corresponding to column B among multiple pixels. Additionally, for convenience of explanation, reference symbols indicating column numbers are written in uppercase and may be used together with reference symbols to distinguish similar components, such as 1st, 2nd, 3rd, etc. In this case, each component may be distinguished using expressions such as 1stX, 2ndX, 1stY, 2ndY, etc. For example, "OTA1[A]" may refer to the 1stA amplifier, which may refer to the first amplifier among the amplifiers corresponding to column A. As another example, "AZS2[B]" may be referred to as the 2B auto-zero switch, which refers to the second auto-zero switch among the auto-zero switches corresponding to column B. As another example, "vCRB[A]" may be referred to as the A variable ramp buffer, which refers to the variable ramp buffer corresponding to column A. Unless otherwise defined, the reference symbols and terms described above will be understood in the context of the detailed description.

[0023] The row driver (120) can provide various control signals to multiple pixels included in the pixel array (110). The multiple pixels can operate according to the control of the row driver (120).

[0024] The pixel load block (130) may include a plurality of pixel load circuits (PLD[A]–PLD[n]). The plurality of pixel load circuits (PLD[A]–PLD[n]) may each be connected to a plurality of column lines (CL[A]–CL[n]). The plurality of pixel load circuits (PLD[A]–PLD[n]) may each provide pixel bias currents for a plurality of pixel voltages (VPIX[A]–VPIX[n]) provided through the plurality of column lines (CL[A]–CL[n]). For example, the A pixel load circuit (PLD[A]) may be connected to the A column line (CL[A]) and may provide a first pixel bias current for the A column line (CL[A]). By the first pixel bias current, the A column line (CL[A]) may be quickly initialized. In one embodiment, the A pixel voltage (VPIX[A]) of the A column line (CL[A]) may be partially controlled by the first pixel bias current. Although not illustrated in the drawings, a plurality of pixel load circuits (PLD[A] to PLD[n]) may operate in response to the same bias signal. That is, each of the plurality of pixel load circuits (PLD[A] to PLD[n]) may generate a pixel bias current of the same magnitude. However, the scope of the present invention is not limited thereto, and the plurality of pixel load circuits (PLD[A] to PLD[n]) may operate in response to different control signals, and the plurality of pixel load circuits (PLD[A] to PLD[n]) may each individually control the pixel bias current. Related configurations are described below with reference to FIGS. 29 to 37.

[0025] The image sensor device (100) may be configured to convert a plurality of pixel voltages (VPIX[A]–VPIX[n]) output through a plurality of column lines (CL[A]–CL[n]) into digital signals. For example, an ADC block (170) may be configured to convert a plurality of pixel voltages (VPIX[A]–VPIX[n]) into digital signals. As a more detailed example, the ADC circuit (170) may include a plurality of ADC circuits (ADC[A]–ADC[n]).

[0026] Multiple ADC circuits (ADC[A]–ADC[n]) can each receive multiple pixel voltages (VPIX[A]–VPIX[n]) through multiple column lines (CL[A]–CL[n]). Each of the multiple ADC circuits (ADC[A]–ADC[n]) can compare multiple pixel voltages (VPIX[A]–VPIX[n]) with a ramp signal (RAMP) and output digital signals corresponding to the multiple pixel voltages (VPIX[A]–VPIX[n]) based on the comparison result. As an example, the ramp signal (RAMP) can be generated by a ramp generator (140). The ramp signal (RAMP) may be a signal that decreases at a constant rate over time.

[0027] As an example, an ADC circuit (ADC[A]) can receive an A pixel voltage (VPIX[A]) through an A column line (CL[A]). The ADC circuit (ADC[A]) can compare the A pixel voltage (VPIX[A]) with a ramp signal (RAMP) and output an A digital signal based on the comparison result. A B ADC circuit (ADC[B]) can receive a B pixel voltage (VPIX[B]) through a B column line (CL[B]). The B ADC circuit (ADC[B]) can compare the B pixel voltage (VPIX[B]) with a ramp signal (RAMP) and output a B digital signal based on the comparison result.

[0028] According to an embodiment of the present invention, the image sensor device (100) may include a ramp buffer controller (150) and a variable ramp buffer block (160).

[0029] The ramp buffer controller (150) can generate various control signals (CTRL) or bias signals used in the variable ramp buffer block (160). The variable ramp buffer block (160) can receive a ramp signal (RAMP) from the ramp generator (140), buffer the received ramp signal (RAMP), and transmit it to the ADC block (170). In this case, the reliability of the ramp signal (RAMP) can be improved.

[0030] For example, each of the multiple ADC circuits (ADC[A] to ADC[n]) performs a sampling operation using a ramp signal (RAMP). In this case, if the ramp signal (RAMP) is generated from a single ramp generator (140), the waveform or delay time of the ramp signal (RAMP) received by each of the multiple ADC circuits (ADC[A] to ADC[n]) may vary depending on the load of the path through which the ramp signal (RAMP) is transmitted. Accordingly, the operational reliability of the multiple ADC circuits (ADC[A] to ADC[n]) may be reduced.

[0031] A variable column ramp buffer (vCRB; variable Column Ramp Buffer) block (160) (hereinafter referred to as a variable ramp buffer block for convenience of explanation) may include a plurality of variable ramp buffers (vCRB[A]~vCRB[n]). Each of the plurality of variable ramp buffers (vCRB[A]~vCRB[n]) may receive a ramp signal (RAMP) from a ramp generator (130), buffer the received ramp signal (RAMP), and provide it to a plurality of ADC circuits (ADC[A]~ADC[n]).

[0032] In one embodiment, a plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can perform a buffering operation for a ramp signal (RAMP) using bias signals generated by a ramp buffer controller (150).

[0033] In one embodiment, the ADC block (170) can perform a correlated double sampling (CDS) operation. For example, each of the plurality of pixel voltages (VPIX[A]–VPIX[n]) can correspond to a reset level and a signal level for the corresponding pixel. The plurality of ADC circuits (ADC[A]–ADC[n]) of the ADC block (170) can each perform reset sampling for the reset level of the plurality of pixel voltages (VPIX[A]–VPIX[n]) and perform signal sampling for the signal level of the plurality of pixel voltages (VPIX[A]–VPIX[n]). Since the reset levels of the plurality of pixel voltages (VPIX[A]–VPIX[n]) can have similar levels, the time at which the ramp signal (RAMP) becomes lower than the reset level of the plurality of pixel voltages (VPIX[A]–VPIX[n]) during the reset sampling operation can be similar. In this case, as multiple ADC circuits (ADC[A]~ADC[n]) perform sampling simultaneously within a short period of time, noise may occur in the power supply voltage or ground voltage connected to the multiple ADC circuits (ADC[A]~ADC[n]), or the level of the power supply voltage may fluctuate. This may reduce the operational reliability of the image sensor device (100).

[0034] In one embodiment, each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) of the variable ramp buffer block (160) can apply a different offset to the ramp signal (RAMP) using a control signal (CTRL). In this case, the signals output from the plurality of variable CRB circuits (vCRB[A] to vCRB[n]) can be varied. Accordingly, a different offset can be applied to the input of each of the plurality of ADC circuits (ADC[A] to ADC[n]). In this case, when the plurality of ADC circuits (ADC[A] to ADC[n]) perform a conversion operation (e.g., reset sampling) for pixel voltages of the same or similar level, the sampling timing can be dispersed. In this case, abrupt level / voltage fluctuations in the power supply voltage or ground voltage connected to the plurality of ADC circuits (ADC[A] to ADC[n]) can be reduced. The configuration and operation of variable ramp buffers (vCRB[A]~vCRB[n]) according to embodiments of the present invention will be described in more detail with reference to the drawings below.

[0035] FIG. 3a is a circuit diagram showing some examples of pixels included in the pixel array of FIG. 2. FIG. 3b is a timing diagram to explain the operation of the first ADC circuit of FIG. 2. The horizontal axis of FIG. 3b indicates time, and the vertical axis indicates the level of each signal.

[0036] Referring to FIGS. 2, FIGS. 3a, and FIGS. 3b, a pixel (PIX) may include first to fourth photodiodes (PD1 to PD4), first to fourth transmission gates (TG1 to TG4), a reset gate (TG), a source follower (SF), and a select gate (SG). In one embodiment, each of the first to fourth transmission gates (TG1 to TG4), the reset gate (TG), and the select gate (SG) may refer to a transistor (e.g., an NMOS transistor) configured to operate in response to a corresponding signal.

[0037] The first to fourth photodiodes (PD1 to PD4) can generate photocharges in response to light incident from the outside. The first to fourth transmission gates (TG1 to TG4) are each connected between the first to fourth photodiodes (PD1 to PD4) and a floating diffusion (FD) node (n_FD) and can operate in response to the first to fourth transmission signals (TX). The reset gate (RG) is connected between the power supply voltage (VDD) and the FD node (n_FD) and can operate in response to the reset signal (RX). The source follower (SF) and the select gate (SG) can be connected in series between the power supply voltage (VDD) and the first column line (CL[A]). The source follower (SF) operates in response to the level of the FD node (n_FD), and the select gate (SG) can operate in response to the select signal (SEL). In one embodiment, the level of the first pixel voltage (VPIX[A]) output through the first column line (CL[A]) may vary depending on the level of the FD node (n_FD).

[0038] In one embodiment, the A pixel load circuit (PLD[A]) can be connected to the A column line (CL[A]) and can provide a first pixel bias current.

[0039] The pixel structure of FIG. 3a, for example, a structure in which four photodiodes share one FD node (n_FD), is an example and the scope of the invention is not limited thereto. A plurality of pixels included in the image sensor device (100) may be implemented in various structures, for example, a single photodiode structure, a split diode structure, etc., or may further include additional circuits for a structure for DCG (dual conversion gain), a structure for a global shutter, etc.

[0040] In the following, to briefly explain the operation of the pixel (PIX) and the ADC circuit (ADC), each operation is described based on one photodiode (e.g., PD1). As shown in FIG. 3b, during the interval (ta-ti) between time points a to i, the select signal (SEL) may be maintained at a high level. During the interval (ta-tb) between time points a to b, the reset signal (RX) may be at a high level. In this case, in response to the high-level reset signal (RX), the reset gate (RG) may be turned on. Accordingly, the FD node (n_FD) may be reset to a level corresponding to the power supply voltage (VDD), and the first pixel voltage (VPIX[A]) may have a reset level corresponding to the FD node (n_FD).

[0041] Subsequently, the A ADC circuit (ADC[A]) can perform a reset sampling operation. For example, the A ADC circuit (ADC[A]) can compare the reset level of the ramp signal (RAMP) and the A pixel voltage (VPIX[A]) during the interval (tc-te) of the c to e timestamps. At the d timet (td) when the ramp signal (RAMP) becomes lower than the reset level of the A pixel voltage (VPIX[A]), the A ADC circuit (ADC[A]) can output or store a digital signal corresponding to the reset level of the A pixel voltage (VPIX[A]).

[0042] Subsequently, during the interval (tf-tg) of the f to g time points, the first transmission signal (TX1) may be maintained at a high level. In response to the high level of the first transmission signal (TX1), the first transmission gate (TG1) may be turned on. Accordingly, the photocharge generated by the first photodiode (PD1) may be transferred to the FD node (n_FD), and the level of the FD node (n_FD) may be lowered. At this time, as the level of the FD node (n_FD) is lowered, the A pixel voltage (VPIX[A]) may be lowered. In one embodiment, the A pixel voltage (VPIX[A]) may be lowered to a signal level corresponding to the level of the FD node (n_FD).

[0043] Subsequently, the A ADC circuit (ADC[A]) can perform a signal sampling operation. For example, the A ADC circuit (ADC[A]) can compare the signal levels of the ramp signal (RAMP) and the A pixel voltage (VPIX[A]) during the interval (tg-ti) of time points g through i. At time point h (th), when the ramp signal (RAMP) becomes lower than the signal level of the A pixel voltage (VPIX[A]), the A ADC circuit (ADC[A]) can output or store a digital signal corresponding to the signal level of the A pixel voltage (VPIX[A]).

[0044] The operation of the pixel (PIX) and the ADC circuit for the pixel (PIX) described with reference to FIGS. 3a and 3b is merely an example, and the scope of the invention is not limited thereto. For example, it will be understood that the operation described above can be varied in many ways depending on the structure and operation method of the pixel (PIX).

[0045] FIGS. 4a through 4d are drawings illustrating ramp buffers and ADC circuits. For convenience of explanation, some components are omitted. For example, for brevity of the drawings and convenience of explanation, A and B ADC circuits (ADC[A], ADC[B]) connected to A and B column lines (CL[A], CL[B]) and A and B ramp buffers (CRB[A], CRB[B]) configured to provide a ramp signal buffered by the A and B ADC circuits (ADC[A], ADC[B]) are shown. However, the scope of the invention is not limited thereto, and other ADC circuits or column ramp buffers may have structures similar to those described with reference to FIGS. 4a through 4d.

[0046] First, referring to FIG. 4a, the A ramp buffer (CRB[A]) may be configured to buffer a ramp signal (RAMP) and output an A ramp buffer output (CRB_OUT[A]). For example, the A ramp buffer (CRB[A]) may include an A current bias circuit (CB[A]) and an A driving transistor (MPd[A]). In one embodiment, the A driving transistor (MPd[A]) may be a PMOS (P-channel Metal-Oxide-Semiconductor) transistor.

[0047] A current bias circuit (CB[A]) is connected between the power supply voltage (VDD) and the A node (n[A]) and can be configured to generate or flow a predetermined bias current. A driving transistor (MPd[A]) is connected between the A node (n[A]) and the ground voltage (VSS) and can operate in response to a ramp signal (RAMP). Through the A node (n[A]), an A ramp buffer output (CRB_OUT[A]) can be output. For example, the current flowing through the A driving transistor (MPd[A]) can be varied in response to the level of the ramp signal (RAMP). That is, as the level of the ramp signal (RAMP) decreases, the current flowing through the A driving transistor (MPd[A]) can increase, and accordingly, the A ramp buffer output (OUT_CRB[A]) can decrease. Therefore, the A ramp buffer output (CRB_OUT[A]) may be a signal in which the ramp signal (RAMP) is buffered.

[0048] The A ADC circuit (ADC[A]) may include an A non-inverting input capacitor (Cp[A]), an A inverting input capacitor (Cn[A]), a first A amplifier (OTA1[A]), a second A amplifier (OTA2[A]), a first A counter (CNT[A]), and first A and second A auto-zero switches (AZS1[A], AZS2[A]).

[0049] The A non-inverting input capacitor (Cp[A]) can be connected between the A ramp buffer output (CRB_OUT[A]) of the A ramp buffer (CRB[A]) and the non-inverting input terminal (+) of the 1A amplifier (OTA1[A]). The A inverting input capacitor (Cn[A]) can be connected between the A pixel voltage (VPIX[A]) and the inverting input terminal (-) of the 1A amplifier (OTA1[A]).

[0050] The first amplifier (OTA1[A]) can compare the first non-inverting input (INp[A]) and the second inverting input (INn[A]) and output the comparison result. In one embodiment, the first amplifier (OTA1[A]) may be an operational transconductance amplifier (OTA). For example, when the first non-inverting input (INp[A]) is higher than the second inverting input (INn[A]), the first amplifier (OTA1[A]) may output a high level to the second non-inverting output (OUTp[A]) and a low level to the second inverting output (OUTn[A]). Conversely, when the A non-inverting input (INp[A]) is lower than the A inverting input [INn[A]], the 1A amplifier (OTA1[A]) can output a low level to the A non-inverting output (OUTp[A]) and a high level to the A inverting output (OUTn[A]).

[0051] For example, as shown in FIG. 4b, the first A amplifier (OTA1[A]) may include a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2), and a zero NMOS transistor (MN0).

[0052] The first PMOS transistor (MP1) may be connected between the power supply voltage (VDD) and the A inverting output (OUTn[A]). The second PMOS transistor (MP_a2) may be connected between the power supply voltage (VDD) and the A non-inverting output (OUTp[A]). The gate of the first PMOS transistor (MP1) and the gate of the second PMOS transistor (MP2) may be connected to the A inverting output (OUTn[A]). The first NMOS transistor (MN1) may be connected between the A inverting output (OUTn[A]) and one end of the zero NMOS transistor (MN0). The gate of the first NMOS transistor (MN1) may be connected to the A non-inverting input (INp[A]). The second NMOS transistor (MN2) may be connected between the non-inverting output (OUTp[A]) and one end of the zero NMOS transistor (MN0). The gate of the second NMOS transistor (MN2) can be connected to the A inverting input (INn[A]). The other end of the first NMOS transistor (MN0) is connected to the ground voltage (VSS), and the gate of the first NMOS transistor (MN0) can operate in response to a current bias circuit signal (CB).

[0053] As shown in FIG. 4b, the first amplifier (OTA1[A]) may have the structure of an operational transconductance amplifier (OTA) configured to compare a non-inverting input (INp[A]) and an inverting input (INn[A]) and output a comparison result.

[0054] In one embodiment, the first A amplifier (OTA1[A]) may perform an auto-zeroing operation before performing a sampling operation. For example, the first A auto-zero switch (AZS1[A]) may be connected between the A inverting output (OUTn[A]) and the A non-inverting input (INp[A]), and the second A auto-zero switch (AZS2[A]) may be connected between the A non-inverting output (OUTp[A]) and the A inverting input (INn[A]).

[0055] Auto zero switches (AZS1[A], AZS2[B]) can operate in response to an auto zero signal (AZ). For example, as the first A auto zero switch (AZS1[A]) is turned on in response to the auto zero signal (AZ), the levels of the A inverted output (OUTn[A]) and the A non-inverted input (INp[A]) can be equalized, and as the second A auto zero switch (AZS2[A]) is turned on in response to the auto zero signal (AZ), the levels of the A non-inverted output (OUTp[A]) and the A inverted input (INn[A]) can be equalized.

[0056] The second amplifier (OTA2[A]) can output the A non-inverted output (OUTp[A]) of the first amplifier (OTA1[A]) by inverting it. In one embodiment, the output of the second amplifier (OTA2[A]) may be an A comparison signal (COMP[A]). In one embodiment, the second amplifier (OTA2[A]) may be an Operational Transconductance Amplifier (OTA).

[0057] Accordingly, when the A ramp buffer output (CRB_OUT[A]) corresponding to the A ramp signal (RAMP) is higher than the A pixel signal (VPIX[A]), the A comparison signal (COMP[A]) may be at a logic low level, and when the first ramp buffer output (CRB_OUT[A]) corresponding to the A ramp signal (RAMP) is lower than the A pixel signal (VPIX[A]), the A comparison signal (COMP[A]) may be at a logic high level. The A counter (CNT[A]) may store or output a corresponding digital value in response to the A comparison signal (COMP[A]).

[0058] The B ramp buffer (CRB[B]) may include a B current bias circuit (CB[B]) and a B driving PMOS transistor (MPd[B]), and may output a B ramp buffer output (CRB_OUT[B]) in response to a ramp signal (RAMP). The B ADC circuit (ADC[B]) may include a B non-inverting input capacitor (Cp[B]), a B inverting input capacitor (Cn[B]), a first B amplifier (OTA1[B]), a second B amplifier (OTA2[B]), a B counter (CNT[B]), and auto-zero switches (AZS1[B], AZS2[B]). In one embodiment, the structure and operation of the B ramp buffer (CRB[B]) and the B ADC circuit (ADC[B]) are similar to the structure and operation of the A ramp buffer (CRB[A]) and the A ADC circuit (ADC[A]), so a detailed description thereof is omitted.

[0059] In one embodiment, the A and B ramp buffers (CRB[A], CRB[B]) may operate in response to the same bias signal. That is, the outputs (CRB_OUT[A], CRB_OUT[B]) of the A and B ramp buffers (CRB[A], CRB[B]) may be substantially the same or similar.

[0060] For example, as illustrated in FIG. 4c, the first ramp buffer (CRB[A]) may include a first driving transistor (MPd[A]), a first bias transistor (MPb1[A]), and a second bias transistor (MPb2[A]). In one embodiment, the first driving transistor (MPd[A]), the first bias transistor (MPb1[A]), and the second bias transistor (MPb2[A]) may each be a PMOS transistor.

[0061] The A driving transistor (MPd[A]), the first A bias transistor (MPb1[A]), and the second A bias transistor (MPb2[A]) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The A driving transistor (MPd[A]) may operate in response to a ramp signal (RAMP), the first A bias transistor (MPb1[A]) may operate in response to a first bias signal (CP), and the second A bias transistor (MPb2[A]) may operate in response to a second bias signal (BP).

[0062] The B ramp buffer (CRB[B]) may include a B driving transistor (MPd[B]), a first B bias transistor (MPb1[B]), and a second B bias transistor (MPb2[B]). Each of the B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), and the second B bias transistor (MPb2[B]) may be a PMOS transistor.

[0063] The B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), and the second B bias transistor (MPb2[B]) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The B driving transistor (MPd[B]) may operate in response to a ramp signal (RAMP), the first B bias transistor (MPb1[B]) may operate in response to a first bias signal (CP), and the second B bias transistor (MPb2[B]) may operate in response to a second bias signal (BP).

[0064] In one embodiment, the first and second bias signals (CP, BP) may be signals generated by the ramp buffer controller (150). As described above, the first A and second A bias transistors (MPb1[A], MPb2[A]) of the first ramp buffer (CRB[A]) and the first B and second B bias transistors (MPb1[B], MPb2[B]) of the second ramp buffer (CRB[B]) may share the same bias signals (CP, BP).

[0065] In this case, the first bias current (i) flowing from the A lamp buffer (CRB[A]) b1 ) and the second bias current (i) flowing in the B lamp buffer (CRB[B]). b2 ) may have the same or similar size (e.g., iref) or be driven at the same or similar timing. In this case, the first ramp buffer output (CRB_OUT[A]) output through the A node (n[A]) and the second ramp buffer output (CRB_OUT[B]) output through the B node (n[B]) may have the same or similar size or be driven at similar timing.

[0066] In one embodiment, the A ADC circuit (ADC[A]) can perform a sampling operation by comparing the A ramp buffer output (CRB_OUT[A]) and the A pixel voltage (VPIX[A]), and the B ADC circuit (ADC[B]) can perform a sampling operation by comparing the B ramp buffer output (CRB_OUT[B]) and the B pixel voltage (VPIX[B]). In this case, the A pixel voltage (VPIX[A]) may be a voltage output from a first pixel connected to the A column line (CL[A]) among a plurality of pixels included in the pixel array (110), and the B pixel voltage (VPIX[B]) may be a voltage output from a second pixel connected to the B column line (CL[B]) among a plurality of pixels included in the pixel array (110). The first and second pixels may operate in response to the same selection signal (SEL). Alternatively, the first and second pixels may be located in the same row.

[0067] In the following, for the sake of brevity of the drawings and convenience of explanation, embodiments of the present invention are described based on the reset sampling operation of ADC circuits. However, the scope of the present invention is not limited thereto, and ADC circuits can perform reset sampling operation and signal sampling operation. Additionally, depending on the structure of the pixel, ADC circuits can perform sampling operation according to high conversion gain and low conversion gain.

[0068] As illustrated in FIG. 4d, the A ADC circuit (ADC[A]) and the B ADC circuit (ADC[B]) can perform a reset sampling operation. For example, during the interval (t1-t2) of the first and second time points, the auto-zero signal (AZ) can be maintained at a high level. In this case, in response to the high-level auto-zero signal (AZ), the A ADC circuit (ADC[A]) and the B ADC circuit (ADC[B]) can perform an auto-zero operation. As an example, during the auto zero period (AZ Period), the auto zero switches (AZS1[A], AZS2[A], AZS1[B], AZS2[B]) are turned on, and accordingly, the inverting inputs (INn[A], INn[B]) and non-inverting inputs (INp[A], INp[B]) of the amplifiers (OTA1[A], OTA1[B]) can be initialized.

[0069] Subsequently, during the interval of the third to fifth time points (t3-t5), the A ADC circuit (ADC[A]) and the B ADC circuit (ADC[B]) may perform reset sampling. For example, during the interval of the third to fifth time points (t3-t5), the ramp generator (140) may generate a ramp signal (RAMP). In response to the ramp signal (RAMP), the A ramp buffer (CRB[A]) may generate an A ramp buffer output (CRB_OUT[A]), and the B ramp buffer (CRB[B]) may generate a B ramp buffer output (CRB_OUT[B]). In one embodiment, since the A and B ramp buffers (CRB[A], CRB[B]) operate using the same bias signals (BP, CP), the A and B ramp buffer outputs (CRB_OUT[A], CRB_OUT[B]) may be substantially the same or similar.

[0070] The A ramp buffer output (CRB_OUT[A]) can be provided to the A non-inverting input (INp[A]) through the A non-inverting input capacitor (Cp[A]) of the A ADC circuit (ADC[A]). The B ramp buffer output (CRB_OUT[B]) can be provided to the second non-inverting input (INp[B]) through the B non-inverting input capacitor (Cp[B]) of the B ADC circuit (ADC[B]). That is, during the interval of the third to fifth time points (t3~t5), the A and B non-inverting inputs (INp[A], INp[B]) can be reduced in a form similar to the A and B ramp buffer outputs (CRB_OUT[A], CRB_OUT[B]), respectively.

[0071] The A ADC circuit (ADC[A]) can compare the A non-inverting input (INp[A]) and the A inverting input (INn[A]). The B ADC circuit (ADC[B]) can compare the B non-inverting input (INp[B]) and the B inverting input (INn[B]). At this time, the A inverting input (INn[A]) can correspond to the reset level of the A pixel voltage (VPIX[A]), and the B inverting input (INn[B]) can correspond to the reset level of the B pixel voltage (VPIX[B]).

[0072] In this case, the A and B non-inverting inputs (INp[A], INp[B]) have similar waveforms, and the A and B inverting inputs (INn[A], INn[B]) may have similar levels. Therefore, the point at which the A non-inverting input (INp[A]) becomes lower than the A inverting input (INn[A]) and the point at which it becomes lower than the B non-inverting input (INp[B]) and the B inverting input (INn[B]) may be the same (e.g., the fourth point in time (t4)). In this case, the A and B comparison signals (COMP[A], COMP[B]) generated from the A and B ADC circuits (ADC[A], ADC[B]) may change to a high level simultaneously or within a short time interval.

[0073] At the point when comparison signals A and B (COMP[A], COMP[B]) change to a high level, fluctuations may occur in the power supply voltage (VDD) connected to the ADC circuits. Alternatively, although not illustrated in the drawing, fluctuations may occur in the ground voltage (VSS) connected to the ADC circuits. That is, during the reset sampling interval, if multiple ADC circuits (ADC[A]–ADC[n]) perform sampling simultaneously or within a short time interval (i.e., if comparison signals are output simultaneously), noise may occur due to abrupt fluctuations in the power supply voltage or ground voltage. This degrades the overall operational reliability of the image sensor device.

[0074] FIG. 5 is a block diagram showing the variable ramp buffer and ADC circuit of the image sensor device of FIG. 1. For convenience of explanation, a detailed description of the previously described components is omitted. Referring to FIG. 1 and FIG. 5, the image sensor (100) may include a first variable ramp buffer (vCRB[A]), a second variable ramp buffer (vCRB[B]), a first ADC circuit (ADC[A]), and a second ADC circuit (ADC[B]). Since the first ADC circuit (ADC[A]) and the second ADC circuit (ADC[B]) have been described with reference to FIG. 4a, a detailed description thereof is omitted.

[0075] A variable ramp buffer (vCRB[A]) can generate a first ramp output voltage (vCRB_OUT[A]) in response to a ramp signal (RAMP) (hereinafter, for convenience of explanation, the output of the variable ramp buffer is referred to as the "ramp output voltage"). For example, the first variable ramp buffer (vCRB[A]) may include a first driving transistor (MPd[A]), a first current bias circuit (CB[A]), and a first current control circuit (CC[A]). In one embodiment, the first driving transistor (MPd[A]) and the first current bias circuit (CB[A]) are similar to those described with reference to FIG. 4a, so a detailed description thereof is omitted.

[0076] The A current control circuit (CC[A]) may be configured to control the bias current generated by the A current bias circuit (CB[A]) or flowing through the A current bias circuit (CB[A]). In one embodiment, when the bias current of the A variable ramp buffer (vCRB[A]) is varied, the level of the A ramp output voltage (vCRB_OUT[A]) may be varied. For example, when the bias current is decreased, the level of the A ramp output voltage (vCRB_OUT[A]) may be decreased. When the bias current is increased, the level of the A ramp output voltage (vCRB_OUT[A]) may be increased.

[0077] The B variable ramp buffer (vCRB[B]) can generate a B ramp output voltage (vCRB_OUT[B]) in response to a ramp signal (RAMP). For example, the B variable ramp buffer (vCRB[B]) may include a driving transistor (MPd[B]), a B current bias circuit (CB[B]), and a B current control circuit (CC[B]). In one embodiment, the B driving transistor (MPd[B]) and the second current bias circuit (CB[B]) are similar to those described with reference to FIG. 4a, so a detailed description thereof is omitted.

[0078] The B current control circuit (CC[B]) may be configured to control the bias current generated by or flowing through the B current bias circuit (CB[B]). Since the operation of the B current control circuit (CC[B]) is similar to the operation of the A current control circuit (CC[A]), a detailed description thereof is omitted.

[0079] In one embodiment, the A and B driving transistors (MPd[A], MPd[A]) may operate in response to the same ramp signal (RAMP). The A and B current bias circuits (CB[A], CB[B]) may operate in response to the same bias signals. On the other hand, the A current control circuit (CC[A]) and the B current control circuit (CC[B]) may operate in response to different control signals.

[0080] That is, as the A current control circuit (CC[A]) and the B current control circuit (CC[B]) are controlled individually, the bias currents of the A and B variable ramp buffers (vCRB[A], vCRB[B]) can be controlled individually. Accordingly, the first and second ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can also be controlled individually.

[0081] By individually controlling the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]), the A non-inverting input (INp[A]) of the A ADC circuit (ADC[A]) and the B non-inverting input (INp[B]) of the B ADC circuit (ADC[B]) may have a predetermined offset. In this case, even if the A and B pixel voltages (VPIX[A], VPIX[B]) have the same or similar levels, the sampling timing of the A and B ADC circuits (ADC[A], ADC[B]) (i.e., the timings when the A and B comparison signals (COMP[A], COMP[B]) become high levels) may be dispersed. Accordingly, abrupt fluctuations in the power supply voltage (VDD) or ground voltage (VSS) can be prevented. The structure and operation of a variable ramp buffer according to an embodiment of the present invention will be described in more detail with reference to the drawings below.

[0082] FIG. 6 is a circuit diagram showing the variable ramp buffers of FIG. 5. Referring to FIG. 1, FIG. 5, and FIG. 6, the A variable ramp buffer (CRB[A]) may include an A driving transistor (MPd[A]), a first A bias transistor (MPb1[A]), a second A bias transistor (MPB2[A]), and an A current control circuit (CC[A]). The A current control circuit (CC[A]) may include a first A control transistor (MPc1[A]), a second A control transistor (MPC2), and an A control switch circuit (SW[A]). In one embodiment, the A driving transistor (MPd[A]), the first A bias transistor (MPb1[A]), the second A bias transistor (MPB2[A]), the first A control transistor (MPc1[A]), and the second A control transistor (MPc2[A]) may each be a PMOS transistor.

[0083] The A driving transistor (MPd[A]), the 1A bias transistor (MPb1), and the 2A bias transistor (MPB2) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The 1A control transistor (MPc1[A]) may be connected between the power supply voltage (VDD) and the 1st control switch circuit (SW[A]). The 2A control transistor (MPc2[A]) may be connected between the power supply voltage (VDD) and the 1st control switch circuit (SW[A]).

[0084] The first control switch circuit (SW[A]) may include a plurality of control switches. For example, one of the plurality of control switches of the first control switch circuit (SW[A]) may be configured to switch between the first A node (n1[A]) and the first control transistor (MPc1[A]). Another of the plurality of control switches of the first control switch circuit (SW[A]) may be configured to switch between the first A node (n1[A]) and the first control transistor (MPc1[A]). The first A node (n1[A]) may be a node between the first A and second A bias transistors (MPb1[A], MPb2[A]).

[0085] The B variable ramp buffer (CRB[B]) may include a B driving transistor (MPd[B]), a first B bias transistor (MPb1[B]), a second B bias transistor (MPB2[B]), and a B current control circuit (CC[B]). The B current control circuit (CC[B]) may include a first B control transistor (MPc1[B]), a second B control transistor (MPC2), and a B control switch circuit (SW[B]). In one embodiment, the B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), the second B bias transistor (MPB2[B]), the first B control transistor (MPc1[B]), and the second B control transistor (MPc2[B]) may each be a PMOS transistor.

[0086] The B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), and the second B bias transistor (MPb2[B]) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The first B control transistor (MPc1[B]) may be connected between the power supply voltage (VDD) and the B control switch circuit (SW[B]). The second B control transistor (MPc2[B]) may be connected between the power supply voltage (VDD) and the B control switch circuit (SW[B]).

[0087] The second control switch circuit (SW[B]) may include a plurality of control switches. For example, one of the plurality of control switches of the second control switch circuit (SW[B]) may be configured to switch between the first B node (n1[B]) and the first control transistor (MPc1[B]). Another of the plurality of control switches of the second control switch circuit (SW[B]) may be configured to switch between the first B node (n1[B]) and the first control transistor (MPc1[B]). The first B node (n1[B]) may be a node between the first and second bias transistors (MPb1[B], MPb2[B]).

[0088] The A and B driving transistors (MPd[A], MPd[A]) can operate in response to a ramp signal (RAMP). The 1A and 1B bias transistors (MPb1[A], MPb1[B]) can operate in response to a first bias signal (CP). The 2A and 2B bias transistors (MPb2[A], MPb2[B]), the 1A and 1B control transistors (MPc1[A], MPc1[B]), and the 2A and 2B control transistors (MPc2[A], MPc2[A]), each of which can operate in response to a second bias signal (BP).

[0089] In one embodiment, depending on the switching operation of the A control switch circuit (SW[A]) and the B control switch circuit (SW[B]), the first and second bias currents (i b1 , i b2 The magnitude of ) can be adjusted. In one embodiment, the first bias current (i b1 ) may refer to the current provided to the A node (n[A]). The second bias current (i b2 ) may refer to the current provided to the B node (n[B]). The first and second bias currents (i b1 , i b2 ) can be determined based on the connection structure of the bias transistors, the effective size (e.g., W / L, etc.), or the gate voltage (e.g., the magnitude of the bias signals).

[0090] For example, the A control switch circuit (SW[A]) can operate in response to the A control signal (CTRL[A]), and the B control switch circuit (SW[B]) can operate in response to the B control signal (CTRL[B]). That is, the A and B control switch circuits (SW[A], SW[B]) can be controlled individually. In one embodiment, the A and B control signals (CTRL[A], CTRL[B]) can be generated by the ramp buffer controller (150) of FIG. 1.

[0091] When the first and second control transistors (MPc1[A], MPc2[A]) are connected to the first A node (n1[A]) by the A control switch circuit (SW[A]), the second A bias transistor (MPb2[A]) operating in response to the second bias signal (BP) and the first A and second A control transistors (MPc1[A], MPc2[A]) are connected in parallel. In this case, since the effective width of the channel of the transistor operating in response to the second bias signal (BP) increases, the first bias current (i b1 ) can increase relatively. The first bias current (ib1 If ) increases relatively, the A lamp output voltage (vCRB_OUT[A]) output through the A node (n[A]) may increase.

[0092] As another example, when the first B and second B control transistors (MPc1[B], MPc2[B]) are not connected to the first B node (n1[B]) by the B control switch circuit (SW[B]), only the second B bias transistor (MPb2[B]) operates in response to the second bias signal (BP), so the second bias current (i b2 ) can be relatively reduced. The second bias current (i b1 If ) decreases relatively, the B ramp output voltage (vCRB_OUT[B]) output through the B node (n[B]) may decrease.

[0093] As described above, by the operation of the A and B control switch circuits (SW[A], SW[B]), the first and second bias currents (i b1 , i b2 ) can be controlled individually, and accordingly, the first and second lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be controlled individually.

[0094] FIGS. 7a and 7b are diagrams illustrating the operation of applying an offset to the inverting input terminal of the first amplifier by means of the operation of the A variable ramp buffer of FIG. 6. Referring to FIGS. 7a and 7b, the A variable ramp buffer (vCRB[A]) may include an A driving transistor (MPd[A]), 1A and 2A bias transistors (MPb1[A], MPb2[A]), 1A and 2A control transistors (MPc1[A], MPc2[A]), and an A control switch circuit (SW[A]). The 1A amplifier (OTA1[A]) may include a plurality of transistors (MP1, MP2, MN0, MN1, MN2), auto zero switches (AZS1[A], AZS2[A]), and input capacitors (Cp[A], Cn[A]). The structure of the A variable ramp buffer (vCRB[A]) and the 1A amplifier (OTA1[A]) has been described previously, so a detailed description thereof is omitted.

[0095] First, referring to FIG. 7a, the A variable ramp buffer (vCRB[A]) can generate an A ramp output voltage (vCRB_OUT[A]) in response to a ramp signal (RAMP). The 1A amplifier (OTA1[A]) can receive the A ramp output voltage (vCRB_OUT[A]) as an A non-inverting input (INp[A]) through the A non-inverting input capacitor (Cp[A]). The A amplifier (OAT1[A]) can receive the A pixel voltage (VPIX[A]) as an A inverting input (INn[A]) through the A inverting input capacitor (Cn[A]).

[0096] The first A amplifier (OTA1[A]) may perform an auto-zero operation before performing a comparison operation. For example, in response to an auto-zero signal (AZ), the first A and second A auto-zero switches (AZS1[A], AZS2[A]) of the first A amplifier (OTA1[A]) may be turned on. Accordingly, the A non-inverting input (INp[A]) and the A inverting input (INn[A]) may be initialized. As an example, it is assumed that the A non-inverting input (INp[A]) is set to a first voltage (V1) by the auto-zero operation.

[0097] While the auto-zero operation is being performed, the A control switch circuit (SW[A]) of the A variable ramp buffer (vCRB[A]) can be turned on in response to the A control signal (CTRL[A]). For example, the first and second control transistors (MPc1[A], MPc2[A]) can be connected to the first A node (n1[A]) by the A control switch circuit (SW[A]).

[0098] Accordingly, the first bias current (i b1 ) can be generated through the 1A and 2A control transistors (MPc1[A], MPc2[A]) and the 2A bias transistor (MPb2[A]). In this case, the 1st bias current (i b1 ) can have a magnitude of i0+α. The first bias current (i b1 When ) has a magnitude of i0+α, the A ramp output voltage (vCRB_OUT[A]) can have a magnitude of V0+ΔV. That is, in the auto-zero operation of the first amplifier (OTA1[A]), the first ramp output voltage (vCRB_OUT[A]) has a magnitude of V0+ΔV, and the first non-inverting input (INp[A]) of the first amplifier (OTA1[A]) can have a magnitude of V1.

[0099] Next, referring to FIG. 7b, the A amplifier (OTA1[A]) can complete the auto-zero operation. In this case, the 1A and 2A auto-zero switches (AZS1[A], AZS2[A]) can be turned off. Some of the control switches in the A control switch circuit (SW[A]) of the A variable ramp buffer (vCRB[A]) can be turned off. For example, the control switch between the 1A control transistor (MPc1[A]) and the 1A node (n1[A]) can be turned off. In this case, the first bias current (i b1 ) is generated by the 2A bias transistor (MPb2[A]) and the 2A control transistor (MPc2[A]), so it can be relatively reduced.

[0100] As an example, the first bias current (i b1 ) can decrease from i0+α to i0. (i.e., decrease by α) The first bias current (i b1 As ) decreases to i0, the A ramp output voltage (vCRB_OUT[A]) can decrease from V0+ΔV to V0 (i.e., decrease by ΔV). As the A ramp output voltage (vCRB_OUT[A]) decreases, the A non-inverting input (INp[A]) can decrease by ΔV due to the A non-inverting input capacitor (Cp[A]). Consequently, due to the operation of the A variable ramp buffer (vCRB[A]), the A non-inverting input (INp[A]) of the 1A amplifier (OTA1[A]) can be adjusted to V1-ΔV after auto-zero operation. In other words, an offset of -ΔV can be applied to the A non-inverting input (INp[A]) of the 1A amplifier (OTA1[A]).

[0101] As described above, as the bias current of the variable ramp buffer is controlled individually, the offset of the non-inverting input to the multiple ADC circuits can be individually adjusted. In this case, the sampling timing of the multiple ADC circuits can be distributed.

[0102] FIG. 8 is a timing diagram showing the operation of the variable ramp buffers and ADC circuits of FIG. 5. FIG. 9a and FIG. 9b are diagrams for explaining the operation of the variable ramp buffers according to the flowchart of FIG. 8. Referring to FIG. 5, FIG. 6, FIG. 8, FIG. 9a, and FIG. 9b, during the interval (t1-t2) of the first and second time points, the A and B ADC circuits (ADC[A], ADC[B]) can perform an auto-zero operation. For example, during the interval (t1-t2) of the first and second time points, the auto-zero signal (AZ) can maintain a high level. In response to the high-level auto-zero signal (AZ), the auto-zero switches (AZS1[A], AZS2[A], AZS1[B], AZS2[B]) of the A and B ADC circuits (ADC[A], ADC[B]) can be turned on. Accordingly, the A and B non-inverting inputs (INp[A], INp[B]) can be set to a predetermined level.

[0103] During the interval of the first and second time points (t1-t2) (i.e., during auto-zero operation), the A and B variable ramp buffers (vCRB[A], vCRB[B]) are the first and second bias currents (i b1 , i b2 By adjusting each of the A and B lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]), the A and B lamp output voltages can be adjusted.

[0104] For example, as illustrated in FIG. 9a, the A control switch circuit (SW[A]) of the A variable ramp buffer (vCRB[A]) can connect the 1A and 2A control transistors (MPc1[A], MPc2[A]) to the 1A node (n1[A]) in response to the A control signal (CTRL[A]). In this case, the first bias current (i) is passed through a first path (PT1) comprising the 2A bias transistor (MPb2[A]) and the 1A and 2A control transistors (MPc1[A], MPc2[A]). b1) can be generated. At this time, the first bias current (i b1 ) can have a magnitude of i0+α. The B control switch circuit (SW[B]) of the B variable ramp buffer (vCRB[B]) may not connect the 1B and 2B control transistors (MPc1[B], MPc2[B]) to the 1B node (n1[B]) in response to the B control signal (CTRL[B]). In this case, the second bias current (i) through the second path (PT2) including the 2B bias transistor (MPb2[B]) b2 ) can be generated. At this time, the second bias current (i b2 ) can have a magnitude of i0-β. As previously explained, the first bias current (i b1 ) is the second bias current (i b2 Because it is greater than ), the A lamp output voltage (vCRB_OUT[A]) can be greater than the B lamp output voltage (vCRB_OUT[B]).

[0105] In one embodiment, during auto-zero operation, the non-inverting input terminals (INp[A, INp[B]]) of the A and B ADC circuits (ADC[A], ADC[B]) are set to a specific level, and each of the A ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be set to a different level.

[0106] Again, referring to FIG. 8, at the second time point (t2), the auto-zero operation is terminated. For example, at the second time point (t2), the auto-zero signal (AZ) is changed to a low level. In response to the low-level auto-zero signal (AZ), the auto-zero switches (AZS1[A], AZS2[A], AZS1[B], AZS2[B]) of the A and B ADC circuits (ADC[A], ADC[B]) may be turned off.

[0107] At the second time point (t2), the A and B variable ramp buffers (vCRB[A], vCRB[B]) have first and second bias currents (ib1 , i b2 By adjusting ) respectively, the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be adjusted. For example, as shown in FIG. 9b, the A control switch circuit (SW[A]) of the A variable ramp buffer (vCRB[A]) may, in response to the A control signal (CTRL[A]), connect the 2A control transistor (MPc2[A]) to the 1A node (n1[A]) without connecting the 1A control transistor (MPc1[A]) to the 1A node (n1[A]). In this case, the first bias current (i) through the 2A bias transistor (MPb2[A]) and the 2A control transistor (MPc2[A]) b1 ) is generated. At this time, the first bias current (i b1 ) can be reduced to the magnitude of i0. The first bias current (i b1 As ) decreases, the magnitude of the A lamp output voltage (vCRB_OUT[A]) may decrease.

[0108] The B control switch circuit (SW[B]) of the B variable ramp buffer (vCRB[B]) can, in response to the B control signal (CTRL[B]), connect the 2B control transistor (MPc2[B]) to the 1B node (n1[B]) without connecting the 1B control transistor (MPc1[B]) to the 1B node (n1[B]). In this case, the 2B bias current (i) through the 2B bias transistor (MPb2[B]) and the 2B control transistor (MPc2[B]) b2 ) is generated. At this time, the second bias current (i b2 ) can be increased by the magnitude of i0. The second bias current (i b2 As ) increases, the magnitude of the B lamp output voltage (vCRB_OUT[B]) may increase.

[0109] In one embodiment, first and second bias currents (i b1 , i b2Since ) is substantially the same, the A and B lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]) will be set to the same level.

[0110] In one embodiment, after the auto-zero operation is performed, the A ramp output voltage (vCRB_OUT[A]) may decrease and the B ramp output voltage (vCRB_OUT[B]) may increase due to the operation of the A and B variable ramp buffers (vCRB[A], vCRB[B]). In this case, as described with reference to FIG. 7b, the A non-inverting input (INp[A]) may decrease as the A ramp output voltage (vCRB_OUT[A]) decreases, and the B non-inverting input (INp[B]) may increase as the B ramp output voltage (vCRB_OUT[B]) increases. In this case, the A non-inverting input (INp[A]) and the B non-inverting input (INp[B]) may have a predetermined difference (e.g., an offset) from each other. In one embodiment, the offset between the A non-inverting input (INp[A]) and the B non-inverting input (INp[B]) may be maintained in a subsequent sampling operation.

[0111] In one embodiment, for the sake of brevity of the drawings and convenience of explanation, it is described that the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) are controlled immediately after the auto-zero operation ends (e.g., at a second time point (t2)), but the scope of the present invention is not limited thereto. For example, the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) may be controlled after a predetermined time has elapsed from the second time point (t2). This is to generate coupling by fluctuations in the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) after the A and B non-inverting inputs (INp[A], INp[B]) are floating (i.e., after the auto-zero switches are turned off).

[0112] Subsequently, during the interval of the third to sixth time points (t3-t6), the A and B ADC circuits (ADC[A], ADC[B]) can perform a sampling operation. For example, a ramp generator (140) can generate a ramp signal (RAMP). The A and B variable ramp buffers (vCRB[A], vCRB[B]) can adjust the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) in response to the ramp signal (RAMP). In one embodiment, during the sampling interval, the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) may have the same level or the same waveform. On the other hand, since the A non-inverting input (INp[A]) and the B non-inverting input (INp[B]) have a certain difference (e.g., offset) from each other, even if the levels of the A and B inverting inputs (INn[A], INn[B]) are the same (in other words, the A and B pixel voltages (VPIX[A], VPIX[B]) are the same), the timing of sampling by the A and B ADC circuits (ADC[A], ADC[B]) can be dispersed.

[0113] For example, the A ADC circuit (ADC[A]) can generate an A comparison signal (COMP[A]) by comparing an A non-inverting input (INp[A]) and an A inverting input (INn[A]), and the B ADC circuit (ADC[B]) can generate a B comparison signal (COMP[B]) by comparing a B non-inverting input (INp[B]) and a B inverting input (INn[B]). At this time, the A non-inverting input (INp[A]) may be lower than the A inverting input (INn[A]) at a fourth time point (t5). In response to this, the A comparison signal (COMP[A]) may be generated. On the other hand, the B non-inverting input (INp[B]) may be lower than the B inverting input (INn[B]) at a fifth time point (t5) after the B fourth time point (t4). In response to this, the B comparison signal (COMP[B]) can be generated.

[0114] That is, in reset sampling, multiple ADC circuits (ADC[A]–ADC[n]) are configured to sample the reset levels of multiple pixel voltages (VPIX[A]–VPIX[n]), respectively. At this time, since the reset levels of the multiple pixel voltages (VPIX[A]–VPIX[n]) have the same or similar levels, if sampling is performed using the same ramp signal, multiple comparison signals are generated simultaneously at the same time or within a short period. In this case, due to the simultaneous generation of comparison signals, abrupt fluctuations in the power supply voltage (VDD) or ground voltage (VSS) may occur.

[0115] On the other hand, according to an embodiment of the present invention, different offsets can be applied to non-inverting inputs (INp) (or inputs corresponding to ramp signals) provided to amplifiers of a plurality of ADC circuits (ADC[A]–ADC[n]) using variable ramp buffers (vCRB). For example, during auto-zero operation for a plurality of ADC circuits (ADC[A]–ADC[n]), the variable ramp buffers (vCRB) can individually control each bias current. In this case, the ramp output voltages (vCRB_OUT) may have different levels. After auto-zero operation for a plurality of ADC circuits (ADC[A]–ADC[n]), the variable ramp buffers (vCRB) can adjust each bias current to a reference current (e.g., i0). In this case, the ramp output voltages (vCRB_OUT) may increase or decrease. By increasing or decreasing the ramp output voltages (vCRB_OUT), the non-inverting inputs (INp) provided to the amplifiers of the multiple ADC circuits (ADC[A] to ADC[n]) can be increased or decreased, respectively, and such increase or decrease can provide an offset between the non-inverting inputs (INp). Therefore, since sampling is performed using non-inverting inputs with different offsets in the multiple ADC circuits (ADC[A] to ADC[n]), the timing of the generation of the comparison signal can be dispersed. Consequently, abrupt fluctuations in the power supply voltage (VDD) or ground voltage (VSS) can be prevented.

[0116] In one embodiment, a plurality of pixel voltages (VPIX[A]–VPIX[n]) input to a plurality of ADC circuits (ADC[A]–ADC[n]) may be output through a plurality of column lines (CL[A]–CL[n]) from a plurality of pixels of the pixel error (110). In this case, the plurality of pixels may operate in response to the same selection signal (SEL). That is, the plurality of pixels may be located in the same row. Or the plurality of pixels may operate together during a single readout operation.

[0117] In the following, to facilitate the explanation of embodiments of the present invention, the structure or operation of a variable ramp buffer (vCRB) configured to control the outputs of the variable ramp buffer (vCRB) individually is described in detail. However, it will be understood that the scope of the present invention is not limited to the illustrated drawings and embodiments, and that the variable ramp buffers described below can be applied to the embodiments described above. That is, when the outputs of the variable ramp buffer (vCRB) are controlled individually, different offsets may be applied to the inputs of each of the plurality of ADC circuits according to the embodiments described above. Accordingly, the sampling timing of the ADC circuits is dispersed, and sudden fluctuations in the power supply voltage or ground voltage can be prevented.

[0118] FIG. 10 is a circuit diagram showing the variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 10, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-1, vCRB[B]-1). The A and B variable ramp buffers (vCRB[A]-1, vCRB[B]-1) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]) described above, respectively.

[0119] The A variable ramp buffer (vCRB[A]-1) may include an A driving transistor (MPd[A]), a 1A bias transistor (MPb1[A]), a 2A bias transistor (MPb2[A]), and an A current control circuit (CC[A]-1). The B variable ramp buffer (vCRB[B]-1) may include a B driving transistor (MPd[B]), a 1B bias transistor (MPb1[B]), a 2B bias transistor (MPb2[B]), and a B current control circuit (CC[B]-1). Since the A driving transistor (MPd[A]), the 1A bias transistor (MPb1[A]), the 2A bias transistor (MPb2[A]), the B driving transistor (MPd[B]), the 1B bias transistor (MPb1[B]), and the 2A bias transistor (MPb2[B]) have been described previously, a detailed description thereof is omitted.

[0120] The A current control circuit (CC[A]-1) may include a 3A control transistor (MPc3[A]) and a 4A control transistor (MPc4[A]). The 3A control transistor (MPc3[A]) is connected between the power supply voltage (VDD) and the 1A node (n1[A]) and may operate in response to a 3A control signal (CTRL3[A]). The 4A control transistor (MPc4[A]) is connected between the power supply voltage (VDD) and the 1A node (n1[A]) and may operate in response to a 4A control signal (CTRL3[A]).

[0121] The B current control circuit (CC[B]-1) may include a 3B control transistor (MPc3[B]) and a 4B control transistor (MPc4[B]). The 3B control transistor (MPc3[B]) is connected between the power supply voltage (VDD) and the 1B node (n1[B]) and can operate in response to a 3B control signal (CTRL3[B]). The 4B control transistor (MPc4[B]) is connected between the power supply voltage (VDD) and the 1B node (n1[B]) and can operate in response to a 4B control signal (CTRL4[B]).

[0122] Similar to what was previously described, the A and B variable ramp buffers (vCRB[A]-1, vCRB[B]-1) each have first and second bias currents (i b1 , i b2 ) can be controlled. For example, during auto-zero operation, the A current control circuit (CC[A]-1) can turn on the 3A control transistor (MPc3[A]) and the 4A control transistor (MPc4[A]), and the B current control circuit (CC[B]-1) can turn off the 3B control transistor (MPc3[B]) and the 4B control transistor (MPc4[B]). In this case, the first bias current (i b1 ) is the second bias current (i b2 It can be larger than )

[0123] After the auto-zero operation, the A current control circuit (CC[A]-1) can turn off the 3A control transistor (MPc3[A]) and turn on the 4A control transistor (MPc4[A]). The B current control circuit (CC[B]-1) can turn off the 3B control transistor (MPc3[B]) and turn on the 4B control transistor (MPc4[B]). In this case, the first bias current (i b1 ) decreases, and the second bias current (i b2 ) can increase. The first bias current (i b1Due to the decrease of ), the A lamp output voltage (vCRB_OUT[A]) may decrease, and the second bias current (i b2 As ) increases, the B ramp output voltage (vCRB_OUT[B]) may decrease. Accordingly, an offset may be applied to the non-inverting inputs (INp[A], INp[B]) of the ADC circuits (ADC[A], ADC[B]). Since the operating principle for this has been explained previously, a detailed explanation thereof is omitted.

[0124] As described above, each of the A and B variable ramp buffers (vCRB[A]-1, vCRB[B]-1) can control the bias current by directly turning on or off the control transistors. Depending on the control of the bias current, the ramp output voltage (vCRB_OUT) can be controlled, and accordingly, an offset can be applied to the non-inverting inputs (INp[A], INp[B]) of the ADC circuits (ADC[A], ADC[B]).

[0125] FIG. 11 is a circuit diagram showing the variable ramp buffer of FIG. 1. FIG. 12a and FIG. 12b are drawings for explaining the operation of the variable ramp buffer of FIG. 11. Referring to FIG. 1, FIG. 11, FIG. 12a, and FIG. 12b, the image sensor device (100) may include a first variable ramp buffer (vCRB[A]-2), a second variable ramp buffer (vCRB[B]-2), and a third control switch circuit (SW[A / B]). The first variable ramp buffer (vCRB[A]-2) and the second variable ramp buffer (vCRB[B]-2) may correspond to the first and second variable ramp buffers (vCRB[A], vCRB[B]) described above.

[0126] The A variable ramp buffer (vCRB[A]-2) may include an A driving transistor (MPd[A]), a 1A bias transistor (MPb1[A]), a 2A bias transistor (MPb2[A]), and an A current control circuit (MPc[A]). The B variable ramp buffer (vCRB[B]-2) may include a B driving transistor (MPd[B]), a 1B bias transistor (MPb1[B]), a 2B bias transistor (MPb2[B]), and a B current control circuit (MPc[B]). Since the A driving transistor (MPd[A]), the 1A bias transistor (MPb1[A]), the 2A bias transistor (MPb2[A]), the B driving transistor (MPd[B]), the 1B bias transistor (MPb1[B]), and the 2B bias transistor (MPb2[B]) are similar to those previously described, a detailed description thereof is omitted.

[0127] The A current control circuit (CC[A]-2) may include a first A control transistor (MPc1[A]) and an A control switch circuit (SW[A]). The first A control transistor (MPc1[A]) and the A control switch (SW[A]) may be connected in series between the first A nodes (n1[A]). The first A control transistor (MPc1[A]) may operate in response to a second bias signal (BP). The A control switch circuit (SW[A]) may operate in response to an A control signal (CTRL[A]).

[0128] The B current control circuit (CC[B]-2) may include a first B control transistor (MPc1[B]) and a B control switch circuit (SW[B]). The first B control transistor (MPc1[B]) and the B control switch (SW[B]) may be connected in series between the first B nodes (n1[B]). The first B control transistor (MPc1[B]) may operate in response to a second bias signal (BP). The B control switch circuit (SW[A]) may operate in response to a B control signal (CTRL[B]).

[0129] The AB control switch circuit (SW[A / B]) may be connected between the A current control circuit (CC[A]-2) and the B current control circuit (CC[B]-2). For example, the AB control switch circuit (SW[A / B]) may be connected between the first node of the A current control circuit (CC[A]-2) and the second node of the B current control circuit (CC[B]-2). The first node of the A current control circuit (CC[A]-2) may refer to the node between the first A control transistor (MPc1[A]) and the A control switch circuit (SW[A]). The second node of the B current control circuit (CC[B]-2) may refer to the node between the first B control transistor (MPc1[B]) and the B control switch circuit (SW[B]). The AB control switch circuit (SW[A / B]) can operate in response to the AB control signals (CTRL[A / B]).

[0130] In one embodiment, the A, B, and AB control signals (CTRL[A], CTRL[B], CTRL[A / B]) can each be controlled individually. That is, the A, B, and AB control switch circuits (SW[A], SW[B], SW[A / B]) can operate individually or independently. Depending on the operation of the A, B, and AB control switch circuits (SW[A], SW[B], SW[A / B]), the bias currents (i) of the A and B variable ramp buffers (vCRB[A], vCRB[B]) b1 , i b2 ) can be controlled.

[0131] For example, as illustrated in FIG. 12a, during the auto-zero operation of the ADC circuits, the A and B control switch circuits (SW[A], SW[A / B]) may be turned on, and the B control switch circuit (SW[B]) may be turned off. In this case, the 2A bias transistor (MPb2[A]) and the A control transistor (MPc[A]) of the A variable ramp buffer (vCRB[A]-2), and the B control transistor (MPc[B]) of the B variable ramp buffer (vCRB[B]-2) are connected in parallel. That is, through the three transistors (MPb2[A], MPc[A], MPc[B]), the first bias current (i b1 ) can be generated. On the other hand, the second bias current (i b2 ) is generated through the 2B bias transistor (MPb2[B]) (i.e., one transistor). In this case, the 1st bias current (i b1 ) can have a relatively large magnitude of i0+α, and the second bias current (i b2 ) can have a relatively small magnitude of i0-β. Accordingly, the A lamp output voltage (vCRB_OUT[A]) can be greater than the B lamp output voltage (vCRB_OUT[B]).

[0132] Next, as illustrated in FIG. 12b, during the sampling operation of the ADC circuits, the A and B control switch circuits (SW[A], SW[B]) may be turned on, and the AB control switch circuit (SW[A / B]) may be turned off. In this case, the first bias current (i) is applied through the 2A bias transistor (MPb2[A]) and the A control transistor (MPc[A]) (i.e., two transistors) of the A variable ramp buffer (vCRB[A]-2). b1 ) is generated, and a second bias current (i) is generated through the second B bias transistor (MPb2[B]) and the second B control transistor (MPc[B]) (i.e., two transistors) of the second B variable ramp buffer (vCRB[B]-2). b2) can be generated. In this case, the first and second bias currents (i b1 , i b2 ) can be identical to each other. Accordingly, the A and B lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be identical to each other.

[0133] As described above, the variable ramp buffers (vCRB) control the bias current through a switching operation so that the ramp output voltage (vCRB_OUT) can be controlled individually for each column. Accordingly, different offsets can be applied to the non-inverting inputs of each of the multiple ADC circuits. In this case, it is prevented that the multiple ADC circuits perform simultaneous sampling (i.e., that the comparison signal (COMP) is generated simultaneously) in reset sampling or low-light environments, and accordingly, sudden fluctuations in the power supply voltage or ground voltage can be prevented. The configuration of the variable ramp buffer described above is merely an example, and the scope of the present invention is not limited thereto.

[0134] FIG. 13 is a circuit diagram showing the variable ramp buffer of FIG. 1. FIG. 14a and FIG. 14b are drawings for explaining the operation of the variable ramp buffer of FIG. 13. Referring to FIG. 1, FIG. 13, FIG. 14a, and FIG. 14b, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-3, vCRB[B]-3). The A and B variable ramp buffers (vCRB[A]-3, vCRB[B]-3) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]), respectively.

[0135] The A variable ramp buffer (vCRB[A]-3) may include an A driving transistor (MPd[A]), a first A bias transistor (MPb1[A]), and a second A bias transistor (MPb2[A]). The A driving transistor (MPd[A]), the first A bias transistor (MPb1[A]), and the second A bias transistor (MPb2[A]) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD).

[0136] The B variable ramp buffer (vCRB[B]-3) may include a B driving transistor (MPd[B]), a first B bias transistor (MPb1[B]), and a second B bias transistor (MPb2[B]). The B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), and the second B bias transistor (MPb2[B]) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD).

[0137] Similar to what was previously described, the A and B driving transistors (MPd[A], MPd[B]) can operate in response to a ramp signal (RAMP), and the 1A and 1B bias transistors (MPb1[A], MPb1[B]) can operate in response to a first bias signal (CP).

[0138] On the other hand, the 2A bias transistor (MPb2[A]) can operate in response to the 2A bias signal (BP[A]), and the 2B bias transistor (MPb2[B]) can operate in response to the 2B bias signal (BP[B]). In this case, the 2A and 2B bias signals (BP[A], BP[B]) can each be controlled individually. That is, the 2A and 2B bias transistors (MPb2[A], MPb2[B]) can each operate in response to the individually controlled bias signals (BP[A], BP[B]). In this case, through the 2A and 2B bias signals (BP[A], BP[B]), the bias currents (i) of the A and B variable ramp buffers (vCRB[A]-3, vCRB[B]-3) b1 , i b2 ) and outputs (vCRB_OUT[A], vCRB_OUT[B]) can be controlled individually.

[0139] For example, as illustrated in FIG. 14a, during the auto-zero operation of the ADC circuits, the second A bias signal (BP[A]) may be provided at a first voltage (V1), and the second B bias signal (BP[B]) may be provided at a second voltage (V2) lower than the first voltage (V1). In this case, the first bias current (i) of the A variable ramp buffer (vCRB[A]-3) b1 ) can have a magnitude of i0+α, and the second bias current (i) of the B variable ramp buffer (vCRB[B]-3) b1 ) can have a magnitude of i0-β. Therefore, the A lamp output voltage (vCRB_OUT[A]) can be greater than the B lamp output voltage (vCRB_OUT[B]).

[0140] Next, as illustrated in FIG. 14b, after the auto-zero operation of the ADC circuits is completed, the 2A and 2B bias signals (BP[A], BP[B]) can be provided as a zero voltage (V0). In this case, the first and second bias currents (ib1 , i b2 ) can be the same as i0. Therefore, the A and B lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be the same as each other.

[0141] As described above, the bias signals applied to the bias transistors of the variable ramp buffers (vCRB) can be individually controlled so that the ramp output voltage can be controlled, and accordingly, different offsets can be applied to the inputs of the plurality of ADC circuits.

[0142] FIG. 15 is a circuit diagram showing the variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 15, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-4, vCRB[B]-4). The A and B variable ramp buffers (vCRB[A]-4, vCRB[B]-4) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]) described above, respectively.

[0143] The A variable ramp buffer (vCRB[A]-4) may include an A driving transistor (MPd[A]), a first A bias transistor (MPb1[A]), a second A bias transistor (MPb2[A]), and an A gate control circuit (GCC[A]-4). The A driving transistor (MPd[A]), the first A bias transistor (MPb1[A]), and the second A bias transistor (MPb2[A]) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS).

[0144] The B variable ramp buffer (vCRB[B]-4) may include a B driving transistor (MPd[B]), a first B bias transistor (MPb1[B]), a second B bias transistor (MPb2[B]), and a B gate control circuit (GCC[B]-4). The B driving transistor (MPd[B]), the first B bias transistor (MPb1[B]), and the second A bias transistor (MPb2[A]) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS).

[0145] The A and B driving transistors (MPd[A], MPd[B]) can operate in response to a ramp signal (RAMP). The 1A and 1B bias transistors (MPb1[A], MPb1[B]) can operate in response to a first bias signal (CP). The 2A bias transistor (MPb2[A]) can operate in response to a gate voltage (vg1). The 2B bias transistor (MPb2[B]) can operate in response to a second gate voltage (vg2).

[0146] In one embodiment, the first gate voltage (vg1) can be generated by the A gate control circuit (GCC[A]-4), and the second gate voltage (vg2) can be generated by the B gate control circuit (GCC[B]-4). For example, the A gate control circuit (GCC[A]-4) can generate the first gate voltage (vg1) based on the second bias signal (BP) in response to the A control signal (CTRL[A]). The B gate control circuit (GCC[B]-4) can generate the second gate voltage (vg2) based on the second bias signal (BP) in response to the B control signal (CTRL[B]).

[0147] In one embodiment, according to the first gate voltage (vg1), a first bias current (i b1 The magnitude of ) can be controlled, and depending on the second gate voltage (vg2), the second bias current (i b2The magnitude of ) can be controlled. Accordingly, as the first and second gate voltages (vg1, vg2) are controlled individually, the A and B ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be controlled individually.

[0148] FIG. 16 is a circuit diagram showing the variable ramp buffer of FIG. 15. FIG. 17 is a timing diagram to explain the operation of the variable ramp buffer of FIG. 16. For convenience of explanation, detailed descriptions of the previously described components are omitted.

[0149] Referring to FIGS. 1, 15, and 16, the A gate control circuit (GCC[A]-4) may include an A sampling transistor (MP_SP[A]), an A sampling capacitor (C_SP[A]), and an A dummy control switch (dSW[A]). The A sampling transistor (MP_SP[A]) may be connected between the gate of a second bias signal (BP) and a second A bias transistor (MPb2[A]). In one embodiment, the A sampling transistor (MP_SP[A]) may be a PMOS transistor and may operate in response to a sampling signal (SMP). The A sampling capacitor (C_SP[A]) may be connected between the power supply voltage (VDD) and the gate of the second A bias transistor (MPb2[A]). The A dummy control switch (dSW[A]) may include a plurality of PMOS transistors connected to the gate of the second A bias transistor (MPb2[A]). Multiple PMOS transistors can operate in response to the A control signal (CTRL[A]).

[0150] The B gate control circuit (GCC[B]-4) may include a B sampling transistor (MP_SP[B]), a B sampling capacitor (C_SP[B]), and a B dummy control switch (dSW[B]). The B sampling transistor (MP_SP[B]) may be connected between the gate of the second bias signal (BP) and the gate of the second B bias transistor (MPb2[B]). In one embodiment, the B sampling transistor (MP_SP[B]) may be a PMOS transistor and may operate in response to the sampling signal (SMP). The B sampling capacitor (C_SP[B]) may be connected between the power supply voltage (VDD) and the gate of the second B bias transistor (MPb2[B]). The B dummy control switch (dSW[B]) may include a plurality of PMOS transistors connected to the gate of the second B bias transistor (MPb2[B]). Multiple PMOS transistors can operate in response to the B control signal (CTRL[B]).

[0151] In one embodiment, the gate voltages A and B (vg[A], vg[B]) can be individually controlled according to the operation of the A and B dummy control switches (dSW[A], dSW[B]). For example, as shown in FIG. 17, during the interval (ta-tb) of time points a and b, the sampling signal (SMP) can be maintained at a logic low. In response to the sampling signal (SMP) at a logic low, the A and B sampling transistors (MP_SP[A], MP_SP[B]) can be turned on. Accordingly, the A and B sampling capacitors (C_SP[A], C_SP[B]) can be charged to a level corresponding to the second bias signal (BP). In other words, the gate voltages A and B (vg[A], vg[B]) can be charged to a level corresponding to the second bias signal (BP).

[0152] Subsequently, during the interval of the first and second time points (t1-t2), the auto-zero signal (AZ) may be maintained at a high level. That is, during the interval of the first and second time points (t1-t2), an auto-zero operation for the ADC circuits may be performed. During the interval of the first and second time points (t1-t2) (i.e., the auto-zero operation interval), at least some PMOS transistors of the A dummy control switch (dSW[A]) may be turned off in response to the A control signal (CTRL[A]). In this case, due to the clock feedthrough effect caused by the switching operation of the A dummy control switch (dSW[A]), the amount of charge stored in the A sampling capacitor (C_SP[A]) varies. The change in the amount of charge of the A sampling capacitor (C_SP[A]) causes a change in the A gate voltage (vg[A]). In one embodiment, the A gate voltage (vg[A]) can be increased to a predetermined level by the switching operation of the A dummy control switch (dSW[A]). Subsequently, when the PMOS transistors of the A dummy control switch (dSW[A]) are turned on, the A gate voltage (vg[A]) can be maintained at a constant level again.

[0153] During the interval of the first and second time points (t1-t2) (i.e., the auto-zero operation interval), the B dummy control switch (dSW[A]) does not perform a switching operation. In this case, the B gate voltage (vg[B]) can be maintained constant.

[0154] As described above, the gate voltages A and B (vg[A], vg[B]) can be individually controlled by the switching operation of the A and B dummy control switches (dSW[A], dSW[B]). In this case, the first and second bias currents (i b1 , i b2) can be controlled individually, and accordingly, the A and B lamp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be controlled individually.

[0155] Subsequent operations (e.g., application of offsets to the non-inverting inputs (INp[A], INp[B]) of the A and B ADC circuits (ADC[A], ADC[B])) and the resulting effects (variance in sampling timing) are similar to those described with reference to FIG. 8, so a detailed description thereof is omitted.

[0156] As described above, in the A and B variable ramp buffers (vCRB[A]-4, vCRB[B]-4), the A and B gate voltages (vg[A], vg[B]) can be controlled through the switching operation of the A and B dummy control switches (dSW[A], dSW[B]). Accordingly, the A and B ramp output voltages (vCRB_OUT[A]), vCRB_OUT[B]) can be controlled individually.

[0157] In one embodiment, the amount of change in the gate voltages A and B (vg[A], vg[B]) can be controlled by adjusting the number of PMOS transistors performing the switching operation in the A and B dummy control switches (dSW[A], dSW[B]). For example, if n PMOS transistors among the PMOS transistors of the A dummy control switch (dSW[A]) perform the switching operation, the A gate voltage (vg[A]) may have a level of Vn. If m PMOS transistors different from n among the PMOS transistors of the A dummy control switch (dSW[A]) perform the switching operation, the A gate voltage (vg[A]) may have a level of Vm different from Vn. That is, depending on the number of PMOS transistors performing the switching operation, the effective size of the control switch that causes the clock feedthrough effect is varied, and accordingly, the amount of change in the gate voltage can be varied.

[0158] FIG. 18 is a circuit diagram showing the variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 18, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-5, vCRB[B]-5). The A and B variable ramp buffers (vCRB[A]-5, vCRB[B]-5) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]), respectively.

[0159] The A variable ramp buffer (vCRB[A]-5) may include an A driving transistor (MPd[A]), a 1A bias transistor (MPb1[A]), a 2A bias transistor (MPb2[A]), an A sampling transistor (MP_SP[A]), and an A variable sampling capacitor (vC_SP[A]). The B variable ramp buffer (vCRB[B]-5) may include a B driving transistor (MPd[B]), a 1B bias transistor (MPb1[B]), a 2B bias transistor (MPb2[B]), a B sampling transistor (MP_SP[B]), and a B variable sampling capacitor (vC_SP[B]).

[0160] The A driving transistor (MPd[A]), the 1A bias transistor (MPb1[A]), the 2A bias transistor (MPb2[A]), the A sampling transistor (MP_SP[A]), the B driving transistor (MPd[B]), the 1B bias transistor (MPb1[B]), the 2B bias transistor (MPb2[B]), and the B sampling transistor (MP_SP[B]) have been described previously, so a detailed description thereof is omitted.

[0161] The A variable sampling capacitor (vC_SP[A]) can be connected between the gate of the 2A bias transistor (MPb2[A]) and the A control signal (CTRL[A]). When the A control signal (CTRL[A]) is controlled, the A gate voltage (vg[A]) can be varied according to the coupling to the A variable sampling capacitor (vC_SP[A]).

[0162] Similarly, the B variable sampling capacitor (vC_SP[B]) can be connected between the gate of the 2B bias transistor (MPb2[A]) and the B control signal (CTRL[B]). When the B control signal (CTRL[B]) is controlled, the B gate voltage (vg[B]) can be varied according to the coupling to the B variable sampling capacitor (vC_SP[B]).

[0163] FIG. 19 is a circuit diagram showing the variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 19, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-6, vCRB[B]-6). The A and B variable ramp buffers (vCRB[A]-6, vCRB[B]-6) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]), respectively. For convenience of explanation, mention and detailed description of the previously described components are omitted.

[0164] A variable sampling capacitor (VC_SP[A]) may be connected between the gate of a second bias transistor (MPb2[A]) and a selection circuit (SEL[A]). The selection circuit (SEL[A]) may output either a ground voltage (VSS) or a power supply voltage (VDD) in response to a control signal (CTRL[A]). A variable sampling capacitor (VC_SP[B]) may be connected between the gate of a second bias transistor (MPb2[B]) and a selection circuit (SEL[B]). The selection circuit (SEL[B]) may output either a ground voltage (VSS) or a power supply voltage (VDD) in response to a control signal (CTRL[B]).

[0165] In one embodiment, the A and B gate voltages (vg[A], vg[B]) can be controlled individually depending on the operation of the A and B selectors (SEL[A], SEL[B]). For example, prior to the auto-zero operation, the A selector (SEL[A]) can output a power supply voltage (VDD). During the auto-zero operation, the A selector (SEL[A]) can alternately output a power supply voltage (VDD) and a ground voltage (VSS) in response to the A control signal (CTRL[A]). In this case, the A gate voltage (vg[A]) can be reduced according to the coupling effect with respect to the A variable sampling capacitor (VC_SP[A]). After the auto-zero operation, the A selector (SEL[A]) can output a power supply voltage (VDD). In this case, the A gate voltage (vg[A]) can be changed to a level corresponding to the second bias signal (BP).

[0166] Alternatively, prior to the auto-zero operation, the A selector (SEL[A]) may alternately output the power supply voltage (VDD) and the ground voltage (VSS) based on a first ratio (e.g., the output ratio of the power supply voltage (VDD)) in response to the A control signal (CTRL[A]). During the auto-zero operation, the A selector (SEL[A]) may alternately output the power supply voltage (VDD) and the ground voltage (VSS) based on a second ratio greater than the first ratio (i.e., the power supply voltage (VDD) is output for a longer period compared to the first ratio). In this case, the A gate voltage (vg[A]) may increase according to the coupling effect with respect to the A variable sampling capacitor (VC_SP[A]). After the auto-zero operation, the A selector (SEL[A]) can alternately output the power supply voltage (VDD) and the ground voltage (VSS) based on the first ratio in response to the A control signal (CTRL[A]).

[0167] In one embodiment, the method of controlling the B gate voltage (vg[B]) by the B selector (SEL[B]) is similar to that described above, so a detailed description thereof is omitted.

[0168] FIG. 20 is a circuit diagram showing the variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 20, the image sensor device (100) may include A and B variable ramp buffers (vCRB[A]-7, vCRB[B]-7). The A and B variable ramp buffers (vCRB[A]-7, vCRB[B]-7) may correspond to the A and B variable ramp buffers (vCRB[A], vCRB[B]) described above, respectively. For convenience of explanation, the description and detailed explanation of the components described above are omitted.

[0169] The A sampling transistor (MP_SP[A]) can operate in response to the A sampling signal (SMP[A]). The B sampling transistor (MP_SP[B]) can operate in response to the B sampling signal. At this time, the A and B gate voltages (vg[A], vg[B]) can be controlled according to the control of the A and B sampling signals (SMP[A], SMP[B]).

[0170] For example, the level of the A gate voltage (vg[A]) can be controlled for the voltage magnitude or sampling time of the A sampling signal (SMP[A]), and the level of the B gate voltage (vg[B]) can be controlled for the voltage magnitude or sampling time of the B sampling signal (SMP[B]). As a more detailed example, the A sampling signal (SMP[A]) can be maintained at a low level for a first time, and the B sampling signal (SMP[B]) can be maintained at a low level for a second time that is longer than the first time. In this case, the A sampling transistor (MP_SP[A]) can be turned on for the first time in response to the A sampling signal (SMP[A]), and the B sampling transistor (MP_SP[B]) can be turned on for the second time in response to the B sampling signal (SMP[B]). Accordingly, the A gate voltage (vg[A]) may be sampled or charged to a first voltage, and the B gate voltage (vg[B]) may be sampled or charged to a second voltage higher than the first voltage. Since the A and second gate voltages (vg[A], vg[B]) are different from each other, the corresponding variable ramp buffers (vCRR_OUT[A], vCRB_OUT[B]) will be different. Subsequently, prior to the sampling operation of the ADC circuit, the A and B sampling signals (SMP[A], SMP[B]) may each maintain a low level for the same third time. Accordingly, the A and B gate voltages (vg[A], vg[B]) may be sampled or charged to the same level.

[0171] As described above, the A and B gate voltages (vg[A], vg[B]) can be controlled, respectively, according to the voltage level or sampling time of the A and B sampling signals (SMP[A], SMP[B]). Since the operations of the variable ramp buffers (vCRB[A], vCRB[B]) and the connected ADC circuits (ADC[A], ADC[B]) have been previously described, a detailed explanation thereof is omitted.

[0172] As described with reference to FIGS. 18 through 20, in various structures, as the A and B control signals (CTRL[A], CTRL[B]) are controlled, the A and B gate voltages (vg[A], vg[B]) can be controlled individually. In this case, as previously described, the bias currents (i b1 , i b2 The ADC and ramp output voltages (vCRB_OUT[A], vCRB_OUT[B]) can be controlled individually. Accordingly, as previously described, different offsets can be applied to the inputs of each ADC circuit (e.g., non-inverting inputs). As a result, in certain situations or environments (e.g., reset sampling, low light environment, etc.), the sampling timing of multiple ADC circuits (ADC[A]~ADC[n]) (e.g., when the ramp signal (or corresponding ramp output voltage) becomes lower than the pixel voltage) is distributed, thereby preventing abrupt fluctuations in the power supply voltage (VDD) or ground voltage (VSS).

[0173] FIG. 21 is a flowchart showing the operation of the image sensor device of FIG. 1. For convenience of explanation, the image sensor device (100) is described with reference to FIG. 21 for a reset sampling operation for pixels corresponding to one row of a plurality of pixels. That is, the image sensor device (100) can generate frame data by repeatedly performing the operation according to the flowchart of FIG. 21.

[0174] Referring to FIGS. 1 and FIGS. 21, in step S111, the image sensor device (100) can perform an auto-zero operation. For example, each of the plurality of ADC circuits (ADC[A] to ADC[n]) of the image sensor device (100) can perform an auto-zero operation. In one embodiment, during the auto-zero operation, the auto-zero switches (AZS) of each of the plurality of ADC circuits (ADC[A] to ADC[n]) can be turned on in response to an auto-zero signal. Through the auto-zero operation, the inputs of each of the plurality of ADC circuits (ADC[A] to ADC[n]) can be initialized.

[0175] In step S112, the image sensor device (100) can adjust the bias current of each column of variable ramp buffers. For example, as previously described, each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can control or adjust the bias current in response to a corresponding control signal (CTRL). Accordingly, the output voltages (vCRB_OUT[A] to vCRB_OUT[B]) of each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) may vary. Since the bias current control operation and structure or the output voltage control operation and structure of each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) have been previously described, a detailed description thereof is omitted.

[0176] In one embodiment, the bias current of each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can be adjusted differently from one another. For example, the A variable ramp buffer (vCRB[A]) can adjust the bias current to a first value, the B variable ramp buffer (vCRB[B]) can adjust the bias current to a second value different from the first value, and the C variable ramp buffer (vCRB[C]) can adjust the bias current to a third value different from the first and second values. In this case, the output voltages of the A, B, and C variable ramp buffers (vCRB[A], vCRB[B], vCRB[C]) can have different levels.

[0177] In one embodiment, the ramp buffer controller (150) of the image sensor device (100) can generate a control signal (CTRL) so that the bias current of each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) is individually controlled.

[0178] In one embodiment, the operation of step S112 (i.e., the operation of adjusting the bias current) can be performed in parallel with the operation of step S111 (i.e., the auto-zero operation). In this case, the inputs of a plurality of ADC circuits (ADC[A] to ADC[n]) can be fixed to an initial value by the auto-zero operation, and the outputs of a plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can have different levels.

[0179] In step S120, the image sensor device (100) can adjust the bias currents of a plurality of variable ramp buffers (vCRB[A] to vCRB[n]) to a reference current. For example, when the auto-zero operation of a plurality of ADC circuits (ADC[A] to ADC[n]) is completed, the bias currents of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can be adjusted to a reference current. Since the bias current control operation and structure of each of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) have been described previously, a detailed description thereof is omitted. As the bias currents of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) are adjusted to a reference current, the outputs of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can be set to the same level.

[0180] That is, when the auto-zero operation of multiple ADC circuits (ADC[A]–ADC[n]) is completed, the outputs of multiple variable ramp buffers (vCRB[A]–vCRB[n]) may change. At this time, the amount of change of each output may differ. The amount of change of the outputs of the multiple variable ramp buffers (vCRB[A]–vCRB[n]) may be reflected in the inputs of the multiple ADC circuits (ADC[A]–ADC[n]) through the input capacitors of the multiple ADC circuits (ADC[A]–ADC[n]). In other words, different offsets may be applied to the inputs of the multiple ADC circuits (ADC[A]–ADC[n]).

[0181] In step S130, the image sensor device (100) can perform a sampling operation. For example, during the sampling operation, the ramp generator (140) can generate a ramp signal (RAMP). A plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can generate outputs based on the ramp signal (RAMP). The outputs of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can each be provided as non-inverting inputs to a plurality of ADC circuits (ADC[A] to ADC[n]). The plurality of ADC circuits (ADC[A] to ADC[n]) can each receive a plurality of pixel voltages (VPIX[A] to VPIX[n]) as inverting inputs. The plurality of ADC circuits (ADC[A] to ADC[n]) can perform a sampling operation by comparing the non-inverting inputs and the inverting inputs, respectively.

[0182] In this case, as previously described, each of the non-inverting inputs of the multiple ADC circuits (ADC[A]–ADC[n]) can maintain a different offset. In this case, the sampling times of the multiple ADC circuits (ADC[A]–ADC[n]) can be dispersed in situations where multiple pixel voltages (VPIX[A]–VPIX[n]) have similar levels (e.g., reset levels or low-light environments). Accordingly, abrupt fluctuations (i.e., noise) in the power supply voltage or ground voltage can be prevented.

[0183] In one embodiment, after the operation described above, the plurality of ADC circuits (ADC[A] to ADC[n]) of the image sensor device (100) can perform a signal sampling operation. At this time, similar to what was previously described, the outputs of the plurality of variable ramp buffers (vCRB[A] to vCRB[n]) maintain the same level and the same waveform, but different offsets will be maintained in the non-inverting inputs (INP[A] to INP[n]) of each of the plurality of ADC circuits (ADC[A] to ADC[n]). Therefore, since different offsets are maintained in each of the plurality of ADC circuits (ADC[A] to ADC[n]), the reliability of the image data corresponding to the digital output of the plurality of ADC circuits (ADC[A] to ADC[n]) can be improved.

[0184] FIG. 22 is a circuit diagram showing a variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 22, an image sensor device (100) may include a variable ramp buffer (vCRB-8). The variable ramp buffer (vCRB-8) of FIG. 22 may correspond to each of the variable ramp buffers (vCRB[A] to vCRB[n]) of FIG. 1.

[0185] The variable ramp buffer (vCRB-8) may include a driving transistor (MPd), a current bias circuit (CB), a current control circuit (CC), and a gate control circuit (GCC). The driving transistor (MPd) and the current bias circuit (CB) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The driving transistor (MPd) may operate in response to a ramp signal (RAMP). The current bias circuit (CB) may generate a bias current used to generate the ramp output voltage (vCRB_OUT[A]).

[0186] In one embodiment, the current control circuit (CC) may be configured to control the current generated in the current bias circuit (CB). For example, the current control circuit (CC) may be connected in parallel with the current bias circuit (CB) between the power supply voltage (VDD) and the zero node (n0). The current control circuit (CC) may include at least some of the embodiments described with reference to FIGS. 5 through 12b (i.e., a current control circuit configured to control the effective channel width or length of the bias transistors that generate the bias current). The gate control circuit (GCC) may be configured to control the gate voltage provided to the current bias circuit (CB). In one embodiment, the gate control circuit (GCC) may include at least some of the embodiments described with reference to FIGS. 13 through 20 (i.e., a gate control circuit configured to control the gate voltage of the bias transistors).

[0187] In one embodiment, the current control circuit (CC) and the gate control circuit (GCC) may operate in response to a control signal (CTRL) and a bias signal (BIAS). Since the specific operation and configuration of the current control circuit (CC) and the gate control circuit (GCC) have been described previously, a detailed description thereof is omitted.

[0188] The variable ramp buffer (vCRB-8) can control the bias current by controlling the width or length of the effective channel of the bias transistor configured to generate the bias current using a current control circuit (CC), or by controlling the gate voltage of the bias transistor configured to generate the bias current using a gate control circuit (GCC). In this case, the ramp output voltage (vCRB_OUT) can be controlled individually. Since the subsequent operation following the individual control of the ramp output voltage (vCRB_OUT) (e.g., the method and operation of applying different offsets to each of the multiple ADC circuits (ADC[A]~ADC[n])) has been described previously, a detailed explanation thereof is omitted.

[0189] FIG. 23 is a block diagram showing a variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 23, an image sensor device (100) may include a variable ramp buffer (vCRB-9). The variable ramp buffer (vCRB-9) of FIG. 23 may correspond to each of the variable ramp buffers (vCRB[A] to vCRB[n]) of FIG. 1.

[0190] The variable ramp buffer (vCRB-9) may include a driving transistor (MPd) and a variable current bias circuit (vCB). The driving transistor (MPd) and the variable current bias circuit (VCB) may be connected in series between the ground voltage (VSS) and the power supply voltage (VDD). The driving transistor (MPd) may operate in response to a ramp signal (RAMP). The variable current bias circuit (VCB) may be configured to generate a bias current.

[0191] In one embodiment, the variable current bias circuit (VCB) may be configured to control the bias current in response to a bias signal (BIAS) and a control signal (CTRL). Since subsequent operations following the control of the bias current (e.g., the ramp output voltage (vCRB_OUT) and the corresponding application of an offset to the ADC circuit (ADC)) have been described previously, a detailed description thereof is omitted.

[0192] As described above, according to embodiments of the present invention, a plurality of variable ramp buffers (vCRB[A] to vCRB[n]) can individually control the bias current. In this case, different offsets may be applied to the non-inverting inputs (INp) input to each of the plurality of ADC circuits (ADC[A] to ADC[n]), and accordingly, the sampling times of the plurality of ADC circuits (ADC[A] to ADC[n]) may be distributed in specific situations (e.g., reset sampling, low-light environment, etc.).

[0193] FIG. 24 is a block diagram showing a variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 24, an image sensor device (100) may include a variable ramp buffer (vCRB-10). The variable ramp buffer (vCRB-10) of FIG. 24 may correspond to each of the variable ramp buffers (vCRB[A] to vCRB[n]) of FIG. 1.

[0194] The variable ramp buffer (vCRB-10) may include a driving transistor (MNd), a current bias circuit (CB), and a current control circuit (CC). The driving transistor (MNd) and the current bias circuit (CB) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS). In one embodiment, the driving transistor (MNd) may be an NMOS transistor. The driving transistor (MNd) may operate in response to a ramp signal (RAMP).

[0195] A current bias circuit (CB) may be configured to generate a bias current used in a variable ramp buffer (VCB-10). In one embodiment, the current bias circuit (CB) may include NMOS transistors connected in series or parallel, and the NMOS transistors may operate in response to a bias signal.

[0196] A current control circuit (CC) may be connected in parallel with a current bias circuit (CB) at the zero node (n0) and ground voltage (VSS) and configured to control the bias current. In one embodiment, the current control circuit (CC) of FIG. 24 is similar to the operation of the current control circuit described with reference to FIG. 5 through FIG. 12b, except that it is implemented using an NMOS transistor, so a detailed description thereof is omitted. In one embodiment, since the current control circuit (CC) is implemented using an NMOS transistor, each signal level or voltage level may differ, but this will be readily understood by those skilled in the art to which the present invention pertains.

[0197] FIG. 25 is a block diagram showing a variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 25, an image sensor device (100) may include a variable ramp buffer (vCRB-11). The variable ramp buffer (vCRB-11) of FIG. 25 may correspond to each of the variable ramp buffers (vCRB[A] to vCRB[n]) of FIG. 1.

[0198] The variable ramp buffer (vCRB-11) may include a driving transistor (MNd), a current bias circuit (CB), a current control circuit (CC), and a gate control circuit (GCC). Since the driving transistor (MNd), the current bias circuit (CB), and the current control circuit (CC) have been described with reference to FIG. 24, a detailed description thereof is omitted.

[0199] The variable ramp buffer (vCRB-11) of FIG. 25 may further include a gate control circuit (GCC) compared to the variable ramp buffer (vCRB-10) of FIG. 24. The gate control circuit (GCC) may be configured to control the gate voltage provided to the current bias circuit (CB). In one embodiment, the configuration of the gate control circuit (GCC) is similar to the operation of the gate control circuit described with reference to FIG. 13 through 20, except that it is implemented using an NMOS transistor; therefore, a detailed description thereof is omitted. In one embodiment, since the gate control circuit (GCC) is implemented using an NMOS transistor, each signal level or voltage level may differ, but this will be readily understood by those skilled in the art to which the present invention pertains.

[0200] FIG. 26 is a block diagram showing a variable ramp buffer of FIG. 1. Referring to FIG. 1 and FIG. 26, an image sensor device (100) may include a variable ramp buffer (vCRB-12). The variable ramp buffer (vCRB-12) of FIG. 26 may correspond to each of the variable ramp buffers (vCRB[A] to vCRB[n]) of FIG. 1.

[0201] The variable ramp buffer (vCRB-12) may include a driving transistor (MNd) and a variable current bias circuit (vCB). The driving transistor (MNd) and the variable current bias (VCB) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS). The driving transistor (MNd) may operate in response to a ramp signal (RAMP). The variable current bias circuit (vCB) may be configured to control the bias current.

[0202] As described above, the variable ramp buffer (vCRB) can be implemented in various ways. It will be understood that the present invention may include various variations of the embodiments described above.

[0203] FIG. 27 is a block diagram showing a partial configuration of an image sensor device according to an embodiment of the present invention. For convenience of explanation, components unnecessary for describing the configuration and operation of the variable ramp buffer are omitted below. Also, for convenience of explanation, an embodiment of the present invention is described based on eight columns, but the scope of the present invention is not limited thereto.

[0204] Referring to FIG. 27, the image sensor device (200) may include a ramp generator (240), a ramp buffer controller (250), a variable ramp buffer block (260), and an ADC block (270). Since the ramp generator (240) and the variable ramp buffer controller (250) have been described previously, a detailed description thereof is omitted.

[0205] The variable ramp buffer block (260) may include a plurality of variable ramp buffers (vCRB[A] to vCRB[H]). The ADC block (270) may include a plurality of ADC circuits (ADC[A] to ADC[H]). The plurality of variable ramp buffers (vCRB[A] to vCRB[H]) may buffer a ramp signal (RAMP) in response to a plurality of control signals (CTRL[A] to CTRL[D]). The buffered ramp signals may each be provided to a plurality of ADC circuits (ADC[A] to ADC[H]).

[0206] In one embodiment, some of the variable ramp buffers (vCRB[A] to vCRB[H]) may operate in response to the same control signal. In this case, the same offset may be applied to the corresponding ADC circuits. For example, the A and E variable ramp buffers (vCRB[A], vCRB[E]) may operate in response to the A control signal (CTRL[A]), the B and F variable ramp buffers (vCRB[B], vCRB[F]) may operate in response to the B control signal (CTRL[B]), the C and G variable ramp buffers (vCRB[C], vCRB[G]) may operate in response to the C control signal (CTRL[C]), and the D and H variable ramp buffers (vCRB[D], vCRB[H]) may operate in response to the D control signal (CTRL[D]).

[0207] In this case, the outputs of the A and E variable ramp buffers (vCRB[A], vCRB[E]) will be identical or similar to each other, the outputs of the B and F variable ramp buffers (vCRB[B], vCRB[F]) will be identical or similar to each other, the outputs of the C and G variable ramp buffers (vCRB[C], vCRB[G]) will be identical or similar to each other, and the outputs of the D and H variable ramp buffers (vCRB[D], vCRB[H]) will be identical or similar to each other. Accordingly, a first offset may be applied to the A and E ADC circuits (ADC[A], ADC[E]), a second offset may be applied to the B and F ADC circuits (ADC[B], ADC[F]), a third offset may be applied to the C and G ADC circuits (ADC[C], ADC[G]), and a fourth offset may be applied to the D and H ADC circuits (ADC[D], ADC[H]). At this time, the first to fourth offsets may be different from each other.

[0208] As described above, some of the multiple variable ramp buffers (ADC[A]–ADC[H]) may operate in response to the same control signal. In this case, the same offset may be applied to the corresponding ADC circuits. However, different offsets will be applied to the ADC circuits corresponding to the variable ramp buffers that operate in response to different control signals.

[0209] FIG. 28 is a block diagram showing an image sensor device according to an embodiment of the present invention. For convenience of explanation, components unnecessary for describing the configuration and operation of the variable ramp buffer are omitted below. Referring to FIG. 28, the image sensor device (300) may include a ramp generator (340), a variable ramp buffer controller (350), a variable ramp buffer block (360), and an ADC block (370). Since the ramp generator (340) and the variable ramp buffer controller (350) have been described previously, a detailed description thereof is omitted.

[0210] The variable ramp buffer block (360) may include a plurality of variable ramp buffers (vCRB[A] to vCRB[D]). The ADC block (370) may include a plurality of ADC circuits (ADC[A] to ADC[H]). The plurality of variable ramp buffers (vCRB[A] to vCRB[D]) may each operate in response to the A through D control signals (CTRL[A] to CTRL[D]). Since the operation of the plurality of variable ramp buffers (vCRB[A] to vCRB[D]) is similar to that described above, a detailed description thereof is omitted.

[0211] In one embodiment, each of the plurality of variable ramp buffers (vCRB[A] to vCRB[D]) can provide an output to at least two ADC circuits. In other words, at least two ADC circuits can share one variable ramp buffer. For example, the A variable ramp buffer (vCRB[A]) can buffer a ramp signal (RAMP) in response to the A control signal (CTRL[A]). The output of the A variable ramp buffer (vCRB[A]) can be provided to the A and E ADC circuits (ADC[A], ADC[E]). The B variable ramp buffer (vCRB[B]) can buffer a ramp signal (RAMP) in response to the B control signal (CTRL[B]). The output of the B variable ramp buffer (vCRB[B]) can be provided to the B and F ADC circuits (ADC[B], ADC[F]). The C variable ramp buffer (vCRB[C]) can buffer a ramp signal (RAMP) in response to the C control signal (CTRL[C]). The output of the C variable ramp buffer (vCRB[C]) can be provided to the C and G ADC circuits (ADC[C], ADC[G]). The D variable ramp buffer (vCRB[D]) can buffer a ramp signal (RAMP) in response to the D control signal (CTRL[D]). The output of the D variable ramp buffer (vCRB[D]) can be provided to the D and H ADC circuits (ADC[D], ADC[H]). Accordingly, different offsets can be applied to multiple ADC circuits (ADC[A]~ADC[H]).

[0212] FIG. 29 is a block diagram showing an image sensor device according to an embodiment of the present invention. For convenience of explanation, some components are omitted. Referring to FIG. 29, the image sensor device (400) may include a variable pixel load block (430), a ramp generator (440), a ramp buffer block (460), an ADC block (470), and a pixel load controller (490). Since the ramp generator (430) and the ADC block (460) have been described previously, a detailed description thereof is omitted.

[0213] The ramp buffer block (460) may include a plurality of ramp buffers (CRB[A] to CRB[H]). Each of the plurality of ramp buffers (CRB[A] to CRB[H]) may be similar to the one described with reference to FIG. 4a and FIG. 4c. That is, each of the plurality of ramp buffers (CRB[A] to CRB[H]) may be configured to buffer a ramp signal (RAMP).

[0214] The pixel load controller (490) may be configured to control the variable pixel load block (480). For example, the pixel load controller (490) may generate control signals (CTRL[A]–CTRL[D]). The control signals (CTRL[A]–CTRL[D]) may be provided to the variable pixel load block (430).

[0215] The variable pixel load block (430) may include a plurality of variable pixel load circuits (vPLD[A] to vPLD[H]). Each of the plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) is connected to a plurality of column lines and can provide pixel bias current to each of the plurality of column lines. The initialization speed of the plurality of column lines can be accelerated by the plurality of variable pixel load circuits (vPLD[A] to vPLD[H]).

[0216] In one embodiment, a plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) may operate in a manner similar to the operation of a variable ramp buffer described with reference to FIGS. 1 to 29. For example, during the auto-zero operation of a plurality of ADC circuits (ADC[A] to ADC[H]), the plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) may each control the pixel bias current differently from one another. After the auto-zero operation of the plurality of ADC circuits (ADC[A] to ADC[H]) is completed, the plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) may control the pixel bias current equally from one another. In this case, similar to the operating principle described above, different offsets may be applied to the inverting input terminals (INn) of multiple ADC circuits (ADC[A] to ADC[H]), and accordingly, even if the pixel voltages (VPIX[A] to VPIX[B]) are identical, the sampling times of the multiple ADC circuits (ADC[A] to ADC[H]) may be distributed. The configuration and operation of the multiple variable pixel load circuits (vPLD[A] to vPLD[H]) are described in more detail with reference to the drawings below.

[0217] In one embodiment, a plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) may operate individually in response to a plurality of control signals (CTRL[A] to CTRL[D]). For example, the A and E variable pixel load circuits (vPLD[A], vPLD[E]) may operate in response to the A control signal (CTRL[A]). The B and F variable pixel load circuits (vPLD[B], vPLD[F]) may operate in response to the B control signal (CTRL[B]). The C and G variable pixel load circuits (vPLD[C], vPLD[G]) may operate in response to the C control signal (CTRL[C]). The D and H variable pixel load circuits (vPLD[D], vPLD[H]) may operate in response to the D control signal (CTRL[D]). In this case, a first offset may be applied to the A and E ADC circuits (ADC[A], ADC[E]), a second offset may be applied to the B and F ADC circuits (ADC[B], ADC[F]), a third offset may be applied to the C and G ADC circuits (ADC[C], ADC[G]), and a fourth offset may be applied to the D and H ADC circuits (ADC[D], ADC[H]). At this time, the first to fourth offsets may be different from each other.

[0218] FIG. 30 is a block diagram showing the variable pixel load circuit and ADC circuit of FIG. 29. FIG. 31 is a timing diagram for explaining the operation of the variable pixel load circuit of FIG. 30. For the sake of brevity of the drawings and convenience of explanation, some components are omitted. Referring to FIG. 29 through FIG. 31, the image sensor device (400) may include A and B ramp buffers (CRB[A], CRB[B]), A and B ADC circuits (ADC[A], ADC[B]), and A and B variable pixel load circuits (vPLD[A], vPLD[B]). Since the A and B ramp buffers (CRB[A], CRB[B]) and A and B ADC circuits (ADC[A], ADC[B]) have been described with reference to FIG. 4a, a detailed description thereof is omitted.

[0219] The A variable pixel load circuit (PLD[A]) can be connected to the A column line (CL[A]) to which the A pixel voltage (VPIX[A]) is provided. The A variable pixel load circuit (PLD[A]) has a first pixel bias current (i bp1 It may include a A variable current bias circuit (vCB[A]) configured to generate ). The A variable current bias circuit (vCB[A]) generates a first pixel bias current (i) in response to an A control signal (CTRL[A]). bp1 Can control ).

[0220] The B variable pixel load circuit (PLD[B]) can be connected to the B column line (CL[B]) to which the B pixel voltage (VPIX[B]) is provided. The B variable pixel load circuit (PLD[B]) has a second pixel bias current (i bp2 It may include a B variable current bias circuit (vCB[B]) configured to generate ). The B variable current bias circuit (vCB[B]) generates a second pixel bias current (i) in response to a B control signal (CTRL[B]). bp2 Can control ).

[0221] In one embodiment, the A and B variable current bias circuits (vCB[A], vCB[B]) may be implemented in a manner similar to the variable current bias circuit (vCB) described with reference to FIG. 26. For example, each of the A and B variable current bias circuits (vCB[A], vCB[B]) may include a switch circuit and a control transistor, and through the operation of the switch circuit, the effective size of the transistor generating the barpixel bias current may be controlled. Alternatively, each of the A and B variable current bias circuits (vCB[A], vCB[B]) may include a circuit for controlling the gate voltage of the transistor generating the barpixel bias current. However, the scope of the invention is not limited thereto.

[0222] In one embodiment, first and second pixel bias currents (i bp2 , i bp2 Depending on ), the A and B pixel voltages (VPIX[A], VPIX[B]) may be varied. In this case, similar to the operating principle described above, different offsets may be applied to the A and B ADC circuits (ADC[A], ADC[B]).

[0223] For example, as illustrated in FIG. 31, during the interval (t1-t2) of the first and second time points, the auto-zero signal (AZ) may maintain a high level. In response to the high-level auto-zero signal (AZ), the A and B ADC circuits (ADC[A], ADC[B]) may perform an auto-zero operation. During the auto-zero operation of the A and B ADC circuits (ADC[A], ADC[B]), the A variable pixel load circuit (vPLD[A]) responds to the A control signal (CTRL[A]) to the first pixel bias current (i bp1 ) controls to the first level, and the B variable pixel load circuit (vPLD[B]) responds to the A control signal (CTRL[B]) to the second pixel bias current (i bp2) can be controlled to a second level different from the first level (e.g., the second level is higher than the first level). In this case, the A pixel voltage (VPIX[A]) is the first pixel bias current (i bp1 It can increase by a level corresponding to the amount of change of ), and the B pixel voltage (VPIX[B]) is the second pixel bias current (i bp2 It can be reduced by a level corresponding to the amount of change of ).

[0224] After the second time point (t2), the auto zero signal (AZ) changes to a low level. In the interval (t2-t6) of the second to sixth time points, the A and B ADC circuits (ADC[A], ADC[B]) can perform a reset sampling operation.

[0225] After the auto-zero operation of the A and B ADC circuits (ADC[A], ADC[B]) is completed (i.e., after the second time point (t2)), the A variable pixel load circuit (vPLD[A]) responds to the A control signal (CTRL[A]) to the first pixel bias current (i bp1 ) controls the reference level, and the B variable pixel load circuit (vPLD[B]) responds to the B control signal (CTRL[B]) to the second pixel bias current (i bp2 ) can be controlled to a reference level. In this case, the A pixel voltage (VPIX[A]) is the first pixel bias current (i bp1 It can be reduced by a level corresponding to the amount of change of ), and the B pixel voltage (VPIX[B]) is the second pixel bias current (i bp2 It can be increased by a level corresponding to the amount of change of ). In this case, the A and B pixel voltages (VPIX[A], VPIX[B]) can correspond to the reset level.

[0226] Different offsets may be applied to the A and B inverted inputs (INn[A], INn[B]) depending on the change in the A and B pixel voltages (VPIX[A], VPIX[B]) at the second time point (t2). For example, at the second time point (t2), as the A pixel voltage (VPIX[A]) decreases, the A inverted input (INn[A]) may decrease by a predetermined level due to the coupling of the A inverted input capacitor (Cn[A]) of the A ADC circuit (ADC[A]). Additionally, as the B pixel voltage (VPIX[B]) increases, the B inverted input (INn[B]) may increase by a predetermined level due to the coupling of the B inverted input capacitor (Cn[B]) of the B ADC circuit (ADC[B]).

[0227] That is, due to the operation of the A and B variable pixel load circuits (vPLD[A], vPLD[B]), the A and B inverting inputs (INn[A], INn[B]) of the A and B ADC circuits (ADC[A], ADC[B]) may have different offsets. In this case, at the fourth time point (t4), as the A non-inverting input (INp[A]) becomes lower than the A inverting input (INn[A]), the A comparison signal (COMP[A]) is generated, and at the fifth time point (t5), as the B non-inverting input (INp[B]) becomes lower than the B inverting input (INn[B]), the B comparison signal (COMP[B]) may be generated.

[0228] In other words, different offsets can be applied to the A and B ADC circuits (ADC[A], ADC[B]) by the operation of the A and B variable pixel load circuits (vPLD[A], vPLD[B]), and accordingly, even if the A and B pixel voltages (VPIX[A], VPIX[B]) are the same, the sampling times of the A and B ADC circuits (ADC[A], ADC[B]) can be distributed.

[0229] FIG. 32 is a block diagram showing an image sensor device according to an embodiment of the present invention. For convenience of explanation, some components are omitted. Referring to FIG. 32, the image sensor device (500) may include a variable pixel load block (530), a ramp generator (540), a ramp buffer block (560), an ADC block (570), and a pixel load controller (590). Since the ramp generator (530) and the ADC block (560) have been described previously, a detailed description thereof is omitted.

[0230] The variable pixel load block (530) may include a plurality of variable pixel load circuits (vPLD[A] to vPLD[H]). The plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) may operate in response to a plurality of pixel control signals (CTRL_P[A] to CTRL_P[D]) from the pixel load controller (590). Since the operation of the plurality of variable pixel load circuits (vPLD[A] to vPLD[H]) has been described with reference to FIGS. 29 to 31, a detailed description thereof is omitted.

[0231] The variable ramp buffer block (560) may include a plurality of variable ramp buffer blocks (vCRB[A] to vCRB[H]). The plurality of variable ramp buffer blocks (vCRB[A] to vCRB[H]) may operate in response to a plurality of ramp control signals (CTRL_R[A] to CTRL_R[D]) from the ramp buffer controller (550). Since the operation of the plurality of variable ramp buffer blocks (vCRB[A] to vCRB[H]) has been described with reference to FIGS. 5 to 28, a detailed description thereof is omitted. Through the structure described above, different offsets may be applied to a plurality of ADC circuits (ADC[A] to ADC[H]).

[0232] FIG. 33 is a block diagram showing the variable ramp buffer, variable pixel load circuit, and ADC circuit of FIG. 32. Referring to FIG. 31 through FIG. 33, the image sensor device (500) may include a first variable ramp buffer (vCRB[A]), a first pixel load circuit (vPLD[A]), and a first ADC circuit (ADC[A]). Since the detailed configurations of each of the first variable ramp buffer (vCRB[A]), the first pixel load circuit (vPLD[A]), and the first ADC circuit (ADC[A]) have been described previously, a detailed description thereof is omitted.

[0233] In one embodiment, before and after the auto-zero operation of the A ADC circuit (ADC[A]), the A variable ramp buffer (vCRB[A]) can control the first ramp bias current (irb1) to vary the A variable ramp buffer output (vCRB_OUT[A]), and the A variable pixel load circuit (vPLD[A]) can control the first pixel bias current ( ibp1 By controlling ), the A pixel voltage (VPIX[A]) can be varied. In this case, as previously described, an offset can be applied to the A non-inverting input (INp[A]) and the A inverting input (INn[A]) of the A ADC circuit (ADC[A]), respectively. As described above, different offsets can be applied to each of the ADC circuits using a variable ramp buffer (vCRB) and a variable pixel load circuit (vPLD).

[0234] FIG. 34 is a block diagram showing an image sensor device according to an embodiment of the present invention. FIG. 35 is a block diagram showing a ramp buffer, a variable pixel buffer, and an ADC circuit of FIG. 34. Referring to FIG. 34 and FIG. 35, the image sensor device (600) may include a ramp generator (640), a ramp buffer block (660), an ADC block (670), a pixel buffer controller (6a0), and a pixel buffer block (6b0). Since the ramp generator (640), the ramp buffer block (660), and the ADC block (670) have been described previously, a detailed description thereof is omitted.

[0235] The ramp buffer block (660) may include a plurality of ramp buffers (CRB[A] to CRB[H]). Each of the plurality of ramp buffers (CRB[A] to CRB[H]) may be similar to the one described with reference to FIG. 4a and FIG. 4c. That is, each of the plurality of ramp buffers (CRB[A] to CRB[H]) may be configured to buffer a ramp signal (RAMP).

[0236] A variable pixel buffer controller (6a0) may be configured to control a variable pixel buffer block (6b0). For example, the variable pixel buffer controller (6a0) may generate control signals (CTRL[A]–CTRL[D]). The control signals (CTRL[A]–CTRL[D]) may be provided to the variable pixel buffer block (6b0).

[0237] The variable pixel buffer block (6b0) may include a plurality of variable pixel buffers (vCPB[A] to vCPB[H]). The plurality of variable pixel buffers (vCPB[A] to vCPB[H]) may be configured to buffer a plurality of pixel voltages (VPIX[A] to VPIX[H]). At this time, the plurality of variable pixel buffers (vCPB[A] to vCPB[H]) may each operate in response to a plurality of control signals (CTRL[A] to CTRL[D]), and accordingly, different offsets may be applied to a plurality of ADC circuits (ADC[A] to ADC[H]).

[0238] For example, in the embodiments described with reference to FIGS. 1 through 28, different offsets are applied to non-inverting inputs (e.g., inputs corresponding to ramp signals) input to a plurality of ADC circuits (ADC[A] to ADC[H]) as the variable ramp buffers are controlled individually. On the other hand, in the embodiment of FIG. 34, the variable pixel buffers (vCPB[A] to vCPB[H]) may operate similarly to the variable ramp buffers (vCRB) described above, but may be configured to buffer the pixel voltage (VPIX). In this case, similar to the operating principle described above, different offsets may be applied to inverting inputs (e.g., inputs corresponding to pixel voltage) input to a plurality of ADC circuits (ADC[A] to ADC[H]). Accordingly, the sampling times of the plurality of ADC circuits (ADC[A] to ADC[H]) may be distributed.

[0239] For example, as illustrated in FIG. 35, the image sensor (600) may include A and B ramp buffers (CRB[A], CRB[B]), A and B variable pixel buffers (vCPB[A], vCPB[B]), and A and B ADC circuits (ADC[A], ADC[B]). Since the A and B ramp buffers (CRB[A], CRB[B]) and the A and B ADC circuits (ADC[A], ADC[B]) have been described previously, a detailed description thereof is omitted.

[0240] The A variable pixel buffer (vCPB[A]) may include an A driving transistor (MNd[A]) and an A variable current bias circuit (VCB[A]). The A driving transistor (MNd[A]) and the A variable current bias circuit (VCB[A]) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS).

[0241] The A driving transistor (MNd[A]) may be an NMOS transistor. The A driving transistor (MNd[A]) may operate in response to the A pixel voltage (VPIX[A]). The A variable current bias circuit (VCB[A]) may control the first bias current (ibp1) in response to the A control signal (CTRL[A]). In this case, similar to the description above, the first offset may be applied to the inverted input (INn[A]) of the A ADC circuit (ADC[A]).

[0242] The B variable pixel buffer (vCPB[B]) may include a B driving transistor (MNd[B]) and a B variable current bias circuit (VCB[B]). The B driving transistor (MNd[B]) and the B variable current bias circuit (VCB[B]) may be connected in series between the power supply voltage (VDD) and the ground voltage (VSS).

[0243] The B driving transistor (MNd[B]) may be an NMOS transistor. The B driving transistor (MNd[B]) may operate in response to the B pixel voltage (VPIX[B]). The B variable current bias circuit (VCB[B]) may control the second bias current (ibp2) in response to the B control signal (CTRL[B]). In this case, similar to what was previously described, a second offset may be applied to the inverted input (INn[A]) of the B ADC circuit (ADC[B]). In one embodiment, the first and second offsets may vary depending on the control of the first and second bias currents (ibp1, ibp2). Since the principle of offset control operation is similar to what was previously described, a detailed description thereof is omitted.

[0244] As described above, the image sensor device may include variable pixel buffers (vCPB) configured to buffer pixel voltage. The variable pixel buffers (vCPB) can control the bias current before and after the auto-zero operation of the ADC circuits, and accordingly, different offsets can be applied to each of the ADC circuits.

[0245] In one embodiment, in the embodiment of FIG. 34, a ramp signal (RAMP) is described as being buffered by a plurality of ramp buffers (CRB[A] to CRB[H]), but the scope of the present invention is not limited thereto. For example, some of the plurality of ADC circuits (ADC[A] to ADC[H]) may share the same ramp buffer (CRB). As an example, as described with reference to FIG. 28, the A and E ADC circuits (ADC[A], ADC[E]) may share the A ramp buffer (CRB[A]). Alternatively, the plurality of ramp buffers (CRB[A] to CRB[H]) may be omitted, in which case the ramp signal (RAMP) may be provided directly to the plurality of ADC circuits (ADC[A] to ADC[H]).

[0246] FIG. 36 is a block diagram showing an image sensor device according to an embodiment of the present invention. FIG. 37 is a block diagram showing a variable ramp buffer, a variable pixel buffer, and an ADC circuit of FIG. 36. Referring to FIG. 36 and FIG. 37, the image sensor device (700) may include a ramp generator (730), a ramp buffer controller (750), a variable ramp buffer block (660), an ADC block (770), a pixel buffer controller (7a0), and a variable pixel buffer block (7b0). Since each component of the image sensor device (700) has been described previously, a detailed description thereof is omitted.

[0247] According to the embodiment of FIG. 36, the variable ramp buffer block (760) may include a plurality of variable ramp buffers (vCRB[A] to vCRB[H]). The variable pixel buffer block (7b0) may include a plurality of variable pixel buffers (vCPB[A] to vCPB[H]). The ADC block (770) may include a plurality of ADC circuits (ADC[A] to ADC[H]).

[0248] Multiple variable ramp buffers (vCRB[A]~vCRB[H]) can buffer a ramp signal (RAMP) and provide it to each of multiple ADC circuits (ADC[A]~ADC[H]). Multiple variable pixel buffers (vCPB[A]~vCPB[H]) can buffer multiple pixel voltages (VPIX[A]~VPIX[H]) and provide them to each of multiple ADC circuits (ADC[A]~ADC[H]).

[0249] In one embodiment, a plurality of variable ramp buffers (vCRB[A] to vCRB[H]) can operate in response to A to D ramp control signals (CTRL_R[A] to CTRL_R[D]), and a plurality of variable pixel buffers (vCPB[A] to vCPB[H]) can operate in response to A to D pixel control signals (CTRL_P[A] to CTRL_P[D]).

[0250] For example, as illustrated in FIG. 37, the A and B variable ramp buffers (vCRB[A], vCRB[B]) may each include A and B driving transistors (MPd[A], MPd[B]) and A and B ramp variable current biases (VCB_R[A], VCB_R[B]). The A and B driving transistors (MPd[A], MPd[B]) may operate in response to a ramp signal (RAMP), and the A and B ramp variable current biases (VCB_R[A], VCB_R[B]) may each operate in response to A and B ramp control signals (CTRL_R[A], CTRL_R[B]). In one embodiment, each of the A and B variable ramp buffers (vCRB[A], vCRB[B]) may be the variable ramp buffer (vCRB-9) described with reference to FIG. 23. In other words, each of the A and B variable ramp buffers (vCRB[A], vCRB[B]) can be configured to control the bias current according to the various embodiments described above.

[0251] The A and B variable pixel buffers (vCPB[A]) may include A and B driving transistors (MNd[A], MNd[B]) and A and B pixel variable current biases (VCB_P[A], VCB_P[B]). The A and B driving transistors (MNd[A], MNd[B]) may each operate in response to A and B pixel voltages (VPIX[A], VPIX[B]), and the A and B pixel variable current biases (VCB_P[A], VCB_P[B]) may each operate in response to A and B pixel control signals (CTRL_P[A], CTRL_P[B]). In one embodiment, the A and B variable pixel buffers (vCPB[A], vCPB[B]) may each be the variable pixel buffer (vCPB) described above. In other words, each of the A and B variable pixel buffers (vCPB[A], vCPB[B]) can be configured to control the bias current according to the various embodiments described above.

[0252] In this case, different offsets may be applied to multiple ADC circuits (ADC[A] to ADC[H]). Since the detailed operation can be easily implemented or understood through a combination of the embodiments described above, a detailed description thereof is omitted.

[0253] As described above, according to embodiments of the present invention, an image sensor device may include a plurality of variable ramp buffers. Each of the plurality of variable ramp buffers can control a ramp output voltage corresponding to a ramp signal by controlling a bias current. In this case, different offsets may be applied to the non-inverting inputs of a plurality of ADC circuits corresponding to the ramp signal. Alternatively, the image sensor device may include a plurality of variable pixel buffers. Each of the plurality of variable pixel buffers can control pixel output voltages corresponding to a plurality of pixel voltages by controlling a bias current. In this case, different offsets may be applied to the inverting inputs of a plurality of ADC circuits corresponding to a plurality of pixel voltages. Accordingly, in certain situations, simultaneous sampling by a plurality of ADC circuits and the resulting abrupt voltage fluctuations can be prevented.

[0254] FIGS. 38 and 39 are drawings showing a stacked structure of an image sensor device according to an embodiment of the present invention. First, referring to FIGS. 2 and FIGS. 38, the image sensor device (1000) may include an upper semiconductor die (DIE_T) (hereinafter referred to as "Top die" for convenience of explanation) and a lower semiconductor die (DIE_T) (hereinafter referred to as "Bottom die" for convenience of explanation). The top die (DIE_T) may include a pixel array (110) comprising a plurality of pixels (PIX). The bottom die (DIE_B) may include the remaining components excluding the pixel array (110). In one embodiment, the bottom plate (DIE_B) may include a plurality of variable ramp buffers (vCRB), a plurality of ADC circuits (ADC), a plurality of variable pixel load circuits (vPLD), or a plurality of variable pixel buffers (VCPR), which may be implemented through one or a combination of at least two of the various embodiments described with reference to FIGS. 1 to 37.

[0255] Next, referring to FIG. 2 and FIG. 38, the image sensor device (2000) may include an upper semiconductor die (DIE_T) (hereinafter referred to as “Top die” for convenience of explanation), a middle semiconductor die (DIE_M) (hereinafter referred to as “Middle die” for convenience of explanation), and a lower semiconductor die (DIE_B) (hereinafter referred to as “Bottom die” for convenience of explanation).

[0256] The top plate (DIE_T) may include a portion of the pixel circuit (PCXa) for each of the plurality of pixels (PIX) of the pixel array (110), and the middle plate (DIE_M) may include the remainder of the pixel circuit (PCXb) for each of the plurality of pixels (PIX). For example, in the pixel (PIX) of FIG. 3a, the remaining components (e.g., TG, RG, SF, SG, etc.), excluding the photodiode (PD), may be pixel circuits for the pixel (PIX). A portion of the pixel circuit (PCXa) and the photodiode (PD) of the pixel (PIX) may be formed on the top plate (DIE_T), and the remainder of the pixel circuit (PCXb) of the pixel (PIX) may be formed on the middle plate (DIE_M). The bottom plate (DIE_B) may include the remaining components excluding the pixel array (110). For example, the bottom plate (DIE_B) may include a plurality of variable ramp buffers (vCRB), a plurality of ADC circuits (ADC), a plurality of variable pixel load circuits (vPLD), or a plurality of variable pixel buffers (VCPR). The plurality of variable ramp buffers (vCRB), a plurality of ADC circuits (ADC), or a plurality of variable pixel buffers (VCPR) may be implemented through one or a combination of at least two of the various embodiments described with reference to FIGS. 1 to 37.

[0257] In one embodiment, a plurality of variable ramp buffers (vCRB), a plurality of ADC circuits (ADC), or a plurality of variable pixel buffers (VCPR) may be formed across a middle plate (DIE_M) and a lower plate (DIE_B). For example, a plurality of variable pixel buffers (VCPR) may be formed on the lower plate (DIE_B), and a plurality of variable ramp buffers (vCRB) and a plurality of ADC circuits (ADC) may be formed on the middle plate (DIE_M). Alternatively, a plurality of variable ramp buffers (vCRB) and a plurality of variable pixel buffers (VCPR) may be formed on the middle plate (DIE_M), and a plurality of ADC circuits (ADC) may be formed on the lower plate (DIE_B). The foregoing description is merely an example, and the scope of the invention is not limited thereto. The implementation method of each component may be varied in many ways.

[0258] The above description describes specific embodiments for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be simply modified or easily modified. Furthermore, the present invention will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present invention should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this invention.

Claims

Claim 1 An image sensor device comprises: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to the ramp signal and a first control signal; a second variable ramp buffer configured to output a second output voltage in response to the ramp signal and a second control signal; and a first analog-to-digital converting (ADC) circuit configured to sample a first digital signal based on a first pixel voltage received through a first column line and the first output voltage. An image sensor device comprising a second ADC circuit configured to sample a second digital signal based on a second pixel voltage received through a second column line and the second output voltage, wherein the first variable ramp buffer is further configured to vary the first output voltage to a first level during the auto-zero operation of the first and second ADC circuits and to vary the first output voltage to a reference level after the auto-zero operation, and the second variable ramp buffer is further configured to vary the second output voltage to a second level different from the first level during the auto-zero operation and to vary the second output voltage to the reference level after the auto-zero operation. Claim 2 An image sensor device according to claim 1, further comprising: a first pixel configured to output the first pixel voltage through the first column line; and a second pixel configured to output the second pixel voltage through the second column line, wherein the first and second pixels operate in response to the same selection signal. Claim 3 An image sensor device according to claim 2, wherein the first pixel voltage corresponds to the reset level of the first pixel, the second pixel voltage corresponds to the reset level of the second pixel, the first ADC circuit samples the first digital signal at a first time point, and the second ADC circuit samples the second digital signal at a second time point different from the first time point. Claim 4 An image sensor device according to claim 1, wherein the first ADC circuit comprises: a first amplifier including a first inverting input, a first non-inverting input, a first inverting output, and a first non-inverting output; a first auto-zero switch connected between the first non-inverting input and the first inverting output and configured to operate in response to an auto-zero signal; and a first non-inverting input capacitor connected between the first non-inverting input and the first output voltage, and the second ADC circuit comprises: a first amplifier including a second inverting input, a second non-inverting input, a second inverting output, and a second non-inverting output; a second auto-zero switch connected between the second non-inverting input and the second inverting output and configured to operate in response to an auto-zero signal; and a second non-inverting input capacitor connected between the second non-inverting input and the second output voltage. Claim 5 In claim 4, after the auto-zero operation, the first non-inverting input has a first offset corresponding to the difference between the first level and the reference level, and the second non-inverting input has a second offset corresponding to the difference between the second level and the reference level, and the first offset and the second offset are different image sensor devices. Claim 6 An image sensor device according to claim 5, wherein while the ramp signal is output, the first non-inverting input maintains the first offset and the second non-inverting input maintains the second offset. Claim 7 An image sensor device according to claim 1, further comprising: a third variable ramp buffer configured to output a third output voltage in response to the ramp signal and the third control signal; and a third ADC circuit configured to output a third digital signal based on the third pixel voltage received through the third column line and the third output voltage, wherein during the auto-zero operation of the third ADC circuit, the third variable ramp buffer varies the third output voltage to a third level, and after the auto-zero operation of the third ADC circuit, the third output voltage is further configured to vary the third output voltage to a reference level. Claim 8 An image sensor device according to claim 1, further comprising: a third variable ramp buffer configured to output a third output voltage in response to the ramp signal and the first control signal; a fourth variable ramp buffer configured to output a fourth output voltage in response to the ramp signal and the second control signal; a third ADC circuit configured to sample a third digital signal based on a third pixel voltage received through a third column line and the third output voltage; and a fourth ADC circuit configured to sample a fourth digital signal based on a fourth pixel voltage received through a fourth column line and the fourth output voltage. Claim 9 An image sensor device according to claim 1, further comprising: a first pixel load circuit connected to the first column line and configured to generate a first pixel bias current; and a second pixel load circuit connected to the second column line and configured to generate a second pixel bias current. Claim 10 An image sensor device according to claim 9, wherein during the auto-zero operation, the first pixel load circuit controls the first pixel bias current to a first level and the second pixel load circuit controls the second pixel bias current to a second level different from the first level, and after the auto-zero operation, the first pixel load circuit controls the first pixel bias current to a reference level and the second pixel load circuit controls the second pixel bias current to the reference level. Claim 11 An image sensor device comprising: a ramp generator configured to generate a ramp signal; a first variable ramp buffer configured to output a first output voltage in response to the ramp signal and a first control signal; and a first analog-to-digital converting (ADC) circuit configured to output a first digital signal based on a first pixel voltage received through a first column line and the first output voltage, wherein the first variable ramp buffer comprises: a first driving transistor connected between a first node where the first output voltage is output and a ground voltage and configured to operate in response to the ramp signal; and a first variable current bias circuit connected between the first node and a power supply voltage and configured to control a first bias current provided to the first node in response to the first control signal, wherein the first variable current bias circuit is further configured to drive the first bias current to a first magnitude during the auto-zero operation of the first ADC circuit and to drive the first bias current to a reference magnitude after the auto-zero operation. Claim 12 An image sensor device according to claim 11, wherein the first variable current bias circuit comprises: a first bias transistor connected between the first node and the second node and configured to operate in response to a first bias signal; a second bias transistor connected between the second node and the power supply voltage and configured to operate in response to a second bias signal; and a first current control circuit connected between the second node and the power supply voltage and configured to operate in response to a first control signal. Claim 13 An image sensor device according to claim 11, wherein the first current control circuit comprises: a first control transistor configured to operate in response to the second bias signal; and a first control switch configured to operate in response to the first control signal, wherein the first control transistor and the first control switch are connected in series between the power supply voltage and the second node, and during the auto-zero operation, the first control switch is turned on and after the auto-zero operation, the first control switch is turned off, or during the auto-zero operation, the first control switch is turned off and after the auto-zero operation, the first control switch is turned on. Claim 14 An image sensor device according to claim 11, comprising: a second variable ramp buffer configured to output a second output voltage in response to the ramp signal and the second control signal; and a second ADC circuit configured to output a second digital signal based on a second pixel voltage received through a second column line and the second output voltage, wherein the second variable ramp buffer comprises: a second driving transistor connected between a third node where the second output voltage is output and the ground voltage and configured to operate in response to the ramp signal; and a second variable current bias circuit connected between the third node and the power supply voltage and configured to control a second bias current provided to the third node in response to the second control signal, wherein the second variable current bias circuit is further configured to drive the second bias current to a second magnitude during the auto-zero operation of the second ADC circuit and to drive the second bias current to a reference magnitude after the auto-zero operation. Claim 15 An image sensor device according to claim 14, further comprising a third control switch connected between the first variable current bias circuit and the second variable current bias circuit, wherein the third control switch is turned on during the auto-zero operation of the first and second ADC circuits and the third control switch is turned off after the auto-zero operation of the first and second ADC circuits. Claim 16 In claim 11, the first variable current bias circuit comprises: a first bias transistor connected between the first node and the second node and configured to operate in response to a first bias signal; a second bias transistor connected between the second node and the power supply voltage and configured to operate in response to a first gate voltage; and a first gate control circuit configured to control the first gate voltage based on a second bias signal in response to the first control signal, wherein the first gate control circuit varies the first gate voltage to a first level during the auto-zero operation and varies the first gate voltage to a level corresponding to the second bias signal after the auto-zero operation. Claim 17 In claim 16, the first gate control circuit comprises: a first sampling capacitor connected between the gate of the second bias transistor and the power supply voltage; a first sampling transistor connected between the second bias signal and the gate of the second bias transistor and configured to operate in response to the sampling signal; and a first dummy switch circuit connected to the gate of the second bias transistor and configured to operate in response to the first control signal, wherein the first dummy switch circuit comprises a plurality of transistors configured to operate individually in response to the first control signal. Claim 18 An image sensor device according to claim 17, wherein during the auto-zero operation, M (where M is an integer greater than or equal to 0) of the plurality of transistors of the first dummy switch circuit are turned on, and after the auto-zero operation, N (where N is an integer greater than or equal to 0) of the plurality of transistors of the first dummy switch circuit are turned on. Claim 19 An image sensor device comprising: a ramp generator configured to generate a ramp signal; a variable ramp buffer block configured to buffer the ramp signal and output a plurality of output voltages; and an analog to digital converting (ADC) block configured to compare a plurality of pixel voltages received through a plurality of column lines with the plurality of output voltages, respectively, and to sample a plurality of digital signals corresponding to each of the plurality of pixel voltages, wherein while the ADC block performs an auto-zero operation, at least two of the plurality of output voltages have different levels, and after the auto-zero operation, the plurality of output voltages have the same level. Claim 20 In claim 19, the image sensor device further comprises a plurality of pixels each connected to the plurality of column lines and configured to operate in response to the same selection signal, the ADC block comprises a plurality of ADC circuits, and during a reset sampling operation for the plurality of pixels, at least two of the plurality of ADC circuits perform sampling at different times.

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