Semiconductor devices and a method of forming the same

Abstract

A semiconductor device comprises a first channel pattern and a second channel pattern spaced apart from each other in a first direction on a substrate, a first gate electrode on the first channel pattern and extending in the first direction, a second gate electrode on the second channel pattern and extending in the first direction, and a separation insulation pattern between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode are aligned with each other in the first direction. The separation insulation pattern includes a lower pattern and an upper pattern stacked in a vertical direction perpendicular to the upper surface of the substrate. The interface between the lower pattern and the upper pattern is located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. The problem to be solved

[0003] The technical problem to be achieved by the present invention is to provide a semiconductor device capable of minimizing manufacturing defects and a method for manufacturing the same.

[0004] Another technical objective of the present invention is to provide a semiconductor device that is easy to manufacture and has excellent reliability, and a method for manufacturing the same. means of solving the problem

[0005] A semiconductor device according to the present invention may include: a first channel pattern and a second channel pattern spaced apart from each other in a first direction on a substrate; a first gate electrode on the first channel pattern and extending in the first direction; a second gate electrode on the second channel pattern and extending in the first direction; and a separation insulation pattern between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode may be aligned with each other in the first direction. The separation insulation pattern may include a lower pattern and an upper pattern stacked in a vertical direction perpendicular to the upper surface of the substrate. The interface between the lower pattern and the upper pattern may be located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern.

[0006] A semiconductor device according to the present invention may include: a first active pattern and a second active pattern spaced apart from each other in a first direction and extending in a second direction on a substrate, wherein the first direction and the second direction are parallel to the upper surface of the substrate and intersect each other; a device isolation layer between the first active pattern and the second active pattern; a first channel pattern on the first active pattern; a second channel pattern on the second active pattern; a first gate electrode extending in the first direction and crossing the first active pattern and the first channel pattern; a second gate electrode extending in the first direction and crossing the second active pattern and the second channel pattern; and a separation insulation pattern interposed between the first gate electrode and the second gate electrode and disposed on the device isolation layer. The first gate electrode and the second gate electrode may be aligned with each other in the first direction. The separation insulation pattern may include a lower pattern and an upper pattern stacked in a third direction perpendicular to the upper surface of the substrate. The upper surface of the lower pattern may be located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern.

[0007] A semiconductor device according to the present invention may include: a first active pattern and a second active pattern on a substrate that are spaced apart from each other in a first direction and extend in a second direction, wherein the first direction and the second direction are parallel to and intersect each other on the upper surface of the substrate; a first channel pattern on the first active pattern; first source / drain patterns on the first active pattern that are spaced apart from each other in the second direction with the first channel pattern in between; a second channel pattern on the second active pattern; second source / drain patterns on the second active pattern that are spaced apart from each other in the second direction with the second channel pattern in between; a first gate electrode that extends in the first direction and crosses the first active pattern and the first channel pattern; a second gate electrode that extends in the first direction and crosses the second active pattern and the second channel pattern; and a separation insulation pattern interposed between the first gate electrode and the second gate electrode. The first gate electrode and the second gate electrode may be aligned with each other in the first direction. The above-described isolation pattern may include a lower pattern and an upper pattern stacked in a third direction perpendicular to the upper surface of the substrate. The interface between the lower pattern and the upper pattern may be located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern. The first source / drain patterns may have a different conductivity type from the second source / drain patterns.

[0008] A method for manufacturing a semiconductor device according to the present invention comprises: forming a first active pattern and a second active pattern on a substrate that are spaced apart from each other in a first direction and extend in a second direction, wherein the first direction and the second direction are parallel to the upper surface of the substrate and intersect each other; forming a device isolation film between the first active pattern and the second active pattern; forming a first channel pattern and a second channel pattern respectively on the first active pattern and the second active pattern; forming a first lower mask film covering the first channel pattern, the second channel pattern, and the device isolation film between them; forming a first separation hole between the first channel pattern and the second channel pattern that penetrates the first lower mask film and exposes the upper surface of the device isolation film; forming a lower pattern within the first separation hole, wherein the upper surface of the lower pattern is located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern; and removing the first lower mask film. Forming a first gate electrode that extends in the first direction, crosses the first active pattern and the first channel pattern, and covers a portion of the lower pattern; forming a second gate electrode that extends in the first direction, crosses the second active pattern and the second channel pattern, and covers the remainder of the lower pattern; forming a second separation hole that penetrates a portion of the first gate electrode and a portion of the second gate electrode and exposes the upper surface of the lower pattern; and forming an upper pattern within the second separation hole.

[0009] According to some embodiments, the lower pattern may be formed using a bottom-up filling process.

[0010] According to some embodiments, forming the upper pattern may include depositing the upper pattern conformally to covering the side of the first gate electrode exposed by the second separation hole, the upper surface of the lower pattern, and the side of the second gate electrode, and the upper pattern may include an empty region therein.

[0011] According to some embodiments, forming the upper pattern may include forming a first sublayer by filling a portion of the second separation hole with a fluid insulating material; and forming a second sublayer by performing a surface treatment process on the upper surface of the first sublayer.

[0012] According to some embodiments, the upper pattern may include an inter-mixing layer formed between the first sublayer and the second sublayer.

[0013] According to some embodiments, the lower pattern may include an impurity layer adjacent to the upper surface of the lower pattern. The impurity layer may include an element different from that of the lower pattern.

[0014] According to some embodiments, the method may further comprise forming first source / drain patterns spaced apart from each other in the second direction with the first channel pattern in between on the first active pattern; and forming second source / drain patterns spaced apart from each other in the second direction with the second channel pattern in between on the second active pattern. The first source / drain patterns may have a different conductivity type from the second source / drain patterns.

[0015] According to some embodiments, the method may further comprise forming a first interlayer insulating film covering the first and second source / drain patterns; and forming a gap region extending in the first direction within the interlayer insulating film and exposing the first channel pattern, the second channel pattern, and the device isolation film between them. The first lower mask film may fill the gap region, and the first isolation hole may penetrate the first lower mask film within the gap region to expose the upper surface of the device isolation film.

[0016] According to some embodiments, the second gate electrode may include a material different from the first gate electrode.

[0017] According to some embodiments, each of the first channel pattern and the second channel pattern may include a plurality of semiconductor patterns spaced apart from each other in a third direction perpendicular to the upper surface of the substrate. Effects of the invention

[0018] According to the concept of the present invention, the isolation insulation pattern may include a lower pattern and an upper pattern stacked vertically between a first gate electrode and a second gate electrode. The lower pattern may be formed before the formation of the first and second gate electrodes, and the upper pattern may be formed after the formation of the first and second gate electrodes to penetrate the first and second gate electrodes. In this case, as the lower pattern is provided between the device isolation film and the upper pattern, the loss of the device isolation film during the formation of the upper pattern may be minimized. Additionally, as the upper pattern is formed on the lower pattern, the vertical length of the upper pattern may be reduced, and accordingly, the formation of the upper pattern may be easy.

[0019] Additionally, the interface between the lower pattern and the upper pattern may be located at a height lower than the uppermost surfaces of the first channel pattern and the second channel pattern, respectively, which are disposed below the first and second gate electrodes. That is, the upper surface of the lower pattern may be located at a height lower than the uppermost surfaces of the first channel pattern and the second channel pattern, and accordingly, during the manufacturing process of the semiconductor device, the removal of films formed between the first channel pattern and the lower pattern, and between the second channel pattern and the lower pattern, may be easy.

[0020] Accordingly, a semiconductor device and a method for manufacturing the same can be provided, which can minimize manufacturing defects, is easy to manufacture, and has excellent reliability. Brief explanation of the drawing

[0021] FIG. 1 is a plan view of a semiconductor device according to some embodiments of the present invention. FIGS. 2a, 2b, 2c, and 2d are cross-sectional views along A-A', B-B', CC', and D-D' of FIG. 1, respectively. FIGS. 3a to 20a, FIGS. 3b to 20b, FIGS. 3c to 20c, and FIGS. 3d to 20d are cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIGS. 21 to 31 are drawings showing a semiconductor device according to some embodiments of the present invention, and are cross-sectional views corresponding to A-A' of FIG. 1. Specific details for implementing the invention

[0022] The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings.

[0023] FIG. 1 is a plan view of a semiconductor device according to some embodiments of the present invention. FIG. 2a, FIG. 2b, FIG. 2c and FIG. 2d are cross-sectional views along A-A', B-B', CC' and D-D' of FIG. 1, respectively.

[0024] Referring to FIGS. 1, 2a through 2d, a first active pattern (AP1) and a second active pattern (AP2) may be disposed on a substrate (100). The substrate (100) may be a semiconductor substrate. For example, the substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, or an SOI (Silicon on Insulator) substrate. The first active pattern (AP1) and the second active pattern (AP2) may be spaced apart from each other in a first direction (D1) and may extend in a second direction (D2). The first direction (D1) and the second direction (D2) may be parallel to and intersect with the upper surface (100U) of the substrate (100). Each of the first active pattern (AP1) and the second active pattern (AP2) may protrude from the upper surface (100U) of the substrate (100) along a third direction (D3) perpendicular to the upper surface (100U) of the substrate (100). Each of the first active pattern (AP1) and the second active pattern (AP2) may be a part of the substrate (100) protruding from the substrate (100).

[0025] A device isolation film (110) may be disposed on the upper surface (100U) of the substrate (100) and on each side of the first active pattern (AP1) and the second active pattern (AP2), and may extend in the second direction (D2). The device isolation film (110) may extend in the second direction (D2) between the first active pattern (AP1) and the second active pattern (AP2). The device isolation film (110) may include an oxide, a nitride, and / or an oxynitride.

[0026] A first channel pattern (CH1) and first source / drain patterns (SD1) may be disposed on the first active pattern (AP1). The first source / drain patterns (SD1) may be spaced apart from each other in the second direction (D2), and the first channel pattern (CH1) may be interposed between the first source / drain patterns (SD1). According to some embodiments, the first channel pattern (CH1) may include first semiconductor patterns (SP1) spaced apart from each other in the third direction (D3). The lowest layer of the first semiconductor patterns (SP1) may be spaced apart from the first active pattern (AP1) along the third direction (D3). The first semiconductor patterns (SP1) may be interposed between the first source / drain patterns (SD1). Each of the first semiconductor patterns (SP1) may be connected to the first source / drain patterns (SD1) and may be in contact with the first source / drain patterns (SD1). Each of the first source / drain patterns (SD1) may be connected (or in contact) to the sides of the first semiconductor patterns (SP1). Although the number of the first semiconductor patterns (SP1) is shown as four, the concept of the present invention is not limited thereto. The first semiconductor patterns (SP1) may include, for example, at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0027] The first source / drain patterns (SD1) may be epitaxial patterns formed using the first active pattern (AP1) as a seed. The first source / drain patterns (SD1) may include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). The first source / drain patterns (SD1) may be configured to provide tensile strain or compressive strain to the first channel pattern (CH1). The first source / drain patterns (SD1) may further include impurities. The impurities may be employed to improve the electrical characteristics of the first transistor comprising the first source / drain patterns (SD1). If the first transistor is an NMOSFET, the impurity may be phosphorus (P), for example. If the first transistor is a PMOSFET, the impurity may be boron (B), for example.

[0028] A second channel pattern (CH2) and second source / drain patterns (SD2) may be disposed on the second active pattern (AP2). The second source / drain patterns (SD2) may be spaced apart from each other in the second direction (D2), and the second channel pattern (CH2) may be interposed between the second source / drain patterns (SD2). According to some embodiments, the second channel pattern (CH2) may include second semiconductor patterns (SP2) spaced apart from each other in the third direction (D3). The second semiconductor pattern (SP2) of the lowest layer among the second semiconductor patterns (SP2) may be spaced apart from the second active pattern (AP2) along the third direction (D3). The second semiconductor patterns (SP2) may be interposed between the second source / drain patterns (SD2). Each of the second semiconductor patterns (SP2) may be connected to the second source / drain patterns (SD2) and may be in contact with the second source / drain patterns (SD2). Each of the second source / drain patterns (SD2) may be connected (or in contact) to the sides of the second semiconductor patterns (SP2). Although the number of the second semiconductor patterns (SP2) is shown as four, the concept of the invention is not limited thereto. The second semiconductor patterns (SP2) may include, for example, at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0029] The second source / drain patterns (SD2) may be epitaxial patterns formed using the second active pattern (AP2) as a seed. The second source / drain patterns (SD2) may include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). The second source / drain patterns (SD2) may be configured to provide tensile strain or compressive strain to the second channel pattern (CH2). The second source / drain patterns (SD2) may further include impurities. The impurities may be employed to improve the electrical characteristics of the second transistor comprising the second source / drain patterns (SD2). If the second transistor is an NMOSFET, the impurity may be phosphorus (P), for example. If the second transistor is a PMOSFET, the impurity may be boron (B), for example.

[0030] The first channel pattern (CH1) and the second channel pattern (CH2) may be spaced apart from each other in the first direction (D1). The second source / drain patterns (SD2) may be spaced apart from the first source / drain patterns (SD1) along the first direction (D1). According to some embodiments, the first source / drain patterns (SD1) may have a different conductivity type from the second source / drain patterns (SD2). The first source / drain patterns (SD1) may have a first conductivity type, and the second source / drain patterns (SD2) may have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0031] A first gate electrode (GE1) may be disposed on the first active pattern (AP1) and the first channel pattern (CH1). The first gate electrode (GE1) may extend in the first direction (D1) to cross the first active pattern (AP1) and the first channel pattern (CH1) and may cover the first channel pattern (CH1). The first gate electrode (GE1) may extend along the first direction (D1) onto the upper surface (110U) of the device isolation film (110). The first channel pattern (CH1) may overlap the first gate electrode (GE1) perpendicularly (for example, in the third direction (D3)). The first source / drain patterns (SD1) may be disposed on both sides of the first gate electrode (GE1). The first gate electrode (GE1) may be disposed on the uppermost first semiconductor pattern (SP1) among the first semiconductor patterns (SP1) and may extend between the first semiconductor patterns (SP1), and between the lowermost first semiconductor pattern (SP1) among the first semiconductor patterns (SP1) and the first active pattern (AP1). The first gate electrode (GE1) may cover the sides facing each other in the first direction (D1) of the first channel pattern (CH1) (for example, the sides facing each other in the first direction (D1) of each of the first semiconductor patterns (SP1).

[0032] A first gate insulation pattern (GI1) may be interposed between the first active pattern (AP1) and the first gate electrode (GE1), and between the first channel pattern (CH1) and the first gate electrode (GE1). The first gate insulation pattern (GI1) may be interposed between each of the first semiconductor patterns (SP1) and the first gate electrode (GE1), and may surround the outer surface of each of the first semiconductor patterns (SP1). Each of the first semiconductor patterns (SP1) may be spaced apart from the first gate electrode (GE1) with the first gate insulation pattern (GI1) in between. The first gate insulation pattern (GI1) may extend between each of the first source / drain patterns (SD1) and the first gate electrode (GE1). The first gate insulation pattern (GI1) may extend along the bottom surface of the first gate electrode (GE1) and may be interposed between the first gate electrode (GE1) and the device isolation film (110).

[0033] Gate spacers (GSP) may be disposed on the sides of the first gate electrode (GE1). The gate spacers (GSP) may be disposed on the first semiconductor pattern (SP1) of the top layer and may extend along the sides of the first gate electrode (GE1). The first gate insulating pattern (GI1) may extend on the sides of the first gate electrode (GE1) and may be interposed between the first gate electrode (GE1) and the gate spacers (GSP).

[0034] Spacer patterns (ISP) may be interposed between the first semiconductor patterns (SP1) of the first channel pattern (CH1), and between the first semiconductor pattern (SP1) of the bottom layer and the first active pattern (AP1). The spacer patterns (ISP) may be spaced apart from each other in the second direction (D2) with the first gate electrode (GE1) in between. Each of the spacer patterns (ISP) may be interposed between the first source / drain pattern (SD1) among the first source / drain patterns (SD1) and the first gate electrode (GE1). Each of the first source / drain patterns (SD1) may be in contact with the first semiconductor patterns (SP1) and may be spaced apart from the first gate electrode (GE1) with the spacer patterns (ISP) in between. Each of the first source / drain patterns (SD1) may be in contact with a corresponding spacer pattern (ISP) among the spacer patterns (ISP). The first gate insulation pattern (GI1) may be interposed between each of the first gate electrode (GE1) and the first semiconductor patterns (SP1), and may extend between each of the first gate electrode (GE1) and the spacer patterns (ISP). Each of the spacer patterns (ISP) may be in contact with the first gate insulation pattern (GI1).

[0035] The first gate electrode (GE1) may comprise a doped semiconductor, a conductive metal nitride, and / or a metal. According to some embodiments, the first gate electrode (GE1) may comprise a first conductive pattern (CP1) on the first active pattern (AP1) and the first channel pattern (CH1), a second conductive pattern (CP2) on the first conductive pattern (CP1), and a third conductive pattern (CP3) on the second conductive pattern (CP2). The first conductive pattern (CP1) may be on the top layer first semiconductor pattern (SP1), interposed between the first semiconductor patterns (SP1), and between the bottom layer first semiconductor pattern (SP1) and the first active pattern (AP1). The first conductive pattern (CP1) may surround the outer surface of each of the first semiconductor patterns (SP1). The first conductive pattern (CP1) may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The second conductive pattern (CP2) may be on the first semiconductor pattern (SP1) of the top layer and may fill the space between the first semiconductor patterns (SP1) and between the first semiconductor pattern (SP1) of the bottom layer and the first active pattern (AP1). The second conductive pattern (CP2) may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The third conductive pattern (CP3) may be on the first semiconductor pattern (SP1) of the top layer and may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The second conductivity pattern (CP2) can be extended between the third conductivity pattern (CP3) and the gate spacers (GSP), and the first conductivity pattern (CP1) can be extended between the second conductivity pattern (CP2) and the gate spacers (GSP).The first gate insulation pattern (GI1) may extend between the first conductivity pattern (CP1) and the gate spacers (GSP). For example, the first conductivity pattern (CP1) and the third conductivity pattern (CP3) may comprise a conductive metal nitride (e.g., TiN), and the second conductivity pattern (CP2) may comprise a metal carbide (e.g., TiAlC).

[0036] The first gate insulation pattern (GI1) may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric film. The high dielectric film may include a material having a dielectric constant greater than that of a silicon oxide film, such as a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO). The gate spacers (GSP) may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The spacer patterns (ISP) may include a low dielectric film (for example, silicon nitride). For example, the spacer patterns (ISP) may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

[0037] The first gate electrode (GE1), the first channel pattern (CH1), and the first source / drain patterns (SD1) can form a gate-all-around field effect transistor or a multi-bridge channel field effect transistor (MBCFET).

[0038] A second gate electrode (GE2) may be disposed on the second active pattern (AP2) and the second channel pattern (CH2). The second gate electrode (GE2) may extend in the first direction (D1) to cross the second active pattern (AP2) and the second channel pattern (CH2) and may cover the second channel pattern (CH2). The second gate electrode (GE2) may extend along the first direction (D1) onto the upper surface (110U) of the device isolation film (110). The second channel pattern (CH2) may overlap the second gate electrode (GE2) perpendicularly (for example, in the third direction (D3)). The second source / drain patterns (SD2) may be disposed on both sides of the second gate electrode (GE2). The second gate electrode (GE2) may be disposed on the uppermost second semiconductor pattern (SP2) among the second semiconductor patterns (SP2) and may extend between the second semiconductor patterns (SP2), and between the lowermost second semiconductor pattern (SP2) among the second semiconductor patterns (SP2) and the second active pattern (AP2). The second gate electrode (GE2) may cover the sides facing each other in the first direction (D1) of the second channel pattern (CH2) (for example, the sides facing each other in the first direction (D1) of each of the second semiconductor patterns (SP2)).

[0039] A second gate insulation pattern (GI2) may be interposed between the second active pattern (AP2) and the second gate electrode (GE2), and between the second channel pattern (CH2) and the second gate electrode (GE2). The second gate insulation pattern (GI2) may be interposed between each of the second semiconductor patterns (SP2) and the second gate electrode (GE2), and may surround the outer surface of each of the second semiconductor patterns (SP2). Each of the second semiconductor patterns (SP2) may be spaced apart from the second gate electrode (GE2) with the second gate insulation pattern (GI2) in between. The second gate insulation pattern (GI2) may extend between each of the second source / drain patterns (SD2) and the second gate electrode (GE2). The second gate insulation pattern (GI2) may extend along the bottom surface of the second gate electrode (GE2) and may be interposed between the second gate electrode (GE2) and the device isolation film (110).

[0040] The gate spacers (GSP) may be disposed on the sides of the second gate electrode (GE2). The gate spacers (GSP) may be disposed on the uppermost second semiconductor pattern (SP2) and may extend along the sides of the second gate electrode (GE2). The second gate insulation pattern (GI2) may extend on the sides of the second gate electrode (GE2) and may be interposed between the second gate electrode (GE2) and the gate spacers (GSP). The second gate insulation pattern (GI2) may be interposed between the second gate electrode (GE2) and each of the second semiconductor patterns (SP2) and may extend between the second gate electrode (GE2) and each of the second source / drain patterns (SD2). Each of the second source / drain patterns (SD2) may be in contact with the second semiconductor patterns (SP2) and may be spaced apart from the second gate electrode (GE2) with the second gate insulation pattern (GI2) in between. Each of the second source / drain patterns (SD2) may be in contact with the second gate insulation pattern (GI2).

[0041] The second gate electrode (GE2) may comprise a doped semiconductor, a conductive metal nitride, and / or a metal. The second gate electrode (GE2) may comprise a material different from that of the first gate electrode (GE1). According to some embodiments, the second gate electrode (GE2) may comprise a fourth conductive pattern (CP4) on the second active pattern (AP2) and the second channel pattern (CH2), a fifth conductive pattern (CP5) on the fourth conductive pattern (CP4), and a sixth conductive pattern (CP6) on the fifth conductive pattern (CP5). The fourth conductive pattern (CP4) may be on the uppermost second semiconductor pattern (SP2) and may fill the space between the second semiconductor patterns (SP2) and between the lowermost second semiconductor pattern (SP2) and the second active pattern (AP2). The fourth conductive pattern (CP4) may surround the outer surface of each of the second semiconductor patterns (SP2). The fourth conductivity pattern (CP4) may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The fifth conductivity pattern (CP5) may be on the second semiconductor pattern (SP2) of the uppermost layer and may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The sixth conductivity pattern (CP6) may be on the first semiconductor pattern (SP1) of the uppermost layer and may extend along the first direction (D1) onto the upper surface (100U) of the device isolation film (110). The fifth conductivity pattern (CP5) may extend between the sixth conductivity pattern (CP6) and the gate spacers (GSP), and the fourth conductivity pattern (CP4) may extend between the fifth conductivity pattern (CP5) and the gate spacers (GSP). The second gate insulation pattern (GI2) can be extended between the fourth conductivity pattern (CP4) and the gate spacers (GSP).For example, the fourth conductive pattern (CP4) and the fifth conductive pattern (CP5) may include different conductive metal nitrides. For example, the fourth conductive pattern (CP4) may include TiAlN, and the fifth conductive pattern (CP5) may include TiN. The sixth conductive pattern (CP6) may include a metal carbide (for example, TiAlC).

[0042] The second gate insulation pattern (GI2) may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high dielectric film. The high dielectric film may include a material having a dielectric constant greater than that of a silicon oxide film, such as a hafnium oxide film (HfO), an aluminum oxide film (AlO), or a tantalum oxide film (TaO).

[0043] The second gate electrode (GE2), the second channel pattern (CH2), and the second source / drain patterns (SD2) can form a gate-all-around field effect transistor or a multi-bridge channel field effect transistor (MBCFET).

[0044] A separation insulation pattern (200) may be disposed between the first gate electrode (GE1) and the second gate electrode (GE2), and may be disposed on the device isolation film (110) between the first active pattern (AP1) and the second active pattern (AP2). The separation insulation pattern (200) may extend between the first gate insulation pattern (GI1) and the second gate insulation pattern (GI2) to contact the upper surface (110U) of the device isolation film (110), and may extend in the third direction (D3) to separate the first gate electrode (GE1) and the second gate electrode (GE2) from each other. The first gate electrode (GE1) and the second gate electrode (GE2) may be spaced apart from each other in the first direction (D1) with the separation insulation pattern (200) in between, and may be aligned with each other in the first direction (D1).

[0045] The above isolation insulation pattern (200) may include a lower pattern (210) and an upper pattern (220) stacked along the third direction (D3). The lower pattern (210) may be interposed between the first gate electrode (GE1) and the second gate electrode (GE2), and may extend between the first gate insulation pattern (GI1) and the second gate insulation pattern (GI2) to contact the upper surface (110U) of the device isolation film (110). The lower surface (210L) of the lower pattern (210) may contact the upper surface (110U) of the device isolation film (110). According to some embodiments, the upper surface (110U) of the device isolation film (110) may be substantially flat, and accordingly, the lower surface (210L) of the lower pattern (210) may also be substantially flat. The lower pattern (210) may have a pillar shape extending in the third direction (D3). The upper surface (210U) of the lower pattern (210) may be located at a height lower than the uppermost surface (CH1_U) of the first channel pattern (CH1) and the uppermost surface (CH2_U) of the second channel pattern (CH2). In this specification, the height may be measured in the third direction (D3) from the upper surface (100U) of the substrate (100). The uppermost surface (CH1_U) of the first channel pattern (CH1) may be the upper surface of the uppermost first semiconductor pattern (SP1) among the first semiconductor patterns (SP1), and the uppermost surface (CH2_U) of the second channel pattern (CH2) may be the upper surface of the uppermost second semiconductor pattern (SP2) among the second semiconductor patterns (SP2).

[0046] The upper pattern (220) may be interposed between the first gate electrode (GE1) and the second gate electrode (GE2) and may be placed on the lower pattern (210). The lower surface (220L) of the upper pattern (220) may be in contact with the upper surface (210U) of the lower pattern (210). The interface (INF) between the lower pattern (210) and the upper pattern (220) may be located at a height lower than the uppermost surface (CH1_U) of the first channel pattern (CH1) and the uppermost surface (CH2_U) of the second channel pattern (CH2). According to some embodiments, the upper pattern (220) may be extended in the third direction (D3) and may include an empty region (230) therein. The empty region (230) may be referred to as a void or a seam, for example. The upper pattern (220) can cover the first side (GE1_S) of the first gate electrode (GE1) and the second side (GE2_S) of the second gate electrode (GE2), which are opposite each other in the first direction (D1), and can cover the upper surface (210U) of the lower pattern (210).

[0047] According to some embodiments, the gate spacers (GSP) may extend in the first direction (D1) to cover the sides of the first gate electrode (GE1) facing each other in the second direction (D2), the sides of the separating insulation pattern (200) facing each other in the second direction (D2), and the sides of the second gate electrode (GE2) facing each other in the second direction (D2). The gate spacers (GSP) may cover the sides of the lower pattern (210) facing each other in the second direction (D2) and the sides of the upper pattern (220) facing each other in the second direction (D2). The separating insulation pattern (200) may be interposed between the gate spacers (GSP).

[0048] According to some embodiments, the first conductive pattern (CP1) and the second conductive pattern (CP2) of the first gate electrode (GE1) may cover one of the sides facing each other in the first direction (D1) of the lower pattern (210). The first conductive pattern (CP1) may be interposed between the second conductive pattern (CP2) and the one of the sides facing each other in the first direction (D1) of the lower pattern (210). The third conductive pattern (CP3) of the first gate electrode (GE1) may cover one of the sides facing each other in the first direction (D1) of the upper pattern (220). The fourth to sixth conductive patterns (CP4, CP5, CP6) of the second gate electrode (GE2) may cover the other of the sides facing each other in the first direction (D1) of the lower pattern (210). The sixth conductive pattern (CP6) of the second gate electrode (GE2) can cover the other of the sides facing each other in the first direction (D1) of the upper pattern (220).

[0049] The lower pattern (210) and the upper pattern (220) may include an insulating material. According to some embodiments, the lower pattern (210) may include silicon nitride, and for example, at least one of SiN and SiCN. The upper pattern (220) may include silicon nitride (for example, SiN, SiCN), silicon oxide and / or silicon oxynitride. The lower pattern (210) and the upper pattern (220) may include the same insulating material or different insulating materials.

[0050] Each of the lower pattern (210) and the upper pattern (220) may have a width according to the first direction (D1). The width (210W) of the lower pattern (210) may be, for example, 10 nm to 20 nm. According to some embodiments, the width (210W) of the upper surface (210U) of the lower pattern (210) may be the same as the width (220W) of the lower surface (220L) of the upper pattern (220). The vertical length (210H) of the lower pattern (210) according to the third direction (D3) may be, for example, greater than 0 nm and less than or equal to 35 nm.

[0051] A first interlayer insulating film (140) may be disposed on the substrate (100) and may cover the first and second gate electrodes (GE1, GE2), the gate spacers (GSP), the first and second source / drain patterns (SD1, SD2), and the separation insulating pattern (200). The gate spacers (GSP) may be interposed between the first gate electrode (GE1) and the first interlayer insulating film (140), between the separation insulating pattern (200) and the first interlayer insulating film (140), and between the second gate electrode (GE2) and the first interlayer insulating film (140). The first interlayer insulating film (140) may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film.

[0052] An upper film (150) may be disposed on the first interlayer insulating film (140) and may cover the top surfaces of the first and second gate electrodes (GE1, GE2) and the gate spacers (GSP). The isolation insulating pattern (200) may extend in the third direction (D3) and penetrate the upper film (150). The upper film (150) may, for example, comprise silicon nitride. According to some embodiments, the upper film (150) may be provided locally on the top surfaces of the first and second gate electrodes (GE1, GE2). In this case, the first interlayer insulating film (140) and the gate spacers (GSP) may extend onto the sides of the upper film (150), and the upper film (150) may comprise silicon nitride or metal.

[0053] A second interlayer insulating film (160) may be disposed on the upper film (150) and may cover the uppermost surface of the separated insulating pattern (200). The second interlayer insulating film (160) may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film.

[0054] Active contacts (AC) may be disposed on each side of the first gate electrode (GE1) and the second gate electrode (GE2) and may be connected to the first and second source / drain patterns (SD1, SD2). Each of the active contacts (AC) may be connected to a corresponding one of the first and second source / drain patterns (SD1, SD2) by penetrating the second interlayer insulating film (160), the top film (150), and the first interlayer insulating film (140). The active contacts (AC) may include a conductive material.

[0055] According to the concept of the present invention, the isolation insulation pattern (200) may include the lower pattern (210) and the upper pattern (220) stacked along the third direction (D3). The lower pattern (210) may be formed before the formation of the first and second gate electrodes (GE1, GE2), and the upper pattern (220) may be formed after the formation of the first and second gate electrodes (GE1, GE2) to penetrate the first and second gate electrodes (GE1, GE2). In this case, as the lower pattern (210) is provided between the device isolation film (110) and the upper pattern (220), the loss of the device isolation film (110) during the formation of the upper pattern (220) may be minimized. Additionally, as the upper pattern (220) is formed on the lower pattern (210), the vertical length of the upper pattern (220) (for example, the length along the third direction (D3)) may be reduced, and accordingly, the formation of the upper pattern (220) may be easy.

[0056] Additionally, the interface (INF) between the lower pattern (210) and the upper pattern (220) may be located at a lower height than the uppermost surface (CH1_U) of the first channel pattern (CH1) and the uppermost surface (CH2_U) of the second channel pattern (CH2). That is, the upper surface (210U) of the lower pattern (210) may be located at a lower height than the uppermost surface (CH1_U) of the first channel pattern (CH1) and the uppermost surface (CH2_U) of the second channel pattern (CH2), and accordingly, during the manufacturing process of the semiconductor device, the films formed between the first channel pattern (CH1) and the lower pattern (210), and between the second channel pattern (CH2) and the lower pattern (210) may be easily removed.

[0057] Accordingly, a semiconductor device and a method for manufacturing the same can be provided, which can minimize manufacturing defects, is easy to manufacture, and has excellent reliability.

[0058] FIGS. 3a to 20a, FIGS. 3b to 20b, FIGS. 3c to 20c, and FIGS. 3d to 20d are cross-sectional views illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIGS. 3a to 20a are cross-sectional views corresponding to A-A' of FIG. 1, FIGS. 3b to 20b are cross-sectional views corresponding to B-B' of FIG. 1, FIGS. 3c to 20c are cross-sectional views along C-C' of FIG. 1, and FIGS. 3d to 20d are cross-sectional views along D-D' of FIG. 1. For the sake of simplification of the explanation, descriptions that overlap with the semiconductor device described with reference to FIG. 1 and FIGS. 2a to 2d are omitted.

[0059] Referring to FIGS. 1 and FIGS. 3a through 3d, a first active pattern (AP1) and a second active pattern (AP2) may be formed on a substrate (100). The first active pattern (AP1) and the second active pattern (AP2) may be spaced apart from each other in the first direction (D1) and may extend in the second direction (D2). First semiconductor patterns (SP1) may be formed on the first active pattern (AP1) and may be spaced apart from each other along the third direction (D3). The first semiconductor pattern (SP1) of the lowest layer among the first semiconductor patterns (SP1) may be spaced apart from the first active pattern (AP1) along the third direction (D3). Second semiconductor patterns (SP2) may be formed on the second active pattern (AP2) and may be spaced apart from each other along the third direction (D3). The second semiconductor pattern (SP2) of the lowest layer among the second semiconductor patterns (SP2) can be spaced apart from the second active pattern (AP2) along the third direction (D3).

[0060] First sacrifice patterns (102A) may be formed between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the lowest layer, and between the first semiconductor patterns (SP1). Second sacrifice patterns (102B) may be formed between the second active pattern (AP2) and the second semiconductor pattern (SP2) of the lowest layer, and between the second semiconductor patterns (SP2). The first semiconductor patterns (SP1) and the first sacrifice patterns (102A) may be extended in the second direction (D2) on the first active pattern (AP1), and the second semiconductor patterns (SP2) and the second sacrifice patterns (102B) may be extended in the second direction (D2) on the second active pattern (AP2). The first and second sacrificial patterns (102A, 102B) may include a material having etch selectivity with respect to the first and second semiconductor patterns (SP1, SP2). For example, the first and second sacrificial patterns (102A, 102B) may include silicon-germanium (SiGe), and the first and second semiconductor patterns (SP1, SP2) may include silicon (Si).

[0061] Forming the first and second semiconductor patterns (SP1, SP2), the first and second sacrificial patterns (102A, 102B), and the first and second active patterns (AP1, AP2) may, for example, include alternately and repeatedly stacking sacrificial layers and semiconductor layers on the substrate (100), and patterning the sacrificial layers, the semiconductor layers, and the upper surface of the substrate (100) to form trenches (T) that define the first and second semiconductor patterns (SP1, SP2), the first and second sacrificial patterns (102A, 102B), and the first and second active patterns (AP1, AP2). The trenches (T) may have a line shape extending in the second direction (D2) and may be spaced apart from each other in the first direction (D1).

[0062] A device isolation layer (110) may be formed to fill the lower portion of each of the trenches (T). Forming the device isolation layer (110) may, for example, include forming an insulating layer that fills the trenches (T) on the substrate (100), and recessing the insulating layer so that the sides of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrificial patterns (102A, 102B) are exposed. The device isolation layer (110) may extend in the second direction (D2) between the first active pattern (AP1) and the second active pattern (AP2).

[0063] Referring to FIGS. 1 and FIGS. 4a through 4d, a sacrifice gate pattern (SGE) may be formed to cross the first and second active patterns (AP1, AP2), the first and second semiconductor patterns (SP1, SP2), and the first and second sacrifice patterns (102A, 102B). The sacrifice gate pattern (SGE) may extend in the first direction (D1) to cross the first and second active patterns (AP1, AP2), the first and second semiconductor patterns (SP1, SP2), the first and second sacrifice patterns (102A, 102B), and the device isolation film (110). The above sacrifice gate pattern (SGE) can cover the sides facing each other in the first direction (D1) of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrifice patterns (102A, 102B), and can cover the upper surface (110U) of the device isolation film (110).

[0064] An etch stop pattern (104) may be extended in the first direction (D1) along the lower surface of the sacrifice gate pattern (SGE). The etch stop pattern (104) may be interposed between the sacrifice gate pattern (SGE) and the respective sides of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrifice patterns (102A, 102B) facing each other in the first direction (D1), and may be extended between the sacrifice gate pattern (SGE) and the device isolation film (110). A mask pattern (106) may be extended in the first direction (D1) along the upper surface of the sacrifice gate pattern (SGE).

[0065] Forming the sacrificial gate pattern (SGE) and the etch stop pattern (104) may, for example, include sequentially forming the first and second semiconductor patterns (SP1, SP2), the first and second sacrificial patterns (102A, 102B), and the etch stop film and sacrificial gate film covering the device isolation film (110) on the substrate (100); forming the mask pattern (106) that defines the region where the sacrificial gate pattern (SGE) is to be formed on the sacrificial gate film; and sequentially patterning the sacrificial gate film and the etch stop film using the mask pattern (106) as an etching mask. The etch stop pattern (104) may, for example, include a silicon oxide film. The sacrificial gate pattern (SGE) may include a material having etch selectivity for the etch stop pattern (104). The sacrificial gate pattern (SGE) may, for example, include polysilicon.

[0066] Gate spacers (GSP) may be formed on the sides of the sacrificial gate pattern (SGE). Forming the gate spacers (GSP) may, for example, include forming a gate spacer film (not shown) covering the mask pattern (106), the sacrificial gate pattern (SGE), and the etch stop pattern (104) on the substrate (100), and anisotropically etching the gate spacer film. The mask pattern (106) and the gate spacers (GSP) may, for example, comprise silicon nitride.

[0067] Parts of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrificial patterns (102A, 102B) can be removed from both sides of the sacrificial gate pattern (SGE). Removing said parts of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrificial patterns (102A, 102B) may, for example, include etching said parts of the first and second semiconductor patterns (SP1, SP2) and the first and second sacrificial patterns (102A, 102B) by performing an etching process using the mask pattern (106) and the gate spacers (GSP) as an etching mask. The etching process may be performed until the upper surfaces of the first and second active patterns (AP1, AP2) are exposed from both sides of the sacrificial gate pattern (SGE).

[0068] Referring to FIGS. 1, 5a through 5d, according to some embodiments, spacer patterns (ISP) may be formed between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the bottom layer, and between the first semiconductor patterns (SP1). Forming the spacer patterns (ISP) may, for example, include horizontally recessing the sides of the first sacrificial patterns (102A) to form recessed regions between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the bottom layer, and between the first semiconductor patterns (SP1); forming a spacer film that fills the recessed regions; and anisotropically etching the spacer film so that the spacer patterns (ISP) are formed locally within the recessed regions.

[0069] First source / drain patterns (SD1) may be formed on both sides of the sacrifice gate pattern (SGE) and on the first active pattern (AP1). The first source / drain patterns (SD1) may be formed by performing an optional epitaxial growth process using the first semiconductor patterns (SP1) and the first active pattern (AP1) as seeds. Each of the first source / drain patterns (SD1) may be in contact with the sides of the first semiconductor patterns (SP1). The first source / drain patterns (SD1) may be spaced apart from the first sacrifice patterns (102A) with the spacer patterns (ISP) in between. The first source / drain patterns (SD1) may be in contact with the spacer patterns (ISP). Forming the first source / drain patterns (SD1) may further include injecting impurities (e.g., phosphorus (P) or boron (B)) into the first source / drain patterns (SD1) simultaneously with or after the selective epitaxial growth process.

[0070] Second source / drain patterns (SD2) may be formed on both sides of the sacrificial gate pattern (SGE) and on the second active pattern (AP2). The second source / drain patterns (SD2) may be formed by performing an optional epitaxial growth process using the second semiconductor patterns (SP2) and the second active pattern (AP2) as seeds. Each of the second source / drain patterns (SD2) may be in contact with the sides of the second semiconductor patterns (SP2). According to some embodiments, the second source / drain patterns (SD2) may be in contact with the sides of the second sacrificial patterns (102B). Forming the second source / drain patterns (SD2) may further include injecting impurities (e.g., phosphorus (P) or boron (B)) into the second source / drain patterns (SD2) simultaneously with or after the selective epitaxial growth process.

[0071] A first interlayer insulating film (140) may be formed on the substrate (100) and may cover the sacrificial gate pattern (SGE), the gate spacers (GSP), the device isolation film (110), and the first and second source / drain patterns (SD1, SD2). Forming the first interlayer insulating film (140) may, for example, include forming an insulating film covering the mask pattern (106), the sacrificial gate pattern (SGE), the gate spacers (GSP), the device isolation film (110), and the first and second source / drain patterns (SD1, SD2) on the substrate (100), and flattening the insulating film until the upper surface of the sacrificial gate pattern (SGE) is exposed. The mask pattern (106) may be removed by the flattening process.

[0072] Referring to FIGS. 1, 6a through 6d, the sacrificial gate pattern (SGE) and the etch stop pattern (104) can be removed, and accordingly, a gap region (GAP) can be formed within the first interlayer insulating film (140). The gap region (GAP) can be formed between the gate spacers (GSP) and can extend in the first direction (D1). The gap region (GAP) can expose the upper surface (110U) of the device isolation film (110) and the sides of the first sacrificial patterns (102A) and the second sacrificial patterns (102B). Forming the gap region (GAP) may further include removing the first sacrificial patterns (102A) and the second sacrificial patterns (102B). Accordingly, the gap region (GAP) may extend between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the lowest layer, between the first semiconductor patterns (SP1), between the second active pattern (AP2) and the second semiconductor pattern (SP2) of the lowest layer, and between the second semiconductor patterns (SP2). The first semiconductor patterns (SP1) may be referred to as the first channel pattern (CH1), and the second semiconductor patterns (SP2) may be referred to as the second channel pattern (CH2).

[0073] Referring to FIGS. 1 and FIGS. 7a through 7d, a gate insulating film (GI) may be formed to conformally cover the inner surface of the gap region (GAP). The gate insulating film (GI) may cover the upper surfaces of the first and second active patterns (AP1, AP2) and the upper surface (110U) of the device isolation film (110) within the gap region (GAP), and may surround the respective outer surfaces of the first and second semiconductor patterns (SP1, SP2). The gate insulating film (GI) may conformally cover the gate spacers (GSP), the spacer patterns (ISP), and the second source / drain patterns (SD2) within the gap region (GAP).

[0074] Third sacrifice patterns (132) may be formed to fill the space between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the lowest layer, and between the first semiconductor patterns (SP1). Fourth sacrifice patterns (134) may be formed to fill the space between the second active pattern (AP2) and the second semiconductor pattern (SP2) of the lowest layer, and between the second semiconductor patterns (SP2). Forming the third and fourth sacrificial patterns (132, 134) may, for example, include forming a sacrificial film covering the first and second active patterns (AP1, AP2), the first and second semiconductor patterns (SP1, SP2) and the device isolation film (110) within the gap region (GAP), and removing a portion of the sacrificial film so that the sacrificial film remains locally between the first active pattern (AP1) and the first semiconductor pattern (SP1) of the bottom layer, between the first semiconductor patterns (SP1), between the second active pattern (AP2) and the second semiconductor pattern (SP2) of the bottom layer, and between the second semiconductor patterns (SP2). The third and fourth sacrificial patterns (132, 134) may include a metal oxide (for example, aluminum oxide).

[0075] Referring to FIGS. 1 and FIGS. 8a through 8d, a first protective layer (135) may be formed to fill a portion of the gap region (GPA). The first protective layer (135) may conformally cover the first channel pattern (CH1), the third sacrifice patterns (132), the second channel pattern (CH2), and the fourth sacrifice patterns (134), and may extend onto the upper surface (110U) of the device isolation layer (110). The first protective layer (135) may extend onto the gate spacers (GSP). The first protective layer (135) may comprise a metal nitride (for example, TiN).

[0076] A first lower mask film (170) may be formed to fill the remainder of the gap region (GAP). The first lower mask film (170) may cover the upper surface of the first interlayer insulating film (140). A first upper mask film (172) may be formed on the first lower mask film (170). The first lower mask film (170) may include an anti-reflective material (e.g., Bottom Anti-Reflective Coating (BARC) material), and the first upper mask film (172) may include a metal oxide (e.g., TiO2).

[0077] A first photoresist pattern (174) may be formed on the first upper mask film (172). The first photoresist pattern (174) may have a first opening (174OP) that overlaps vertically (for example, in the third direction (D3)) with the device isolation film (110) between the first channel pattern (CH1) and the second channel pattern (CH2). The first opening (174OP) may have a line shape extending in the second direction (D2).

[0078] Referring to FIGS. 1, 9a through 9d, an etching process may be performed to etch portions of the first upper mask film (172), the first lower mask film (170), the first protective film (135), and the gate insulating film (GI) exposed by the first opening (174OP). During the etching process, the first interlayer insulating film (140) and the gate spacers (GSP) may not be etched. Accordingly, a first isolation hole (200H) may be formed on the device isolation film (110) between the first channel pattern (CH1) and the second channel pattern (CH2), and between the gate spacers (GSP). The first separation hole (200H) may extend in the third direction (D3) between the gate spacers (GSP) and may penetrate the first upper mask film (172), the first lower mask film (170), the first protective film (135), and the gate insulating film (GI). The first separation hole (200H) may expose the upper surface (110U) of the device isolation film (110) between the first channel pattern (CH1) and the second channel pattern (CH2). After the first separation hole (200H) is formed, the first photoresist pattern (174) and the first upper mask film (172) may be removed.

[0079] Referring to FIGS. 1, 10a through 10d, a lower pattern (210) may be formed to fill the lower portion of the first separation hole (200H). The lower pattern (210) may be formed using a bottom-up filling process. The lower pattern (210) may be in contact with the upper surface (110U) of the device isolation film (110) and may have a pillar shape extending in the third direction (D3). The upper surface (210U) of the lower pattern (210) may be located at a lower height than the uppermost surface (CH1_U) of the first channel pattern (CH1) and the uppermost surface (CH2_U) of the second channel pattern (CH2). The uppermost surface (CH1_U) of the first channel pattern (CH1) may be the upper surface of the uppermost first semiconductor pattern (SP1) among the first semiconductor patterns (SP1), and the uppermost surface (CH2_U) of the second channel pattern (CH2) may be the upper surface of the uppermost second semiconductor pattern (SP2) among the second semiconductor patterns (SP2).

[0080] During the bottom-up filling process, a bottom film (212) may be formed on the first bottom mask film (170) and the first interlayer insulating film (140) and may be formed to cover the top surfaces of the gate spacers (GSP). The bottom film (212) may comprise the same material as the bottom pattern (210). A second protective film (176) may be formed on the bottom film (212) and may fill the remainder of the first separation hole (200H). The second protective film (176) may comprise silicon oxide, for example.

[0081] Referring to FIGS. 1, 11a through 11d, the second protective film (176), the lower film (212), and the first lower mask film (170) can be flattened until the upper surface of the first interlayer insulating film (140) and the upper surfaces of the gate spacers (GSP) are exposed. By the flattening process, the remainder of the second protective film (176) may remain within the first separation hole (200H), and the lower film (212) may be removed. By the flattening process, the remainder of the first lower mask film (170) may remain between the gate spacers (GSP). After the flattening process, the remainder of the second protective film (176) may be removed within the first separation hole (200H), and accordingly, the upper surface (210U) of the lower pattern (210) may be exposed. Removing the remainder of the second protective film (176) can be performed, for example, using a dry or wet etching process.

[0082] Referring to FIG. 1 and FIG. 12a to FIG. 12d, the remainder of the first lower mask film (170) can be removed. Removing the remainder of the first lower mask film (170) can be performed, for example, by using an etching and / or stripping process.

[0083] A second lower mask layer (180) may be formed on the first interlayer insulating layer (140) and may extend between the gate spacers (GSP) to cover the first channel pattern (CH1) and the third sacrificial patterns (132). The second lower mask layer (180) may cover the first protective layer (135) on the first channel pattern (CH1) and the third sacrificial patterns (132), and may cover a portion of the lower pattern (210). A second upper mask layer (182) may be formed on the second lower mask layer (180). The second lower mask layer (180) and the second upper mask layer (182) may expose the first protective layer (135) on the second channel pattern (CH2) and the fourth sacrificial patterns (134), and may expose the remainder of the lower pattern (210). The second lower mask film (180) may include an anti-reflective material (e.g., BARC (Bottom Anti-Reflective Coating) material), and the second upper mask film (182) may include a metal oxide (e.g., TiO2).

[0084] Referring to FIG. 1 and FIG. 13a through FIG. 13d, the first protective film (135) on the second channel pattern (CH2) and the fourth sacrifice patterns (134) can be removed. Accordingly, the gate insulating film (GI) on the second channel pattern (CH2) can be exposed, and the sides of the fourth sacrifice patterns (134) can be exposed.

[0085] Referring to FIGS. 1 and FIGS. 14a through 14d, the second lower mask layer (180) and the second upper mask layer (182) can be removed. Accordingly, the first protective layer (135) on the first channel pattern (CH1) and the third sacrificial patterns (132) can be exposed. Removing the second lower mask layer (180) and the second upper mask layer (182) can be performed, for example, using an etching and / or stripping process. Subsequently, the fourth sacrificial patterns (134) can be removed. Accordingly, the gate insulating layer (GI) between the second semiconductor patterns (SP2) of the second channel pattern (CH2), and between the second semiconductor pattern (SP2) of the lowest layer of the second semiconductor patterns (SP2) and the second active pattern (AP2) can be exposed.

[0086] Referring to FIGS. 1 and FIGS. 15a through 15d, the first protective film (135) on the first channel pattern (CH1) and the third sacrificial patterns (132) can be removed. Accordingly, the gate insulating film (GI) on the first channel pattern (CH1) can be exposed, and the sides of the third sacrificial patterns (132) can be exposed.

[0087] A first conductive film (CL1) may be formed to cover the first channel pattern (CH1), the third sacrificial patterns (132), the lower pattern (210), and the second channel pattern (CH2). The first conductive film (CL1) may fill the space between the second semiconductor patterns (SP2) of the second channel pattern (CH2) and the space between the second semiconductor pattern (SP2) of the lowest layer among the second semiconductor patterns (SP2) and the second active pattern (AP2). The first conductive film (CL1) may cover the upper surface (210U) of the lower pattern (210) and may extend onto the sides of the gate spacers (GSP). The first conductive film (CL1) may include a conductive metal nitride, and, for example, may include TiAlN.

[0088] A third lower mask layer (184) may be formed on the first interlayer insulating layer (140) and may extend between the gate spacers (GSP) to cover the first conductive film (CL1) on the second channel pattern (CH2). The third lower mask layer (184) may cover a portion of the first conductive film (CL1) on the lower pattern (210). A third upper mask layer (186) may be formed on the third lower mask layer (184). The third lower mask layer (184) and the third upper mask layer (186) may expose the first conductive film (CL1) on the first channel pattern (CH1) and the third sacrificial patterns (132), and may expose a portion of the first conductive film (CL1) on the lower pattern (210). The third lower mask film (184) may include an anti-reflective material (e.g., BARC (Bottom Anti-Reflective Coating) material), and the third upper mask film (186) may include a metal oxide (e.g., TiO2).

[0089] Referring to FIGS. 1, 16a through 16d, the first conductive film (CL1) on the first channel pattern (CH1) and the third sacrificial patterns (132) can be removed, and a portion of the first conductive film (CL1) on the lower pattern (210) can be removed. Accordingly, the gate insulating film (GI) on the first channel pattern (CH1) can be exposed, and the sides of the third sacrificial patterns (132) can be exposed.

[0090] Referring to FIGS. 1, 17a through 17d, the third lower mask film (184) and the third upper mask film (186) can be removed. Accordingly, the first conductive film (CL1) on the second active pattern (AP2), the second channel pattern (CH2), and the lower pattern (210) can be exposed. Removing the third lower mask film (184) and the third upper mask film (186) can be performed, for example, using an etching and / or stripping process. Afterward, the third sacrificial patterns (132) can be removed. Accordingly, the gate insulating film (GI) between the first semiconductor patterns (SP1) of the first channel pattern (CH1), and between the first semiconductor pattern (SP1) of the lowest layer of the first semiconductor patterns (SP1) and the first active pattern (AP1) can be exposed.

[0091] Referring to FIGS. 1 and FIGS. 18a through 18d, a second conductive film (CL2) may be formed to cover the first channel pattern (CH1), the lower pattern (210), and the second channel pattern (CH2). The second conductive film (CL2) may surround the outer surface of each of the first semiconductor patterns (SP1) of the first channel pattern (CH1), and may cover the upper surface of the first active pattern (AP1) and the upper surface of the device isolation film (110). The second conductive film (CL2) may cover the lower pattern (210) and may cover the first conductive film (CL1) on the lower pattern (210) and the second channel pattern (CH2). The second conductive film (CL2) may include a conductive metal nitride and may include a material different from the first conductive film (CL1). The second conductive film (CL2) above may include TiN, for example.

[0092] A third conductive film (CL3) may be formed to cover the first channel pattern (CH1), the lower pattern (210), and the second channel pattern (CH2). The third conductive film (CL3) may cover the second conductive film (CL2) on the first channel pattern (CH1). The third conductive film (CL3) may fill the space between the first semiconductor patterns (SP1) and the space between the first semiconductor pattern (SP1) of the lowest layer among the first semiconductor patterns (SP1) and the first active pattern (AP1). The third conductive film (CL3) may cover the second conductive film (CL2) on the lower pattern (210) and may cover the first conductive film (CL1) and the second conductive film (CL2) on the second channel pattern (CH2). The third conductive film (CL3) may include metal carbide (e.g., TiAlC).

[0093] A fourth conductive film (CL4) may be formed to cover the first channel pattern (CH1). The fourth conductive film (CL4) may cover the second conductive film (CL2) and the third conductive film (CL3) on the first channel pattern (CH1). The fourth conductive film (CL4) may include a conductive metal nitride (e.g., TiN).

[0094] The first to fourth conductive films (CL1, CL2, CL3, CL4) may be formed locally within the first interlayer insulating film (140) and between the gate spacers (GSP).

[0095] Referring to FIG. 1 and FIG. 19a to FIG. 19d, an upper film (150) may be formed on the first interlayer insulating film (140) and may cover the uppermost surfaces of the gate spacers (GSP) and the first to fourth conductive films (CL1, CL2, CL3, CL4).

[0096] A second separation hole (200T) may be formed to penetrate the upper film (150) and the first to fourth conductive films (CL1, CL2, CL3, CL4). The second separation hole (200T) may extend in the third direction (D3) between the gate spacers (GSP) and may expose the upper surface (210U) of the lower pattern (210). Forming the second separation hole (200T) may include patterning the upper film (150) and the first to fourth conductive films (CL1, CL2, CL3, CL4) using a dry etching process.

[0097] Referring to FIGS. 1, 20a through 20d, an upper pattern (220) may be formed within the second separation hole (200T). According to some embodiments, forming the upper pattern (220) may include forming an upper insulating film conformally covering the inner surface of the second separation hole (200T) using an atomic layer deposition, physical vapor deposition, and / or chemical vapor deposition method on the upper film (150), and flattening the upper insulating film until the upper surface of the upper film (150) is exposed. The upper pattern (220) may be in contact with the upper surface (210U) of the lower pattern (210). According to some embodiments, the upper pattern (220) may extend in the third direction (D3) and may include an empty region (230) therein. The above empty area (230) may be referred to as a void or a seam, for example. The lower pattern (210) and the upper pattern (220) may be referred to as a separated insulation pattern (200).

[0098] Referring again to FIGS. 1, 2a through 2d, the lower pattern (210) can penetrate the gate insulating film (GI) and come into contact with the upper surface (110U) of the device isolation film (110). The gate insulating film (GI) can be separated by the lower pattern (210) into a first gate insulating pattern (GI1) on the first active pattern (AP1) and the first channel pattern (CH1), and a second gate insulating pattern (GI2) on the second active pattern (AP2) and the second channel pattern (CH2). The second conductive film (CL2), the third conductive film (CL3), and the fourth conductive film (CL4) on the first active pattern (AP1) and the first channel pattern (CH1) may be referred to as the first conductive pattern (CP1), the second conductive pattern (CP2), and the third conductive pattern (CP3), respectively, and the first to third conductive patterns (CP1, CP2, CP3) may be referred to as the first gate electrode (GE1). The first conductive film (CL1), the second conductive film (CL2), and the third conductive film (CL3) on the second active pattern (AP2) and the second channel pattern (CH2) may be referred to as the fourth conductive pattern (CP4), the fifth conductive pattern (CP5), and the sixth conductive pattern (CP6), respectively, and the fourth to sixth conductive patterns (CP4, CP5, CP6) may be referred to as the second gate electrode (GE2). The first gate electrode (GE1) and the second gate electrode (GE2) can be spaced apart from each other in the first direction (D1) with the separation insulation pattern (200) in between, and can be aligned with each other in the first direction (D1).

[0099] A second interlayer insulating film (160) may be formed on the upper film (150) and may cover the uppermost surface of the separated insulating pattern (200). Active contacts (AC) may be formed on each side of the first gate electrode (GE1) and the second gate electrode (GE2). Each of the active contacts (AC) may be connected to a corresponding one of the first and second source / drain patterns (SD1, SD2) by penetrating the second interlayer insulating film (160), the upper film (150), and the first interlayer insulating film (140).

[0100] FIG. 21 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0101] Referring to FIGS. 1 and FIGS. 21, the upper pattern (220) of the separated insulation pattern (200) may be placed on the lower pattern (210), and the lower surface (220L) of the upper pattern (220) may be in contact with the upper surface (210U) of the lower pattern (210). According to some embodiments, the upper pattern (220) may be extended in the third direction (D3) and may include a void area (230) therein. The void area (230) may be referred to as a void or a seam, for example. The side (220S) of the upper pattern (220) may be inclined with respect to the lower surface (220L) of the upper pattern (220).

[0102] Each of the lower pattern (210) and the upper pattern (220) may have a width according to the first direction (D1). According to some embodiments, the width (210W) of the upper surface (210U) of the lower pattern (210) may be greater than the width (220W) of the lower surface (220L) of the upper pattern (220). The width (220W) of the upper pattern (220) according to the first direction (D1) may increase from the bottom to the top.

[0103] FIG. 22 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0104] Referring to FIGS. 1 and FIGS. 22, the lower pattern (210) of the isolation insulation pattern (200) may have a pillar shape extending in the third direction (D3). The lower surface (210L) of the lower pattern (210) may be in contact with the upper surface (110U) of the device isolation film (110), and the upper surface (210U) of the lower pattern (210) may be in contact with the lower surface (220L) of the upper pattern (220). The side surface (210S) of the lower pattern (210) may be inclined with respect to the lower surface (210L) of the lower pattern (210).

[0105] Each of the lower pattern (210) and the upper pattern (220) may have a width according to the first direction (D1). According to some embodiments, the width (210W) of the upper surface (210U) of the lower pattern (210) may be the same as the width (220W) of the lower surface (220L) of the upper pattern (220). The width (220W) of the lower pattern (210) according to the first direction (D1) may decrease from the top to the bottom.

[0106] FIG. 23 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0107] Referring to FIGS. 1 and FIGS. 23, the lower pattern (210) of the isolation insulation pattern (200) may have a pillar shape extending in the third direction (D3). The lower surface (210L) of the lower pattern (210) may contact the upper surface (110U) of the device isolation film (110), and the upper surface (210U) of the lower pattern (210) may contact the lower surface (220L) of the upper pattern (220). Each of the lower pattern (210) and the upper pattern (220) may have a width according to the first direction (D1). According to some embodiments, the width (210W) of the upper surface (210U) of the lower pattern (210) and the width (210W) of the lower surface (210L) of the lower pattern (210) may be smaller than the width (220W) of the lower surface (220L) of the upper pattern (220).

[0108] FIG. 24 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0109] Referring to FIG. 1 and FIG. 24, the lower pattern (210) of the isolation insulation pattern (200) may have a pillar shape extending in the third direction (D3). The lower surface (210L) of the lower pattern (210) may be in contact with the upper surface (110U) of the device isolation film (110), and the upper surface (210U) of the lower pattern (210) may be in contact with the lower surface (220L) of the upper pattern (220). Each of the lower pattern (210) and the upper pattern (220) may have a width according to the first direction (D1). According to some embodiments, the width (210W) of the upper surface (210U) of the lower pattern (210) may be smaller than the width (220W) of the lower surface (220L) of the upper pattern (220). The width (220W) of the lower pattern (210) according to the first direction (D1) can increase from the top to the bottom.

[0110] FIG. 25 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1.For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0111] Referring to FIGS. 1 and FIGS. 25, the lower pattern (210) of the isolation insulation pattern (200) may have a pillar shape extending in the third direction (D3). The lower surface (210L) of the lower pattern (210) may contact the upper surface (110U) of the device isolation film (110), and the upper surface (210U) of the lower pattern (210) may contact the lower surface (220L) of the upper pattern (220). According to some embodiments, the upper surface (210U) of the lower pattern (210) may have a curved shape protruding toward the upper pattern (220). Accordingly, the upper surface (210U) of the lower pattern (210) may contact a part of the lower surface (220L) of the upper pattern (220).

[0112] FIG. 26 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0113] Referring to FIGS. 1 and FIGS. 26, the lower pattern (210) of the separated insulation pattern (200) may have a pillar shape extending in the third direction (D3). The upper surface (210U) of the lower pattern (210) may be in contact with the lower surface (220L) of the upper pattern (220). According to some embodiments, the lower pattern (210) may include an impurity layer (240) adjacent to the upper surface (210U) of the lower pattern (210). The impurity layer (240) may include the same material or the same element as the lower pattern (210). The impurity layer (240) may further include elements different from the lower pattern (210). The thickness (240T) of the impurity layer (240) along the third direction (D3) may be, for example, less than 5 nm.

[0114] FIG. 27 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1.For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0115] Referring to FIG. 1 and FIG. 27, according to some embodiments, the upper pattern (220) of the separated insulation pattern (200) may include at least one first sublayer (222) and at least one second sublayer (224) that are alternately and repeatedly stacked along the third direction (D3) on the upper surface (210U) of the lower pattern (210). The lower surface (220L) of the upper pattern (220) may be in contact with the upper surface (210U) of the lower pattern (210). The lower surface (220L) of the upper pattern (220) may correspond to the lower surface of the lowest first sublayer (222) among the plurality of first sublayers (222).

[0116] Each of the first sublayer (222) and the second sublayer (224) may have a thickness according to the third direction (D3). The thickness (222T) of the first sublayer (222) may be greater than the thickness (224T) of the second sublayer (224). The thickness (224T) of the second sublayer (224) may be, for example, less than 5 nm.

[0117] The first sublayer (222) may be formed using a filling process with a fluid insulating material, and the second sublayer (224) may be formed by performing a surface treatment process on the upper surface of the first sublayer (222). The first sublayer (222) may include, for example, at least one of SiCN, SiN, and SiCON, and the second sublayer (224) may include, for example, at least one of SiN, SiON, SiCO, SiCON, SiO2, and SiCOH.

[0118] FIG. 28 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1.For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0119] Referring to FIGS. 1 and FIGS. 28, according to some embodiments, the upper pattern (220) of the separated insulation pattern (200) may include at least one first sublayer (222) and at least one second sublayer (224) alternately and repeatedly stacked along the third direction (D3) on the upper surface (210U) of the lower pattern (210), and an inter-mixing layer (226) between the first sublayer (222) and the second sublayer (224). The first sublayer (222) and the second sublayer (224) are each identical to the first sublayer (222) and the second sublayer (224) described with reference to FIGS. 1 and FIGS. 27.

[0120] Each of the first sublayer (222), the second sublayer (224), and the mixed layer (226) may have a thickness according to the third direction (D3). The thickness (222T) of the first sublayer (222) may be greater than the thickness (224T) of the second sublayer (224) and the thickness (226T) of the mixed layer (226). The thickness (224T) of the second sublayer (224) may be, for example, less than 5 nm, and the thickness (226T) of the mixed layer (226) may be, for example, less than 5 nm. The mixed layer (226) may contain the same material or the same element as the first sublayer (222) and the second sublayer (224).

[0121] FIG. 29 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0122] Referring to FIG. 1 and FIG. 29, according to some embodiments, the upper surface (110U) of the device isolation film (110) may be recessed toward the interior of the device isolation film (110). The lower surface (210L) of the lower pattern (210) may come into contact with the recessed upper surface (110U) of the device isolation film (110), and accordingly, the lower surface (210L) of the lower pattern (210) may include a convex curved surface toward the interior of the device isolation film (110).

[0123] FIG. 30 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0124] Referring to FIG. 1 and FIG. 30, according to some embodiments, the first channel pattern (CH1) may be the upper portion of the first active pattern (AP1) protruding from the first active pattern (AP1). The device isolation layer (110) may be disposed on both sides of the first active pattern (AP1) and may expose the first channel pattern (CH1). The first gate electrode (GE1) may cover the upper and side surfaces of the first channel pattern (CH1) and may extend in the first direction (D1) and extend onto the device isolation layer (110). The first gate insulation pattern (GI1) may be interposed between the first channel pattern (CH1) and the first gate electrode (GE1) and may extend between the device isolation layer (110) and the first gate electrode (GE1). The first gate electrode (GE1), the first channel pattern (CH1), and the first source / drain patterns (SD1) can form a Fin Field Effect Transistor (FINFET).

[0125] The second channel pattern (CH2) may be the upper portion of the second active pattern (AP2) protruding from the second active pattern (AP2). The device isolation layer (110) may be placed on both sides of the second active pattern (AP2) and may expose the second channel pattern (CH2). The second gate electrode (GE2) may cover the upper and side surfaces of the second channel pattern (CH2) and may extend in the first direction (D1) and extend onto the device isolation layer (110). The second gate insulation pattern (GI2) may be interposed between the second channel pattern (CH2) and the second gate electrode (GE2) and may extend between the device isolation layer (110) and the second gate electrode (GE2). The second gate electrode (GE2), the second channel pattern (CH2), and the second source / drain patterns (SD2) can form a Fin Field Effect Transistor (FINFET).

[0126] FIG. 31 is a drawing showing a semiconductor device according to some embodiments of the present invention, and is a cross-sectional view corresponding to A-A' of FIG. 1. For the sake of simplicity, the differences from the semiconductor device described with reference to FIGS. 1 and FIGS. 2a to 2d will be mainly explained.

[0127] Referring to FIG. 1 and FIG. 31, according to some embodiments, a first channel separation pattern (300) may extend in the third direction (D3) and penetrate the first active pattern (AP1) and the first channel pattern (CH1). The first active pattern (AP1) may be separated into a pair of first active patterns (AP1) by the first channel separation pattern (300), and the first channel pattern (CH1) may be separated into a pair of first channel patterns (CH1) by the first channel separation pattern (300). Each of the pair of first channel patterns (CH1) may include the first semiconductor patterns (SP1) spaced apart from each other in the third direction (D3).

[0128] A pair of first gate electrodes (GE1) may each be disposed on a pair of first channel patterns (CH1). The pair of first gate electrodes (GE1) may comprise different materials. A first gate separation pattern (310) may be disposed on the first channel separation pattern (300) and may be interposed between the pair of first gate electrodes (GE1). First source / drain patterns may be disposed on each side of the pair of first gate electrodes (GE1) and may be connected to each of the pair of first channel patterns (CH1). The pair of first gate electrodes (GE1), the pair of first channel patterns (CH1), and the first source / drain patterns may constitute a field-effect transistor having a forksheet structure.

[0129] The second channel separation pattern (320) may extend in the third direction (D3) and penetrate the second active pattern (AP2) and the second channel pattern (CH2). The second active pattern (AP2) may be separated into a pair of second active patterns (AP2) by the second channel separation pattern (320), and the second channel pattern (CH2) may be separated into a pair of second channel patterns (CH2) by the second channel separation pattern (320). Each of the pair of second channel patterns (CH2) may include the second semiconductor patterns (SP2) spaced apart from each other in the third direction (D3).

[0130] A pair of second gate electrodes (GE2) may be disposed on each of the pair of second channel patterns (CH2). The pair of second gate electrodes (GE2) may comprise different materials. A second gate separation pattern (330) may be disposed on the second channel separation pattern (320) and may be interposed between the pair of second gate electrodes (GE2). Second source / drain patterns may be disposed on each side of the pair of second gate electrodes (GE2) and may be connected to each of the pair of second channel patterns (CH2). The pair of second gate electrodes (GE2), the pair of second channel patterns (CH2), and the second source / drain patterns may constitute a field-effect transistor having a forksheet structure.

[0131] The above separation insulation pattern (200) may be disposed between the pair of first gate electrodes (GE1) and the pair of second gate electrodes (GE2), and on the device isolation film (110). The above separation insulation pattern (200) may be interposed between one of the pair of first gate electrodes (GE1) and one of the pair of second gate electrodes (GE2). The pair of second gate electrodes (GE2) may be separated (or separated) from the pair of first gate electrodes (GE1) by the above separation insulation pattern (200).

[0132] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A semiconductor device comprising: a first channel pattern and a second channel pattern spaced apart from each other in a first direction on a substrate; a first gate electrode on the first channel pattern and extending in the first direction; a second gate electrode on the second channel pattern and extending in the first direction; and a separation insulation pattern between the first gate electrode and the second gate electrode, wherein the first gate electrode and the second gate electrode are aligned with each other in the first direction, and the separation insulation pattern comprises a lower pattern and an upper pattern stacked in a vertical direction perpendicular to the upper surface of the substrate, and the interface between the lower pattern and the upper pattern is located at a height lower than the uppermost surface of the first channel pattern and the uppermost surface of the second channel pattern. Claim 2 A semiconductor device according to claim 1, wherein the lower pattern has a pillar shape extending in the vertical direction. Claim 3 A semiconductor device according to claim 2, wherein the upper pattern covers the side of the first gate electrode, the upper surface of the lower pattern and the side of the second gate electrode, and includes an empty region therein. Claim 4 A semiconductor device according to claim 3, wherein the upper surface of the lower pattern contacts the lower surface of the upper pattern, and each of the lower pattern and the upper pattern has a width according to the first direction, and the width of the upper surface of the lower pattern is the same as the width of the lower surface of the upper pattern. Claim 5 A semiconductor device according to claim 4, wherein the lower pattern has a width that decreases from the top to the bottom. Claim 6 A semiconductor device according to claim 3, wherein the upper surface of the lower pattern contacts the lower surface of the upper pattern, and each of the lower pattern and the upper pattern has a width along the first direction, and the width of the upper surface of the lower pattern is smaller than the width of the lower surface of the upper pattern. Claim 7 A semiconductor device according to claim 6, wherein the lower pattern has a width that increases from the upper part to the lower part. Claim 8 A semiconductor device according to claim 3, wherein the upper surface of the lower pattern contacts the lower surface of the upper pattern, and each of the lower pattern and the upper pattern has a width along the first direction, and the width of the upper surface of the lower pattern is greater than the width of the lower surface of the upper pattern. Claim 9 A semiconductor device according to claim 2, wherein the upper pattern comprises a first sublayer and a second sublayer stacked in the vertical direction on the upper surface of the lower pattern, each of the first sublayer and the second sublayer having a thickness along the vertical direction, and the thickness of the second sublayer is smaller than the thickness of the first sublayer. Claim 10 A semiconductor device comprising: a first active pattern and a second active pattern spaced apart from each other in a first direction and extending in a second direction on a substrate, wherein the first direction and the second direction are parallel to and intersect each other on the upper surface of the substrate; a device isolation layer between the first active pattern and the second active pattern; a first channel pattern on the first active pattern; a second channel pattern on the second active pattern; a first gate electrode extending in the first direction and crossing the first active pattern and the first channel pattern; a second gate electrode extending in the first direction and crossing the second active pattern and the second channel pattern; and a separation insulation pattern interposed between the first gate electrode and the second gate electrode and disposed on the device isolation layer, wherein the first gate electrode and the second gate electrode are aligned with each other in the first direction, and the separation insulation pattern includes a lower pattern and an upper pattern stacked in a third direction perpendicular to the upper surface of the substrate, and the upper surface of the lower pattern is located at a height lower than the upper surface of the first channel pattern and the upper surface of the second channel pattern.

Images