Integrated circuit device

Abstract

An integrated circuit element comprises a fin-shaped active region extending in a first horizontal direction, a nanosheet stack comprising a plurality of nanosheets facing the fin surface at a position spaced vertically from the fin surface of the fin-shaped active region, a device isolation layer covering the sidewalls of the fin-shaped active region, and a gate line extending in a second horizontal direction intersecting the first horizontal direction over the fin-shaped active region and the device isolation layer, and including a work function metal-containing structure surrounding the plurality of nanosheets, wherein the first thickness in the vertical direction of the portion of the work function metal-containing structure covering the upper surface of the nanosheet stack is greater than the second thickness in the second horizontal direction of the portion covering the sidewalls of the nanosheet stack.

Description

Technology Field

[0001] The technical concept of the present invention relates to an integrated circuit device, and in particular to an integrated circuit device equipped with a field-effect transistor. Background Technology

[0002] Due to advancements in electronic technology, the downscaling of integrated circuit devices is progressing rapidly. Since highly downscaled integrated circuit devices require not only fast operating speeds but also operational accuracy, there is a need to develop manufacturing methods for integrated circuit devices that possess a stable structure within a relatively small area and can improve the performance and reliability of field-effect transistors. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide an integrated circuit device having a stable structure and capable of improving the performance and reliability of a field-effect transistor in an integrated circuit device having a transistor region with a reduced area due to downscaling. means of solving the problem

[0004] An integrated circuit device according to one embodiment of the technical concept of the present invention comprises: a fin-shaped active region extending in a first horizontal direction; a nanosheet stack comprising a plurality of nanosheets facing the fin-shaped upper surface at a position spaced vertically from the fin-shaped active region; a device isolation film covering the sidewalls of the fin-shaped active region; and a gate line extending in a second horizontal direction intersecting the first horizontal direction over the fin-shaped active region and the device isolation film, and comprising a work function metal-containing structure surrounding the plurality of nanosheets, wherein the first thickness in the vertical direction of the portion of the work function metal-containing structure covering the upper surface of the nanosheet stack is greater than the second thickness in the second horizontal direction of the portion covering the sidewalls of the nanosheet stack.

[0005] An integrated circuit device according to another embodiment of the technical concept of the present invention comprises: a first fin-shaped active region extending in a first horizontal direction in a first transistor region; a second fin-shaped active region extending in the first horizontal direction in a second transistor region; a first nanosheet stack comprising a plurality of first region nanosheets facing the first fin upper surface at a position spaced vertically from the first fin upper surface of the first fin-shaped active region; a second nanosheet stack comprising a plurality of second region nanosheets facing the second fin upper surface at a position spaced vertically from the second fin upper surface of the second fin-shaped active region; and a gate line extending in a second horizontal direction that encloses the plurality of first region nanosheets and the plurality of second region nanosheets and intersects the first horizontal direction, wherein the gate line comprises a first conductivity type blanket work function metal-containing layer enclosing the plurality of first region nanosheets and a second conductivity type work function metal-containing structure enclosing the plurality of second region nanosheets, and among the work function metal-containing structure, the second nanosheet The first thickness in the vertical direction of the portion covering the upper surface of the stack is greater than the second thickness in the second horizontal direction of the portion covering the side wall of the second nanosheet stack.

[0006] An integrated circuit device according to another embodiment of the technical concept of the present invention comprises: a first fin-shaped active region extending in a first horizontal direction in an NMOS transistor region; a second fin-shaped active region extending in the first horizontal direction in a PMOS transistor region; a device isolation film covering both sidewalls of the first fin-shaped active region and the second fin-shaped active region in a second horizontal direction intersecting the first horizontal direction; a first nanosheet stack comprising a plurality of first region nanosheets facing the first fin surface at a position spaced vertically from the first fin surface of the first fin-shaped active region; a second nanosheet stack comprising a plurality of second region nanosheets facing the second fin surface at a position spaced vertically from the second fin surface of the second fin-shaped active region; and a gate line extending in the second horizontal direction over the first fin-shaped active region, the second fin-shaped active region, and the device isolation film, wherein the gate line comprises a P-type work function metal-containing structure surrounding the plurality of second region nanosheets and the plurality The N-type blanket work function metal-containing layer comprises a portion surrounding a first region nanosheet and a portion surrounding a plurality of second region nanosheets and a P-type work function metal-containing structure, wherein the first thickness in the vertical direction of the portion covering the upper surface of the second nanosheet stack among the P-type work function metal-containing structures is greater than the second thickness in the second horizontal direction of the portion covering the sidewall of the second nanosheet stack, and both sidewalls in the second horizontal direction of the P-type work function metal-containing structures are each formed with an uneven surface.

[0007] A method for manufacturing an integrated circuit device according to one embodiment of the technical concept of the present invention comprises the steps of: forming a fin-shaped active region extending in a first horizontal direction on a substrate; forming a device isolation film covering the sidewalls of the fin-shaped active region; forming a nanosheet stack comprising a plurality of nanosheets facing the fin surface at a position spaced vertically from the fin surface of the fin-shaped active region; and forming a gate line extending in a second horizontal direction intersecting the first horizontal direction and surrounding the plurality of nanosheets on the fin-shaped active region and the device isolation film. The step of forming the gate line may include forming a work function metal-containing structure having a structure in which the first thickness in the vertical direction of the portion covering the upper surface of the nanosheet stack is greater than the second thickness in the second horizontal direction of the portion covering the sidewalls of the nanosheet stack.

[0008] In exemplary embodiments, the step of forming the work function metal-containing structure may include the step of forming an uneven surface on both side walls of the work function metal-containing structure in the second horizontal direction.

[0009] In other exemplary embodiments, the step of forming the work function metal-containing structure comprises the step of forming a plurality of work function metal-containing patterns arranged in a row along the vertical direction, each disposed between each of the plurality of nanosheets; the step of forming a work function metal-containing liner covering the plurality of nanosheets and the plurality of work function metal-containing patterns; and the step of forming an upper work function metal-containing block covering the upper surface of the work function metal-containing liner, wherein in the step of forming the upper work function metal-containing block, the thickness of the upper work function metal-containing block in the vertical direction may be greater than the thickness of each of the plurality of work function metal-containing patterns in the vertical direction.

[0010] In other exemplary embodiments, in the step of forming the plurality of work function metal-containing patterns, the width of each of the plurality of work function metal-containing patterns in the second horizontal direction may be equal to or smaller than the width of each of the plurality of nanosheets.

[0011] In other exemplary embodiments, the step of forming the work function metal-containing liner comprises the step of forming a vertical extension of the work function metal-containing liner covering the sidewalls of each of the plurality of nanosheets and the plurality of work function metal-containing patterns, and the step of including a horizontal extension of the work function metal-containing liner overlapping the device isolation layer in the vertical direction, and the step of forming the work function metal-containing structure further comprises the step of forming a lower work function metal-containing block covering the horizontal extension of the work function metal-containing liner at a position overlapping the device isolation layer in the vertical direction, and the thickness of the lower work function metal-containing block in the vertical direction may be smaller than the thickness of the upper work function metal-containing block.

[0012] In other exemplary embodiments, in the step of forming the work function metal-containing structure, the first thickness of the work function metal-containing structure may be greater than the third thickness in the vertical direction of the portion of the work function metal-containing structure that covers the device isolation film.

[0013] In other exemplary embodiments, after the step of forming the nanosheet stack and before the step of forming the gate line, the method further comprises the step of forming a gate dielectric film covering the plurality of nanosheets, and the step of forming the work function metal-containing structure may include the step of forming a plurality of work function metal-containing patterns disposed one by one between each of the plurality of nanosheets, aligned in a row along the vertical direction, and in contact with the gate dielectric film; the step of forming a work function metal-containing liner covering the plurality of nanosheets and the plurality of work function metal-containing patterns and in contact with the gate dielectric film; and the step of forming an upper work function metal-containing block covering the upper surface of the work function metal-containing liner and spaced apart from the gate dielectric film in the vertical direction with the work function metal-containing liner in between.

[0014] In other exemplary embodiments, the step of forming the gate line further includes the step of forming a blanket work function metal-containing layer that wraps the work function metal-containing structure over the fin-shaped active region, and the blanket work function metal-containing layer may have a conductivity type different from that of the work function metal-containing structure.

[0015] In other exemplary embodiments, the step of forming the work function metal-containing structure includes the step of forming an uneven surface on both side walls of the work function metal-containing structure in the second horizontal direction, and the step of forming the blanket work function metal-containing layer may include the step of forming a plurality of protrusions that are in contact with the uneven surface and protrude toward the region between each of the plurality of nanosheets in the second horizontal direction.

[0016] A method for manufacturing an integrated circuit device according to another embodiment of the technical concept of the present invention comprises the steps of: forming a first fin-shaped active region disposed on a first transistor region on a substrate and extending in a first horizontal direction, and a second fin-shaped active region disposed on a second transistor region on the substrate and extending in the first horizontal direction; forming a first nanosheet stack disposed on a first fin upper surface of the first fin-shaped active region and comprising a plurality of first region nanosheets, and forming a second nanosheet stack disposed on a second fin upper surface of the second fin-shaped active region and comprising a plurality of second region nanosheets; and forming a gate line that surrounds the plurality of first region nanosheets and the plurality of second region nanosheets and extends in a second horizontal direction intersecting the first horizontal direction, wherein the step of forming the gate line comprises the step of forming a work function metal-containing structure in which the first thickness in the vertical direction of the portion covering the upper surface of the second nanosheet stack in the second transistor region is greater than the second thickness in the second horizontal direction of the portion covering the sidewall of the second nanosheet stack, and the plurality of first regions in the first transistor region The method includes the step of forming a blanket work function metal-containing layer that encloses a nanosheet and encloses a plurality of second region nanosheets and a work function metal-containing structure in the second transistor region, wherein the blanket work function metal-containing layer is composed of a first conductivity type metal-containing film and the work function metal-containing structure may be composed of a second conductivity type metal-containing film.

[0017] In exemplary embodiments, the step of forming the work function metal-containing structure may include the step of forming an uneven surface on both side walls in the second horizontal direction of the work function metal-containing structure.

[0018] In other exemplary embodiments, the step of forming the blanket work function metal-containing layer may include the step of forming a plurality of protrusions facing the uneven surface on the blanket work function metal-containing layer.

[0019] In other exemplary embodiments, the step of forming the work function metal-containing structure comprises: forming a plurality of work function metal-containing patterns arranged in a row along the vertical direction, each disposed between each of the plurality of second region nanosheets; forming a work function metal-containing liner covering the plurality of second region nanosheets and the plurality of work function metal-containing patterns; and forming an upper work function metal-containing block covering the upper surface of the work function metal-containing liner in the second transistor region, wherein in the step of forming the upper work function metal-containing block, the thickness of the upper work function metal-containing block in the vertical direction may be greater than the thickness of each of the plurality of work function metal-containing patterns in the vertical direction.

[0020] In other exemplary embodiments, in the step of forming the plurality of work function metal-containing patterns, the width of each of the plurality of work function metal-containing patterns in the second horizontal direction may be equal to or smaller than the width of each of the plurality of second region nanosheets.

[0021] In other exemplary embodiments, in the step of forming the plurality of work function metal-containing patterns, the width of each of the plurality of work function metal-containing patterns in the second horizontal direction may be equal to or greater than the width of each of the plurality of second region nanosheets.

[0022] In other exemplary embodiments, after the step of forming the first pin-shaped active region and the second pin-shaped active region, the method further comprises the step of forming a device isolation film covering the sidewalls of each of the first pin-shaped active region and the second pin-shaped active region, and the step of forming the work function metal-containing liner includes the step of forming a vertical extension of the work function metal-containing liner covering the sidewalls of each of the plurality of second region nanosheets and a horizontal extension of the work function metal-containing liner overlapping with the device isolation film in the vertical direction, and the step of forming the work function metal-containing structure further comprises the step of forming a lower work function metal-containing block spaced apart from the upper work function metal-containing block, covering the horizontal extension of the work function metal-containing liner at a position overlapping with the device isolation film in the vertical direction when forming the upper work function metal-containing block, and in the vertical direction, the thickness of the lower work function metal-containing block may be smaller than the thickness of the upper work function metal-containing block.

[0023] In other exemplary embodiments, after the step of forming the first pin-shaped active region and the second pin-shaped active region, the method further comprises the step of forming a device isolation film covering the sidewalls of each of the first pin-shaped active region and the second pin-shaped active region, and in the step of forming the work function metal-containing structure, the first thickness of the work function metal-containing structure may be greater than the third thickness in the vertical direction of the portion of the work function metal-containing structure covering the device isolation film.

[0024] In other exemplary embodiments, the step of forming the gate line further includes the step of forming a gap-fill metal film covering the blanket work function metal-containing layer in the first transistor region and the second transistor region, and the gap-fill metal film in the second transistor region may be spaced apart from the work function metal-containing structure with the blanket work function metal-containing layer in between.

[0025] A method for manufacturing an integrated circuit device according to another embodiment of the technical concept of the present invention comprises the steps of: forming a first fin-shaped active region disposed in a first transistor region on a substrate and extending in a first horizontal direction, and a second fin-shaped active region disposed in a second transistor region on the substrate and extending in the first horizontal direction; forming a device isolation film covering the sidewalls of each of the first fin-shaped active region and the second fin-shaped active region; forming a first nanosheet stack disposed on the first fin upper surface of the first fin-shaped active region and comprising a plurality of first region nanosheets, and forming a second nanosheet stack disposed on the second fin upper surface of the second fin-shaped active region and comprising a plurality of second region nanosheets; and forming a gate line that surrounds the plurality of first region nanosheets and the plurality of second region nanosheets and extends in a second horizontal direction intersecting the first horizontal direction on the first fin-shaped active region, the second fin-shaped active region, and the device isolation film, wherein the step of forming the gate line comprises a portion covering the upper surface of the second nanosheet stack in the second transistor region. The method comprises the steps of: forming a work function metal-containing structure having a first thickness in the vertical direction that is greater than the second thickness in the second horizontal direction of the portion covering the sidewall of the second nanosheet stack, and having an uneven surface on both sidewalls in the second horizontal direction; and forming a blanket work function metal-containing layer that encloses the plurality of first region nanosheets in the first transistor region and encloses the plurality of second region nanosheets and the work function metal-containing structure in the second transistor region, wherein the step of forming the work function metal-containing structure comprises the step of forming a plurality of work function metal-containing patterns arranged one by one between each of the plurality of second region nanosheets and aligned in a row along the vertical direction.The method may include the steps of forming a work function metal-containing liner covering the plurality of second region nanosheets and the plurality of work function metal-containing patterns, forming an upper work function metal-containing block covering the uppermost surface of the work function metal-containing liner in the second transistor region, and forming a lower work function metal-containing block spaced apart from the upper work function metal-containing block and having a thickness smaller than that of the upper work function metal-containing block in the vertical direction.

[0026] In exemplary embodiments, the step of forming the blanket work function metal-containing layer may include the step of forming a plurality of protrusions facing the uneven surface on the blanket work function metal-containing layer. Effects of the invention

[0027] According to an integrated circuit device based on the technical concept of the present invention, even if the areas of a first transistor region and a second transistor region having different channel types are reduced and the separation distance between the first transistor region and the second transistor region is narrowed due to down-scaling of the integrated circuit device, different electrical characteristics required in each of the first transistor region and the second transistor region can be stably secured according to various arrangement structures in the integrated circuit device, and the performance and reliability of each of the first transistor region and the second transistor region can be secured. In addition, the possibility of process defects occurring during the manufacturing process of the integrated circuit device can be eliminated. Brief explanation of the drawing

[0028] FIG. 1 is a planar layout diagram for explaining an integrated circuit element according to embodiments of the technical concept of the present invention. Figure 2 is a cross-sectional view along the line X1 - X1' of Figure 1. Figure 3 is a cross-sectional view along the Y1 - Y1' line of Figure 1. Figure 4 is a cross-sectional view showing an enlarged view of the part labeled "EX1" in Figure 3. FIGS. 5 and FIGS. 6 are cross-sectional views illustrating integrated circuit elements according to other embodiments of the technical concept of the present invention. FIGS. 7 and 8 are cross-sectional views illustrating an integrated circuit element according to other embodiments of the technical concept of the present invention. FIGS. 9a to 15b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention, where FIGS. 9a, FIGS. 11a, FIGS. 12a, FIGS. 13a, FIGS. 14a, and FIGS. 15a are cross-sectional views showing an exemplary cross-sectional structure in the order of process of a portion corresponding to the cross-section along the X1 - X1' line of FIG. 1, and FIGS. 9b, FIGS. 10, FIGS. 11b, FIGS. 12b, FIGS. 13b, FIGS. 14b, and FIGS. 15b are cross-sectional views showing an exemplary cross-sectional structure in the order of process of a portion corresponding to the cross-section along the Y1 - Y1' line of FIG. 1. FIGS. 16a to 16q are cross-sectional views illustrating an enlarged cross-sectional configuration according to the process sequence in the part corresponding to “EX1A” in FIG. 14b, in order to explain in more detail the method of manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. Specific details for implementing the invention

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0030] FIG. 1 is a planar layout diagram for explaining an integrated circuit element (100) according to embodiments of the technical concept of the present invention. FIG. 2 is a cross-sectional view along the line X1 - X1' of FIG. 1. FIG. 3 is a cross-sectional view along the line Y1 - Y1' of FIG. 1. FIG. 4 is an enlarged cross-sectional view of the portion labeled "EX1" in FIG. 3. With reference to FIG. 1 to 4, an integrated circuit element (100) comprising a field-effect transistor having a gate-all-around (GAA) structure including an active region in the shape of a nanowire or nanosheet and a gate surrounding the active region will be described.

[0031] Referring to FIGS. 1 to 4, an integrated circuit element (100) may include a plurality of pin-shaped active regions (F1) that extend parallel to each other along a first horizontal direction (X direction). A plurality of gate lines (160) may extend over the plurality of pin-shaped active regions (F1) in a second horizontal direction (Y direction) that intersects the first horizontal direction (X direction). The first horizontal direction (X direction) and the second horizontal direction (Y direction) may be mutually orthogonal directions. The integrated circuit element (100) may include a plurality of transistors disposed at the intersection points where the plurality of gate lines (160) and the plurality of pin-shaped active regions (F1) intersect. The plurality of transistors may be field-effect transistors having a gate-all-around structure. The plurality of transistors may include a plurality of NMOS transistors (NTR) and a plurality of PMOS transistors (PTR). In the integrated circuit element (100), the region where the NMOS transistor (NTR) is placed is referred to as the first transistor region (TA1), and the region where the PMOS transistor (PTR) is placed can be referred to as the second transistor region (TA2).

[0032] A plurality of pin-shaped active regions (F1) may each have a pin top surface (FF). A plurality of pin-shaped active regions (F1) may each be made of silicon (Si). A plurality of nanosheet stacks (NSS) may be disposed on the pin top surface (FF) of each of the plurality of pin-shaped active regions (F1). A plurality of nanosheet stacks (NSS) may face the pin top surface (FF) at a position spaced apart in a vertical direction (Z direction) from the pin top surface (FF) of each of the plurality of pin-shaped active regions (F1). A plurality of nanosheet stacks (NSS) may each include at least one nanosheet. As used herein, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. It should be understood that the nanosheet includes nanowires.

[0033] In the present example, a configuration in which a plurality of nanosheet stacks (NSS) each include a first nanosheet (N1), a second nanosheet (N2), and a third nanosheet (N3) is illustrated, but the number of nanosheets included in each of the plurality of nanosheet stacks (NSS) can be varied. For example, each of the plurality of nanosheet stacks (NSS) may include at least one or at least two nanosheets, and the number of nanosheets constituting the nanosheet stacks (NSS) is not particularly limited. The first to third nanosheets (N1, N2, N3) may each have a channel region. In exemplary embodiments, the first to third nanosheets (N1, N2, N3) included in the nanosheet stacks (NSS) may each be composed of a Si layer, a SiGe film, or a combination thereof. In exemplary embodiments, the first to third nanosheets (N1, N2, N3) may each have a vertical thickness selected within the range of about 4 nm to about 6 nm. In exemplary embodiments, the first to third nanosheets (N1, N2, N3) may have substantially the same thickness. The first to third nanosheets (N1, N2, N3) may be made of the same material.

[0034] In this specification, a nanosheet stack (NSS) disposed in a first transistor region (TA1) is referred to as the first nanosheet stack, and the first to third nanosheets (N1, N2, N3) included in the nanosheet stack (NSS) in the first transistor region (TA1) may each be referred to as the first region nanosheet. Additionally, in this specification, a nanosheet stack (NSS) disposed in a second transistor region (TA2) is referred to as the second nanosheet stack, and the first to third nanosheets (N1, N2, N3) included in the nanosheet stack (NSS) in the second transistor region (TA2) may each be referred to as the second region nanosheet.

[0035] As illustrated in FIGS. 3 and 4, both sidewalls in the second horizontal direction (Y direction) of each of the plurality of pin-shaped active regions (F1) may be covered with a device isolation film (112). The device isolation film (112) may include portions that overlap with the gate line (160) in the vertical direction (Z direction). The device isolation film (112) may be made of a silicon oxide film, but is not limited thereto. As illustrated in FIGS. 3 and 4, at least one gate line (160) selected from the plurality of gate lines (160) may extend in the second horizontal direction (Y direction) over the plurality of pin-shaped active regions (F1) and the device isolation film (112) across the first transistor region (TA1) and the second transistor region (TA2). In the present specification, among the plurality of pin-type active regions (F1), the pin-type active region (F1) disposed in the first transistor region (TA1) is referred to as the first pin-type active region, and among the plurality of pin-type active regions (F1), the pin-type active region (F1) disposed in the second transistor region (TA2) may be referred to as the second pin-type active region. Each of the plurality of gate lines (160) may wrap the first to third nanosheets (N1, N2, N3) included in the nanosheet stack (NSS) that overlap in the vertical direction (Z direction).

[0036] Each of the multiple gate lines (160) may be composed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the materials constituting the multiple gate lines (160) are not limited to those exemplified above.

[0037] In exemplary embodiments, at least one gate line (160) selected from a plurality of gate lines (160) may include a first conductivity type work function metal-containing structure disposed in a first transistor region (TA1) and a second conductivity type work function metal-containing structure disposed in a second transistor region (TA2). If the first transistor region (TA1) is an NMOS transistor region, the first conductivity type work function metal-containing structure may be an N-type work function metal-containing structure, and if the second transistor region (TA2) is a PMOS transistor region, the second conductivity type work function metal-containing structure may be a P-type work function metal-containing structure. In exemplary embodiments, the N-type work function metal-containing structure may include a TiAlC film, and the P-type work function metal-containing structure may include a TiN film, a WN film, or a MoN film.

[0038] As illustrated in FIGS. 3 and 4, at least one gate line (160) selected from a plurality of gate lines (160) may include a blanket work function metal-containing layer (164) that encloses first to third nanosheets (N1, N2, N3) in a first transistor region (TA1), and a work function metal-containing structure (162) that encloses first to third nanosheets (N1, N2, N3) in a second transistor region (TA2). The blanket work function metal-containing layer (164) may form an N-type work function metal-containing structure, and the work function metal-containing structure (162) may form a P-type work function metal-containing structure. The blanket work function metal-containing layer (164) may include a first region portion that encloses the first to third nanosheets (N1, N2, N3) in the first transistor region (TA1), and a second region portion that encloses the first to third nanosheets (N1, N2, N3) and the work function metal-containing structure (162) in the second transistor region (TA2). The first region portion and the second region portion of the blanket work function metal-containing layer (164) may be continuously connected to form a single unit.

[0039] As illustrated in more detail in FIG. 4, the first thickness (TH11) in the vertical direction (Z direction) of the portion covering the upper surface of the nanosheet stack (NSS) in the work function metal-containing structure (162) in the second transistor region (TA2) (i.e., the upper surface of the third nanosheet stack (N3) of the uppermost layer among the first to third nanosheets (N1, N2, N3)) may be greater than the second thickness (TH12) in the second horizontal direction (Y direction) of the portion covering the sidewalls of the nanosheet stack (NSS) (i.e., the sidewalls of each of the first to third nanosheets (N1, N2, N3)). For example, the first thickness (TH11) may be about 3 to about 20 times greater than the second thickness (TH12), but is not limited thereto.

[0040] As illustrated in FIG. 4, the work function metal-containing structure (162) may include a plurality of work function metal-containing patterns (162A), a work function metal-containing liner (162B), and a plurality of work function metal-containing blocks (162C1, 162C2).

[0041] A plurality of work function metal-containing patterns (162A) are arranged one by one between each of the first to third nanosheets (N1, N2, N3) and between the pin-shaped active region (F1) and the first nanosheet (N1), and can be aligned in a row along the vertical direction (Z direction). Each of the plurality of work function metal-containing patterns (162A) can be in contact with at least one of the first to third nanosheets (N1, N2, N3). In the second horizontal direction (Y direction), the first to third nanosheets (N1, N2, N3) have a first width (W11), and the second width (W12) of each of the plurality of work function metal-containing patterns (162A) may be equal to or smaller than the first width (W11).

[0042] The work function metal-containing liner (162B) can conformally cover the first to third nanosheets (N1, N2, N3) and a plurality of work function metal-containing patterns (162A). The work function metal-containing liner (162B) can be in contact with each of the plurality of work function metal-containing patterns (162A). The work function metal-containing liner (162B) may include a vertical extension (162B1) and a horizontal extension (162B1) integrally connected to the vertical extension (162B1) and arranged to overlap the device isolation film (112) in a vertical direction (Z direction). The vertical extension (162B1) of the work function metal-containing liner (162B) covers the sidewalls of each of the first to third nanosheets (N1, N2, N3) surrounded by the work function metal-containing structure (162) and the sidewalls of each of the plurality of work function metal-containing patterns (162A), and can be extended in a zigzag manner along the vertical direction (Z direction).

[0043] A plurality of work function metal-containing blocks (162C1, 162C2) may include an upper work function metal-containing block (162C1) and a lower work function metal-containing block (162C2) that are spaced apart from each other. The upper work function metal-containing block (162C1) may cover the upper surface of the work function metal-containing liner (162B) at a position that overlaps in the vertical direction (Z direction) with the first to third nanosheets (N1, N2, N3) surrounded by the work function metal-containing structure (162). The lower work function metal-containing block (162C2) may cover the horizontal extension (162B1) of the work function metal-containing liner (162B) at a position that overlaps in the vertical direction (Z direction) with the device isolation film (112). The upper work function metal-containing block (162C1) and the lower work function metal-containing block (162C2) may each be in contact with the work function metal-containing liner (162B). The thickness of the upper work function metal-containing block (162C1) in the vertical direction (Z direction) may be greater than the thickness of each of the plurality of work function metal-containing patterns (162A) in the vertical direction (Z direction). The thickness of the lower work function metal-containing block (162C2) in the vertical direction (Z direction) may be smaller than the thickness of the upper work function metal-containing block (162C1) in the vertical direction (Z direction).

[0044] Among the work function metal-containing structure (162) formed by a combination of a plurality of work function metal-containing patterns (162A), a work function metal-containing liner (162B), and a plurality of work function metal-containing blocks (162C1, 162C2), both side walls in the second horizontal direction (Y direction) may each be formed of an uneven surface. As illustrated in FIGS. 3 and 4, at least one of the pair of uneven surfaces forming both side walls in the second horizontal direction (Y direction) of the work function metal-containing structure (162) may face a nanosheet stack (NSS) placed in the first transistor region (TA1) in the second horizontal direction (Y direction). The surfaces (which may be referred to as first surfaces) covering the first to third nanosheets (N1, N2, N3) surrounded by the work function metal-containing structure (162) in the pair of uneven surfaces included in the work function metal-containing structure (162) may be formed as convex surfaces protruding toward the nanosheet stack (NSS) placed in the first transistor region (TA1). The surfaces (which may be referred to as second surfaces) covering the region between each of the first to third nanosheets (N1, N2, N3) surrounded by the work function metal-containing structure (162) in the pair of uneven surfaces included in the work function metal-containing structure (162) and the region between the fin-shaped active region (F1) and the first nanosheet (N1) may be formed as concave surfaces concave toward the nanosheet stack (NSS) placed in the first transistor region (TA1).

[0045] In the second transistor region (TA2), the first thickness (TH11) in the vertical direction (Z direction) of the portion covering the upper surface of the nanosheet stack (NSS) in the work function metal-containing structure (162) may be greater than the third thickness (TH13) in the vertical direction (Z direction) of the portion covering the device isolation film (112) in the work function metal-containing structure (162).

[0046] In exemplary embodiments, a plurality of work function metal-containing patterns (162A), work function metal-containing liners (162B), and a plurality of work function metal-containing blocks (162C1, 162C2) may each be made of a TiN film, a WN film, or a MoN film. For example, a plurality of work function metal-containing patterns (162A), work function metal-containing liners (162B), and a plurality of work function metal-containing blocks (162C1, 162C2) may each be made of a TiN film. In exemplary embodiments, a plurality of work function metal-containing patterns (162A) and work function metal-containing liners (162B) may be obtained through an atomic layer deposition (ALD) process, and a plurality of work function metal-containing blocks (162C1, 162C2) may each be obtained through a physical vapor deposition (PVD) process.

[0047] As described above, in the second transistor region (TA2), the blanket work function metal-containing layer (164) may include a second region portion that encloses the first to third nanosheets (N1, N2, N3) and the work function metal-containing structure (162). In the second transistor region (TA2), the work function metal-containing structure (162) may include a portion interposed between the first to third nanosheets (N1, N2, N3) covered by the work function metal-containing structure (162) and the blanket work function metal-containing layer (164).

[0048] In the second transistor region (TA2), the blanket work function metal-containing layer (164) may include a plurality of protrusions (164P) protruding toward the uneven surfaces included in each of the two side walls in the second horizontal direction (Y direction) of the work function metal-containing structure (162). The plurality of protrusions (164P) of the blanket work function metal-containing layer (164) may protrude toward the region between each of the first to third nanosheets (N1, N2, N3) that are surrounded by the work function metal-containing structure (162) and in contact with a plurality of concave surfaces included in the uneven surface of the blanket work function metal-containing layer (164). Each of the plurality of protrusions (164P) of the blanket work function metal-containing layer (164) may face the work function metal-containing pattern (162A) included in the work function metal-containing structure (162) in the second horizontal direction (Y direction). The protrusion (164P) of the blanket work function metal-containing layer (164) can be spaced apart from the work function metal-containing pattern (162A) in the second horizontal direction (Y direction) with the work function metal-containing liner (162B) in between.

[0049] As illustrated in FIG. 4, at least one gate line (160) selected from a plurality of gate lines (160) may further include a gap-fill metal film (166) covering a blanket work-function metal-containing layer (164) and a work-function metal-containing structure (162). In the first transistor region (TA1), the gap-fill metal film (166) is in contact with the blanket work-function metal-containing layer (164), and in the second transistor region (TA2), the gap-fill metal film (166) may be spaced apart from the work-function metal-containing structure (162) with the blanket work-function metal-containing layer (164) in between. The gap-fill metal film (166) may be made of W, Al, or a combination thereof.

[0050] A gate dielectric film (152) may be interposed between the first to third nanosheets (N1, N2, N3) and the blanket work function metal-containing layer (164) in the first transistor region (TA1), and between the first to third nanosheets (N1, N2, N3) and the work function metal-containing structure (162) in the second transistor region (TA2). The gate dielectric film (152) may include portions covering the surface of each of the first to third nanosheets (N1, N2, N3), portions covering the sidewalls of the gate line (160), and portions covering the upper surface of the device isolation film (112).

[0051] In the first transistor region (TA1), the gate dielectric film (152) may be in contact with the blanket work function metal-containing layer (164). In the second transistor region (TA2), the gate dielectric film (152) may include portions in contact with a plurality of work function metal-containing patterns (162A) and portions in contact with a work function metal-containing liner (162B). In the second transistor region (TA2), the gate dielectric film (152) may be spaced vertically (Z direction) from the upper work function metal-containing block (162C1) with the work function metal-containing liner (162B) in between.

[0052] In exemplary embodiments, the gate dielectric film (152) may be composed of a stacked structure of an interface film (152A) and a high dielectric film (152B). The interface film (152A) may be composed of a low dielectric material film having a dielectric constant of about 9 or less, for example, a silicon oxide film, a silicon oxynitride film, or a combination thereof. In exemplary embodiments, the interface film (152A) may be omitted. The high dielectric film (152B) may be composed of a material having a dielectric constant greater than that of the silicon oxide film. For example, the high dielectric film (152B) may have a dielectric constant of about 10 to 25. The high dielectric film (152B) may be composed of hafnium oxide, but is not limited thereto.

[0053] An integrated circuit element (100) may include a plurality of source / drain regions (130) disposed on a plurality of pin-shaped active regions (F1). A plurality of source / drain regions (130) disposed on a single pin-shaped active region (F1) may be spaced apart from each other in a first horizontal direction (X direction) with a single gate line (160) in between. Each of the plurality of source / drain regions (130) may be in contact with a first to third nanosheet (N1, N2, N3) included in an adjacent nanosheet stack (NSS).

[0054] Among the plurality of source / drain regions (130), the source / drain region (130) located in the first transistor region (TA1) may be composed of a Si layer doped with an n-type dopant or a SiC layer doped with an n-type dopant. The n-type dopant may be selected from P (phosphorus), As (arsenic), and Sb (antimony). Among the plurality of source / drain regions (130), the source / drain region (130) located in the second transistor region (TA2) may be composed of a SiGe film doped with a p-type dopant. The p-type dopant may be selected from B (boron) and Ga (gallium).

[0055] As illustrated in FIG. 2, a plurality of gate lines (160) may each include a main gate portion (160M) extending in a second horizontal direction (Y direction) and covering the upper surface of a nanosheet stack (NSS), and a plurality of sub-gate portions (160S) integrally connected to the main gate portion (160M) and disposed within the space between each of the first to third nanosheets (N1, N2, N3) and the space between the fin upper surface (FF) and the first nanosheet (N1). In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions (160S) may be smaller than the thickness of the main gate portion (160M). Among the first to third nanosheets (N1, N2, N3), the second and third nanosheets (N2, N3), excluding the first nanosheet (N1), may have a gate-all-around (GAA) structure in which they are completely surrounded by the gate line (160).

[0056] Each of the multiple sub-gate portions (160S) included in the multiple gate lines (160) may be spaced apart from the source / drain region (130) with the gate dielectric film (152) in between. The gate dielectric film (152) may be interposed between the sub-gate portions (160S) included in the gate lines (160) and each of the first to third nanosheets (N1, N2, N3), and between the sub-gate portions (160S) included in the gate lines (160) and the source / drain region (130). The multiple gate lines (160), the multiple nanosheet stacks (NSS), and the multiple source / drain regions (130) may constitute a multiple nanosheet transistor.

[0057] As illustrated in FIG. 2, both sidewalls of the gate line (160) may be covered by a plurality of insulating spacers (118). Each of the plurality of insulating spacers (118) may cover the sidewalls of the main gate portion (160M) on the upper surface of the nanosheet stack (NSS). Each of the plurality of insulating spacers (118) may be spaced apart from the gate line (160) with the gate dielectric film (152) in between. Each of the plurality of insulating spacers (118) may be made of silicon nitride, silicon oxide, SiOC, SiOCN, SiCN, SiBN, SiON, SiBCN, SiOF, SiOCH, or a combination thereof. The plurality of insulating spacers (118) may be made of a single film made of one material film selected from the materials listed above, or a multi-film comprising a plurality of material films selected from the materials listed above. As used in this specification, the terms SiOC, SiOCN, SiCN, SiBN, SiON, SiBCN, SiOF, and SiOCH refer to materials composed of the elements included in each term, and are not chemical formulas representing stoichiometric relationships.

[0058] The upper surface of each of the gate line (160), gate dielectric film (152), and insulating spacer (118) may be covered with a capping insulating pattern (168). Each of the capping insulating pattern (168) may be made of a silicon nitride film.

[0059] A plurality of source / drain regions (130), device isolation films (112), and a plurality of insulating spacers (118) may be covered with an insulating liner (142). An inter-gate insulating film (144) may be disposed over the insulating liner (142). The inter-gate insulating film (144) may fill the space between a pair of adjacent gate lines (160) in a first horizontal direction (X direction). In exemplary embodiments, the insulating liner (142) may be made of silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, and the inter-gate insulating film (144) may be made of silicon oxide, but is not limited thereto.

[0060] As illustrated in FIG. 2, a plurality of source / drain contacts (CA) may be disposed on a source / drain region (130) between a pair of adjacent gate lines (160) among a plurality of gate lines (160). Each of the plurality of source / drain contacts (CA) may be configured to be electrically connected to at least one selected from the plurality of source / drain regions (130). A metal silicide film (172) may be interposed between the source / drain region (130) and the source / drain contact (CA). The metal silicide film (172) may be in contact with the corresponding source / drain region (130). The source / drain contact (CA) may be in contact with the metal silicide film (172) by penetrating the gate-to-gate insulating film (144) and the insulating liner (142) in a vertical direction (Z direction). The source / drain contact (CA) can be configured to be connected to the source / drain region (130) through a metal silicide film (172). The source / drain contact (CA) can penetrate a portion of the source / drain region (130) in a vertical direction (Z direction). An insulating liner (142) and a gate-to-gate insulating film (144) can surround the sidewalls of the source / drain contact (CA).

[0061] In exemplary embodiments, the metal silicide film (172) may comprise Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film (172) may be made of titanium silicide. In exemplary embodiments, the source / drain contact (CA) may be made only of a metal plug made of a single metal. In other exemplary embodiments, the source / drain contact (CA) may comprise a metal plug and a conductive barrier film surrounding the metal plug. The metal plug may be made of Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, combinations thereof, or alloys thereof, but is not limited thereto. The conductive barrier film may be made of a metal or a conductive metal nitride. For example, the conductive barrier film may be composed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited to these.

[0062] The upper surface of each of the source / drain contact (CA), the plurality of capping insulation patterns (168), and the gate-to-gate insulation film (144) may be covered by an upper insulation structure (180). The upper insulation structure (180) may include an etch stop film (182) and an upper insulation film (184) stacked sequentially on each of the plurality of source / drain contacts (CA), the plurality of capping insulation patterns (168), and the gate-to-gate insulation film (144). The etch stop film (182) may be made of silicon carbide (SiC), SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The upper insulation film (184) may be made of an oxide film, a nitride film, an ultra-low-k (ULK) film having an ultra-low dielectric constant of about 2.2 to about 2.4, or a combination thereof. For example, the upper insulating film (184) may be made of a TEOS (tetraethylorthosilicate) film, an HDP (high density plasma) oxide film, a BPSG (boro-phospho-silicate glass) film, an FCVD (flowable chemical vapor deposition) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof, but is not limited to these.

[0063] As illustrated in FIG. 2, a source / drain via contact (VA) may be disposed on a source / drain contact (CA). Each of the source / drain via contacts (VA) may pass through an upper insulating structure (180) and come into contact with the source / drain contact (CA). Among the plurality of source / drain regions (130), the source / drain region (130) connected to the source / drain contact (CA) may be configured to be electrically connected to the source / drain via contact (VA) through a metal silicide film (172) and the source / drain contact (CA). Each of the plurality of source / drain via contacts (VA) may be made of Mo or W, but is not limited thereto. A gate contact may be disposed on the upper portion of each of the plurality of gate lines (160). The gate contact may be configured to be connected to the gate line (160) by penetrating the upper insulating structure (180) and the capping insulating pattern (168) in a vertical direction (Z direction). The bottom surface of the gate contact may be in contact with the top surface of the gate line (160). The gate contact may include a contact plug made of Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, a combination thereof, or an alloy thereof. In exemplary embodiments, the gate contact may further include a conductive barrier pattern that surrounds a portion of the contact plug. The conductive barrier pattern may be made of a metal or a metal nitride. For example, the conductive barrier pattern may be made of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto.

[0064] The upper surface of the upper insulating structure (180) may be covered with a front-side interlayer insulating film (186). The constituent material of the front-side interlayer insulating film (186) is generally the same as that described above for the constituent material of the upper insulating film (184). A plurality of first wiring layers (M1) may be arranged to penetrate the front-side interlayer insulating film (186). A plurality of first wiring layers (M1) may include a first wiring layer (M1) connected to a source / drain via contact (VA). A plurality of first wiring layers (M1) may be made of Mo, W, Co, Ru, Mn, Ti, Ta, Al, Cu, a combination thereof, or an alloy thereof, but is not limited to these.

[0065] A front-side wiring structure (FWS) may be disposed on a plurality of first wiring layers (M1) and an interlayer insulating film (186). The front-side wiring structure (FWS) may include a plurality of second wiring layers (M2), a plurality of via contacts, and an interlayer insulating film (188) covering them. A plurality of second wiring layers (M2) may include a plurality of word lines. The constituent material of each of the plurality of second wiring layers (M2) and the plurality of via contacts is generally the same as described above for the constituent material of the plurality of first wiring layers (M1). The constituent material of the interlayer insulating film (188) is generally the same as described above for the constituent material of the upper insulating film (184).

[0066] According to the integrated circuit device (100) described with reference to FIGS. 1 to 4, even if the area of ​​each of the first transistor region (TA1) and the second transistor region (TA2), which have different channel types, is reduced and the distance between the first transistor region (TA1) and the second transistor region (TA2) is narrowed due to down-scaling of the integrated circuit device (100), different electrical characteristics required in each of the first transistor region (TA1) and the second transistor region (TA2) can be stably secured according to various arrangement structures in the integrated circuit device including the first transistor region (TA1) and the second transistor region (TA2), and the performance and reliability of each of the first transistor region (TA1) and the second transistor region (TA2) can be secured. In addition, the possibility of process defects occurring during the manufacturing process of the integrated circuit device (100) can be eliminated.

[0067] FIGS. 5 and FIGS. 6 are cross-sectional views illustrating integrated circuit elements (200, 300) according to other embodiments of the technical concept of the present invention. FIGS. 5 and FIGS. 6 illustrate an enlarged cross-sectional configuration of a portion of the integrated circuit elements (200, 300) corresponding to the area labeled "EX1" in FIGS. 3. In FIGS. 5 and FIGS. 6, the same reference numerals as in FIGS. 1 to 4 indicate the same components, and detailed descriptions thereof are omitted here.

[0068] Referring to FIG. 5, the integrated circuit element (200) has a configuration generally identical to that described with respect to the integrated circuit element (100) with reference to FIG. 1 to 4. However, the integrated circuit element (200) includes a work function metal-containing structure (262).

[0069] The work function metal-containing structure (262) generally has the structure described with reference to FIG. 4 for the work function metal-containing structure (162). However, the work function metal-containing structure (262) includes a plurality of work function metal-containing patterns (262A) arranged one by one between each of the first to third nanosheets (N1, N2, N3) covered by the work function metal-containing structure (262) and between the pin-shaped active region (F1) and the first nanosheet (N1). In the second horizontal direction (Y direction), the first to third nanosheets (N1, N2, N3) covered by the work function metal-containing structure (262) have a first width (W21), and the second width (W22) of each of the plurality of work function metal-containing patterns (262A) is smaller than the first width (W21). The more detailed configuration of the plurality of work function metal-containing patterns (262A) is generally the same as described for the plurality of work function metal-containing patterns (162A) with reference to FIG. 4.

[0070] Referring to FIG. 6, the integrated circuit element (300) has a configuration generally identical to that described with respect to the integrated circuit element (100) with reference to FIG. 1 to 4. However, the integrated circuit element (300) includes a work function metal-containing structure (362).

[0071] The work function metal-containing structure (362) generally has the structure described with reference to FIG. 4 for the work function metal-containing structure (162). However, the work function metal-containing structure (362) includes a plurality of work function metal-containing patterns (362A) arranged one by one between each of the first to third nanosheets (N1, N2, N3) covered by the work function metal-containing structure (362) and between the pin-shaped active region (F1) and the first nanosheet (N1). In the second horizontal direction (Y direction), the first to third nanosheets (N1, N2, N3) covered by the work function metal-containing structure (362) have a first width (W31), and the second width (W32) of each of the plurality of work function metal-containing patterns (362A) is larger than the first width (W31). The more detailed configuration of the plurality of work function metal-containing patterns (362A) is generally the same as described for the plurality of work function metal-containing patterns (162A) with reference to FIG. 4.

[0072] FIGS. 7 and FIGS. 8 are cross-sectional views for explaining an integrated circuit element (400) according to other embodiments of the technical concept of the present invention, FIG. 7 is a cross-sectional view corresponding to the X1 - X1' line cross-section of FIG. 1 of the integrated circuit element (400), and FIG. 8 is a cross-sectional view corresponding to the Y1 - Y1' line cross-section of FIG. 1 of the integrated circuit element (400). In FIGS. 7 and FIG. 8, the same reference numerals as in FIGS. 1 to 4 indicate the same components, and detailed descriptions thereof are omitted here.

[0073] Referring to FIGS. 7 and FIGS. 8, the integrated circuit element (400) has a configuration generally identical to that described with respect to the integrated circuit element (100) with reference to FIGS. 1 to 4. However, the integrated circuit element (400) includes a backside wiring structure (BWS).

[0074] The backside wiring structure (BWS) can cover the backside surface (BS) of each of the plurality of pin-shaped active regions (F1) and the backside surface (112B) of the device isolation film (112). The backside wiring structure (BWS) may include a backside contact (DBC) configured to be connected to a source / drain region (130), a backside insulating spacer (492) surrounding the backside contact (DBC), a power rail wiring (MPR) connected to the backside contact (DBC), and a backside interlayer insulating film (496). A metal silicide film (490) may be interposed between the source / drain region (130) and the backside contact (DBC).

[0075] The backside contact (DBC) is configured to be connected to a corresponding source / drain region (130) through a metal silicide film (490) and may extend vertically (in the Z direction) from the corresponding source / drain region (130) toward the backside surface (BS) of the pin-shaped active region (F1). The backside interlayer insulating film (496) may be interposed between a plurality of pin-shaped active regions (F1) and power rail wiring (MPR) to insulate them from each other. In exemplary embodiments, the power rail wiring (MPR) may be connected to a ground node or a power node, but is not limited thereto.

[0076] The constituent materials of the backside contact (DBC) and power rail wiring (MPR), respectively, are generally the same as those described above for the constituent materials of the plurality of first wiring layers (M1). The constituent material of the metal silicide film (490) is the same as that described above for the metal silicide film (172). The constituent material of the backside insulation spacer (492) is generally the same as those described above for the constituent materials of the plurality of insulation spacers (118). The constituent material of the backside interlayer insulation film (496) is generally the same as that described above for the upper insulation film (184).

[0077] FIGS. 9a to 15b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. More specifically, FIGS. 9a, 11a, 12a, 13a, 14a, and 15a are cross-sectional views showing an exemplary cross-sectional structure in the order of process of a portion corresponding to the cross-section along the X1-X1' line of FIG. 1, and FIGS. 9b, 10, 11b, 12b, 13b, 14b, and 15b are cross-sectional views showing an exemplary cross-sectional structure in the order of process of a portion corresponding to the cross-section along the Y1-Y1' line of FIG. 1. An exemplary method for manufacturing an integrated circuit element (100) described with reference to FIGS. 1 to 4 will be explained with reference to FIGS. 9a to 15b. In FIGS. 9a to 15b, the same reference numerals as in FIGS. 1 to 4 indicate the same components, and a detailed description of these is omitted here.

[0078] Referring to FIGS. 9a and 9b, a stacked structure can be formed on a substrate (102) in which a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS) are alternately stacked one layer at a time. In the stacked structure, the plurality of sacrificial semiconductor layers (104) and the plurality of nanosheet semiconductor layers (NS) may be made of semiconductor materials with different etching selectivity ratios. In exemplary embodiments, the plurality of nanosheet semiconductor layers (NS) may be made of Si layers, and the plurality of sacrificial semiconductor layers (104) may be made of SiGe films. The SiGe films constituting the sacrificial semiconductor layers (104) may have a Ge content ratio selected within the range of about 5 atomic% to about 50 atomic%, for example, about 10 atomic% to about 40 atomic%.

[0079] A mask pattern having openings that partially expose the upper surface of the stacked structure is formed, and a portion of each of the plurality of sacrificial semiconductor layers (104), the plurality of nanosheet semiconductor layers (NS), and the substrate (102) is etched using the mask pattern as an etching mask to form a plurality of fin-shaped active regions (F1). A plurality of trench regions (T1) may be defined on the substrate (102) by the plurality of fin-shaped active regions (F1). A portion of each of the plurality of sacrificial semiconductor layers (104) and the plurality of nanosheet semiconductor layers (NS) may remain on the fin upper surface (FF) of the plurality of fin-shaped active regions (F1).

[0080] Referring to FIG. 10, a device isolation film (112) can be formed on the result of performing the processes described with reference to FIG. 9a and FIG. 9b. The device isolation film (112) can be formed to fill a plurality of trench regions (T1) and cover the side walls of each of a plurality of fin-shaped active regions (F1). After the device isolation film (112) is formed, a stacked structure consisting of a plurality of sacrificial semiconductor layers (104) remaining on the substrate (102) and a plurality of nanosheet semiconductor layers (NS) protrudes over the upper surface of the device isolation film (112), and the upper surface of the uppermost nanosheet semiconductor layer (NS) among the plurality of nanosheet semiconductor layers (NS) can be exposed.

[0081] Referring to FIGS. 11a and 11b, a plurality of dummy gate structures (DGS) can be formed on the result of performing the processes described with reference to FIG. 10. Each of the plurality of dummy gate structures (DGS) can be formed to extend long in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures (DGS) may include a dummy oxide film (D122), a dummy gate layer (D124), and a capping layer (D126) that are sequentially stacked on a stacked structure comprising a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS). In exemplary embodiments, the dummy gate layer (D124) may be made of polysilicon, and the capping layer (D126) may be made of silicon nitride.

[0082] A plurality of insulating spacers (118) covering both side walls of each of a plurality of dummy gate structures (DGS) are formed, and the plurality of dummy gate structures (DGS) and the plurality of insulating spacers (118) are used as etching masks to etch parts of each of a plurality of sacrificial semiconductor layers (104) and a plurality of nanosheet semiconductor layers (NS), and parts of each of a plurality of fin-shaped active regions (F1), thereby dividing the plurality of nanosheet semiconductor layers (NS) into a plurality of nanosheet stacks (NSS) including first to third nanosheets (N1, N2, N3), and forming a plurality of recesses (R1) on the upper portion of each of the plurality of fin-shaped active regions (F1).

[0083] Referring to FIGS. 12a and 12b, a plurality of source / drain regions (130) filling a plurality of recesses (R1) can be formed in the result of FIGS. 11a and 11b. In exemplary embodiments, to form a plurality of source / drain regions (130), a semiconductor material can be epitaxially grown from the sidewalls of each of the first to third nanosheets (N1, N2, N3) exposed in the plurality of recesses (R1) and from the surface of a plurality of fin-shaped active regions (F1). The process of forming the plurality of source / drain regions (130) can be performed separately by distinguishing between a first transistor region (TA1) and a second transistor region (TA2) (see FIG. 3). In exemplary embodiments, a source / drain region (130) placed in the first transistor region (TA1) can be formed first, and then a source / drain region (130) placed in the second transistor region (TA2) can be formed. In other exemplary embodiments, a source / drain region (130) placed in the second transistor region (TA2) may be formed first, and then a source / drain region (130) placed in the first transistor region (TA1) may be formed.

[0084] After that, an insulating liner (142) covering the result in which a plurality of source / drain regions (130) are formed is formed, and a gate-to-gate insulating film (144) is formed on the insulating liner (142). Then, a portion of each of the insulating liner (142) and the gate-to-gate insulating film (144) can be etched to expose the upper surface of a plurality of capping layers (D126) (see FIG. 11a and FIG. 11b). After that, the plurality of capping layers (D126) can be removed to expose a dummy gate layer (D124), and a portion of the insulating liner (142) and the gate-to-gate insulating film (144) can be removed so that the upper surface of the gate-to-gate insulating film (144) and the upper surface of the dummy gate layer (D124) are at approximately the same level.

[0085] Referring to FIGS. 13a and 13b, a gate space (GS) can be provided by removing the dummy gate layer (D124) and the dummy oxide film (D122) from the results of FIGS. 12a and 12b.

[0086] Referring to FIGS. 14a and 14b, a plurality of sacrificial semiconductor layers (104) remaining on the substrate (102) through the gate space (GS) in the result of FIGS. 13a and 13b can be selectively removed, thereby extending the gate space (GS) to the space between each of the first to third nanosheets (N1, N2, N3) and the space between the first nanosheet (N) and the fin surface (FF).

[0087] Referring to FIGS. 15a and 15b, a gate dielectric film (152) can be formed covering the exposed surfaces of each of the first to third nanosheets (N1, N2, N3) and a plurality of pin-shaped active regions (F1) in the results of FIGS. 14a and 14b. An ALD process may be used to form the gate dielectric film (152). Then, a gate line (160) can be formed on the gate dielectric film (152) to fill the gate space (GS) (see FIGS. 14a and 14b). Then, a portion of each of the gate line (160), the gate dielectric film (152), and the insulating spacer (118) can be removed from their respective upper surfaces to lower their respective heights, and a plurality of capping insulating patterns (168) can be formed covering each of the gate line (160), the gate dielectric film (152), and the insulating spacer (118).

[0088] FIGS. 16a to 16q are cross-sectional views illustrating an enlarged cross-sectional configuration according to the process sequence in the portion corresponding to “EX1A” in FIG. 14b, in order to explain in more detail the process of forming a gate dielectric film (152) and a gate line (160) as described with reference to FIGS. 15a and 15b. In FIGS. 16a to 16q, the same reference numerals as in FIGS. 1 to 4 and FIGS. 9a to 15b indicate the same components, and a detailed description of these is omitted here.

[0089] Referring to FIG. 16a, as described with reference to FIG. 14a and FIG. 14b, a gate space (GS) can be formed that exposes the first to third nanosheets (N1, N2, N3), a pin surface (FF), and a device isolation film (112).

[0090] Referring to FIG. 16b, a gate dielectric film (152) can be formed in a stacked structure of an interface film (152A) and a high dielectric film (152B) on the exposed surfaces of the first to third nanosheets (N1, N2, N3), the fin surface (FF), and the device isolation film (112) through the gate space (GS).

[0091] Referring to FIG. 16c, a protective film (PL) can be formed to conformally cover the exposed surfaces of the gate dielectric film (152) exposed through the gate space (GS). The protective film (PL) can serve to protect the gate dielectric film (152) when performing subsequent processes. In exemplary embodiments, the protective film (PL) may be made of a metal oxide film. For example, the protective film (PL) may be made of an aluminum oxide film. An ALD process may be used to form the protective film (PL).

[0092] Referring to FIG. 16d, a dummy support layer (FL1) covering the result of FIG. 16c can be formed. The dummy support layer (FL1) may include portions that fill the space between each of the first to third nanosheets (N1, N2, N3) in each of the first transistor region (TA1) and the second transistor region (TA2), portions that fill the space defined by the protective film (PL) between the pin-shaped active region (F1) and the first nanosheet (N1), and portions that cover the protective film (PL) on the sidewalls of each of the first to third nanosheets (N1, N2, N3).

[0093] In exemplary embodiments, the dummy support layer (FL1) may be made of a metal nitride. For example, the dummy support layer (FL1) may be made of a TiN film, but is not limited thereto. An ALD process or a CVD (chemical vapor deposition) process may be used to form the dummy support layer (FL1).

[0094] Referring to FIG. 16e, a portion of the dummy support layer (FL1) in the result of FIG. 16d can be removed to form a plurality of dummy support patterns (FL1A) consisting of the remaining portions of the dummy support layer (FL1) in the space between each of the first to third nanosheets (N1, N2, N3) in the first transistor region (TA1) and the second transistor region (TA2), and in the space defined by the protective film (PL) between the pin-shaped active region (F1) and the first nanosheet (N1). In exemplary embodiments, the width of the plurality of dummy support patterns (FL1A) in the second horizontal direction (Y direction) may be smaller than the width in the second horizontal direction (Y direction) of the portions of the protective film (PL) covering the first to third nanosheets (N1, N2, N3).

[0095] In exemplary embodiments, wet etching, dry etching, or a combination thereof may be used to remove a portion of the dummy support layer (FL1) to form a plurality of dummy support patterns (FL1A). When the dummy support layer (FL1) is made of a TiN film, since the TiN film has a columnar structure, the portions covering the protective film (PL) on the sidewalls of each of the first to third nanosheets (N1, N2, N3) among the TiN films constituting the dummy support layer (FL1) can be removed at a relatively fast etching rate. On the other hand, the etching rate of the portions filling the space between each of the first to third nanosheets (N1, N2, N3) and the space defined by the protective film (PL) between the fin-shaped active region (F1) and the first nanosheet (N1) may be slower than the etching rate outside each of the first to third nanosheets (N1, N2, N3). Accordingly, after the portions covering the protective film (PL) on the sidewalls of each of the first to third nanosheets (N1, N2, N3) of the TiN film are removed and the protective film (PL) is exposed on the sidewalls of each of the first to third nanosheets (N1, N2, N3), the portions filling the space between each of the first to third nanosheets (N1, N2, N3) of the TiN film and the space defined by the protective film (PL) between the pin-shaped active region (F1) and the first nanosheet (N1) are not removed and remain, thereby forming a plurality of dummy support patterns (FL1A).

[0096] Referring to FIG. 16f, a dummy protection pattern (TL1) can be selectively formed only on the upper surfaces of the portions covering the upper surface of each of the plurality of nanosheet stacks (NSS) among the upper surfaces of the protective film (PL) in each of the first transistor region (TA1) and the second transistor region (TA2), and on the upper surfaces of the portions covering the upper surface of the device isolation film (112). The dummy protection pattern (TL1) may include a plurality of upper dummy protection patterns (TL1A) covering the upper surface of each of the plurality of nanosheet stacks (NSS) among the upper surfaces of the protective film (PL), and a plurality of lower dummy protection patterns (TL1B) covering the upper surface of the device isolation film (112) among the upper surfaces of the protective film (PL). The plurality of upper dummy protection patterns (TL1A) and the plurality of lower dummy protection patterns (TL1B) may be spaced apart from each other. The thickness (TH51) in the vertical direction (Z direction) of each of the multiple upper dummy protection patterns (TL1A) may be greater than the thickness (TH52) in the vertical direction (Z direction) of each of the multiple lower dummy protection patterns (TL1B).

[0097] In exemplary embodiments, the dummy protection pattern (TL1) may be made of a metal nitride. For example, the dummy protection pattern (TL1) may be made of a TiN film, but is not limited thereto. A PVD process may be used to form the dummy protection pattern (TL1). After the dummy protection pattern (TL1) is formed, the sidewalls of a plurality of dummy support patterns (FL1A) may be exposed to the gate space (GS) between the upper dummy protection pattern (TL1A) and the adjacent lower dummy protection pattern (TL1B).

[0098] Referring to FIG. 16g, a mask pattern (MP1) can be formed that selectively covers only the first transistor region (TA1) among the first transistor region (TA1) and the second transistor region (TA2) in the result of FIG. 16f. In exemplary embodiments, the mask pattern (MP1) may be made of a soft hard mask material including a BARC (bottom anti-reflective coating) film, or a spin-on hard mask (SOH) material.

[0099] After that, the mask pattern (MP1) is used as an etching mask to remove the dummy protection pattern (TL1) and the plurality of dummy support patterns (FL1A) in the second transistor region (TA2), and as a result, the exposed protection film (PL) is removed to expose the gate dielectric film (152).

[0100] In exemplary embodiments, a wet etching process may be used to remove a dummy protection pattern (TL1), a plurality of dummy support patterns (FL1A), and a protective film (PL) in a second transistor region (TA2). While removing the dummy protection pattern (TL1) and the plurality of dummy support patterns (FL1A) in the second transistor region (TA2), the lower portion of the dummy protection pattern (TL1B) that is placed in the first transistor region (TA1) and exposed toward the second transistor region (TA2) from the bottom of the mask pattern (MP1) may have a relatively small thickness. Accordingly, while performing the etching process to remove the dummy protection pattern (TL1) and the plurality of dummy support patterns (FL1A) in the second transistor region (TA2), it may be prevented that the dummy protection pattern (TL1) in the first transistor region (TA1) is unintentionally etched from the portion exposed toward the second transistor region (TA2), thereby preventing the formation of a severe lateral recess in the dummy protection pattern (TL1). If a relatively large lateral recess is formed in the dummy protection pattern (TL1) in the first transistor region (TA1) while performing an etching process to remove the dummy protection pattern (TL1) and a plurality of dummy support patterns (FL1A) in the second transistor region (TA2), the structures in the first transistor region (TA1) may be damaged through the lateral recess. According to the technical concept of the present invention, since the lower dummy protection pattern (TL1B) portion of the dummy protection pattern (TL1) disposed in the first transistor region (TA1) and exposed toward the second transistor region (TA2) from the bottom of the mask pattern (MP1) has a relatively small thickness, there is no concern that the structures in the first transistor region (TA1) will be damaged.

[0101] Referring to FIG. 16h, the mask pattern (MP1) in the result of FIG. 16g can be removed to expose a plurality of dummy support patterns (FL1A), dummy protection patterns (TL1), and a protective film (PL) in the first transistor region (TA1). An ashing and stripping process can be used to remove the mask pattern (MP1).

[0102] FIG. 16h illustrates a case in which a plurality of lower dummy protection patterns (TL1B) covering a protective film (PL) on the upper surface of the device isolation film (112) remain in the result after the mask pattern (MP1) is removed, but the technical concept of the present invention is not limited thereto. For example, while the mask pattern (MP1) is being removed, at least a portion of a plurality of lower dummy protection patterns (TL1B) having a relatively small thickness may also be removed together, so that the protective film (PL) is exposed on the upper surface of the device isolation film (112).

[0103] Referring to FIG. 16i, a second conductivity type work function metal-containing film (162L) covering the entire surface of the result of FIG. 16h can be formed in the first transistor region (TA1) and the second transistor region (TA2).

[0104] In the second transistor region (TA2), the work function metal-containing film (162L) may be in contact with the gate dielectric film (152). In the second transistor region (TA2), the work function metal-containing film (162L) may include the space between each of the first to third nanosheets (N1, N2, N3), portions filling the space defined by the gate dielectric film (152) between the pin-shaped active region (F1) and the first nanosheet (N1), portions covering the gate dielectric film (152) on the sidewalls of each of the first to third nanosheets (N1, N2, N3), and portions covering the gate dielectric film (152) on the device isolation film (112). The work function metal-containing film (162L) may be made of a P-type work function metal-containing film, for example, a P-type metal nitride film. In exemplary embodiments, the work function metal-containing film (162L) may comprise a TiN film, a WN film, or a MoN film. For example, the work function metal-containing film (162L) may be made of a TiN film, but is not limited thereto.

[0105] In exemplary embodiments, the work function metal-containing film (162L) and a plurality of dummy support patterns (FL1A) and dummy protection patterns (TL1) in the first transistor region (TA1) may be made of the same constituent material. An ALD process or a CVD process may be used to form the work function metal-containing film (162L).

[0106] Referring to FIG. 16j, a portion of the work function metal-containing film (162L) in the result of FIG. 16i can be removed to form a plurality of work function metal-containing patterns (162A) consisting of the remaining portions of the work function metal-containing film (162L) in the space between each of the first to third nanosheets (N1, N2, N3) in the second transistor region (TA2) and in the space defined by the gate dielectric film (152) between the fin-shaped active region (F1) and the first nanosheet (N1). As described with reference to FIG. 4, the second width (W12) of each of the plurality of work function metal-containing patterns (162A) may be equal to or smaller than the first width (W11) of the first to third nanosheets (N1, N2, N3). In the first transistor region (TA1), after a portion of the work function metal-containing film (162L) is removed, the sidewalls of each of the plurality of dummy support patterns (FL1A) and a portion of the protective film (PL) may be exposed.

[0107] Wet etching, dry etching, or a combination thereof may be used to remove a portion of the work function metal-containing film (162L) to form a plurality of work function metal-containing patterns (162A) in the second transistor region (TA2). When the work function metal-containing film (162L) is made of a TiN film, since the TiN film has a columnar structure, the portions covering the protective film (PL) on the sidewalls of each of the first to third nanosheets (N1, N2, N3) among the TiN films constituting the work function metal-containing film (162L) can be removed at a relatively fast etching rate. On the other hand, the etching rate of the portions filling the space between each of the first to third nanosheets (N1, N2, N3) and the space between the pin-shaped active region (F1) and the first nanosheet (N1) by the gate dielectric film (152) may be slower than the etching rate outside each of the first to third nanosheets (N1, N2, N3). Accordingly, in the second transistor region (TA2), the portions covering the gate dielectric film (152) on the sidewalls of each of the first to third nanosheets (N1, N2, N3) among the TiN films are removed so that the gate dielectric film (152) on the sidewalls of each of the first to third nanosheets (N1, N2, N3) is exposed, and the portions filling the space between each of the first to third nanosheets (N1, N2, N3) among the TiN films and the space defined by the gate dielectric film (152) between the fin-shaped active region (F1) and the first nanosheet (N1) are not removed and remain, thereby forming a plurality of work function metal-containing patterns (162A).

[0108] Referring to FIG. 16k, a work function metal-containing liner (162B) can be formed to conformally cover the front surface of the result of FIG. 16j in the first transistor region (TA1) and the second transistor region (TA2). An ALD process may be used to form the work function metal-containing liner (162B). In exemplary embodiments, the work function metal-containing liner (162B) and a plurality of dummy support patterns (FL1A) in the first transistor region (TA1) may be made of the same material. For example, the work function metal-containing liner (162B) and the plurality of dummy support patterns (FL1A) may be made of the same material film selected from TiN film, WN film, and MoN film.

[0109] Referring to FIG. 16, a work function metal-containing block layer (TL2) can be selectively formed only on the upper surfaces of the portions covering the upper surface of each of the plurality of nanosheet stacks (NSS) among the upper surfaces of the work function metal-containing liner (162B) in each of the first transistor region (TA1) and the second transistor region (TA2), and on the upper surfaces of the portions covering the upper surface of the device isolation film (112). The work function metal-containing block layer (TL2) may include a plurality of upper work function metal-containing block layers (TL2A) covering the upper surface of each of the plurality of nanosheet stacks (NSS) among the upper surfaces of the work function metal-containing liner (162B), and a plurality of lower work function metal-containing block layers (TL2B) covering the upper surface of the device isolation film (112) among the upper surfaces of the work function metal-containing liner (162B). A plurality of upper work function metal-containing block layers (TL2A) and a plurality of lower work function metal-containing block layers (TL2B) may be spaced apart from each other. The thickness (TH61) in the vertical direction (Z direction) of each of the plurality of upper work function metal-containing block layers (TL2A) may be greater than the thickness (TH62) in the vertical direction (Z direction) of each of the plurality of lower work function metal-containing block layers (TL2B).

[0110] In exemplary embodiments, the work function metal-containing block layer (TL2) may be made of a metal nitride. For example, the work function metal-containing block layer (TL2) may be made of a TiN film, but is not limited thereto. A PVD process may be used to form the work function metal-containing block layer (TL2). After the work function metal-containing block layer (TL2) is formed, a work function metal-containing liner (162B) may be exposed to the gate space (GS) between the upper work function metal-containing block layer (TL2A) and the adjacent lower work function metal-containing block layer (TL2B).

[0111] Referring to FIG. 16m, a mask pattern (MP2) can be formed that selectively covers only the second transistor region (TA2) among the first transistor region (TA1) and the second transistor region (TA2) in the result of FIG. 16l. In exemplary embodiments, the mask pattern (MP2) may be made of a soft hardmask material including a BARC film or a spin-on hardmask material.

[0112] After that, the work function metal-containing block layer (TL2), the work function metal-containing liner (162B), and a plurality of dummy support patterns (FL1A) can be removed in the first transistor region (TA1) using the mask pattern (MP2) as an etching mask to expose the protective film (PL). In the second transistor region (TA2), an upper work function metal-containing block (162C1) and a lower work function metal-containing block (162C2) can be formed, consisting of the remaining portions of the work function metal-containing block layer (TL2).

[0113] In exemplary embodiments, a wet etching process may be used to remove the work function metal-containing block layer (TL2), the work function metal-containing block layer (TL2), and a plurality of dummy support patterns (FL1A) from the first transistor region (TA1). While removing the work function metal-containing block layer (TL2), the work function metal-containing block layer (TL2), and the plurality of dummy support patterns (FL1A) from the first transistor region (TA1), the lower portion of the work function metal-containing block layer (TL2B) placed in the second transistor region (TA2) and exposed toward the first transistor region (TA1) from the bottom of the mask pattern (MP2) may have a relatively small thickness. Accordingly, while performing an etching process to remove the work function metal-containing block layer (TL2), the work function metal-containing block layer (TL2), and a plurality of dummy support patterns (FL1A) in the first transistor region (TL1), it is possible to prevent the work function metal-containing block layer (TL2) in the second transistor region (TA2) from being unintentionally etched from the portion exposed toward the first transistor region (TA1), thereby preventing the formation of a severe lateral recess in the work function metal-containing block layer (TL2). If a relatively large lateral recess is formed in the work function metal-containing block layer (TL2) in the second transistor region (TA2) while removing the work function metal-containing block layer (TL2), the work function metal-containing block layer (TL2), and a plurality of dummy support patterns (FL1A) in the first transistor region (TA1), the structures in the second transistor region (TA2) may be damaged through said lateral recess. According to the technical concept of the present invention, since the lower part of the work function metal-containing block layer (TL2B) of the work function metal-containing block layer (TL2), which is disposed in the second transistor region (TA2) and exposed toward the first transistor region (TA1) from the bottom of the mask pattern (MP2), has a relatively small thickness, there is no risk of damage to the structures in the second transistor region (TA2).

[0114] After the work function metal-containing block layer (TL2), the work function metal-containing block layer (TL2), and a plurality of dummy support patterns (FL1A) are removed from the first transistor region (TA1), the portion of the upper work function metal-containing block layer (TL2A) of the work function metal-containing block layer (TL2) remaining in the second transistor region (TA2) remains as the upper work function metal-containing block (162C1), and the portion of the lower work function metal-containing block layer (TL2B) of the work function metal-containing block layer (TL2) remaining in the second transistor region (TA2) may remain as the lower work function metal-containing block (162C2).

[0115] Referring to FIG. 16n, the mask pattern (MP2) in the result of FIG. 16m can be removed to expose the upper work function metal-containing block (162C1), the lower work function metal-containing block (162C2), and the work function metal-containing liner (162B) in the second transistor region (TA2). An ashing and stripping process may be used to remove the mask pattern (MP2).

[0116] Referring to FIG. 16o, the protective film (PL) in the first transistor region (TA1) in the result of FIG. 16n can be selectively removed to expose the gate dielectric film (152) in the first transistor region (TA1).

[0117] Referring to FIG. 16p, a blanket work function metal-containing layer (164) can be formed on the front surface of the result of FIG. 16o. The blanket work function metal-containing layer (164) can be formed to surround the first to third nanosheets (N1, N2, N3) in the first transistor region (TA1) and to include portions that fill the space between each of the first to third nanosheets (N1, N2, N3), portions that fill the space defined by the gate dielectric film (152) between the fin-shaped active region (F1) and the first nanosheet (N1), and portions that cover the gate dielectric film (152) on the sidewalls of each of the first to third nanosheets (N1, N2, N3). Additionally, the blanket work function metal-containing layer (164) can be formed to surround the first to third nanosheets (N1, N2, N3) and the work function metal-containing structure (162) in the second transistor region (TA2).

[0118] While forming the blanket work function metal-containing layer (164), a plurality of protrusions (164P) may be formed on the inner surface of the blanket work function metal-containing layer (164) that contacts the work function metal-containing liner (162B), protruding toward the region between each of the first to third nanosheets (N1, N2, N3) surrounded by the work function metal-containing structure (162). The plurality of protrusions (164P) may contact a plurality of concave surfaces included in the uneven surface of the blanket work function metal-containing layer (164).

[0119] Referring to FIG. 16q, a gate line (160) can be formed by forming a gap-fill metal film (166) covering a work function metal-containing structure (162) in the first transistor region (TA1) and the second transistor region (TA2) of the result of FIG. 16p.

[0120] As described above with reference to FIGS. 15a and 15b, after forming a plurality of capping insulation patterns (168) covering each upper surface of a gate line (160), a gate dielectric film (152), and an insulating spacer (118), a source / drain contact hole is formed to expose a plurality of source / drain regions (130) between two adjacent gate lines (160) among the plurality of gate lines (160), as illustrated in FIGS. 2 and 3, a metal silicide film (172) is formed on the surface of the plurality of source / drain regions (130) through the source / drain contact hole, and a source / drain contact (CA) that fills the source / drain contact hole is formed on the metal silicide film (172).

[0121] After that, an upper insulating structure (180) can be formed by sequentially forming an etch stop layer (182) and an upper insulating layer (184) that cover the upper surface of each of the source / drain contact (CA), a plurality of capping insulating patterns (168), and a gate-to-gate insulating layer (144). After that, a plurality of source / drain via contacts (VA) connected to the source / drain contact (CA) by penetrating the upper insulating structure (180) in a vertical direction (Z direction), a plurality of gate contacts connected to the gate line (160) by penetrating the upper insulating structure (180) and the capping insulating pattern (168) in a vertical direction (Z direction), and a plurality of shared contacts for electrically connecting the gate line (160) and the source / drain contact (CA) can be formed. After that, an interlayer insulating film (186) covering the upper insulating structure (180) and a plurality of first wiring layers (M1) penetrating the interlayer insulating film (186) can be formed. After that, a front-side wiring structure (FWS) can be formed on the interlayer insulating film (186) and the plurality of first wiring layers (M1) to manufacture the integrated circuit element (100) described with reference to FIGS. 1 to 4.

[0122] According to the manufacturing method of the integrated circuit element (100) described with reference to FIGS. 9a to 16q, when removing unnecessary dummy support pattern (FL1A) and dummy protection pattern (TL1) in the second transistor region (TA2) while protecting the dummy support pattern (FL1A) and dummy protection pattern (TL1) in the first transistor region (TA1) as in the process described with reference to FIGS. 16f and 16g, the lower dummy protection pattern (TL1B) portion of the dummy protection pattern (TL1) exposed toward the second transistor region (TA2) from the bottom of the mask pattern (MP1) may have a relatively small thickness. Therefore, the problem of structures in the first transistor region (TA1) being damaged by the etching atmosphere during the removal of unnecessary dummy support pattern (FL1A) and dummy protection pattern (TL1) in the second transistor region (TA2), which causes the dummy protection pattern (TL1) in the first transistor region (TA1) to be unintentionally etched from the portion exposed toward the second transistor region (TA2), can be prevented.

[0123] In addition, when removing unnecessary multiple work function metal-containing patterns (162A), work function metal-containing liners (162B), and work function metal-containing block layers (TL2) from the first transistor region (TA1) while protecting multiple work function metal-containing patterns (162A), work function metal-containing liners (162B), and work function metal-containing block layers (TL2) required to form a work function metal-containing structure (162) in the second transistor region (TA2) as described in the process with reference to FIG. 161 and FIG. 16m, the portion of the work function metal-containing block layer (TL2) exposed toward the first transistor region (TA1) from the bottom of the mask pattern (MP2) may have a relatively small thickness. Accordingly, the problem of structures in the second transistor region (TA2) being damaged can be prevented by the etching atmosphere during the removal of unnecessary multiple work function metal-containing patterns (162A), work function metal-containing liners (162B), and work function metal-containing block layers (TL2) in the first transistor region (TA1), such that the work function metal-containing block layer (TL2) in the second transistor region (TA2) is unintentionally etched from the portion exposed toward the first transistor region (TA1).

[0124] Accordingly, according to the manufacturing method of the integrated circuit element (100) described with reference to FIGS. 9a to 16q, even if the area of ​​each of the first transistor region (TA1) and the second transistor region (TA2), which have different channel types, is reduced and the distance between the first transistor region (TA1) and the second transistor region (TA2) is narrowed due to down-scaling of the integrated circuit element (100), the possibility of process defects occurring during the manufacturing process of the integrated circuit element (100) is eliminated, thereby enabling stable securing of different electrical characteristics required in each of the first transistor region (TA1) and the second transistor region (TA2) according to various arrangement structures in the integrated circuit element (100) including the first transistor region (TA1) and the second transistor region (TA2), and enabling securing of the performance and reliability of each of the first transistor region (TA1) and the second transistor region (TA2).

[0125] In order to manufacture the integrated circuit element (200, 300) described with reference to FIGS. 5 and 6, the processes described with reference to FIGS. 9a to 15b and FIGS. 16a to 16q may be performed. However, as described with reference to FIG. 16j, in the process of removing a portion of the work function metal-containing film (162L), the amount of work function metal-containing film (162L) removed may be controlled to form a plurality of work function metal-containing patterns (262A) exemplified in FIG. 5 or a plurality of work function metal-containing patterns (362A) exemplified in FIG. 6.

[0126] To manufacture the integrated circuit device (400) described with reference to FIGS. 7 and 8, the processes described with reference to FIGS. 9a to 15b and FIGS. 16a to 16q may be performed. However, after forming the front-side wiring structure (FWS), the substrate (102) may be removed from the back-side surface of the substrate (102) and a portion of each of the plurality of pin-shaped active regions (F1) and the device isolation film (112) may be removed. As a result, the back-side surface (BS) of each of the plurality of pin-shaped active regions (F1) and the back-side surface (112B) of the device isolation film (112) may be exposed. In exemplary embodiments, at least one process selected from a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, or a combination thereof may be used to remove the substrate (102) and to remove a portion of each of the plurality of pin-shaped active regions (F1) and the device isolation film (112).

[0127] Afterward, a contact hole can be formed to expose a selected source / drain area (130) among a plurality of source / drain areas (130). While forming the contact hole, a portion of the selected source / drain area (130) may be consumed so that the shape of the bottom surface of the selected source / drain area (130) becomes concave toward the inside of the corresponding contact hole.

[0128] After that, a backside insulating spacer (492) covering the inner sidewall of each of the plurality of contact holes is formed, a metal silicide film (490) is formed on the surface of the selected source / drain region (130) through the contact hole defined by the backside insulating spacer (492), and a backside contact (DBC) filling the contact hole can be formed. After that, a backside interlayer insulating film (496) covering the backside contact (DBC), the backside surface (BS) of the pin-shaped active region (F1), and the backside surface (112B) of the device isolation film (112) is formed, and a power rail wiring (MPR) connected to the backside contact (DBC) by penetrating the backside interlayer insulating film (496) can be formed.

[0129] Although exemplary manufacturing methods of the integrated circuit elements (100, 200, 300, 400) exemplified in FIGS. 1 to 8 have been described above with reference to FIGS. 9a to 15b and FIGS. 16a to 16q, those skilled in the art will be well aware that various modified and altered integrated circuit elements of various structures can be manufactured from the integrated circuit elements (100, 200, 300, 400) exemplified in FIGS. 1 to 8 by applying various modifications and changes from the description with reference to FIGS. 9a to 15b and FIGS. 16a to 16q.

[0130] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0131] 102: Substrate, 112: Device isolation film, 152: Gate dielectric film, 152A: Interface film, 152B: High dielectric film, 160: Gate line, 160M: Main gate portion, 160S: Sub gate portion, 162: Work function metal-containing structure, 162A: Work function metal-containing pattern, 162B: Work function metal-containing liner, 162B1: Vertical extension, 162B2: Horizontal extension, 162C1: Upper work function metal-containing block, 162C2: Lower work function metal-containing block, 164: Blanket work function metal-containing layer, 166: Gap-fill metal film, 168: Capping insulation pattern.

Claims

Claim 1 An integrated circuit device comprising: a nanosheet stack including a fin-shaped active region extending in a first horizontal direction and a plurality of nanosheets facing the fin-shaped active region at a position spaced vertically from the fin-shaped active region; a device isolation layer covering the sidewalls of the fin-shaped active region; and a gate line including a work function metal-containing structure extending in a second horizontal direction intersecting the first horizontal direction over the fin-shaped active region and the device isolation layer, and surrounding the plurality of nanosheets, wherein the first thickness in the vertical direction of the portion of the work function metal-containing structure covering the upper surface of the nanosheet stack is greater than the second thickness in the second horizontal direction of the portion covering the sidewalls of the nanosheet stack. Claim 2 An integrated circuit element according to claim 1, wherein both side walls in the second horizontal direction of the work function metal-containing structure are each formed with an uneven surface. Claim 3 An integrated circuit device according to claim 1, wherein the work function metal-containing structure comprises a plurality of work function metal-containing patterns arranged in a row along the vertical direction, each disposed between each of the plurality of nanosheets, a work function metal-containing liner covering the plurality of nanosheets and the plurality of work function metal-containing patterns, and an upper work function metal-containing block covering the upper surface of the work function metal-containing liner, wherein the thickness of the upper work function metal-containing block in the vertical direction is greater than the thickness of each of the plurality of work function metal-containing patterns in the vertical direction. Claim 4 In paragraph 3, in the second horizontal direction, the width of each of the plurality of work function metal-containing patterns is equal to or smaller than the width of each of the plurality of nanosheets, in an integrated circuit device. Claim 5 An integrated circuit device according to claim 1, wherein the gate line further comprises a blanket work function metal-containing layer that surrounds the work function metal-containing structure on the fin-shaped active region, the blanket work function metal-containing layer has a conductivity type different from that of the work function metal-containing structure, and both side walls in the second horizontal direction of the work function metal-containing structure are formed of an uneven surface including a plurality of convex surfaces and a plurality of concave surfaces, and the blanket work function metal-containing layer comprises a plurality of protrusions that are in contact with the plurality of concave surfaces included in the uneven surface and protrude toward the region between each of the plurality of nanosheets. Claim 6 A first nanosheet stack comprising a first fin-shaped active region extending in a first horizontal direction in a first transistor region, a second fin-shaped active region extending in the first horizontal direction in a second transistor region, a plurality of first region nanosheets facing the first fin upper surface at a position spaced vertically from the first fin upper surface of the first fin-shaped active region, a second nanosheet stack comprising a plurality of second region nanosheets facing the second fin upper surface at a position spaced vertically from the second fin upper surface of the second fin-shaped active region, and a gate line extending in a second horizontal direction that encloses the plurality of first region nanosheets and the plurality of second region nanosheets and intersects the first horizontal direction, wherein the gate line comprises a first conductivity type blanket work function metal-containing layer enclosing the plurality of first region nanosheets and a second conductivity type work function metal-containing structure enclosing the plurality of second region nanosheets, and the first thickness in the vertical direction of the portion of the work function metal-containing structure covering the upper surface of the second nanosheet stack is the An integrated circuit element with a second thickness in the second horizontal direction that is larger than the second thickness of the portion covering the sidewall of the second nanosheet stack. Claim 7 In claim 6, the integrated circuit element wherein both side walls in the second horizontal direction of the work function metal-containing structure are each formed with an uneven surface. Claim 8 An integrated circuit device according to claim 6, wherein the sidewall facing the first nanosheet stack among the work function metal-containing structures has an uneven surface, the first surfaces covering the plurality of second region nanosheets on the uneven surface are formed as convex surfaces protruding toward the first nanosheet stack, and the second surfaces covering the regions between each of the plurality of second region nanosheets on the uneven surface are formed as concave surfaces concave toward the first nanosheet stack. Claim 9 An integrated circuit device according to claim 6, wherein the work function metal-containing structure comprises a plurality of work function metal-containing patterns arranged in a row along the vertical direction and disposed one between each of the plurality of second region nanosheets, a work function metal-containing liner covering the plurality of second region nanosheets and the plurality of work function metal-containing patterns, and an upper work function metal-containing block covering the upper surface of the work function metal-containing liner, wherein the thickness of the upper work function metal-containing block in the vertical direction is greater than the thickness of each of the plurality of work function metal-containing patterns in the vertical direction. Claim 10 A first fin-shaped active region extending in a first horizontal direction in an NMOS transistor region, a second fin-shaped active region extending in the first horizontal direction in a PMOS transistor region, a device isolation film covering both sidewalls of the first fin-shaped active region and the second fin-shaped active region in a second horizontal direction intersecting the first horizontal direction, a first nanosheet stack comprising a plurality of first region nanosheets facing the first fin surface at a position spaced vertically from the first fin surface of the first fin-shaped active region, a second nanosheet stack comprising a plurality of second region nanosheets facing the second fin surface at a position spaced vertically from the second fin surface of the second fin-shaped active region, and a gate line extending in the second horizontal direction over the first fin-shaped active region, the second fin-shaped active region, and the device isolation film, wherein the gate line comprises a P-type work function metal-containing structure surrounding the plurality of second region nanosheets, a portion surrounding the plurality of first region nanosheets, and the plurality of second region nanosheets and An integrated circuit element comprising an N-type blanket work function metal-containing layer including a portion surrounding the P-type work function metal-containing structure, wherein the first thickness in the vertical direction of the portion covering the upper surface of the second nanosheet stack among the P-type work function metal-containing structure is greater than the second thickness in the second horizontal direction of the portion covering the sidewall of the second nanosheet stack, and both sidewalls in the second horizontal direction of the P-type work function metal-containing structure are each formed with an uneven surface.

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