Optical link for providing diagnosis and monitoring thereof

Abstract

The present invention discloses an optical link having a diagnostic monitoring function implemented therein. According to the present invention, an optical link for providing a diagnostic monitoring function can be implemented by generating a data frame for transmitting image-imposed data and diagnostic data together through a side channel from Time Division Multiplexing (TDM). More specifically, an optical link for providing a diagnostic monitoring function can be implemented by generating a data frame including time-division multiplexed image-imposed data and diagnostic data, so that, together with the image-imposed data, information regarding the connection status of the optical link forming the side channel and the main channel through which the image data is transmitted, information regarding the operation status of the optical link, and identification information of the optical link itself, can be transmitted through a side channel through which image-imposed data, such as rendering setting information in which image data transmitted through the main channel is rendered and channel setting information of the main channel, is transmitted.

Description

Technology Field

[0001] The present invention relates to an optical link for providing a diagnostic monitoring function. Background Technology

[0002] An optical link provides an interface for optical communication between a source device that generates a video signal and a sink device that implements a video image from the video signal of the source device, and may include a video signal line that transmits video data and an auxiliary signal line that transmits video-imposed data regarding configuration information of the source device or sink device, etc., in addition to the video data. The problem to be solved

[0003] One embodiment of the present invention includes an optical link for providing a diagnostic monitoring function that generates a data frame for transmitting image-imposed data and diagnostic data together through a side channel from time division multiplexing (TDM). More specifically, the optical link for providing a diagnostic monitoring function generates a data frame including time-division multiplexed image-imposed data and diagnostic data, so that, together with the image-imposed data, the image-imposed data, such as rendering setting information for rendering image data transmitted through a main channel and channel setting information of the main channel, can be transmitted through a side channel in which image-imposed data is transmitted, along with information regarding the connection status of the optical link forming the main channel and the side channel in which the image data is transmitted, information regarding the operation status of the optical link, and identification information of the optical link itself. means of solving the problem

[0004] In order to achieve the above-mentioned purpose and other purposes, the optical link for providing the diagnostic monitoring function of the present invention is,

[0005] As an optical link forming a main channel through which video data is transmitted and a side channel through which video-imposed data regarding the channel setting of the main channel is transmitted, a data frame can be generated from time-division multiplexing to transmit together diagnostic data including video-imposed data and status information of the optical link through the side channel.

[0006] For example, the data frame may include a special code area and a data area allocated to a time slot or sub-frame of 8 unit time divisions.

[0007] For example, the special code assigned to the special code area may include control information for the time slot or sub-frame of the unit.

[0008] For example, regarding the above data frame, depending on the presence or absence of diagnostic data,

[0009] A data frame of a non-diagnostic instance in which diagnostic data does not exist may include a special code area and a data area alternately allocated to time slots or sub-frames of 8 time-division units, and

[0010] A data frame of a diagnostic instance in which diagnostic data exists may include a special code area assigned to a time slot or sub-frame of a unit corresponding to the start of the data frame in a time slot or sub-frame of eight time-divided units, and a sequence of data areas assigned to time slots or sub-frames of other units that follow the time slot or sub-frame of the unit to which the special code area is assigned along the time axis.

[0011] For example, communication traffic related to image-imposed data, including a request regarding the image-imposed data and a reply to the request,

[0012] Communication traffic related to diagnostic data, including requests regarding the above diagnostic data and replies to those requests, may be performed more frequently than the number of times.

[0013] For example, an optical link for providing a diagnostic monitoring function according to one embodiment of the present invention is,

[0014] Synchronous Time Division Multiplexing (STDM) can be implemented in a data frame of a non-diagnostic instance where the above-mentioned diagnostic data does not exist, in which the time slot or sub-frame assigned to the diagnostic data is filled with stuffing symbols instead of being filled with image-imposed data other than the diagnostic data.

[0015] For example, the data frame of the non-diagnostic instance and the data frame of the diagnostic instance include a Video Interface Signal segment corresponding to the start of the data frame, and Side First packet, Side Second packet, and Side Third packet segments following the Video Interface Signal segment along the time axis.

[0016] The above Video Interface Signal segment includes a special code area and a data area, and

[0017] The special code area of ​​the above Video Interface Signal segment is assigned to a special code indicating the start of a data frame, and

[0018] The data area of ​​the above Video Interface Signal segment can be allocated to video-imposed data.

[0019] For example, each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the above-mentioned non-diagnostic instance includes a special code area and a data area, and

[0020] The data areas of the above Side First packet, Side Second packet, and Side Third packet segments may be filled with stuffing symbols instead of non-existent diagnostic data.

[0021] For example, each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the above diagnostic instance includes a time slot or sub-frame of two unit units preceding and succeeding along the time axis, and

[0022] The preceding time slot of the above Side First packet is filled with a diagnostic data start symbol, and the succeeding time slot of the above Side Third packet is filled with a diagnostic data end symbol, and

[0023] Along the time axis, from the trailing time slot of the Side First packet to the leading time slot of the Side Third packet, the area can be filled with diagnostic data.

[0024] For example, the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet are each filled with a diagnostic data start symbol and a diagnostic data end symbol, and the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet can be allocated as a data area that can be modified between communication hosts.

[0025] For example, the time-divided time slot or sub-frame mentioned above may be allocated as 8 bits.

[0026] For example, the above data frame may be allocated as a total of 64 bits of 8 unit units, with time-divided time slots or sub-frames each allocated as 8 bits as unit units.

[0027] For example, the optical link may be connected on the side channel and may include an FPGA block for generating the data frame.

[0028] For example, the FPGA block may include a multiplexer for selecting and outputting an input channel assigned to the current time slot or sub-frame among a plurality of input channels that are multiplexed through time-division time slots or sub-frames.

[0029] For example, the above data frame, depending on the presence or absence of diagnostic data,

[0030] In the generation of a data frame of a non-diagnostic instance where diagnostic data does not exist, a special code, image-imposed data, and stuffing symbols replacing diagnostic data are stored in a plurality of input channels of the multiplexer or in a plurality of input registers connected to a plurality of input channels.

[0031] In the generation of a data frame of a diagnostic instance in which diagnostic data exists, a special code, image-imposed data, and diagnostic data may be stored in a plurality of input channels of the multiplexer or in a plurality of input registers connected to a plurality of input channels.

[0032] For example, the FPGA block may include a SerDes (Serializer + Deserializer) for converting special codes, image-imposed data and diagnostic data, or parallel data forming image-imposed data and stuffing symbols output from the output channel of the multiplexer into serial data.

[0033] For example, the above SerDes(Serializer+Deserializer) can take as input a sequence of parallel data in which image-imposed data and diagnostic data or image-imposed data and stuffing symbols form a multiplexed data frame, and output a sequence of serial data in which image-imposed data and diagnostic data or image-imposed data and stuffing symbols form a multiplexed data frame.

[0034] For example, an optical link for providing a diagnostic monitoring function according to one embodiment of the present invention may include an optical communication module comprising the FPGA block, wherein a USB-UART converter is connected between the FPGA block and a USB port.

[0035] For example, the above USB-UART converter is,

[0036] A UART interface as a thread executed to convert UART communication data transmitted from the above FPGA block into USB communication data transmitted toward a manager interface connected to the USB port; and

[0037] A USB interface may be included as a thread executed to convert USB communication data transmitted from a manager interface connected to the USB port into UART communication data transmitted toward the FPGA block.

[0038] For example, UART communication data converted through the USB interface can be converted from serial data to parallel data through the SerDes of the FPGA block and processed according to the logic set in the FPGA block.

[0039] For example, the above FPGA block includes FPGA control logic for performing processing according to a pre-set process or logic, and a memory in which data is read, written, and updated in conjunction with the FPGA control logic.

[0040] Diagnostic data and / or image-imposed data stored in memory can be transmitted, updated, or changed according to a process or logic set in the FPGA control logic called according to a control command transmitted from a manager interface forming a USB communication channel with the optical communication module.

[0041] For example, the optical link forms the main channel and side channel between the display source and the display sink, and

[0042] The above FPGA block includes a first FPGA block connected adjacently to a display source and a second FPGA block connected adjacently to a display sink, and

[0043] The first FPGA block stores in its memory diagnostic data obtained through communication with the second FPGA block, together with diagnostic data regarding the connection status between an adjacently connected display source and an optical link, and diagnostic data regarding the connection status between a display sink connected on the opposite side of the optical link and an optical link.

[0044] The second FPGA block stores in its memory diagnostic data obtained through communication with the first FPGA block, together with diagnostic data regarding the connection status between an adjacently connected display sink and an optical link, and diagnostic data regarding the connection status between a display source connected on the opposite side of the optical link and an optical link.

[0045] In order to follow control commands transmitted from a manager interface forming a communication channel with the first FPGA block or the second FPGA block, the first FPGA block or the second FPGA block may transmit, update, or change diagnostic data regarding the connection status between a display source and an optical link and diagnostic data regarding the connection status between a display sink and an optical link stored in its memory according to a pre-set process or logic.

[0046] An optical link for providing a diagnostic monitoring function according to an embodiment of the present invention is an optical communication module including the FPGA block, wherein, on a data transmission channel of the optical communication module,

[0047] A video signal adjustment unit (Re-timer) is connected to the main channel for transmitting video data, and

[0048] The above FPGA block is connected on a side channel for transmitting image-imposed data, and

[0049] The above main channel and side channel may include an optical communication module in which a photoelectric conversion element is connected together.

[0050] For example, the optical communication module may further include a USB-UART converter connected between the FPGA block and the USB port.

[0051] For example, the above USB-UART converter is,

[0052] A USB interface as a thread executed to convert USB communication data transmitted from a manager interface connected to the USB port into UART communication data transmitted toward the FPGA block; and

[0053] It may include a UART interface as a thread that is executed to convert UART communication data transmitted from the above FPGA block into USB communication data transmitted toward a manager interface connected to a USB port.

[0054] For example, the above USB interface and UART interface are,

[0055] As the entire series of continuous data transmitted from one side to the other between the manager interface connected to the above USB port and the USB-UART converter, after the transmission up to the last byte is completed, or

[0056] The USB-UART conversion can be performed after the transmission of the entire series of continuous data transmitted from one side to the other between the above FPGA block and the USB-UART converter is completed up to the last byte.

[0057] For example, the diagnostic data may include at least one of the connection status of the optical link, the operation status of the optical link, and identification information of the optical link itself.

[0058] For example, the above-mentioned image assignment data may include channel setting data related to channel settings of a main channel for transmitting image data, and rendering setting data related to rendering of a display sink where the image data is rendered. Effects of the invention

[0059] According to the present invention, an optical link for providing a diagnostic monitoring function can be implemented by generating a data frame for transmitting image-imposed data and diagnostic data together through a side channel from Time Division Multiplexing (TDM). More specifically, an optical link for providing a diagnostic monitoring function can be implemented by generating a data frame including time-division multiplexed image-imposed data and diagnostic data, so that, together with the image-imposed data, diagnostic data such as information regarding the connection status of the optical link forming the side channel and the main channel through which the image data is transmitted, information regarding the operation status of the optical link, and identification information of the optical link itself, can be transmitted through a side channel through which image-imposed data, such as rendering setting information where image data transmitted through the main channel is rendered and channel setting information of the main channel, is transmitted. Brief explanation of the drawing

[0060] FIG. 1 illustrates a diagram for explaining a main channel for transmitting image data and a side channel for transmitting image-imposed data and diagnostic data in a display port (DP) to which an optical link may be applied to provide a diagnostic monitoring function according to an embodiment of the present invention. FIG. 2 illustrates a diagram for explaining a main channel for transmitting video data and a side channel for transmitting video-imposed data and diagnostic data in an HDMI to which an optical link capable of providing a diagnostic monitoring function according to an embodiment of the present invention can be applied. FIG. 3 is a diagram for explaining the FPGA block illustrated in FIG. 1 or FIG. 2, and includes a configuration comprising an FPGA control logic in which logic or a process is set for processing image-imposed data and diagnostic data, a memory (RAM) in which image-imposed data and diagnostic data processed from the FPGA control logic are stored, and SerDes for converting between serial data and parallel data input / output to the FPGA block, a UART communication channel formed between the FPGA block and a UART-USB converter within an optical communication module including the FPGA block, and a communication channel formed between a peripheral circuit for generating diagnostic data including operating status of the optical link such as operating temperature and operating voltage. FIGS. 4a and 4b are drawings for explaining an optical communication module including an FPGA block illustrated in FIGS. 3, each comprising an optical transmitting module for transmitting image data and an optical receiving module for receiving image data. In each optical transmitting module (Transmitter) and optical receiving module (Receiver), a configuration is shown that includes an image signal adjustment unit (Re-timer) connected on a main channel for transmitting image data and an FPGA block connected on a side channel for transmitting image-imposed data and diagnostic data, and a USB-UART converter formed on a data transmission channel between an FPGA block connected via a manager interface and USB communication and a photoelectric conversion element connected together on the main channel and the side channel. FIG. 5 is a diagram for explaining a USB-UART converter of an optical transmission module and an optical reception module (optical communication module) illustrated in FIG. 4a and 4b, and includes a USB interface for converting USB communication data transmitted from a manager interface connected via USB to the optical communication module and the optical reception module (optical communication module) into UART communication data, and a UART interface for converting UART communication data transmitted from an FPGA block of the optical transmission module and the optical reception module into USB communication data. FIG. 6 is a diagram for explaining the UART interface and USB interface of the USB host controller illustrated in FIG. 5, and a diagram for explaining the memory structure for explaining the UART interface and USB interface as two different threads (Thread A and Thread B) that provide an execution environment within the same process, wherein the Code area (e.g., storing functions), the Data area (e.g., storing global variables), and the Heap area (dynamically allocated memory) of memory are shared, while the Stack area (e.g., storing function parameters) is allocated separately. Figure 7 illustrates a diagram for explaining that, in the same process shown in Figure 6, there are two different threads (Thread A and Thread B) provided with an execution environment, and that the main functions of each thread (thread A's main and thread B's main) and functions called from each main function (add, minus, divide, multiple) are stored in a code area shared with each other at the UART interface and USB interface. FIG. 8 is a diagram illustrating time division multiplexing (TDM) of image-imposed data and diagnostic data for transmitting image-imposed data and diagnostic data together through a side channel. It illustrates that image-imposed data and diagnostic data are time-division multiplexed through a multiplexer from an input channel or an input register connected to the input channel where image-imposed data and diagnostic data are stored, and that a data frame in which image-imposed data and diagnostic data are multiplexed is formed through time-division time slots or sub-frames, and that a data frame of serial data is formed from a SerDes that takes a data frame of parallel data as input. FIG. 9 is a diagram for schematically explaining the processing flow of image-imposed data and diagnostic data transmitted through a side channel, and shows a diagram for explaining an FPGA block including an encoder / decoder that takes as input the flow of multiplexed image-imposed data and diagnostic data output from a MUX for multiplexing the first to eighth input channels input from the input register of the FPGA control logic, and a SerDes for converting the parallel data and serial data of the image-imposed data and diagnostic data to each other. FIG. 10a shows a diagram illustrating synchronous time division (STDM, Synchronous TDM) as an embodiment of the time division multiplexing illustrated in FIG. 9. Figure 10b shows a diagram illustrating asynchronous time division multiplexing (ATDM) as opposed to synchronous time division multiplexing (STDM) illustrated in Figure 10a. Figure 11 illustrates a diagram for explaining a data frame of a non-diagnostic instance that includes only image-imposed data and does not include diagnostic data. Figure 12 illustrates a diagram for explaining a data frame of a diagnostic instance that includes diagnostic data along with image data. FIG. 13 is a diagram illustrating the implementation of synchronous time division multiplexing (STDM) in which time slots or subframes allocated to diagnostic data in a data frame of a non-diagnostic instance where diagnostic data does not exist are filled with stuffing symbols in one embodiment of the present invention, and is a diagram illustrating compatibility with an optical link in which a certain transmission capacity is allocated in a data frame that does not contain diagnostic data. FIG. 14 illustrates a diagram for explaining the overall structure of a system for implementing diagnostic monitoring of an optical link according to one embodiment of the present invention. Figure 15 shows a diagram for explaining the USB host controller illustrated in Figure 14. FIG. 16 illustrates a diagram illustrating that multiple data transmission channels connected to each optical link are multiplexed through a single connection channel between the FPGA circuit and the MCU from time division multiplexing (TDM) between the FPGA circuit and the MCU shown in FIG. 14. FIG. 17 is a diagram illustrating the data structure of UART (universal achromous receiver / transmitter) communication data that is converted from the USB interface of a USB host controller that takes USB communication data as input and transmitted toward a UART-parallel converter, and the diagram illustrates the UART communication data structure including a Stop bit, a Data bit, a Parity bit, a Stop bit, and an IDLE section. FIG. 18 is a diagram illustrating a USB connection between a USB host controller and an optical link as illustrated in FIG. 14, wherein the USB host controller is the host (DFP, Down Facing Port) and the optical link is the device (UFP, Up Facing Port). The diagram shows a MUX that controls switching between the input / output channels of the MUX to allow an Un-flipped or Flipped connection corresponding to the plug orientation according to the connection status between them, and a CC Logic and Vconn switch for powering an EMIC (Electronically Marked IC). FIG. 19 is a diagram illustrating the pin configuration of a USB port (USB C-type) and the Configuration Control (CC) in the USB connection between the USB host controller and the optical link shown in FIG. 14, and is a diagram illustrating the Configuration Channel (CC1, CC2) involved in detecting USB connection / disconnection, setting the roll and plug orientation (Un-flipped or Flipped) between USB communication hosts, and PD communication (power delivery communication or baseband communication). FIG. 20 is a diagram for explaining USB communication between a USB host controller and an optical link as illustrated in FIG. 14, and for detecting USB connection and plug orientation (Un-flipped or Flipped) and role determination in USB communication where the USB host controller is the host and the optical link is the device, a pull-up resistor (Rp) connected to the CC of the USB host controller forming the host, a pull-down resistor (Rd) connected to the CC of the optical link forming the device, and a resistor (Ra) capable of detecting active cable circuitry such as an EMIC (Electronically Marked IC) are shown. FIG. 21 is a diagram illustrating USB communication between a USB host controller and an optical link as illustrated in FIG. 14, and is a diagram illustrating power delivery (or baseband communication) related to power supply and role determination between the CC of the USB host controller and the CC of the optical link, and is a diagram illustrating PD communication encoded in BMC (Biphase Mark Coding). Specific details for implementing the invention

[0061] Hereinafter, an optical link for providing a diagnostic monitoring function according to an embodiment of the present invention will be described with reference to the drawings attached to this specification.

[0062] FIG. 1 illustrates a diagram for explaining a main channel for transmitting image data and a side channel for transmitting image-imposed data and diagnostic data in a display port (DP) to which an optical link may be applied to provide a diagnostic monitoring function according to an embodiment of the present invention.

[0063] FIG. 2 illustrates a diagram for explaining a main channel for transmitting video data and a side channel for transmitting video-imposed data and diagnostic data in an HDMI to which an optical link can be applied to provide a diagnostic monitoring function according to an embodiment of the present invention.

[0064] FIG. 3 is a diagram for explaining the FPGA block illustrated in FIG. 1 or FIG. 2, and includes a configuration comprising an FPGA control logic in which logic or a process is set for processing image-imposed data and diagnostic data, a memory (RAM) in which image-imposed data and diagnostic data processed from the FPGA control logic are stored, and SerDes for converting between serial data and parallel data input / output to the FPGA block, a UART communication channel formed between the FPGA block and a UART-USB converter within an optical communication module including the FPGA block, and a communication channel formed between a peripheral circuit for generating diagnostic data including operating status of the optical link such as operating temperature and operating voltage.

[0065] FIGS. 4a and 4b are drawings for explaining an optical communication module including an FPGA block illustrated in FIG. 3, each comprising an optical transmitting module for transmitting image data and an optical receiving module for receiving image data. In each optical transmitting module (Transmitter) and optical receiving module (Receiver), a configuration is shown that includes an image signal adjustment unit (Re-timer) connected on a main channel for transmitting image data, an FPGA block connected on a side channel for transmitting image-imposed data and diagnostic data, an optical converter connected together on the main channel and the side channel, and a USB-UART converter formed on a data transmission channel between the FPGA block connected via a manager interface and USB communication.

[0066] FIG. 5 is a diagram for explaining a USB-UART converter of an optical transmission module and an optical reception module (optical communication module) illustrated in FIG. 4a and 4b, and includes a USB interface for converting USB communication data transmitted from a manager interface connected via USB to the optical communication module and the optical reception module (optical communication module) into UART communication data, and a UART interface for converting UART communication data transmitted from an FPGA block of the optical transmission module and the optical reception module into USB communication data.

[0067] FIG. 6 is a diagram for explaining the UART interface and USB interface of the USB host controller illustrated in FIG. 5, and a diagram for explaining the memory structure for explaining the UART interface and USB interface as two different threads (Thread A and Thread B) that provide an execution environment within the same process, wherein the Code area (e.g., storing functions), the Data area (e.g., storing global variables), and the Heap area (dynamically allocated memory) of memory are shared, while the Stack area (e.g., storing function parameters) is allocated separately.

[0068] Figure 7 illustrates a diagram for explaining that, in the same process shown in Figure 6, there are two different threads (Thread A and Thread B) provided with an execution environment, and that the main functions of each thread (thread A's main and thread B's main) and functions called from each main function (add, minus, divide, multiple) are stored in a code area shared with each other at the UART interface and USB interface.

[0069] FIG. 8 is a diagram illustrating time division multiplexing (TDM) of image-imposed data and diagnostic data for transmitting image-imposed data and diagnostic data together through a side channel. It illustrates that image-imposed data and diagnostic data are time-division multiplexed through a multiplexer from an input channel or an input register connected to the input channel where image-imposed data and diagnostic data are stored, and that a data frame in which image-imposed data and diagnostic data are multiplexed is formed through time-division time slots or sub-frames, and that a data frame of serial data is formed from a SerDes that takes a data frame of parallel data as input.

[0070] FIG. 9 is a diagram for schematically explaining the processing flow of image-imposed data and diagnostic data transmitted through a side channel, and shows a diagram for explaining an FPGA block including an encoder / decoder that takes as input the flow of multiplexed image-imposed data and diagnostic data output from a MUX for multiplexing the first to eighth input channels input from the input register of the FPGA control logic, and a SerDes for converting the parallel data and serial data of the image-imposed data and diagnostic data to each other.

[0071] FIG. 10a shows a diagram illustrating synchronous time division (STDM, Synchronous TDM) as an embodiment of the time division multiplexing illustrated in FIG. 9.

[0072] Figure 10b shows a diagram illustrating asynchronous time division multiplexing (ATDM) as opposed to synchronous time division multiplexing (STDM) illustrated in Figure 10a.

[0073] Figure 11 illustrates a diagram for explaining a data frame of a non-diagnostic instance that includes only image-imposed data and does not include diagnostic data.

[0074] Figure 12 illustrates a diagram for explaining a data frame of a diagnostic instance that includes diagnostic data along with image data.

[0075] FIG. 13 is a diagram illustrating the implementation of synchronous time division multiplexing (STDM) in which time slots or subframes allocated to diagnostic data in a data frame of a non-diagnostic instance where diagnostic data does not exist are filled with stuffing symbols in one embodiment of the present invention, and is a diagram illustrating compatibility with an optical link in which a certain transmission capacity is allocated in a data frame that does not contain diagnostic data.

[0076] An optical link for providing a diagnostic monitoring function according to one embodiment of the present invention is connected between a display source and a display sink that form a system supporting HDMI (see FIG. 2) or a Display Port (DP, see FIG. 1), and can transmit video data including video information, rendering setting data such as EDID (Extended Display Identification Data) in relation to rendering of the display sink, and channel setting data such as DPCD (Display Port Configuration Data) in relation to channel setting of a main channel (or main lane) that transmits video data, and can generate diagnostic data including status information of the optical link, such as the connection status of the optical link, to provide monitoring of the status information of the optical link.

[0077] An FPGA block may be connected to an optical link according to one embodiment of the present invention, and the FPGA block may not be connected to a main channel (or main lane) that transmits image data, but may be connected to a side channel (auxiliary channel or DDC channel) for transmitting image-imposed data including rendering setting data such as EDID and channel setting data such as DPCD, and may be involved in the overall management of image-imposed data such as storage, modification, and updating of the image-imposed data.

[0078] The above FPGA block may include a first FPGA block connected adjacent to the display source side and a second FPGA block connected adjacent to the display sink side, and a main channel (or main lane) for transmitting image data including image information may be connected from the display source to the display sink without passing through the FPGA block.

[0079] For example, the above FPGA block may be involved in the overall management of image-imposed data, such as the storage, modification, and transmission of image-imposed data including rendering-imposed data and channel-imposed data, such as by participating in link training for setting up a main channel (or main lane) to change the settings of the main channel (or main lane) to be optimized for an optical link, or by storing rendering-imposed data such as EDID (Extended Display Identification Data) related to rendering of a display sink, or channel-imposed data such as DPCD (Display Port Configuration Data) for setting up a main channel (or main lane) for transmitting image data, or by transmitting the stored rendering-imposed data or channel-imposed data, or by modifying the stored data.

[0080] In one embodiment of the present invention, the FPGA block may be involved in the management of diagnostic data, such as storing, changing, and transmitting diagnostic data including, for example, status information of an optical link, which may not be directly related to the setting or management of a main channel (or main lane) for transmitting image information as image-imposed data, for example, and may be involved in the management of diagnostic data, such as storing, changing, and transmitting diagnostic data to provide monitoring of status information of an optical link including, for example, the connection status of an optical link.

[0081] In one embodiment of the present invention, the FPGA block may provide diagnostic monitoring for image-imposed data including status information of the optical link and channel setting data and rendering setting data of the main channel through a data transmission channel and a manager interface (see FIG. 1 and FIG. 2) for monitoring the connection status of the optical link. In various embodiments of the present invention, the manager interface may comprehensively refer to a system connected in parallel with a plurality of optical links to provide diagnostic monitoring for a plurality of optical links (a system for implementing diagnostic monitoring for optical links, hereinafter referred to as a diagnostic monitoring system) or a computing terminal connected individually to each optical link.

[0082] In one embodiment of the present invention, the manager interface (see FIG. 1 and FIG. 2) may form a data transmission channel with at least one of the first and second FPGA blocks connected adjacently to the display source side or the display sink side, and, for example, may obtain status information of an optical link mainly related to the display source, such as the connection status between the display source and the optical link connected adjacently to the first FPGA while connected to the first FPGA block connected adjacently to the display source side, or obtain status information of an optical link mainly related to the display sink, such as the connection status between the display sink and the optical link connected adjacently to the second FPGA block connected adjacently to the display sink side.

[0083] In one embodiment of the present invention, the first FPGA block and the second FPGA block are connected to each other through an optical link, and can communicate information regarding the connection status between the optical link and a display source or display sink connected adjacently to each of the first and second FPGA blocks. Accordingly, through a connection with any one of the first and second FPGA blocks, it is possible to obtain both the status information of the optical link mainly related to the display source (e.g., operating temperature of a location adjacent to the display source), such as the connection status between each display source and the optical link, and the status information of the optical link mainly related to the display sink (e.g., operating temperature of a location adjacent to the display sink), such as the connection status between the display sink and the optical link.

[0084] For example, in one embodiment of the present invention, the manager interface (see FIG. 1 and FIG. 2) is connected to a first FPGA block or a second FPGA block and can obtain information regarding the connection status of the display source side (connection status between the display source and the optical link) stored in the first FPGA block and the connection status of the display sink side (connection status between the display sink and the optical link) stored in the second FPGA block obtained from communication between the first and second FPGA blocks, and can request an update or change of the data regarding the connection status stored in the first and second FPGA blocks based on the obtained data regarding the connection status.

[0085] In one embodiment of the present invention, the FPGA block can generate, store, update, and change image assignment data including channel setting data related to the setting of a main channel (or main lane), such as DPCD transmitted from the display source side or the display sink side, and rendering setting data related to the rendering of a display sink, such as EDID transmitted from the display sink side, and diagnostic data including the connection status between the display source or the display sink and the optical link, the operating status of the optical link (operating status such as operating voltage or operating temperature), and identification information of the optical link itself. The FPGA block can store the latest data over time by updating the data stored in the FPGA block in response to environmental changes, such as changes in the setting environment of the main channel (or main lane) or changes in the connection status of the optical link.

[0086] The above FPGA block (first FPGA block or second FPGA block, see FIG. 3) can receive image-imposed data transmitted from a display source or display sink connected adjacent to itself, or receive image-imposed data transmitted from a display sink or display source on the opposite side of the optical link, and can store or update the received image-imposed data, or read the image-imposed data and process it according to a pre-set logic, for example, read the image-imposed data and change the image-imposed data according to a pre-set logic. Additionally, regarding diagnostic data including status information of the optical link including the connection status with the optical link, the FPGA block (see FIG. 3) receives a request (e.g., a read or write request) from the opposite FPGA block (a second FPGA block or a first FPGA block) transmitted through the optical link, and according to the logic defined in the FPGA block, it can store the diagnostic data in the memory (RAM) of the FPGA block, or obtain and transmit the requested diagnostic data from the memory (RAM) of the FPGA block, or update or change the diagnostic data stored in the memory (RAM) of the FPGA block, or process it according to a pre-set logic in response to a request from a manager interface connected through a data transmission channel with the FPGA block, for example, in response to a request from the manager interface, it can obtain the diagnostic data stored in its own memory (RAM) and transmit it to the manager interface, or request diagnostic data toward the FPGA block connected to the opposite side of the optical link or the display source or display sink, and transmit the obtained data to the manager interface upon obtaining the requested data.

[0087] In one embodiment of the present invention, each logic set in an FPGA block (see FIG. 3) can be executed in parallel as an independent process or independent sequence, and diagnostic data regarding the connection status of an optical link can be stored in memory (RAM) according to independent logic or independent process, and upon a request from a manager interface, the diagnostic data stored in memory (RAM) can be called from an independent process and transmitted to a manager interface (see FIG. 1 and FIG. 2). Thus, in one embodiment of the present invention, each logic or process set in the FPGA block (see FIG. 3) can be executed in parallel and independently of one another, and processing or management of diagnostic data can be implemented while implementing CRUD (create, read, update, delete) operations or transmission operations for the memory of the FPGA block.

[0088] In one embodiment of the present invention, the FPGA block (see FIG. 3) may include a SerDes (Serializer + Deserializer) for converting input / output data of the FPGA block between parallel data and serial data. In one embodiment of the present invention, the SerDes may convert serial data transmitted through an optical link into parallel data input to the FPGA block, and may also convert parallel data transmitted from the FPGA block into serial data transmitted through an optical link. For example, in one embodiment of the present invention, the SerDes may include a shift register for implementing a serializer (parallel to serial) and may include a shift register that outputs parallel data of image-imposed data input from an FPGA block according to a parallel clock as serial data according to a serial clock. Additionally, the SerDes may include a shift register for implementing a deserializer (serial to parallel) and may include a shift register that sequentially receives serial data of image-imposed data transmitted through an optical link and outputs parallel data of image-imposed data according to a parallel clock.

[0089] In one embodiment of the present invention, an optical communication module (see FIG. 4a and FIG. 4b) may be connected between the display source or the display sink, and the optical communication module may include an optical transmission module (see FIG. 4a) connected to the display source side and an optical reception module (see FIG. 4b) connected to the display sink side. In addition, the optical communication module (see FIG. 4a and FIG. 4b) may include the previously described FPGA block (see FIG. 3) and, together with the FPGA block, may include a photoelectric conversion element that implements a photoelectric conversion between an electrical signal and an optical signal.

[0090] The above photoelectric conversion element (see FIG. 4a and FIG. 4b) is intended to implement modulation between an electrical input / output signal and an optical input / output signal, and may include a light-emitting element for converting an electrical signal into an optical signal and transmitting an optical signal through an optical link (an optical fiber of the optical link), and a light-receiving element for converting an optical signal received through an optical link (an optical fiber of the optical link) into an electrical signal.

[0091] In one embodiment of the present invention, a photoelectric conversion element (see FIG. 4a and FIG. 4b) for implementing photoelectric conversion of image data may be connected on a main channel (or main lane) for transmitting image data containing image information, and an image signal adjustment unit (Re-timer) may also be connected to compensate for delays in image data and delays caused along the transmission path of image data to ensure stable signal transmission. More specifically, the image signal adjustment unit (Re-timer) may receive image data from a display source side corresponding to the transmitting end side and retransmit the received image data to a display sink side corresponding to the receiving end side, and at this time, to compensate for delays along the transmission path of the data, playback and readjustment of the image data may be implemented. For example, in one embodiment of the present invention, an image signal adjustment unit (Re-timer) and a photoelectric conversion element may be connected together on a main channel (or main lane) responsible for transmitting image data in an optical communication module for transmitting image data.

[0092] In one embodiment of the present invention, on the data transmission channel of the optical communication module (see FIG. 4a and 4b), a video signal adjustment unit (Re-timer) and a photoelectric conversion element may be connected on the main channel (or main lane) responsible for transmitting video data, and on the side channel (auxiliary channel or DDC channel) responsible for transmitting video-imposed data and diagnostic data, the previously described FPGA block and the photoelectric conversion element connected on the main channel (or main lane) may be connected together. In other words, the photoelectric conversion element of the optical communication module (see FIG. 4a and 4b) is connected together on the main channel (or main lane) responsible for transmitting video data and the side channel (auxiliary channel or DDC channel) responsible for transmitting video-imposed data and diagnostic data, and, for example, the video data output from the video signal adjustment unit (Re-timer) and the video-imposed data and diagnostic data output from the FPGA block may all be modulated from an electrical signal to an optical signal by the photoelectric conversion element. As described below, in an optical link for providing a diagnostic monitoring function according to an embodiment of the present invention, a data frame for transmitting the image-imposed data and the diagnostic data together through the side channel can be generated from time-division multiplexing (see FIG. 8) so that the image-imposed data and the diagnostic data including the status information of the optical link can be transmitted together through the side channel. For example, the image-imposed data and the diagnostic data multiplexed into a single data frame through time-division multiplexing (see FIG. 8) from the FPGA block can be converted from an electrical signal to an optical signal through a photoelectric conversion element (see FIG. 4a and FIG. 4b).

[0093] Similarly, an optical signal regarding image data transmitted from an optical link can be converted into an electrical signal by a photoelectric conversion element (see FIG. 4a and FIG. 4b), and after the image data is replayed or readjusted through an image signal adjustment unit (Re-timer), it can be transmitted to a display sink through a conductive line capable of communicating the electrical signal. An optical signal regarding image-imposed data and diagnostic data transmitted from an optical link can be converted into an electrical signal by a photoelectric conversion element and input into an FPGA block. The image-imposed data and diagnostic data input into the FPGA block (see FIG. 3) can be stored in the memory (RAM) of the FPGA block, or the data stored in the memory (RAM) of the FPGA block can be updated, or the data can be changed according to a logic or process pre-set in the FPGA block, or the data can be transmitted outside the FPGA block (a manager interface connected to a USB port of an optical communication module including the FPGA block as described below, see FIG. 1 and FIG. 2).

[0094] Accordingly, on the data transmission channel of the optical communication module (see FIG. 4a and 4b), a video signal adjustment unit (Re-timer) and a photoelectric converter may be connected to the main channel (or main lane) responsible for transmitting video data, and an FPGA block and a photoelectric converter may be connected to the side channel (auxiliary channel or DDC channel) responsible for transmitting video-imposed data and diagnostic data. Meanwhile, a USB-UART converter may be connected to the data transmission channel between the optical communication module (see FIG. 4a and 4b) and the manager interface (see FIG. 1 and 2) connected to the USB port of the optical communication module. For example, in one embodiment of the present invention, the optical communication module (see FIG. 4a and 4b) may include a USB-UART converter connected between the FPGA block and the USB port. In one embodiment of the present invention, UART (universal achromous receiver / transmitter) communication data transmitted from an FPGA block through the USB-UART converter (see FIG. 4a and 4b) can be converted into USB communication data and transmitted to a manager interface connected to the FPGA block via a data transmission channel (e.g., a manager interface connected via USB to an optical communication module including the FPGA block, see FIG. 1 and 2), and conversely, USB communication data transmitted from a manager interface connected via USB through the USB-UART converter (see FIG. 4a and 4b) can be converted into UART communication data and transmitted to the FPGA block.

[0095] The above USB-UART converter (see FIG. 4a and 4b) can readjust data structures such as the format, coding, signal level, and sequence of data following the USB communication protocol, control information such as the interpretation of the corresponding signal pattern, transmission control and error correction based on the interpretation, and timing such as speed adjustment between communication hosts, message transmission time, and transmission order, into data structures, control information, and timing following the UART communication protocol; conversely, it can readjust data structures, control information, and timing following the UART communication protocol into data structures, control information, and timing following the USB communication protocol. For example, the above USB-UART converter (see FIG. 4a and 4b) can perform a process for readjusting data structures, control information, and timing between different communication protocols.

[0096] For example, a USB-UART converter (see FIG. 4a and FIG. 4b) can create and execute two different threads, each containing a main function, provided with an execution environment within the same process (see FIG. 5), and within the process providing the execution environment for the two different threads, the two different threads can share the code area, data area, and heap area of ​​memory, while the stack area can be allocated individually for each thread (see FIG. 6 and FIG. 7).

[0097] In other words, the optical communication module (see FIG. 4a and FIG. 4b) may include a USB-UART converter connected between the FPGA block and the USB port, and

[0098] The above USB-UART converter is,

[0099] A USB interface (see FIG. 5) as a thread executed to convert USB communication data transmitted from a manager interface connected to the USB port into UART communication data transmitted toward the FPGA block; and

[0100] It may include a UART interface (see FIG. 5) as a thread executed to convert UART communication data transmitted from the above FPGA block into USB communication data transmitted toward a manager interface connected to a USB port.

[0101] That is, the USB-UART converter (see FIG. 5) is provided with an execution environment within the same process and can create and execute two different threads, each containing a main function. The two different threads can each include a thread for converting from USB communication data following the USB communication protocol to UART communication data following the UART communication protocol (USB interface), and conversely, a thread for converting from UART communication data following the UART communication protocol to USB communication data following the USB communication protocol (UART interface). For example, these different threads can be executed independently of each other, and each thread for USB-UART conversion can convert USB communication data or UART communication data input to a USB-UART converter (see FIG. 5) into UART communication data or USB communication data in a unit unit (e.g., a data frame unit) where error detection or error correction is defined, or into a whole series of continuous data transmitted from one side to the other between communication hosts. If USB-UART conversion is performed in the middle of a whole series of continuous data transmitted from one side to the other between communication hosts or a unit unit (e.g., a data frame unit) where error detection or error correction is defined, the data containing errors can be converted before error detection or error correction of the USB communication data or UART communication data and transmitted to the next stage, so that USB-UART conversion can be performed at least in a unit unit (e.g., a data frame unit or a whole series of continuous signals) where error detection or error correction is possible.

[0102] In other words, the above USB interface and UART interface (see FIG. 5) are,

[0103] As the entire series of continuous data transmitted from one side to the other between the manager interface connected to the above USB port and the USB-UART converter, after the transmission up to the last byte is completed, or

[0104] The USB-UART conversion can be performed after the transmission of the entire series of continuous data transmitted from one side to the other between the above FPGA block and the USB-UART converter is completed up to the last byte.

[0105] In one embodiment of the present invention, the USB-UART converter (see FIG. 5) can convert USB communication data into UART communication data that follows the universal achromous receiver / transmitter (UART) protocol, which is an asynchronous serial communication, without accompanying a separate clock signal, and can read data from the baud rate defined by the UART protocol and the start bit (e.g., bit 0) and stop bit (e.g., bit 1). For example, in one embodiment of the present invention, the UART communication channel transmitting the UART communication data can be set to a baud rate of 115200 bps, a data bit of 8 bits, a non-parity bit, and a one stop bit.

[0106] In one embodiment of the present invention, the optical link may include an optical communication module (see FIG. 4a and FIG. 4b) including an FPGA block, and the optical communication module may include an optical transmission module forming a transmitting end and an optical reception module forming a receiving end, wherein the transmitting end and the receiving end may respectively refer to a display source side that transmits image data and a display sink side that receives image data, and for example, the image data may form a unidirectional data flow from the display source side to the display sink side, and unlike such image data, the image-imposed data and diagnostic data may form a bidirectional data flow between the display source side and the display sink side, and for example, a side channel (auxiliary channel or DDC channel) responsible for transmitting the image-imposed data and diagnostic data may support bidirectional communication of a unidirectional data flow from the display source to the display sink and a reverse data flow from the display sink to the display source.

[0107] In one embodiment of the present invention, the optical transmission module (see FIG. 4a) connected to the display source side and the optical reception module (see FIG. 4b) connected to the display sink side may have substantially the same configuration, provided that the main channel (or main lane) responsible for transmitting image data in each optical transmission module and optical reception module may transmit or receive the flow of image data in opposite directions.

[0108] In one embodiment of the present invention, the space between a display source forming one end of the optical link and an optical transmission module (see FIG. 4a) may be formed as a conductive line capable of accommodating the flow of an electrical signal, and the space between a display sink forming the other end of the optical link and an optical reception module (see FIG. 4b) may also be formed as a conductive line capable of accommodating the flow of an electrical signal, wherein the space between the optical transmission module and the optical reception module may be formed as an optical fiber capable of accommodating the flow of an optical signal.

[0109] In one embodiment of the present invention, the FPGA block (see FIG. 3) may be involved in the overall management of diagnostic data, such as the generation, storage, and updating of diagnostic data including at least one of the connection status of the optical link, the operation status of the optical link (operation temperature and operation voltage, etc.), and identification information of the optical link itself, and the transmission of diagnostic data. For example, a manager interface (see FIG. 1 and FIG. 2) may form a host of the USB connection while forming a USB connection with the FPGA block, and the FPGA block may form a device of the USB connection. For example, the FPGA block may perform data communication as a host connected via a USB port, receiving a request for diagnostic data and / or image-imposed data through the USB connection with the manager interface and transmitting the requested diagnostic data and / or image-imposed data.For example, USB communication data transmitted from the above-mentioned manager interface can be converted into UART communication data through a USB-UART converter (see FIG. 4a and FIG. 4b), and the converted UART communication data can be input into an FPGA block (see FIG. 3) and converted from serial data to parallel data through the SerDes of the FPGA block. The converted parallel data can perform operations such as reading data from memory (RAM), writing data to memory (RAM), or transmitting diagnostic data and / or image-imported data stored in memory (RAM) to the manager interface according to logic or processes set in the FPGA block. For example, according to logic or processes called upon a request received from the manager interface, diagnostic data and / or channel setting data and rendering setting data including at least one of the information stored in the memory (RAM) of the FPGA block, such as the connection status of the optical link stored in memory (RAM), the operation status of the optical link (operating temperature and operating voltage, etc.), and identification information of the optical link itself, can be obtained and transmitted to the manager interface.

[0110] In one embodiment of the present invention, diagnostic data including at least one of the connection status of an optical link, the operation status of an optical link, and identification information of the optical link itself may be stored in the memory (RAM) of an FPGA block (see FIG. 3), and the diagnostic data stored in the memory (RAM) of the FPGA block may be transmitted in accordance with a request (control command) from a manager interface connected to a USB port of the FPGA block, for example, the memory of the FPGA block may store diagnostic data including status information mainly related to a display source or display sink, such as the connection status between a display source or display sink connected adjacently to the FPGA block itself and an optical link, together with diagnostic data including status information mainly related to a display sink or display source, such as the connection status between a display sink or display source connected to the opposite side of the optical link and an optical link, for example, according to data communication between a first FPGA block connected to the display source side and a second FPGA block connected to the display sink side, the manager interface may selectively connect to a first FPGA block (e.g., the first FPGA block) among the first and second FPGA blocks Through an optical transmission module including an optical transmission module) or a second FPGA block (e.g., an optical reception module including a second FPGA block), both diagnostic data including status information mainly related to a display source, such as the connection status between a display source and an optical link, and diagnostic data including status information mainly related to a display sink, such as the connection status between a display sink and an optical link, can be obtained, for example, the firstThe second FPGA block can obtain diagnostic data containing status information, primarily related to display sinks or display sources connected to opposite sides, such as the connection status between the optical link and the display sink or display source on opposite sides, through data communication with each other according to periodically set time intervals, and store it in its memory, and can update or change the diagnostic data stored in its memory to the latest data.

[0111] In various embodiments of the present invention, the memory (RAM) of the FPGA block (see FIG. 3) may store both diagnostic data containing state information primarily related to a display source or display sink, such as the connection status with a display source or display sink connected adjacent to the corresponding FPGA block, and diagnostic data containing state information primarily related to a display sink or display source, such as the connection status with a display sink or display source located far from the corresponding FPGA block (see FIG. 3). In this case, the administrator interface may obtain all diagnostic data (e.g., diagnostic data containing other optical link state information), which includes state information of an optical link related to a display source and / or a display sink, such as the connection status between the optical link and the display source and display sink forming both ends of an optical link connection, from a first FPGA block (e.g., an optical transmission module including the first FPGA block, see FIG. 4a) or a second FPGA block (e.g., an optical reception module including the second FPGA block, see FIG. 4b) which is selectively connected among the first and second FPGA blocks. Diagnostic data including status information related to the display source and display sink, including the connection status of the display source and display sink and the optical link stored in the memory (RAM, see FIG. 3) of each FPGA block or the second FPGA block, can be transmitted in response to a request (control command) from the manager interface.However, in various embodiments of the present invention, the first and second FPGA blocks (see FIG. 3) may generate diagnostic data and transmit the generated diagnostic data in response to a request from a manager interface that has formed a USB connection. For example, a process or logic set in the first and second FPGA blocks (see FIG. 3) may be called in response to a request (control command) from the manager interface, and may generate diagnostic data (including other optical link status information) primarily related to the display source or display sink, such as the connection status between the display source or display sink connected to itself and the optical link, or request diagnostic data (including other optical link status information) primarily related to the display sink or display source, such as the connection status between the display sink or display source connected to the opposite side of the optical link and the optical link, from another FPGA block connected via the optical link.

[0112] In one embodiment of the present invention, the image-imposed data and diagnostic data may be transmitted through the same side channel (auxiliary channel or DDC channel), and the data frame transmitted through the side channel may include time-division multiplexing (TDM, see FIG. 8 and FIG. 9) time slots or sub-frames, and through the time-division multiplexing time slots or sub-frames, one side channel may be multiplexed into multiple channels, and different types of image-imposed data and diagnostic data may be transmitted together through one side channel, and in one embodiment of the present invention, the data frame of the side channel may be multiplexed in 8-bit units through 8-bit unit time slots or sub-frames. More specifically, in one embodiment of the present invention, a data frame transmitted through a side channel may include a special code area and a data area transmitted to time-division time slots or sub-frames (see FIGS. 8 and 9), and more specifically, the data frame may include a special code area (K-CODE) and a data area (D-CODE) to which a special code (special code or special character) is assigned as a control symbol, which are assigned to time-division time slots or sub-frames alternately (see FIGS. 11 and 12).

[0113] In one embodiment of the present invention, the special code area (K-CODE, see FIG. 11 and FIG. 12) may refer to the remaining portion of a data frame excluding the data area (D-CODE), and may include control information for each portion of the data frame, for example, a time slot or sub-frame of the data frame (see FIG. 8 and FIG. 9), according to a rule predefined between the communication hosts of the data frame (display source, a first FPGA block connected to the display source side, a display sink, or a second FPGA block connected to the display sink side), and may include control information for each portion of the data frame, for example, a time slot or sub-frame of the data frame, on a data frame of a side channel containing image-imposed data and diagnostic data, such as a special code (BS, BE) representing the start or end of a blanking portion on a data frame containing image data.

[0114] In one embodiment of the present invention, a data frame of a side channel (see FIG. 11 and FIG. 12) containing the image-imposed data and diagnostic data may have a structure in which a special code area (K-CODE, special code, special character) corresponding to a control symbol and a data area (D-CODE) are allocated to different time slots or sub-frames along the time axis, for example, one data frame may have a total transmission capacity of 64 bits, including 8 units of 8-bit time slots or sub-frames. For example, in one embodiment of the present invention, a data frame (see FIG. 11 and FIG. 12) containing both diagnostic data and image-imposed data from time-division multiplexing (see FIG. 8 and FIG. 9) so that diagnostic data and image-imposed data can be transmitted together through one side channel may have a structure in which a special code area (K-CODE) and a data area (D-CODE) of 1 byte each are alternately allocated. However, in one embodiment of the present invention, a data frame of a side channel of a non-diagnostic instance (see FIG. 11) that includes image-imposed data but does not include diagnostic data may have a structure in which a special code area (special code, special character, K-CODE) and a data code (D-CODE) are alternately assigned, as described above; and a data frame of a side channel of a diagnostic instance (see FIG. 12) that includes diagnostic data along with image-imposed data may have a data frame structure different from that of the data frame of the side channel of the non-diagnostic instance (see FIG. 11). As described above, the data frame of a side channel of a non-diagnostic instance (see FIG. 11) may have a data frame structure in which a special code area (special code, special character, K-CODE) and a data area (D-CODE) are alternately assigned, and alternatively,In the data frames of the side channels of the diagnostic instance (see FIG. 12), the special code area and the data area may be alternately allocated in the Video Interface Signal segment corresponding to the start of the frame, but in the Side First packet segment, Side Second packet segment, and Side Third packet segment following the Video Interface Signal segment corresponding to the start of the frame, the special code area (K-CODE) may be allocated only as a data area (D-CODE) without a special code area. For example, in one embodiment of the present invention, a data frame of a side channel of a diagnostic instance where diagnostic data exists (see FIG. 11) may be allocated only a special code area (K-CODE) representing the start of the data frame, and other segments excluding the special code area (K-CODE) of the Video Interface Signal segment corresponding to the start of the data frame, namely the Side First packet segment, Side Second packet segment, and Side Third packet segment, may have only a data area (D-CODE) without a special code area (K-CODE); for example, the diagnostic data start symbol (0xDE) and the diagnostic data end symbol (0xED), which function as control symbols (or control information) to represent the start and end of the Side First packet segment, Side Second packet segment, and Side Third packet segment forming the data area (D-CODE), may function as control symbols (or control information) in one embodiment of the present invention, provided, however, considering the convenience of the process for generating the data frame, for example, the Side First packet segment following the Video Interface Signal segment corresponding to the start of the data frame in the process for generating the data frame, Side Second packet segment,By allocating the entire section of the Side Third packet segment as a data area (D-CODE, diagnostic data) from which the special code area (K-CODE) is excluded, the diagnostic data start symbol (0xDE) and the diagnostic data end symbol (0xED), which represent the start and end of the diagnostic data, can be processed as a payload allocated between them in the same way as the generation of the diagnostic data. For example, the entire section from the diagnostic data start symbol, including the diagnostic data start symbol, to the diagnostic data end symbol, including the diagnostic data end symbol, can be processed as a data area. In practice, the diagnostic data start symbol and the diagnostic data end symbol, which represent the start and end of the diagnostic data respectively, can be allocated as a data area where data can be changed or modified so that autonomous communication rules regarding the start and end of the diagnostic data can be established between communication hosts (e.g., a display source, a first FPGA block on the display source side, a display sink, or a second FPGA block on the display sink side).

[0115] In one embodiment of the present invention, the image assignment data is information related to image data transmitted through a main channel (or main lane), such as configuration information of a main channel (or main lane) like DPCD or rendering configuration information like EDID, and may include multiple communications including requests and replies to requests during a shorter time interval than diagnostic data, which includes status information of an optical link such as the connection status with a display source or display sink, the operating status of the optical link (operating voltage, operating temperature, etc.), and identification information of the optical link itself. For example, during channel equalization related to the configuration of a main channel (or main lane), it is necessary to implement multiple communications between a display source and a display sink, such as requests and replies to requests, such as information related to the configuration of a training pattern and changes to the training pattern, changes to the configuration of the main channel (or main lane), and the success or failure of channel equalization. Thus, a channel for the configuration of a main channel (or main lane) Requests for data for equalization and replies to the requested data, etc., can be transmitted as image-imposed data through a side channel (auxiliary channel or DDC channel).

[0116] In one embodiment of the present invention, both image-imposed data and diagnostic data may be transmitted through a side channel (auxiliary channel or DDC channel); however, as previously described, image-imposed data requires supporting a relatively large number of communications or a large amount of traffic, such as data requests and replies to requested data; conversely, diagnostic data including status information such as the connection status between a display source or display sink and an optical link, the operating status of the optical link (operating voltage, operating temperature, etc.), and identification information of the optical link itself may be sufficient even if it supports a relatively small number of communications or a small amount of traffic for data requests and replies to requested data. For example, the communication traffic for image-imposed data for data requests and replies to requested data transmitted through a side channel (auxiliary channel or DDC channel) and the communication traffic for diagnostic data regarding the connection status of the optical link between the display source and the display sink may be set to different numbers of communications or different amounts of traffic. Considering such an imbalance in communication traffic between image-imposed data and diagnostic data, in one embodiment of the present invention, 1) a data frame structure containing only image-imposed data (data frame of the side channel of a non-diagnostic instance) Structure, see Fig. 11) 2) A data frame structure including both image-imposed data and diagnostic data (data frame structure of the side channel of the diagnostic instance, see Fig. 12) can be considered.

[0117] In one embodiment of the present invention, a data frame (see FIG. 11 and FIG. 12) for time-division multiplexing different image-imposed data and diagnostic data (see FIG. 8 and FIG. 9) may include image-imposed data, and depending on the presence or absence of diagnostic data, if diagnostic data is present, a data frame may be formed in which the data area assigned to the diagnostic data is filled with diagnostic data, and if diagnostic data is not present, a stuffed data frame may be created in which the data area assigned to the diagnostic data is filled with a pre-set stuffing symbol (0x00). In this way, the data frame structure of a non-diagnostic instance in which diagnostic data is not present (see FIG. 11) may have a pattern in which a special code area (K-CODE) and a data area (D-CODE) are alternately repeated. For example, in one embodiment of the present invention, the data frame (see FIG. 11 and FIG. 12) may include time slots or sub-frames (see FIG. 8 and FIG. 9) of eight time-division units, and eight input channels may be multiplexed as each input channel is assigned to each time slot or sub-frame of each unit. For example, an optical link for providing a diagnostic monitoring function according to one embodiment of the present invention may include eight input channels (CH1 to CH8) multiplexed through time-division multiplexing (TDM, see FIG. 8 and FIG. 9) and a multiplexer (MUX) for selecting and outputting an input channel assigned to the current time slot or sub-frame among the eight input channels according to a control signal, and the multiplexer may output any selected input channel among the eight input channels.

[0118] For example, in a data frame of a non-diagnostic instance where only image-assisted data exists (see FIG. 11), the eight input channels (see FIG. 8 and 9) or the input registers connected to the eight input channels may store an 8-bit special code to fill the special code area, the data area assigned to the image-assisted data, and the data area assigned to the diagnostic data, respectively, 8 bits of image-assisted data, and 8 bits of stuffing symbols (stuffing symbols to fill the data area assigned to the diagnostic data, e.g., 0x00); and in a data frame of a diagnostic instance where both image-assisted data and diagnostic data exist (see FIG. 12), the eight input channels (see FIG. 8 and 9) or the input registers connected to the eight input channels may store a special code of the Video Interface Signal segment corresponding to the start of the frame, an 8-bit special code to fill the data area assigned to the image-assisted data and the data area assigned to the diagnostic data, respectively, 8 bits of image-assisted data, and 8 bits of diagnostic data (diagnostic data start symbol). 0xDE and diagnostic data termination symbol 0xED can be stored.

[0119] In one embodiment of the present invention, the multiplexer (see FIG. 8 and FIG. 9) does not fill the time slot or sub-frame assigned to the diagnostic data with image-imposed data other than the diagnostic data even if the diagnostic data does not exist in the input channel assigned to the diagnostic data among each of the eight input channels, and can implement stuffing that fills the frame area assigned to the diagnostic data that does not exist with stuffing symbols (e.g., 0x00). Implementing multiplexing of different image-imposed data and diagnostic data in this way may correspond to synchronous time-division multiplexing (STDM, see FIG. 10a), in which time slots allocated to each channel for TDM are not filled with data from other input channels even when there is no data in the input channel, and may not correspond to asynchronous time-division multiplexing (ATDM, see FIG. 10b), in which time slots allocated to the input channel where there is no data are filled with data from other input channels when there is no data in the input channel.

[0120] For example, in one embodiment of the present invention, implementing synchronous time-division multiplexing (STDM, see FIG. 10a) in which the data area (D-CODE) allocated to the diagnostic data in a data frame of a non-diagnostic instance (see FIG. 11) where the diagnostic data does not exist in the multiplexing between image-imposed data and diagnostic data is filled with stuffing symbols (0x00) without allocating it to another input channel (e.g., image-imposed data), can maintain the data frame of the side channel at a constant data size (8 bytes, 64 bits) regardless of the presence or absence of diagnostic data, and can provide compatibility with an optical link that transmits only image-imposed data without transmitting diagnostic data through the side channel, for example. For example, the side channel of an optical link according to a comparative example (see FIG. 13) that is contrasted with the present invention can transmit only image-imposed data without diagnostic data, and the image-imposed data of 8-bit parallel data can be transmitted through the side channel as a data frame of a constant data size of 32 bits through 1b4b coding. In consideration of compatibility with an optical link that maintains a data frame of a constant data size in this way, one embodiment of the present invention implements synchronous time-division multiplexing (STDM, Synchronous TDM, FIG. 10a) by implementing multiplexing between image-imposed data and diagnostic data (see FIG. 8 and FIG. 9), and by filling the data area (D-CODE) allocated to the diagnostic data in a data frame of a non-diagnostic instance (see FIG. 11) where diagnostic data does not exist with stuffing symbols (0x00) without allocating it to another input channel (e.g., image-imposed data).For example, in one embodiment of the present invention, a data frame (see FIG. 11 and FIG. 12) for implementing time division multiplexing between image-imposed data and diagnostic data may include time slots or sub-frames of 8 unit units, and may form a data frame with a total transmission capacity of 64 bits (8 bytes) by including time slots or sub-frames of 8 unit units each allocated to 8 bits (1 byte), and may maintain a constant transmission capacity regardless of the presence of diagnostic data.

[0121] In one embodiment of the present invention, a data frame of a non-diagnostic instance that includes only image-imposed data and does not include diagnostic data (see FIG. 11) and a data frame of a diagnostic instance that includes both image-imposed data and diagnostic data (see FIG. 12) are described as follows.

[0122] A data frame containing only image-imposed data (data frame of a non-diagnostic instance, see FIG. 11) may have a structure in which a special code area (K-CODE) to which a special code is assigned and a data area (D-CODE) are alternately assigned, and a transmission capacity of 8 bits (1 byte) may be assigned to each special code area (K-CODE) and data area (D-CODE). In this case, image-imposed data may be assigned to the D-CODE following the special code area (K-CODE, e.g., K28.7) that represents the start of the data frame along the time axis, and the D-CODE assigned alternately with the subsequent special code area (K-CODE, e.g., K23.7, K27.7, K29.7) may be filled with stuffing symbols (0x00) (synchronous time-division multiplexing, see FIG. 10a). In one embodiment of the present invention, the data frame of the side channel (see FIG. 11 and FIG. 12) may include a Video Interface Signal segment assigned to image-imposed data (including a special code area K-CODE and a data area D-CODE of 1 byte each), a Side First packet segment (including a special code area K-CODE and a data area D-CODE of 1 byte each), a Side Second packet segment (including a special code area K-CODE and a data area D-CODE of 1 byte each), and a Side Third packet segment (including a special code area K-CODE and a data area D-CODE of 1 byte each).In one embodiment of the present invention, image-imposed data and diagnostic data may be transmitted to a side channel (an auxiliary channel or a DDC channel), and a data frame of the side channel containing such image-imposed data and diagnostic data may include a Video Interface Signal segment corresponding to the start of the frame and a Side Third packet segment corresponding to the end of the frame, and may include a Side First packet segment and a Side Second packet segment interposed between the Video Interface Signal segment and the Side Third packet segment corresponding to the start and end of the frame. In addition, the segments forming the data frame (Video Interface Signal, Side First packet, Side Second packet, Side Third packet) may each include a special code area (K-CODE) and a data area (D-CODE) to which 1 byte is allocated.Here, video assignment data may be assigned to the Video Interface Signal segment corresponding to the beginning of the data frame (more specifically, the data area D-CODE of the Video Interface Signal segment), and diagnostic data may be assigned to each Side First packet, Side Second packet, and Side Third packet segment (D-CODE of the Side First packet, Side Second packet, and Side Third packet segments), and stuffing symbols (0x00) may be filled into each Side First packet, Side Second packet, and Side Third packet segment (D-CODE of each Side First packet, Side Second packet, and Side Third packet segment) in the data frame of a non-diagnostic instance where diagnostic data does not exist (see FIG. 11), and diagnostic data may be filled into each Side First packet, Side Second packet, and Side Third packet segment (D-CODE of the Side First packet, Side Second packet, and Side Third packet segments) in the data frame of a diagnostic instance where diagnostic data exists (see FIG. 12).

[0123] In various embodiments of the present invention, in a data frame of a non-diagnostic instance where diagnostic data does not exist (see FIG. 11), a special code area (K-CODE) and a data area (D-CODE) may be assigned alternately; and in a data frame of a diagnostic instance where diagnostic data exists (see FIG. 12), the Video Interface Signal segment corresponding to the beginning of the data frame may include a special code area (K-CODE) representing the beginning of the data frame and a data area (D-CODE) assigned to image-imposed data, similar to the data frame of the non-diagnostic instance where diagnostic data does not exist (see FIG. 11); however, in the other remaining segments, namely the Side First packet, Side Second packet, and Side Third packet segments, which follow the Video Interface Signal segment corresponding to the beginning of the data frame, only a data area (D-CODE) may be assigned without a special code area (K-CODE); provided, however, among the data areas (D-CODE) of these Side First packet, Side Second packet, and Side Third packet segments, the data area (D-CODE) preceding the Side First packet segment and the data following the Side Third packet segment The area (D-CODE) can be assigned to a diagnostic data start symbol (0xDE) and a diagnostic data end symbol (0xED) that indicate the start of diagnostic data, respectively. Unlike the special code area (K-CODE), a diagnostic data start symbol and a diagnostic data end symbol that can be set or modified according to autonomous rules between the communication host (the first FPGA block on the display source side and the second FPGA block on the display sink side) can be assigned to each.For example, a data frame of a diagnostic instance containing diagnostic data (see FIG. 12) may include a special code area (K-CODE) and a data area (D-CODE) of 1 byte (8 bits), similar to a data frame of a non-diagnostic instance (see FIG. 11); the special code area and the data area of ​​the Video Interface Signal segment may each be allocated as 1 byte, and the remaining subsequent Side First packet, Side Second packet, and Side Third packet segments may be allocated only a data area (D-CODE) without a special code area (K-CODE), and each data area (D-CODE) may be allocated as 1 byte (8 bits); and as previously described, among the Side First packet, Side Second packet, and Side Third packet segments following the Video Interface Signal segment, the preceding data area (1 byte, 8 bits) corresponding to the start of the Side First packet segment and the succeeding data area (1 byte, 8 bits) corresponding to the end of the Side Third packet segment shall each contain a diagnostic data start symbol (0xDE) and a diagnostic data end symbol. A symbol (0xED) can be assigned, and diagnostic data can be assigned to each of the other data areas (1 byte, 8 bits).

[0124] In other words, for a data frame (see FIG. 11 and FIG. 12) for time-division multiplexing (see FIG. 8 and FIG. 9) different image-imposed data and diagnostic data, depending on the presence or absence of diagnostic data, a data frame of a non-diagnostic instance where diagnostic data is not present (see FIG. 11) includes a special code area and a data area alternately assigned to time slots or sub-frames of 8 time-division units, and

[0125] A data frame of a diagnostic instance containing diagnostic data (see FIG. 12) may include a special code area assigned to a time slot or sub-frame of a unit unit corresponding to the start of the data frame in a time slot or sub-frame of eight time-divided units, and a sequence of data areas assigned to time slots or sub-frames of other unit units that follow the time slot or sub-frame of the unit unit to which the special code area is assigned along the time axis.

[0126] More specifically, the data frame of the non-diagnostic instance (see FIG. 11) and the data frame of the diagnostic instance (see FIG. 12) may commonly include a Video Interface Signal segment corresponding to the beginning of the data frame, and Side First packet, Side Second packet, and Side Third packet segments following the Video Interface Signal segment along the time axis.

[0127] The above Video Interface Signal segment may include a special code area and a data area, and

[0128] The special code area of ​​the above Video Interface Signal segment can be assigned to a special code indicating the start of a data frame, and

[0129] The data area of ​​the above Video Interface Signal segment can be allocated to video-imposed data.

[0130] For example, each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the above-mentioned non-diagnostic instance (see FIG. 11) may include a special code area and a data area, and

[0131] The data areas of the above Side First packet, Side Second packet, and Side Third packet segments may be filled with stuffing symbols instead of non-existent diagnostic data.

[0132] For example, each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the diagnostic instance (see FIG. 12) includes a time slot or sub-frame of two unit units preceding and succeeding along the time axis, and

[0133] The preceding time slot of the above Side First packet may be filled with a diagnostic data start symbol, and the succeeding time slot of the above Side Third packet may be filled with a diagnostic data end symbol.

[0134] Along the time axis, from the trailing time slot of the Side First packet to the leading time slot of the Side Third packet, the area can be filled with diagnostic data.

[0135] At this time, the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet are each filled with a diagnostic data start symbol and a diagnostic data end symbol, and the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet can be allocated as a data area that can be modified between communication hosts.

[0136] For example, the time-divided time slot or sub-frame may be allocated as 8 bits, and the data frame (see FIG. 11 and FIG. 12) may be allocated as a total of 64 bits of 8 unit units, with each time-divided time slot or sub-frame allocated as 8 bits as a unit unit.

[0137] In one embodiment of the present invention, for the generation of a side channel data frame (see FIG. 11 and FIG. 12) including the image-assigned data and the diagnostic data, the FPGA block (see FIG. 8 and FIG. 9) may include eight input channels into which special codes, image-assigned data, and diagnostic data are input (e.g., eight input channels connected to input registers storing special codes, image-assigned data, and diagnostic data (or stuffing symbols)), and a multiplexer (MUX) for implementing multiplexing for the eight input channels. For example, in one embodiment of the present invention, the multiplexer (MUX) may form a sequence of parallel data (8 bits) in which the special codes, image-assigned data, and diagnostic data (or stuffing symbols) input through the eight input channels are transmitted through their respective allocated time slots or sub-frames. Line encoding and / or block Block encoding can be performed (see FIG. 9, encoder), for example, an encoder for performing line encoding and / or block encoding can perform appropriate line encoding by balancing positive and negative voltages so that signal distortion due to a DC component does not occur for parallel data in which special codes, image-imposed data, and diagnostic data (or stuffing symbols) are multiplexed (or mixed), and by taking into account synchronization between the display source and the display sink.In addition, the encoder (see FIG. 9) can convert, for example, an 8-bit input into a 10-bit output (8b / 10b encoding) for parallel data in which special codes, image-imposed data, and diagnostic data (or stuffing symbols) are multiplexed (or mixed), and can perform block encoding to balance positive and negative voltages and check for data transmission errors (bit errors).

[0138] For example, in one embodiment of the present invention, the FPGA block (see FIG. 3) may include an FPGA control logic (programmable fabric) for performing processing according to a pre-set process or logic, comprising an array of programmable logic blocks, and a memory (RAM) in which data reading, writing, updating, etc. (e.g., CRUD, create, read, update, delete) is performed in conjunction with the FPGA control logic; additionally, a multiplexer for multiplexing diagnostic data and image-assisted data processed according to the FPGA control logic, an encoder for line encoding and / or block encoding, and parallel data forming diagnostic data and image-assisted data processed according to the FPGA control logic (a sequence of parallel data forming a data frame in which diagnostic data (or stuffing symbols) and image-assisted data are multiplexed, or a sequence of parallel data in which diagnostic data (or stuffing symbols) and image-assisted data are multiplexed), and serial data (a sequence of serial data forming a data frame in which diagnostic data (or stuffing symbols) and image-assisted data are multiplexed, or serial data in which diagnostic data and image-assisted data are multiplexed). Converted into a sequence) or serial data transmitted from a display source, display sink, or FPGA block on the opposite side via an optical link (a sequence of serial data in which diagnostic data (or stuffing symbols) and image-assisted data form a data frame multiplexed, or a sequence of serial data in which diagnostic data (or stuffing symbols) and image-assisted data multiplexed),It may include SerDes (Serializer + Deserializer) for converting into parallel data suitable for processing of an FPGA block (see FIG. 3) (a sequence of parallel data forming a data frame (see FIG. 11 and FIG. 12) in which diagnostic data (or stuffing symbols) and image-imposed data are multiplexed, or a sequence of parallel data in which diagnostic data (or stuffing symbols) and image-imposed data are multiplexed).

[0139] More specifically, in one embodiment of the present invention, the FPGA block (see FIG. 8 and 9) comprises: an input channel (first to eighth input channel) connected to an input register in which a special code is stored from the FPGA control logic; an input channel (first to eighth input channel) connected to an input register receiving image-imposed data processed from the FPGA control logic; a multiplexer that implements multiplexing between the input channel (first to eighth input channel) connected to an input register receiving diagnostic data output from the FPGA control logic as another data processing flow; an encoder that takes as input a sequence of parallel data (8-bit) including a special code, image-imposed data, and diagnostic data output from the multiplexer (a sequence of parallel data in which diagnostic data (or stuffing symbol) and image-imposed data are multiplexed to form a data frame, or a sequence of parallel data in which diagnostic data (or stuffing symbol) and image-imposed data are multiplexed) and encodes the input sequence of parallel data; and a sequence of serial data (diagnostic data (or stuffing symbol)) input according to a parallel clock and a sequence of serial data according to a serial clock and may include SerDes (shift registers) that output a sequence of serial data forming a data frame in which image-imposed data is multiplexed, or a sequence of serial data in which diagnostic data (or stuffing symbols) and image-imposed data are multiplexed. For example, in one embodiment of the present invention, the FPGA block (see FIG. 3, first FPGA block or second FPGA block) stores, modifies, and updates (CRUD, create, read, update, image-imposed data and diagnostic data transmitted from a display source or a display sink, and image-imposed data and diagnostic data transmitted from the second FPGA block on the display sink side or the first FPGA block on the display source side.Image-imposed data and diagnostic data can be processed according to a process or logic that defines a pre-set operation, such as delete), and for example, image-imposed data and diagnostic data transmitted from a display source or a display sink, and image-imposed data and diagnostic data transmitted from a second FPGA block on the display sink side or a first FPGA block on the display source side, can be converted into a sequence of serial data (a sequence of serial data in which diagnostic data (or stuffing symbol) and image-imposed data form a data frame multiplexed with the image-imposed data, or a sequence of serial data in which diagnostic data (or stuffing symbol) and image-imposed data are multiplexed with the image-imposed data) through processing from an input register of the FPGA control logic or an input register connected to the FPGA control logic to a SerDes (shift register), and then transmitted to the opposite side of the optical link through an optical link. For example, the FPGA block (see FIG. 3, first FPGA block or second FPGA block) can generate diagnostic data regarding the status information of an optical link, such as the connection status with the display source or display sink, the operating status of the optical link (operating temperature, operating voltage, etc.), and identification information of the optical link itself, by taking raw data transmitted from the display source or display sink (e.g., image-imposed data such as HPD (hot plug detection) or other data) as input, along with processing image-imposed data and diagnostic data transmitted from the display source or display sink; and the FPGA block (see FIG. 8 and FIG. 9) may include an input register that receives diagnostic data output from FPGA control logic, and as previously described,Through the output channel of a multiplexer (MUX) that implements multiplexing between input channels (first to eighth input channels) into which diagnostic data output from an input register according to a parallel clock is input and input channels (first to eighth input channels) into which image-imposed data is input, the sequence of parallel data including the image-imposed data and the diagnostic data (sequence of parallel data forming a data frame (see FIG. 11 and FIG. 12) in which diagnostic data (or stuffing symbols) and image-imposed data) can be converted into a sequence of serial data including the image-imposed data and the diagnostic data (sequence of serial data forming a data frame (see FIG. 11 and FIG. 12) in which diagnostic data (or stuffing symbols) and image-imposed data) can be converted through an encoder for performing line encoding and / or block encoding and a SerDes (shift register) for conversion into serial data for data transmission via an optical link, and the optical It can be transmitted to the opposite side of the link. For example, the multiplexer (MUX, see FIG. 8 and 9) can implement multiplexing between first to eighth input registers that output special codes, image-imposed data, and diagnostic data according to a parallel clock, or between first to eighth channels connected to these first to eighth input registers, and can output a sequence of parallel data including special codes, image-imposed data, and diagnostic data through multiplexing between the first to eighth channels according to a time slot for time division multiplexing (TDM) or a switching of a control signal synchronized with a sub-frame (a switching of a control signal synchronized with the parallel clock). And, the SerDes (shift register, see FIG. 8 and 9)A sequence of parallel data including special codes, image-imposed data, and diagnostic data output from the output channel of a multiplexer (MUX) is used as input, and a sequence of serial data including special codes, image-imposed data, and diagnostic data can be sequentially output according to a serial clock.

[0140] For example, in one embodiment of the present invention, the input register (see FIG. 9), multiplexer, encoder, and SerDes (shift register, serializer, and deserializer, parallel to serial, serial to parallel) can be synchronized with a parallel clock as input, for example, the multiplexer (MUX) can output parallel data of special codes, image-imposed data, and diagnostic data assigned to a time slot or sub-frame synchronized with the parallel clock, and accordingly, the SerDes (shift register) can receive parallel data according to the parallel clock synchronized with the input register, multiplexer, and encoder, and can output serial data of special codes, image-imposed data, and diagnostic data according to the serial clock.

[0141] In one embodiment of the present invention, data of a side channel including image-imposed data and diagnostic data, or a data frame having a structure as previously described (see FIG. 11 and FIG. 12), may include time slots or sub-frames of 8 units (each unit unit: 8 bits, 1 byte) for time division; for example, in one embodiment of the present invention, a data frame of a non-diagnostic instance that includes only image-imposed data and does not include diagnostic data (see FIG. 11) may have a structure in which a special code area (K-CODE) and a data area (D-CODE) are alternately allocated, and a stuffing symbol (0x00) may be filled in the data area (D-CODE) to which diagnostic data is allocated; otherwise, a data frame of a diagnostic instance that includes both image-imposed data and diagnostic data (see FIG. 12) may have all other areas allocated as a data area (D-CODE) except for a special code area (K28.7) representing the start of the data frame, and a diagnostic data start symbol (0xDE) representing the start of the diagnostic data and the diagnostic data Diagnostic data may be filled in the data area (D-CODE) between the diagnostic data termination symbols (0xED) representing termination. In one embodiment of the present invention, each special code area (K-CODE) and data area (D-CODE) forming a data frame may be allocated as 1 byte (8 bits), and the data capacity of a time slot or sub-frame for time division multiplexing (TDM, see FIG. 8 and FIG. 9) of a data frame including each special code area (K-CODE) and data area (D-CODE) may be determined according to the data capacity of the data frame (8 bytes, 64 bits) and the transmission speed of the optical link (e.g., 16 MBps-byte per second).

[0142] For example, an optical link for providing a diagnostic monitoring function according to one embodiment of the present invention is connected between a display source and a display sink that form a system supporting HDMI (see FIG. 2) or a Display Port (DP, see FIG. 1), and can transmit video data including video information, rendering setting data such as EDID (Extended Display Identification Data) in relation to rendering of the display sink, and video assignment data including channel setting data such as DPCD (Display Port Configuration Data) in relation to channel setting of a main channel (or main lane) that transmits video data.

[0143] More specifically, the video assignment data may be transmitted to a side channel (HDMI's DDC channel or DP's auxiliary channel AUX channel) rather than a main channel (HDMI's main channel or DP's main lane) for high-speed video data transmission in HDMI (see FIG. 2) and DisplayPort (DP, see FIG. 1), and may include video assignment signals such as SCL (clock line of DDC channel), SDA (data line of DDC channel), 5V power supply (DDC_5V), HPD (Hot Plug Detection), and CEC (Customer Electronic Control) in HDMI, and may include video assignment signals such as HPD (Hot Plug Detection) and DPCD (Display Port Configuration Data) in DisplayPort.

[0144] An optical link implementing a diagnostic monitoring function according to an embodiment of the present invention can monitor diagnostic data through a graphic interface screen rendered from a GUI (Graphic User Interface) program on a manager interface connected to a USB port of an optical transmission module (see FIG. 4a) connected to a display source side or an optical reception module (see FIG. 4b) connected to a display sink side. In this way, the output status of the screen rendered on the display sink side can be checked through the diagnostic monitoring function implemented from the optical link according to an embodiment of the present invention. If the screen is not displayed or the output screen status is not good, maintenance costs such as reconnection or repair can be reduced through the diagnostic monitoring function provided by the optical link according to an embodiment of the present invention.

[0145] For example, the diagnostic data corresponding to the diagnostic monitoring target of the optical link according to one embodiment of the present invention includes the connection status between the display source and the display sink (the connection status on the display source and the display sink (e.g., the connection status between the optical link mediating the transmission of video data between the display source and the display sink and the connection status with the display sink), the presence or absence of an output signal on the display source side, the presence or absence of an output signal on the display sink side, the presence or absence of a signal by channel on the display sink side (HDMI Channel 0, Channel 1, Channel 2, Clock Channel (Pixel Clock), DisplayPort Lane 0, Lane 1, Lane 2, Lane 3; see FIG. 1 and 2), the communication status between the display source and the display sink (e.g., the communication status of a side channel supporting bidirectional communication between the display source and the display sink), the operating status of the optical link (operating temperature, operating voltage, etc.), and identification information of the optical link (USB connected USB device recognized from the manager interface forming the host side with the optical link as the device side of the USB communication between the communication host-optical link and the manager interface where the USB communication channel is configured). It may include diagnostic data such as identification information of a USB device-optical link recognized from a combination of the link's VID (Vender ID) and PID (Product ID). For example, in one embodiment of the present invention, it may be determined whether an optical link with a USB communication channel established with a manager interface is a pre-configured or pre-defined USB device, thereby determining whether it corresponds to a diagnostic monitoring target.

[0146] In various embodiments of the present invention, between a GUI program for providing a graphical interface on a manager interface and a USB-connected optical link, it is necessary to match the format of an API (Application Programming Interface), such as the format or structure of communication data. Additionally, in order for diagnostic monitoring to be provided from the manager interface, the USB-connected USB device must be limited to an optical link. Therefore, the manager interface needs to determine whether the product of the USB device with the USB communication channel formed is an optical link. Thus, the manager interface, which determines that the recognized USB device deviates from a pre-set or pre-defined category based on a combination of VID and PID read from the configuration of the USB device with the USB communication channel formed, can output an error message on the graphical interface screen without performing further diagnostic monitoring.

[0147] For example, in one embodiment of the present invention, between the optical link and the manager interface, the quality of the image rendered on the display sink side can be optimized by changing or fixing the image assignment data, which includes rendering configuration data such as EDID (Extended Display Identification Data) in relation to the rendering of the display sink and channel configuration data such as DPCD (Display Port Configuration Data) in relation to the channel configuration of the main channel (or main lane) transmitting image data.

[0148] An optical link for providing a detection monitoring function according to one embodiment of the present invention may be connected to a USB port of an optical link (USB port of an optical transmission module or an optical reception module) directly by a computing terminal forming a manager interface, or connected to a USB port of an optical link (USB port of an optical transmission module or an optical reception module) via a system for implementing diagnostic monitoring of an optical link as described below (hereinafter, diagnostic monitoring system).

[0149] Hereinafter, a system for implementing diagnostic monitoring of an optical link while providing data processing and data transmission channels between an optical link and a manager interface according to an embodiment of the present invention will be described in more detail.

[0150] FIG. 14 illustrates a diagram for explaining the overall structure of a system for implementing diagnostic monitoring of an optical link according to one embodiment of the present invention.

[0151] Figure 15 shows a diagram for explaining the USB host controller illustrated in Figure 14.

[0152] FIG. 16 illustrates a diagram illustrating that multiple data transmission channels connected to each optical link are multiplexed through a single connection channel between the FPGA circuit and the MCU from time division multiplexing (TDM) between the FPGA circuit and the MCU shown in FIG. 14.

[0153] FIG. 17 is a diagram illustrating the data structure of UART (universal achromous receiver / transmitter) communication data that is converted from the USB interface of a USB host controller that takes USB communication data as input and transmitted toward a UART-parallel converter, and the diagram illustrates the UART communication data structure including a Stop bit, a Data bit, a Parity bit, a Stop bit, and an IDLE section.

[0154] FIG. 18 is a diagram illustrating a USB connection between a USB host controller and an optical link as illustrated in FIG. 14, wherein the USB host controller is the host (DFP, Down Facing Port) and the optical link is the device (UFP, Up Facing Port). The diagram shows a MUX that controls switching between the input / output channels of the MUX to allow an Un-flipped or Flipped connection corresponding to the plug orientation according to the connection status between them, and a CC Logic and Vconn switch for powering an EMIC (Electronically Marked IC).

[0155] FIG. 19 is a diagram illustrating the pin configuration of a USB port (USB C-type) and the Configuration Control (CC) in the USB connection between the USB host controller and the optical link shown in FIG. 14, and is a diagram illustrating the Configuration Channel (CC1, CC2) involved in detecting USB connection / disconnection, setting the roll and plug orientation (Un-flipped or Flipped) between USB communication hosts, and PD communication (power delivery communication or baseband communication).

[0156] FIG. 20 is a diagram for explaining USB communication between a USB host controller and an optical link as illustrated in FIG. 14, and for detecting USB connection and plug orientation (Un-flipped or Flipped) and role determination in USB communication where the USB host controller is the host and the optical link is the device, a pull-up resistor (Rp) connected to the CC of the USB host controller forming the host, a pull-down resistor (Rd) connected to the CC of the optical link forming the device, and a resistor (Ra) capable of detecting active cable circuitry such as an EMIC (Electronically Marked IC) are shown.

[0157] FIG. 21 is a diagram illustrating USB communication between a USB host controller and an optical link as illustrated in FIG. 14, and is a diagram illustrating power delivery (or baseband communication) related to power supply and role determination between the CC of the USB host controller and the CC of the optical link, and is a diagram illustrating PD communication encoded in BMC (Biphase Mark Coding).

[0158] A system for implementing diagnostic monitoring of an optical link (hereinafter, diagnostic monitoring system, see FIG. 14) that provides a data processing and data transmission channel between an optical link and a manager interface according to one embodiment of the present invention can provide diagnostic monitoring regarding the connection status of an optical link by transmitting to a manager interface diagnostic data that includes overall optical link status information, such as the connection status of the optical link, the operation status of the optical link, and identification information of the optical link, which can affect the output of image quality rendered on the display sink side, such as the connection status between the optical link and a display source or display sink forming a system that supports HDMI (see FIG. 2) or DisplayPort (see FIG. 1). The optical link corresponding to the diagnostic target from the diagnostic monitoring system (see FIG. 14) can transmit image data including image information, channel configuration data such as DPCD (Display Port Configuration Data) in relation to the configuration of the main channel (or main lane) for transmitting the image data, and rendering configuration data such as EDID (Extended Display Identification Data) in relation to the rendering of the display sink.

[0159] A diagnostic monitoring system (see FIG. 14) that provides a data processing and data transmission channel between an optical link and a manager interface according to one embodiment of the present invention may be connected to a USB port of an optical communication module (see FIG. 4a and FIG. 4b) including an FPGA block (see FIG. 3) of an optical link to diagnose and monitor the status information of the optical link (USB connection). For example, a USB connection may be formed with the diagnostic monitoring system (see FIG. 14) as the host and the FPGA block (see FIG. 3) as the device. The diagnostic monitoring system (see FIG. 14) may transmit a request for diagnostic data to the FPGA block (see FIG. 3) to which a USB communication channel with the diagnostic monitoring system is formed, receive the requested diagnostic data, and request an update, modification, or change of the diagnostic data. In one embodiment of the present invention, the diagnostic monitoring system (see FIG. 14) may form a one-to-many parallel USB connection with a plurality of optical links (e.g., each FPGA block of a plurality of optical links, see FIG. 3) to provide diagnostic monitoring for a plurality of optical links as described below.

[0160] In one embodiment of the present invention, the diagnostic monitoring system (see FIG. 14) may be connected to at least one of the first and second FPGA blocks (see FIG. 1 and FIG. 2) that are connected adjacently to the display source side or the display sink side, and, for example, may obtain diagnostic data mainly related to the display source (e.g., whether there is an output signal of the display source) by being connected to the first FPGA block connected adjacently to the display source side, such as the connection status between the display source and the optical link connected adjacently to the first FPGA, or may obtain diagnostic data mainly related to the display sink (e.g., whether there is an input signal of the display sink) by being connected to the second FPGA block connected adjacently to the display sink side, such as the connection status between the display sink and the optical link connected adjacently to the second FPGA. In addition, the first FPGA block and the second FPGA block are connected to each other through an optical link, and can perform data communication including requesting diagnostic data regarding the connection status between the optical link and a display source or display sink adjacent to each of the first and second FPGA blocks, and receiving the requested diagnostic data. Accordingly, even if the connection is made with either of the first or second FPGA blocks, diagnostic data regarding the connection status between each display source and the optical link and the connection status between the display sink and the optical link can all be obtained.

[0161] A diagnostic monitoring system (see FIG. 14) that provides data processing and data transmission channels between an optical link and a manager interface according to an embodiment of the present invention may form a one-to-many connection with a plurality of optical links (FPGA blocks of each optical link (see FIG. 3) or optical communication modules including FPGA blocks (see FIG. 4a and 4b)) and obtains diagnostic data regarding the connection status of a plurality of optical links, the operation status of a plurality of optical links, and identification information of a plurality of optical links, so as to be able to simultaneously diagnose and monitor the connection status of a plurality of optical links, the operation status of a plurality of optical links, and identification information of a plurality of optical links, wherein a data transmission channel with each optical link may be formed in the diagnostic monitoring system (see FIG. 14), and a plurality of data transmission channels connected in parallel with a plurality of optical links may be formed. In an embodiment of the present invention, on a plurality of data transmission channels, a plurality of USB host controllers that form a one-to-one USB communication channel with each optical link (FPGA blocks of each optical link), a UART-parallel converter connected to a plurality of USB host controllers that forms a one-to-one UART communication channel with a USB host controller, and the It may include a single FPGA block connected in parallel with a plurality of USB host controllers or a plurality of UART-parallel converters to form a one-to-many parallel communication channel with a USB host controller or a UART-parallel converter, a single MCU (Micro Controller Unit) that forms a parallel communication channel with the FPGA block, and a communication module (Ethernet communication module) that forms a parallel communication channel with the MCU. The data transmission channel formed within the diagnostic monitoring system (see FIG. 14) through such a plurality of configurations can be connected from the communication module to a manager interface through a communication network.

[0162] For example, the diagnostic monitoring system (see FIG. 14) may form a one-to-many USB connection in which one USB host controller serves as a common host for multiple USB connections and multiple optical links connected to a USB hub capable of supporting multiple USB connections serve as devices, or alternatively, may form a one-to-one USB connection in which multiple USB host controllers serve as hosts for each USB connection and each optical link serves as a device. The diagnostic monitoring system (see FIG. 14) may have multiple optical links as devices for USB connections and may include multiple USB host controllers as hosts for each USB connection. Accordingly, each USB connection may have one optical link (an FPGA block of the optical link (see FIG. 3) or an optical communication module including an FPGA block (see FIG. 4a and FIG. 4b)) as a device and form a one-to-one USB connection in which each assigned USB host controller among the multiple USB host controllers provided in the diagnostic monitoring system (see FIG. 14) serves as a host. Unlike in one embodiment of the present invention, when the diagnostic monitoring system includes only one single USB host controller and forms a one-to-many USB connection in which a plurality of optical links connected through a USB hub are devices and the single USB host controller provided in the diagnostic monitoring system is the host, the single USB host controller needs to perform a process for setting up a USB communication channel with respect to a plurality of optical links (FGPA blocks of optical links), for example, checking the connection of each USB port provided in the USB hub and setting a role (DRP, Down Facing Port) such as host (DFP, Down Facing Port) and device (UFP, Up Facing Port) regarding data transmission between the optical link as a device connected to the USB port.In cases where Dual Role Port is supported, or detection of pull-up resistors (Rp, see FIG. 20) or pull-down resistors (Rd, see FIG. 20) in relation to data transfer speeds (LS: low speed, HS: high speed, FS: full speed), or setting of roles such as a host (DFP, Down-Facing Port) and device (UFP, Up-Facing Port) related to data transfer and / or a source or sink related to charging (DRP, if Dual Role Port is supported), or baseband communication for power delivery settings including charging power, multiple processes need to be performed to establish each communication channel between a single USB host of a diagnostic monitoring system and multiple optical links (FPGA blocks of optical links), and a structure forming a one-to-many USB connection in which the communication host involved in the multiple processes for establishing each communication channel is limited to a single USB host controller; that is, a single USB host as the communication host of the USB connection, while including multiple USB ports for multiple USB connections with multiple optical links (e.g., including the connection of a USB hub containing multiple USB ports). In a diagnostic monitoring system equipped with a controller, time delays may occur in the configuration of multiple USB communication channels, and additionally, as the USB connection is disconnected, time delays may occur for the reclamation and initialization of computational resources allocated for the configuration of the USB communication channels (e.g., initial level configuration, such as connections with pull-up resistors (Rp, see FIG. 20) or pull-down resistors (Rd, see FIG. 20) of CC (Configuration Channel, CC1, CC2, see FIG. 19), and also,Even when a USB communication channel is established, traffic for communication with multiple optical links (FPGA blocks of optical links (see FIG. 3) or optical communication modules including FPGA blocks (see FIG. 4a and FIG. 4b)) is concentrated on a single USB host controller, which may cause time delays in processing diagnostic data, such as requesting diagnostic data for multiple optical links or receiving, storing, or modifying diagnostic data. In this way, due to the limitation of the limited processing capacity of the single USB host controller provided in the diagnostic monitoring system, time delays may occur in computational processing, such as requesting diagnostic data for each optical link or processing diagnostic data received from each optical link, when USB connection / disconnection events occur, such as establishing a new USB communication channel following the connection of a new optical link (FPGA blocks of optical links or optical communication modules including FPGA blocks) or retrieving a USB communication channel following the disconnection of a previous optical link (FPGA blocks of optical links or optical communication modules including FPGA blocks). Based on such considerations, in a diagnostic monitoring system applicable to one embodiment of the present invention (see FIG. 14), diagnostic monitoring is simultaneously performed on the connection status of a plurality of optical links (connection status between an optical link and a display source and between an optical link and a display sink), the operation status of a plurality of optical links, and status information of an optical link including identification information of a plurality of optical links. At the same time, USB host controllers are provided as communication hosts for USB connections with a plurality of optical links in a number equal to that of the optical links forming each USB communication channel (one-to-one connection between an optical link and a USB host controller), thereby ensuring that no time delay is caused in the transmission or reception of diagnostic data or the processing of diagnostic data in relation to the setting of the USB communication channel of each optical link or the retrieval of the set USB communication channel. For example,By distributing the traffic of the USB communication channel with multiple optical links (FPGA blocks of optical links (see FIG. 3) or optical communication modules including FPGA blocks (see FIG. 4a and FIG. 4b)) to a dedicated USB host controller assigned to each optical link, time delay may not be caused in the processing of diagnostic data containing information regarding the connection status of multiple optical links.

[0163] In one embodiment of the present invention, a plurality of data transmission channels formed in parallel within a diagnostic monitoring system (see FIG. 14) to form a flow of diagnostic data or control signals (or control commands) for processing diagnostic data regarding the connection status of each optical link may be connected in parallel to a single FPGA circuit provided within the diagnostic monitoring system through each USB host controller that functions as a communication host for a USB connection with each optical link, and the flow of diagnostic data or control signals (control commands) for processing diagnostic data for each optical link transmitted along each data transmission channel may be processed in parallel in the FPGA circuit. For example, the FPGA circuit (see FIG. 16) may be advantageous for parallel tasks compared to an MCU connected to the FPGA circuit (see FIG. 16) along a data transmission channel, by including an array of programmable logic blocks, an FPGA control logic (programmable fabric) for performing processing according to a pre-set process or logic, and a memory (RAM) in which data reading, writing, updating, etc. (e.g., CRUD, create, read, update, delete) is performed in conjunction with the FPGA control logic. For example, the FPGA circuit may perform parallel operations such as input / output of diagnostic data or control flow for processing diagnostic data through multiple data transmission channels, and multiple data transmission channels formed in parallel within a diagnostic monitoring system to form individual connection channels with multiple optical links (FPGA blocks of optical links) may be connected in parallel to the FPGA circuit, and may be formed as a single connection channel between the FPGA circuit and the MCU (see FIG. 16).In other words, the data transmission channel through which input / output data for the plurality of optical links is transmitted may be formed as individual connection channels for each optical link between the plurality of host controllers and FPGA circuits, and as a single connection channel between the FPGA circuit and the MCU.

[0164] As described below, unlike the FPGA circuit (see FIG. 16), the MCU can support serial processing and can support time-division multiprocessing. For example, the flow of diagnostic data or control signals for processing diagnostic data for a plurality of optical links connected to a diagnostic monitoring system can be processed in parallel in the FPGA circuit, and the flow of diagnostic data or control signals for processing diagnostic data with the FPGA circuit can be processed in time-division multiprocessing in the serial processing MCU. Accordingly, in one embodiment of the present invention, a data transmission channel formed within the diagnostic monitoring system (see FIG. 14) can be formed as a parallel connection channel from the USB connection with a plurality of optical links to the FPGA circuit for parallel processing, and can be formed as a single connection channel from the FPGA circuit to the MCU for serial processing.

[0165] The above FPGA circuit (see FIG. 16) may include an array of programmable logic blocks, an FPGA control logic (programmable fabric) for performing processing according to a pre-set process or logic, and a memory (RAM) in which operations such as reading, writing, and updating data are performed in conjunction with the FPGA control logic. In addition, it may include a multiplexer (MUX) for multiplexing a plurality of data transmission channels connected in parallel to the FPGA circuit (see FIG. 16) or for multiplexing data input and output through a plurality of data transmission channels connected in parallel to the FPGA circuit (e.g., Time Division Multiplexing).For example, in one embodiment of the present invention, the FPGA circuit may include a multiplexer (MUX) for implementing time division multiplexing (TDM) so that data input and output from a plurality of data transmission channels connected in parallel to the FPGA circuit can be transmitted through a single connection channel, that is, a single connection channel formed between the FPGA circuit and the MCU. Accordingly, diagnostic monitoring regarding the connection status of a plurality of optical links connected to a diagnostic monitoring system according to one embodiment of the present invention may be implemented by time division multiprocessing for each optical link forming a plurality of optical links, and may be implemented by time division multiprocessing of an MCU for controlling the overall operation of the diagnostic monitoring system according to one embodiment of the present invention. For example, the MCU may generate a control signal (control command) to control the overall operation of the diagnostic monitoring system in response to a request from an administrator interface connected to the diagnostic monitoring system through a communication network, and transmit the generated control signal toward the optical link that is the target of the control signal. In response to this, the MCU may receive diagnostic data transmitted from the corresponding optical link and transmit it to the administrator interface connected to the diagnostic monitoring system through a communication network.In this way, the MCU can form a flow of data input / output, such as the transmission of a control signal including a data request for each optical link or the reception of the requested data, through a data transmission channel, and can process tasks related to each optical link through time-division multiprocessing via a multiplexer (MUX) of an FGPA circuit (see FIG. 16) in which a plurality of data transmission channels are connected in parallel. For example, in one embodiment of the present invention, the multiplexer (MUX) of the FPGA circuit can multiplex data input / output through a connection channel with the first to Nth optical links or through a connection channel with the first to Nth optical links through a time-division time slot. For example, according to a control signal (a control signal synchronized with the clock) applied to the multiplexer (MUX), it can sequentially process tasks related to each of the first to Nth optical links while sequentially inputting and outputting data through the connection channel with each optical link while moving from the first optical link to the Nth optical link (MCU: time-division multiprocessing).

[0166] In one embodiment of the present invention, multiplexing data input and output through a connection channel (see FIG. 16) with the first to Nth optical links connected to the diagnostic monitoring system can be implemented, for example, by implementing asynchronous time division multiplexing (ATDM, Asynchronous TDM, see FIG. 10b) in which time slots allocated to the separated optical links are allocated to other optical links when some of the first to Nth optical links are switched from a connected state to a disconnected state, and for example, it may not correspond to synchronous time division multiplexing (STDM, Synchronous TDM, see FIG. 10a) in which time slots allocated to data input and output through the connection channel of the second optical link are left empty or filled with stuffing symbols when some of the first to Nth optical links (second optical link) are switched from a connected state to a disconnected state. For example, in one embodiment of the present invention, a diagnostic monitoring system or an MCU for controlling the overall operation of the diagnostic monitoring system, which sequentially performs tasks related to the first to Nth optical links from asynchronous time division multiplexing (ATDM, Asynchronous TDM, see FIG. 10b), may detect that the second optical link among the first to Nth optical links has switched from a connected state to a disconnected state, and may allocate the time slot allocated to data input / output through the connection channel of the second optical link to another optical link, and the MCU that sequentially performs tasks related to the first to Nth optical links may not perform tasks related to the disconnected second optical link, but may, for example, perform tasks related to the first optical link and immediately skip to tasks related to the third optical link.As described below, a USB host controller (see FIG. 15) forming a host of a USB communication channel with each optical link (an FPGA block of the optical link or an optical communication module including an FPGA block) can switch the output of a GPIO pin to a high / low signal depending on the connection / disconnection status of the optical link forming each USB communication channel. An MCU that detects the switching of the output level of the GPIO pin of such a USB host controller (see FIG. 15) can initiate a reset operation for the USB host controller with the switched output level and control an FPGA circuit (see FIG. 16, e.g., a multiplexer of the FPGA circuit) to allocate a time slot corresponding to another data transmission channel instead of allocating a time slot for time-division multiplexing to the data transmission channel connected to the USB host controller with the detected output level switching (ATDM, see FIG. 16). Accordingly, the MCU can skip directly to the next optical link without performing tasks related to the optical link with the disconnected USB connection, and the operation performed in a time-division manner It prevents wasting computation time on optical links separated from multiprocessing and allows tasks related to other optical links that maintain connection status to be processed just as quickly.

[0167] In one embodiment of the present invention, the respective components connected on the data transmission channel in the diagnostic monitoring system (see FIG. 14) are described as follows. The MCU may include an ALU (arithmetic and logic unit) for arithmetic and logic operations and a cache or register for temporary storage of variables input to and output from the ALU. Unlike an FPGA block (FPGA control logic) that processes pre-set processes or logic independently or in parallel, the MCU supports serial processing but may also support time-sharing multi-processing such as multi-threading. For example, the MCU may be advantageous for sequential or serial tasks and may be composed of a relatively small number of cores to quickly process difficult and small amounts of calculations, whereas the FPGA block (FPGA control logic) may be advantageous for parallel tasks and may quickly process relatively simple and large amounts of calculations. For example, in one embodiment of the present invention, the MCU may function as a central processing unit or a central control unit capable of controlling the overall operation of a diagnostic monitoring system. For example, the MCU may follow a control command received from an administrator terminal through a communication module and transmit a control command (control signal) containing data such as Data, Address, Write, and Read to an FPGA block. For example, it may output a control command to an FPGA circuit containing a Target Address (Device Address) that is the target of the control command among a plurality of optical links, a designation of a write / read mode (Write, Read), and data, and may transmit a control command to the MCU through a parallel communication channel.

[0168] The above FPGA circuit (see FIG. 16) can request diagnostic data such as the connection status of the optical link, the operating status of the optical link, and identification information of the optical link, or receive the requested diagnostic data, or request CRUD (create, read, update, delete) operations of the diagnostic data such as changing or modifying the diagnostic data, for an optical link specified by a control command (e.g., an optical link specified by the Address of the control command, e.g., Target Address or Device Address) among a plurality of optical links connected to a diagnostic monitoring system (see FIG. 14) according to a process or logic set in the FPGA control logic called according to a control command (control signal) of the MCU.

[0169] The above FPGA circuit (see FIG. 14) can transmit a control signal that follows a control command from the MCU to a UART-parallel converter through a parallel communication channel, and the UART-parallel converter can convert parallel data into serial data, such as UART (universal achromous receiver / transmitter) communication data, for example, by forming a UART communication channel, which is an asynchronous serial communication channel, without accompanying a separate clock signal, and it may be possible to read data from a transmission rate (baud rate) defined by the communication protocol and a start bit (e.g., bit 0) and a stop bit (e.g., bit 1).

[0170] The above USB host controller (see FIG. 15) can function as a host for a USB connection formed between a plurality of optical links, wherein each optical link (an FPGA block of the optical link or an optical communication module including an FPGA block) is a device. UART (universal achromous receiver / transmitter) communication data transmitted from a UART-parallel converter through the USB host controller can be converted into USB communication data and transmitted to the USB-connected optical link, and conversely, USB communication data from the USB-connected optical link through the USB host controller can be converted into UART communication data and transmitted to the UART-parallel converter.

[0171] More specifically, the USB host controller (see FIG. 15) may include a UART interface (see FIG. 15) for readjusting data structures such as the format, coding, signal level, and sequence of data following the UART communication protocol, control information such as interpretation of the corresponding signal pattern and transmission control and error correction based on the interpretation, and timing such as speed adjustment between communication hosts, transmission time of messages, and transmission order, to the data structures, control information, and timing following the USB communication protocol, and conversely, a USB interface (see FIG. 15) for readjusting data structures, control information, and timing following the USB communication protocol to the data structures, control information, and timing following the UART communication protocol, and the USB host controller may perform a process for readjusting data structures, control information, and timing between different communication protocols.

[0172] For example, the USB host controller (see FIG. 15) can create and execute two different threads, each containing a main function, within the same process where the execution environment is provided. Within the process providing the execution environment for two different threads, the two different threads can share the code area, data area, and heap area of ​​memory, while the stack area can be allocated individually for each thread.

[0173] For example, two different threads may each include a thread for converting UART communication data following a UART communication protocol to USB communication data following a USB communication protocol (UART interface, see FIG. 15), and conversely, a thread for converting USB communication data following a USB communication protocol to UART communication data following a UART communication protocol (USB interface, see FIG. 15). For example, these different threads (UART interface and USB interface, see FIG. 15) can be executed independently of each other, and each thread for USB-UART conversion (UART interface and USB interface, see FIG. 15) can convert UART communication data or USB communication data input to the USB host controller into USB communication data or UART communication data into a unit unit where error detection or error correction is defined (e.g., a data frame unit or an entire series of continuous signals: e.g., an entire series of continuous signals continuously transmitted from one side forming a communication host to the other side forming a communication host). If the conversion occurs in the middle of a unit unit where error detection or error correction is defined (e.g., a data frame unit or an entire series of continuous signals: e.g., an entire series of continuous signals continuously transmitted from one side forming a communication host to the other side forming a communication host), the UART communication data or USB communication data can be converted into a signal containing an error before error detection or error correction and transmitted to the next stage, so at least a unit unit capable of error detection or error correction (e.g., a data frame unit Or, the conversion from UART to USB can be performed into a whole series of continuous signals: for example, a whole series of continuous signals continuously transmitted from one side forming a communication host to the other side forming a communication host.

[0174] A thread (UART interface, see FIG. 15) for converting UART communication data into USB communication data as input on a data transmission channel from the MCU or FPGA circuit (see FIG. 14) toward a USB-connected optical link, and conversely, a thread (USB interface, see FIG. 15) for converting USB communication data into UART communication data as input on a data transmission channel from the USB-connected optical link toward the MCU or FPGA circuit, can be executed independently of each other, and the two different threads (UART interface and USB interface) can share the code area where functions are stored, the data area where global variables are stored, and the heap area where dynamic memory is allocated within the same process providing the execution environment, while the stack area where local variables or function parameters are stored can be allocated individually to each thread (see FIG. 6 and FIG. 7).As described above, different threads (UART interface and USB interface, see FIG. 15) may each execute independently of each other; however, for example, global variables regarding the connection / disconnection status of the optical link may be stored in a shared data area so that information regarding the connection / disconnection status of the optical link may be shared between different threads (UART interface and USB interface, see FIG. 15); for example, information regarding the connection / disconnection status shared between different threads may be detected from the output level of a GPIO pin of a USB host controller (see FIG. 15) acting as a communication host forming a USB connection with the optical link; for example, the USB host controller forming a USB connection with each optical link may switch the output level of the GPIO pin to a high / low signal according to the transition of the connection / disconnection status of each optical link; such switching of the output level of the GPIO pin of the USB host controller may be detected by the MCU, and a reset operation of the USB host controller may be initiated under the control of the MCU; and the optical shared between the threads (UART interface and USB interface, FIG. 15) executing in the USB host controller Global variables regarding the connection / disconnection of links can be changed.

[0175] In one embodiment of the present invention, by ensuring that different threads (UART interface and USB interface) executed on the USB host controller (see FIG. 15) are executed independently of each other, errors resulting from conflicts between these different threads, such as conflicts between functions, libraries, variables, etc. of the different threads, can be fundamentally prevented.For example, each thread for the above UART-USB conversion (UART interface and USB interface, see FIG. 15) may be executed independently of each other, and each thread for the UART-USB conversion may convert UART communication data or USB communication data input to the USB host controller into USB communication data or UART communication data in the form of a unit unit where error detection or error correction is defined, or a series of continuous data entire units transmitted from one side to the other between communication hosts (entire unit received up to the last byte). If UART-USB conversion occurs in the middle of a series of continuous data entire units transmitted from one side to the other between communication hosts, or a unit unit where error detection or error correction is defined, the data may be converted into data containing errors before error detection or error correction of the UART communication data or USB communication data and transmitted to the next stage (optical link or UART-parallel converter). Therefore, a unit unit capable of error detection or error correction (e.g., a data frame unit) or a series of continuous data transmitted from one side to the other between communication hosts UART-USB conversion can be performed in whole units (whole units received up to the last byte). For example, in one embodiment of the present invention, rather than UART-USB conversion being performed in units of data frames capable of error detection or error correction, cross-conversion operation can be performed only after receiving the entire data up to the last byte as a whole unit of a series of continuous data transmitted from one side to the other between a communication host (a UART-parallel converter and a USB host controller or an optical link and a USB host controller).

[0176] The USB host controller (see FIG. 15) can manage a USB connection in which the USB host controller itself is the host and an optical link (an FPGA block of each optical link or an optical communication module including an FPGA block) that forms a USB connection with a diagnostic monitoring system including the USB host controller is the device. For example, the USB host controller can detect the USB connection of the optical link and output the USB connection / disconnection status of the optical link through a separate GPIO (general purpose IO) pin. For example, in one embodiment of the present invention, the USB host controller (see FIG. 15) can output a high signal from the GPIO pin when the optical link is in a USB connection state, and output a low signal from the GPIO pin when the optical link is in a USB disconnection state. In this way, by switching the output of the GPIO pin (see FIG. 15) of the USB host controller to a high / low signal according to the switching of the USB connection / disconnection state, the MCU that detects the switching of the output of the GPIO pin of the USB host controller can initiate a reset operation for the USB host controller that detects the switching of the output of the GPIO pin. For example, in one embodiment of the present invention, as the reset operation of the USB host controller is initiated under the control of the MCU, initialization for the USB connection can be performed. For example, the USB host controller can connect CC (Configuration Channel, CC1, CC2, see FIG. 19) to a pull-up resistor (Rp, see FIG. 20) so that the USB host controller can be role-determined as a host (DFP, Down Facing Port) according to the USB connection. For example, in the initialization of the USB host controller, an initialization that sets the output level of the USB host controller can be performed.For example, in various embodiments of the present invention, the CC (Configuration Channel, CC1, CC2, see FIG. 19) of the USB host controller may perform baseband communication (e.g., peak-to-peak 1.1V) for setting up a USB communication channel, and may also be connected to VCON to supply power to a device such as an EMIC (Electronically Marked IC). In the event of a USB connection of an optical link, it may display an output level different from the state connected to a pull-up resistor (Rp, see FIG. 19) for detecting the initial connection state or initial role setting. In order to detect the connection state and determine the role between USB communication hosts in a subsequent USB connection through the initialization of the USB host controller, for example, the CC (Configuration Channel) of the USB host controller may be connected to a pull-up resistor (Rp, see FIG. 20) so that the USB host controller is role-set as a host (DFP, Down-Facing Port), and thus the output level may be initialized.

[0177] For example, in one embodiment of the present invention, the reset operation of the USB host controller (see FIG. 15) may include setting the output level of the GPIO pin of the USB host controller and creating different threads for UART-USB conversion, for example, a thread (UART interface) for converting from UART communication data to USB communication data and a kernel object for managing the thread may be created, and a thread (USB interface) for converting from USB communication data to UART communication data and a kernel object for managing the thread may be created, and the threads (UART interface and USB interface) thus created may be executed.

[0178] In one embodiment of the present invention, the USB host controller (see FIG. 15) can detect a USB connection of an optical link and switch the output level of a GPIO pin to a high signal, and the USB host controller can determine whether the USB device (optical link) for which the USB connection has been detected is a predefined optical link through device recognition (emulation) of the optical link (FPGA block of the optical link) for which the USB connection has been detected, along with detection of the USB connection (e.g., detection of a connection of a counterpart device via CC). More specifically, the USB host controller can identify the VID (Vendor ID) as a 16-bit identification identifier for identifying the manufacturer and the PID (Product ID) as a 16-bit identification identifier for identifying the manufacturer's product as identification identifiers assigned to the corresponding USB device (optical link) through device recognition, and can recognize the connected USB device (optical link) from the combination of the VID and PID and can check whether it is a predefined USB device (optical link). In one embodiment of the present invention, if the USB host controller (see FIG. 15) detects the connection of a USB device and determines that the USB device recognized from the combination of VID and PID obtained through device recognition of the connected USB device corresponds to a predefined or pre-set optical link, the output of the GPIO pin of the USB host controller can be output as a high signal indicating the connection status. Conversely, if the USB host controller detects the connection of a USB device but determines that the USB device recognized from the combination of VID and PID obtained through device recognition of the connected USB device does not correspond to a predefined or pre-set optical link, the USB host The controller can output a low signal indicating a disconnected state to the GPIO pin of the USB host controller despite detecting a USB connection.

[0179] In various embodiments of the present invention, diagnostic monitoring through a diagnostic monitoring system (see FIG. 14) requires a USB device that follows a pre-set rule or protocol for smooth communication with the diagnostic monitoring system. For example, a USB device produced by the same manufacturer as the diagnostic monitoring system needs to follow a pre-set rule regarding data structures such as data format, coding, signal level, and sequence in communication with the diagnostic monitoring system, control information such as interpretation of the corresponding signal pattern and transmission control and error correction based on the interpretation, and timing such as speed adjustment between communication hosts, message transmission time, and transmission order. Additionally, even if a USB device is produced by the same manufacturer as the diagnostic monitoring system, for example, it is necessary to block connections with other USB devices other than the optical link in consideration of the connection with the diagnostic monitoring system for diagnosing and monitoring the connection status of the optical link. Based on such considerations, a diagnostic monitoring system according to one embodiment of the present invention can detect a USB connection, read identification markers of VID and PID from device recognition (emulation) of a USB device in which a USB connection is detected, determine whether the recognized USB device corresponds to a predefined USB device or a pre-set USB device according to the combination of the read VID and PID, and output a high / low signal to the output of a GPIO pin of a USB host controller according to the result, and perform diagnostic monitoring of a USB-connected optical link by an MCU that detects the output of a GPIO pin of a USB host controller.

[0180] In one embodiment of the present invention, data and power may be supplied together via a USB connection depending on the USB type supported by the diagnostic monitoring system; for example, power supply may be possible along with data communication between the diagnostic monitoring system forming the USB connection and the optical link; for example, driving power for the optical link (FPGA block of the optical link, see FIG. 3, or optical communication module including the FPGA block, see FIG. 4a and 4b) may be supplied from a diagnostic monitoring system connected to a commercial power grid; in response to a request for power cutoff of the optical link (a power off request) received through a manager interface connected via a communication network (along with the Target Address or Device Address of the optical link to be cut off), the MCU may control the USB host controller to cut off the driving power of the optical link from the USB host controller; in this case, the USB host controller (see FIG. 15) may switch the state of connection / disconnection with the optical link to be cut off, and accordingly, the output level of the GPIO pin of the USB host controller may be switched to a high / low signal, and such GPIO of the USB host controller The MCU, upon detecting a transition in the output level of the pin, can initiate a reset operation of the USB host controller.In one embodiment of the present invention, a reset operation of a USB host controller may be initiated in response to an event of power cutoff from the USB host controller following the disconnection of a USB-connected optical link and a request from a manager interface received from a communication network; the USB host controller may be initialized in accordance with such a reset operation of the USB host controller; a USB communication channel with the optical link may be re-established as the USB connection is detected again after the reset operation following the disconnection of the USB-connected optical link; and as power supply is resumed after the reset operation following the power cutoff from the USB host controller, for example, power supply from the USB host controller may be resumed upon receipt of a request (power on request) from a manager interface via a communication network, thereby re-establishing the USB communication channel with the optical link. At this time, the re-establishment of the USB communication channel with the optical link may mean that the flow of data input / output from the optical link with the established USB connection channel can be processed by the MCU, which detects a change in the output level of a GPIO pin of the USB host controller (see FIG. 15); and the flow of data input / output from the optical link with the established USB connection channel is under the control of the MCU This means that tasks related to the corresponding optical link can be processed by multiplexing together with other data transmission channels through the multiplexer (MUX) of the FPGA circuit (see Fig. 16).In various embodiments of the present invention, the diagnostic monitoring system (see FIG. 14) may turn off power by cutting off power supply from the USB host controller to the optical link in accordance with a request (control command) from the administrator interface transmitted through a communication network, or may turn off power in accordance with a control signal transmitted to the optical link along a data transmission channel (for example, the USB host controller cuts off power supplied to the USB-connected optical link in accordance with a request transmitted from the administrator interface through a communication network). For example, the MCU that transmits a control signal to turn off power to the optical link toward the USB host controller in accordance with a request from the administrator interface transmitted through a communication network may initiate a reset operation for the USB host controller, or the USB host controller (see FIG. 15) may switch the output level of a GPIO pin as a connection from the USB-connected optical link is not detected due to the cutting off of power supply from the USB host controller toward the optical link, and the MCU that detects such switching of output level may initiate a reset operation of the USB host controller.

[0181] In one embodiment of the present invention, the output level of a GPIO pin of a USB host controller (see FIG. 15) forming a communication host for a USB connection can be detected through an MCU that generally controls the operation of a diagnostic monitoring system so that tasks related to an optical link with a USB connection interrupted are not performed according to the switching of USB connection / disconnection with the optical link, and tasks related to an optical link with power supply interrupted are not performed according to a request (power off request) received from an administrator interface via a communication network. The MCU that detects the switching of the output level of the GPIO pin of the USB host controller can block the flow of data input / output related to the optical link with USB disconnection or power supply interrupted from the USB host controller while initiating a reset operation of the USB host controller, and as the flow of data input / output from the USB host controller is interrupted, the time slot allocated to the data transmission channel with which data input / output was interrupted is transferred through the remaining data transmission channel with the other USB-connected optical link via asynchronous time-division multiplexing (see FIG. 10b) through a multiplexer (MUX) of an FPGA circuit (see FIG. 16). By allocating to input / output data, the MCU connected to the FPGA circuit (see FIG. 16) can be prevented from performing tasks related to the optical link when the USB is disconnected or the power supply is interrupted; for example, in one embodiment of the present invention, errors in data processing can be fundamentally prevented through a reset operation of a USB host controller (see FIG. 15) that forms a USB communication channel for data input / output with the optical link while forming a USB connection with the optical link.Error transmission and error processing of data through a data transmission channel formed within a diagnostic monitoring system (see FIG. 14) can be blocked by resetting a USB host controller (Fig. 15) that transmits and receives input / output data toward the optical link (the FPGA block of the optical link (see FIG. 4) or an optical communication module including the FPGA block (see FIG. 4a and FIG. 4b)) while forming a USB connection with the optical link.

[0182] The communication module (see FIG. 14) can receive a request (control command) including Read, Write, Address, Data, etc. transmitted from a manager interface connected via an Ethernet communication network, and can transmit diagnostic data including at least one of the connection status, operation status of the optical link, and identification information of the optical link for a plurality of optical links connected via USB to the diagnostic monitoring system to the manager interface via the communication network. For example, in one embodiment of the present invention, the diagnostic monitoring system can extract the connection address of the manager interface included in the header of an IP packet containing the request (control command) of the manager interface received via the communication network or the request, and transmit the requested data (e.g., diagnostic data including at least one of the connection status of the optical link, operation status of the optical link, and identification information of the optical link) by referencing the extracted connection address of the manager interface. For example, in various embodiments of the present invention, the communication module may transmit various status information regarding an optical link connected via USB to a diagnostic monitoring system in response to a request (control command) from a manager interface transmitted through a communication network. As described above, as information regarding the connection status of the optical link, in addition to status information that may affect the image quality rendered on the display sink side, various status information of the optical link, including identification information of the optical link such as the model name of the optical link and the product serial number of the optical link, and operating status of the optical link such as operating voltage and operating temperature, may be obtained from the corresponding optical link (FPGA block of the optical link) and transmitted to the manager interface through the communication network.

[0183] For example, an administrator or the administrator interface that has checked the status of the optical link through a administrator interface (see FIG. 14) connected via a communication network may transmit a request (control command) to change the status of the optical link to a diagnostic monitoring system, and the communication module may receive a request (control command) from the administrator interface to control the operation of the optical link, such as turning the power on / off of the optical link connected via USB to the diagnostic monitoring system. For example, in one embodiment of the present invention, an MCU that receives a request (control command) to turn off the power of the optical link from the administrator interface may transmit a power-off control signal toward a USB host controller connected to the corresponding optical link, and the USB host controller may turn off the power of the corresponding optical link while cutting off the power supply to the corresponding optical link. Conversely, an MCU that receives a request to turn on the power of the optical link from the administrator interface may transmit a power-on control signal toward a USB host controller connected to the corresponding optical link, and the USB host controller may turn on the power of the corresponding optical link while starting the power supply to the corresponding optical link. At this time, the USB host controller may not detect the connection status of the optical link or may detect the connection status of the optical link depending on whether the power supply is cut off or the power supply is started, and may switch the output of the GPIO pin of the USB host controller (see FIG. 15) to high / low depending on whether the connection status of the optical link is detected.

[0184] In one embodiment of the present invention, the diagnostic monitoring system (see FIG. 14) can perform diagnostic monitoring regarding various optical link status information, such as status information of a plurality of optical links, information regarding the connection status with a display source or display sink that may affect the image quality rendered on the display sink side, operating status of the optical link such as the operating voltage and operating temperature of the optical link, and identification information of the optical link. In this sense, the diagnostic data that can be diagnostically monitored and managed through the diagnostic monitoring system in one embodiment of the present invention may comprehensively refer to information regarding various states of the optical link, such as information regarding the connection status with a display source or display sink (e.g., status information that may affect the image quality rendered on the display sink side, such as the presence or absence of an output signal on the display source side and the presence or absence of an input signal on the display sink side), operating status of the optical link such as the operating voltage or operating temperature, and identification information regarding the optical link itself, such as the model name or serial number of the optical link. In various embodiments of the present invention, the diagnostic monitoring system, along with the monitoring and management of diagnostic data, the display source and the display Diagnostic monitoring and management of image-imposed data may be provided, comprising at least one of channel setting data related to channel settings of a main channel (or main lane) for transmitting image data between sinks and rendering setting data related to rendering performance of a display sink. For example, the diagnostic monitoring system may provide monitoring and management of image-imposed data comprising channel setting data related to channel settings of a main channel (or main lane), such as DPCD, and rendering setting data related to rendering of a display sink, such as EDID.More specifically, monitoring and management regarding image-imposed data, such as requesting image-imposed data for each optical link (FPGA block of the optical link (see FIG. 14)), receiving and changing the requested image-imposed data, can be provided. For example, through the request, reception, and modification of channel configuration data related to the channel configuration of a main channel (or main lane) requested from the administrator interface, the administrator interface or the administrator may check the currently configured channel configuration data, for example, regarding the emphasis level (pre-emphasis level or de-emphasis level) of the signal pattern transmitting video data and the swing level related to peak-to-peak voltage, and request a change to other channel configuration data optimized for the optical link (for example, requesting a change to channel configuration data optimized for the optical link in the event of a failure in link training); and through the request, reception, and modification of rendering configuration data requested from the administrator interface, the administrator interface or the administrator may check the rendering configuration data related to the rendering performance of the currently configured display sink, for example, resolution and refresh rate, and request a change to other rendering configuration data optimized for the display sink (for example, changing rendering performance such as resolution and refresh rate to improve the video quality of the display sink).

[0185] In one embodiment of the present invention, the UART-parallel converter (see FIG. 14) can convert parallel communication data transmitted from an FPGA circuit into UART communication data and transmit it to a USB host controller, and conversely, convert UART communication data transmitted from a USB host controller into parallel communication data and transmit it to an FPGA circuit. At this time, the UART-parallel converter may check the output level of a GPIO pin (see FIG. 15) of a USB host controller and, depending on the output level, may not perform UART-parallel conversion for data input / output through a data transmission channel connected to the corresponding USB host controller. For example, if the output level of a GPIO pin of a USB host controller is switched to a low signal level indicating the disconnection of an optical link connected via USB, the UART-parallel converter may not perform UART-parallel conversion for data input / output through a data transmission channel connected to a USB host controller whose output level has been switched to a low signal.In one embodiment of the present invention, the diagnostic monitoring system may include a plurality of UART-parallel converters (see FIG. 14) connected to each data transmission channel, and each UART-parallel converter (see FIG. 14) may check the output level of a GPIO pin of a USB host controller connected on its data transmission channel, for example, each UART-parallel converter may check the output level of a GPIO pin (see FIG. 15) of a USB host controller connected on its data transmission channel at a preset periodic interval, and a UART-parallel converter in which the GPIO pin of the USB host controller connected on its data transmission channel outputs a high signal may perform UART-parallel conversion, while a UART-parallel converter in which the GPIO pin of the USB host controller connected on its data transmission channel outputs a low signal may not perform UART-parallel conversion. In various embodiments of the present invention, a UART-parallel converter (see FIG. 14) connected to each data transmission channel may check the output level of a GPIO pin (see FIG. 15) of a USB host controller connected on its own data transmission channel and may perform UART-parallel conversion or not perform UART-parallel conversion depending on the output level of the checked GPIO pin, or may perform UART-parallel conversion or not perform UART-parallel conversion depending on the output level of the GPIO pin (see FIG. 15) of a USB host controller connected on each data transmission channel under the control of an MCU that checks the output level of the GPIO pin (see FIG. 15) of a USB host controller connected on each data transmission channel.At this time, the UART-parallel converter (see FIG. 14) and / or MCU check the output level of the GPIO pin (see FIG. 15) of the USB host controller connected to each data transmission channel at preset periodic intervals, and depending on the output level of the GPIO pin (see FIG. 15) of the USB host controller connected to each data transmission channel, the conversion operation of the UART-parallel converter (see FIG. 14) connected to each data transmission channel may or may not perform the conversion operation depending on the output level of the GPIO pin of the USB host controller connected to its data transmission channel. In other words, the UART-parallel converter (see FIG. 14) connected to each data transmission channel may or may not perform the UART-parallel conversion operation depending on the output level of the GPIO pin of the USB host controller connected to its data transmission channel.

[0186] In one embodiment of the present invention, the turn-on process of the diagnostic monitoring system (see FIG. 14) may include an initialization process for each component connected to the data transmission channel of the diagnostic monitoring system. For example, in the initialization of the UART-parallel converter connected to each data transmission channel, the communication channel of the UART may be set, and the transmission rate (Baud rate), data bit, stop bit, parity bit, etc. of the UART communication channel may be set. For example, in one embodiment of the present invention, the UART communication channel may be set to a transmission rate (Baud rate): 115200 bps, data bit: 8 bit, non-parity bit, and one stop bit.

[0187] The communication module (see FIG. 14) can transmit diagnostic data transmitted from each optical link to the administrator interface via a communication network, or receive requests including Read, Write, Address, Data, etc. transmitted from the administrator interface via the communication network. For example, during the initialization of the communication module, an Ethernet communication network can be configured using the User Datagram Protocol (UDP) method, and network information such as an IP address, Sub Mask, Gateway, and MAC Address can be configured. Additionally, the USB host controller can perform a hardware reset, and the initialization of the USB host controller following the reset operation can be performed according to the design of the firmware.

[0188] Although the present invention has been described with reference to embodiments illustrated in the attached drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Explanation of the symbols

[0189] Lane 0~3, Channel 0~2, Clock Channel: Main Channel AUX Channel, DDC Channel: Auxiliary Channel HPD line: Hot Plug Detection line CEC line: Customer Electronic Control line Encoder: Encoder input register: input register SDA, SCL: Data line, Clock line MUX: Multiplexer Diagnosis communication data: Diagnostic data

Claims

Claim 1 An optical link forming a main channel for transmitting video data and a side channel for transmitting video-imposed data regarding the channel settings of the main channel, and an optical link for providing a diagnostic monitoring function that generates a data frame for transmitting together diagnostic data including video-imposed data and status information of the optical link through the side channel from time-division multiplexing. Claim 2 An optical link for providing a diagnostic monitoring function according to claim 1, characterized in that the data frame includes a special code area and a data area assigned to a time slot or sub-frame of a time-divided 8-unit unit. Claim 3 An optical link for providing a diagnostic monitoring function, characterized in that, in paragraph 2, the special code assigned to the special code area includes control information for a time slot or sub-frame of a unit. Claim 4 An optical link for providing a diagnostic monitoring function according to claim 2, wherein, with respect to the data frame, depending on the presence or absence of diagnostic data, the data frame of a non-diagnostic instance in which diagnostic data does not exist comprises a special code area and a data area alternately assigned to time slots or sub-frames of eight time-division units, and the data frame of a diagnostic instance in which diagnostic data exists comprises a special code area assigned to a time slot or sub-frame of a unit corresponding to the start of the data frame in a time slot or sub-frame of eight time-division units, and a sequence of data areas assigned to time slots or sub-frames of other unit units that follow the time slot or sub-frame of the unit unit in which the special code area is assigned along the time axis. Claim 5 An optical link for providing a diagnostic monitoring function, characterized in that, in paragraph 4, communication traffic related to image-imposed data, including a request for image-imposed data and a reply to the request, is performed more frequently than communication traffic related to diagnostic data, including a request for diagnostic data and a reply to the request. Claim 6 An optical link for providing a diagnostic monitoring function, characterized in that, in a data frame of a non-diagnostic instance where the diagnostic data does not exist, the time-slot or sub-frame assigned to the diagnostic data is filled with stuffing symbols instead of being filled with image-imposed data other than the diagnostic data, in accordance with claim 4. Claim 7 An optical link for providing a diagnostic monitoring function, wherein, in paragraph 4, the data frame of the non-diagnostic instance and the data frame of the diagnostic instance include a Video Interface Signal segment corresponding to the start of the data frame and Side First packet, Side Second packet, and Side Third packet segments following the Video Interface Signal segment along the time axis, and the Video Interface Signal segment includes a special code area and a data area, wherein the special code area of ​​the Video Interface Signal segment is assigned to a special code indicating the start of the data frame, and the data area of ​​the Video Interface Signal segment is assigned to image-imposed data. Claim 8 An optical link for providing a diagnostic monitoring function according to claim 7, wherein each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the non-diagnostic instance includes a special code area and a data area, and the data areas of the Side First packet, Side Second packet, and Side Third packet segments are filled with stuffing symbols in place of non-existent diagnostic data. Claim 9 An optical link for providing a diagnostic monitoring function according to claim 7, wherein each of the Side First packet, Side Second packet, and Side Third packet segments of the data frame of the diagnostic instance includes a time slot or sub-frame of two unit units that precede and follow along the time axis, the preceding time slot of the Side First packet is filled with a diagnostic data start symbol, the following time slot of the Side Third packet is filled with a diagnostic data end symbol, and the time axis from the following time slot of the Side First packet to the preceding time slot of the Side Third packet is filled with diagnostic data. Claim 10 An optical link for providing a diagnostic monitoring function, characterized in that, in claim 9, the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet are each filled with a diagnostic data start symbol and a diagnostic data end symbol, and the preceding time slot or preceding sub-frame of the Side First packet and the succeeding time slot or succeeding sub-frame of the Side Third packet are each allocated as a data area that can be modified between communication hosts. Claim 11 An optical link for providing a diagnostic monitoring function, characterized in that, in paragraph 2, the time-divided time slot or sub-frame is allocated as 8 bits. Claim 12 An optical link for providing a diagnostic monitoring function according to claim 11, characterized in that the data frame is allocated a total of 64 bits of 8 unit units, with each unit unit consisting of a time-division time slot or sub-frame allocated to 8 bits. Claim 13 An optical link for providing a diagnostic monitoring function according to claim 1, wherein the optical link is connected on the side channel and includes an FPGA block for generating the data frame. Claim 14 An optical link for providing a diagnostic monitoring function according to claim 13, wherein the FPGA block comprises a multiplexer for selecting and outputting an input channel assigned to the current time slot or sub-frame among a plurality of input channels multiplexed through a time-division time slot or sub-frame. Claim 15 An optical link for providing a diagnostic monitoring function according to claim 14, wherein, depending on the presence or absence of diagnostic data, in the generation of a data frame of a non-diagnostic instance where diagnostic data does not exist, a special code, image-imposed data, and stuffing symbols representing diagnostic data are stored in a plurality of input channels of the multiplexer or a plurality of input registers connected to the plurality of input channels, and in the generation of a data frame of a diagnostic instance where diagnostic data exists, a special code, image-imposed data, and diagnostic data are stored in a plurality of input channels of the multiplexer or a plurality of input registers connected to the plurality of input channels. Claim 16 An optical link for providing a diagnostic monitoring function according to claim 14, wherein the FPGA block comprises a SerDes (Serializer + Deserializer) for converting a special code, image-imposed data, and diagnostic data, or parallel data forming image-imposed data and stuffing symbols, output from the output channel of the multiplexer, into serial data. Claim 17 An optical link for providing a diagnostic monitoring function according to claim 16, wherein the above SerDes (Serializer + Deserializer) takes as input a sequence of parallel data in which image-imposed data and diagnostic data or image-imposed data and stuffing symbols form a multiplexed data frame, and outputs a sequence of serial data in which image-imposed data and diagnostic data or image-imposed data and stuffing symbols form a multiplexed data frame. Claim 18 An optical link for providing a diagnostic monitoring function, wherein, in claim 1, the diagnostic data comprises at least one of the connection status of the optical link, the operation status of the optical link, and identification information of the optical link itself. Claim 19 An optical link for providing a diagnostic monitoring function, wherein, in claim 1, the image assignment data comprises channel setting data related to channel setting of a main channel for transmitting image data and rendering setting data related to rendering of a display sink on which the image data is rendered.

Images