Display device and electronic device

Abstract

The display device of the present invention comprises a display panel including a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area, a plurality of display pads arranged in a pad area within the non-display area, a plurality of signal lines connected to the plurality of pixels, a driving chip electrically connected to the plurality of signal lines, and a test unit arranged adjacent to the driving chip. The test unit includes a plurality of test pads spaced apart from the plurality of display pads in a first direction, a plurality of connecting wires connecting the plurality of test pads and the plurality of signal lines, and a switching transistor connected to the plurality of connecting wires.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device, and more specifically, to a display device and an electronic device with improved reliability. Background Technology

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light-emitting display panels, electro-wetting display panels, and electrophoretic display panels.

[0003] The display panel can be electrically connected by bonding it to electronic components such as a flexible circuit board. The problem to be solved

[0004] The present invention aims to provide a display device and an electronic device with improved reliability by preventing corrosion of the test pad through a switching transistor. means of solving the problem

[0005] A display device according to one embodiment of the present invention includes a display panel comprising a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area, a plurality of display pads arranged in a pad area within the non-display area, a plurality of signal lines connected to the plurality of pixels, a driving chip electrically connected to the plurality of signal lines, and a test unit arranged adjacent to the driving chip. The test unit includes a plurality of test pads spaced apart from the plurality of display pads in a first direction, and a plurality of connecting wires extending in a second direction intersecting the first direction and connecting the plurality of test pads and the plurality of signal lines. Each of the plurality of connecting wires includes a plurality of switching transistors electrically connected to the plurality of test pads and the plurality of signal lines.

[0006] A display device according to one embodiment of the present invention includes a display panel comprising a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area, a plurality of display pads arranged in a pad area within the non-display area, a plurality of signal lines connected to the plurality of pixels, and an inspection unit arranged adjacent to the plurality of display pads. The inspection unit includes a plurality of inspection pads spaced apart from the plurality of display pads in a first direction, and a plurality of connecting wires connecting the plurality of inspection pads and the plurality of signal lines. The plurality of connecting wires include a switching transistor that is turned on in a first mode of the display panel and turned off in a second mode different from the first mode of the display panel.

[0007] An electronic device according to one embodiment of the present invention includes a display device for displaying an image and a processor for providing image data to the display device. The display device includes a display panel comprising a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area, a plurality of display pads arranged in a pad area within the non-display area, a plurality of signal lines connected to the plurality of pixels, a driving chip electrically connected to the plurality of signal lines, and a test unit arranged adjacent to the driving chip. The test unit includes a plurality of test pads spaced apart from the plurality of display pads in a first direction and a plurality of connecting wires connecting the plurality of test pads and the plurality of signal lines. Each of the plurality of connecting wires includes a plurality of switching transistors electrically connected to the plurality of test pads and the plurality of signal lines. Effects of the invention

[0008] In the present invention, switching transistors can be arranged between a test pad and a signal line for testing a display panel. The gate voltage of the switching transistors can be adjusted to turn the switching transistors on or off. When the switching transistors are turned off, no current flows through the test pads, and no potential difference is generated in the test pads. As a result, corrosion caused by the potential difference in the test pads is prevented, and a reliable display device can be provided. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention. FIG. 2 is a schematic diagram of various electronic devices according to one embodiment of the present invention. FIG. 3 is a combined perspective view of an electronic device according to one embodiment of the present invention. FIG. 4 is an exploded perspective view of an electronic device according to one embodiment of the present invention. FIG. 5 is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 6 is a plan view of a display panel according to one embodiment of the present invention. FIG. 7 is a plan view of an input detection unit according to one embodiment of the present invention. FIG. 8 is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 9 is a perspective view of an electronic device according to one embodiment of the present invention. FIGS. 10 and FIGS. 11 are drawings for explaining the operation of the inspection pads of the present invention. FIGS. 12a and FIGS. 12b are enlarged drawings of a portion of a display panel according to one embodiment of the present invention. FIGS. 13a and FIGS. 13b are drawings for explaining the operation of the inspection pads of the present invention. Specific details for implementing the invention

[0010] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0011] In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed / connected / joined on the other component, or that a third component may be placed between them.

[0012] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And / or” includes all one or more combinations that the associated components may define.

[0013] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0014] Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0015] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0016] In this specification, “direct placement” may mean that there are no additional layers, films, regions, plates, etc. between a part such as a layer, film, region, or plate and another part. For example, “direct placement” may mean that two layers or two members are placed without using additional members such as adhesive members between them.

[0017] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0018] Hereinafter, a display device of one embodiment will be described with reference to the drawings.

[0020] FIG. 1 is a block diagram of an electronic device according to one embodiment of the present invention.

[0021] Referring to FIG. 1, an electronic device (ED) according to one embodiment of the present invention may include a display module (DM), a processor (PC), a memory (MM), and a power module (PM).

[0022] The processor (PC) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0023] The memory (MM) may store data information necessary for the operation of the processor (PC) or the display module (DM). When the processor (PC) executes an application stored in the memory (MM), video data signals and / or input control signals are transmitted to the display module (DM), and the display module (DM) can process the received signals to output video information through a display screen.

[0024] The power module (PM) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of an electronic device (ED).

[0025] At least one of each component of the aforementioned electronic device (ED) may be included in a display device according to the embodiments described below. Additionally, some of the individual modules functionally included within a single module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (DM), and the processor (PC), memory (MM), and power module (PM) may be provided in the form of other devices within the electronic device (ED) that are not the display device.

[0026] FIG. 2 is a schematic diagram of various electronic devices according to one embodiment of the present invention.

[0027] Referring to FIG. 2, various electronic devices to which a display module according to one embodiment of the present invention is applied may include not only image display electronic devices such as a smartphone (ED-1a), a tablet PC (ED-1b), a laptop (ED-1c), a TV (ED-1d), and a desk monitor (ED-1e), but also wearable electronic devices such as smart glasses (ED-2a), a head-mounted display (ED-2b), and a smart watch (ED-2c), and automotive electronic devices (ED-3) such as a Center Information Display (CID) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0028] FIG. 3 is an assembled perspective view of an electronic device according to one embodiment of the present invention. FIG. 4 is an exploded perspective view of an electronic device according to one embodiment of the present invention.

[0029] Referring to FIGS. 3 and 4, the electronic device (ED) may be a device that is activated by an electrical signal, displays an image (IM), and detects an external input (TC). For example, the electronic device (ED) may include devices such as a television, monitor, external billboard, personal computer, laptop computer, personal digital terminal, automotive instrument panel, center fascia, navigation, rearview mirror display, game console, smartphone, tablet, smart watch, smart glasses, head-mounted display, and camera. However, the embodiments of the electronic device (ED) described above are exemplary and are not limited to any one of them without departing from the concept of the present invention. In this embodiment, the electronic device (ED) is illustrated as a mobile phone.

[0030] The electronic device (ED) may have a rectangular shape having short sides extended in a first direction (DR1) on a plane and long sides extended in a second direction (DR2) intersecting the first direction (DR1). However, it is not limited thereto, and the electronic device (ED) may have various shapes such as a circle or a polygon on a plane.

[0031] In this embodiment, the third direction (DR3) may be defined as a direction perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2). The front (or top) and back (or bottom) surfaces of each component constituting the electronic device (ED) may be opposite to each other in the third direction (DR3), and the normal direction of each of the front and back surfaces may be substantially parallel to the third direction (DR3). The distance between the front and back surfaces defined along the third direction (DR3) may correspond to the thickness of the component.

[0032] In this specification, “in a plane” may be defined as a state viewed from a third direction (DR3). In this specification, “in a cross-section” may be defined as a state viewed from a first direction (DR1) or a second direction (DR2). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and can be converted to other directions.

[0033] Electronic devices (EDs) can be rigid or flexible. “Flexible” means the ability to bend and can include everything from structures that fold completely to structures that can bend at the nanometer level. For example, flexible electronic devices (EDs) may include curved electronic devices, rollable electronic devices, or foldable electronic devices.

[0034] The electronic device (ED) can display an image (IM) through a display surface (FS) parallel to each of the first direction (DR1) and the second direction (DR2). The image (IM) can include a still image as well as a dynamic image. In FIG. 3, a clock and icons are illustrated as examples of the image (IM).

[0035] The display surface (FS) of the electronic device (ED) may include only a flat surface, or it may further include a curved surface bent from at least one side of the flat surface. The display surface (FS) may correspond to the front surface of the electronic device (ED) and may simultaneously correspond to the front surface of the window (WM). Hereinafter, the display surface (FS) of the electronic device (ED) and the front surface (FS) of the window (WM) will use the same reference numeral.

[0036] An electronic device (ED) according to one embodiment can detect an external input (TC) applied from the outside. The external input (TC) may include various forms of input such as force, pressure, temperature, or light. In this embodiment, the external input (TC) is illustrated as a user's hand applied to the front of the electronic device (ED). However, this is illustrated as an example, and the external input (TC) may include inputs applied in close proximity to the electronic device (ED), such as contact by a pen or hovering.

[0037] The electronic device (ED) can detect user input through a display surface (FS) defined on the front and respond to the detected input signal. However, the area of ​​the electronic device (ED) that detects external input (TC) is not limited to the front of the electronic device (ED) and may be changed according to the design of the electronic device (ED). For example, the electronic device (ED) may detect user input applied to the side or back of the electronic device (ED).

[0038] The electronic device (ED) may include a display device (DD), an electronic module (ELM), a power module (PM), and a housing (HAU). The display device (DD) may include a window (WM) and a display module (DM). The window (WM) and the housing (HAU) may be combined to form the exterior of the electronic device (ED).

[0039] A window (WM) can be placed on a display module (DM). The window (WM) covers the front surface (IS) of the display module (DM) and can protect the display module (DM) from external impacts and scratches. The window (WM) can be bonded to the display module (DM) through an adhesive layer.

[0040] The window (WM) may include an optically transparent insulating material. For example, the window (WM) may include glass or synthetic resin as a base film. The window (WM) may have a single-layer or multi-layer structure. For example, a multi-layer window (WM) may include synthetic resin films bonded with an adhesive, or a glass film and a synthetic resin film bonded with an adhesive. The window (WM) may further include functional layers, such as an anti-fingerprint layer, a phase control layer, and a hard coating layer, disposed on a transparent base film.

[0041] The front surface (FS) of the window (WM) may correspond to the front surface (FS) of the electronic device (ED). The front surface (FS) of the window (WM) may include a transparent area (TA) and a bezel area (BZA).

[0042] The transmission region (TA) may be an optically transparent region. The transmission region (TA) may transmit an image (IM) provided by a display module (DM). In this embodiment, the transmission region (TA) is depicted as having a rectangular shape, but is not limited thereto, and the transmission region (TA) may have various shapes.

[0043] The bezel area (BZA) may be an area with a lower light transmittance compared to the transmission area (TA). The bezel area (BZA) may correspond to an area where a material having a predetermined color is printed. The bezel area (BZA) prevents the transmission of light, thereby preventing a component of the display module (DM) placed overlapping the bezel area (BZA) from being visible from the outside.

[0044] The bezel region (BZA) may be adjacent to the transparent region (TA). The shape of the transparent region (TA) may substantially be defined by the bezel region (BZA). For example, the bezel region (BZA) may be positioned outside the transparent region (TA) to surround the transparent region (TA). However, this is illustrated as an example, and the bezel region (BZA) may be adjacent to only one side of the transparent region (TA) or positioned on a side rather than the front of the electronic device (ED). Additionally, the bezel region (BZA) may be omitted.

[0045] The display module (DM) can be positioned between the window (WM) and the housing (HAU). The display module (DM) can display an image (IM) and detect an external input (TC). The image (IM) can be displayed on the front (IS) of the display module (DM). The front (IS) of the display module (DM) may include an active area (AA) and a peripheral area (NAA).

[0046] The active area (AA) may be an area that is activated according to an electrical signal. For example, the active area (AA) may be an area where an image (IM) is displayed and simultaneously an area where an external input (TC) is detected. The active area (AA) may overlap with at least a portion of the transparent area (TA). Accordingly, the user may view the image (IM) or provide an external input (TC) through the transparent area (TA). However, this is exemplary, and within the active area (AA), the area where the image (IM) is displayed and the area where the external input (TC) is detected may be separated from each other and are not limited to any one embodiment.

[0047] The peripheral area (NAA) may be adjacent to the active area (AA). For example, the peripheral area (NAA) may surround the active area (AA). Driving circuits or driving wiring for driving the active area (AA) may be placed in the peripheral area (NAA). The peripheral area (NAA) may overlap at least a portion of the bezel area (BZA), and components placed in the peripheral area (NAA) may be prevented from being visible from the outside by the bezel area (BZA).

[0048] The display module (DM) may include a display panel and an input detection unit. The display panel may display an image (IM), and the input detection unit may detect an external input (TC). A detailed description thereof will be provided later.

[0049] A portion of the display module (DM) can be bent around a bending axis extending in a first direction (DR1). That is, the portion of the display module (DM) can be bent toward the back surface of the display module (DM) corresponding to the active area (AA). A flexible circuit board (or circuit board) (FCB) can be connected to the bent portion of the display module (DM), and accordingly, the flexible circuit board (FCB) can overlap with the display module (DM) in a plane.

[0050] The flexible circuit board (FCB) can be electrically connected to the display module (DM) on one side of the display module (DM). The flexible circuit board (FCB) can generate an electrical signal provided to the display module (DM) or receive a signal generated by the display module (DM) to calculate a result value including location or intensity information where an external input (TC) is detected.

[0051] The electronic module (ELM) and the power module (PM) can be placed below the display module (DM). The electronic module (ELM) and the power module (PM) can be electrically connected through separate circuit boards.

[0052] The power module (PM) can supply power as needed for the operation of the electronic device (ED). For example, the power module (PM) may include a conventional battery module.

[0053] The electronic module (ELM) may include various functional modules that operate the electronic device (ED). For example, the electronic module (ELM) may include a control module, a wireless communication module, a video input module, an audio input module, an audio output module, a memory module, an optical module, and an external interface module. The electronic module (ELM) may include a main circuit board, and said modules of the electronic module (ELM) may be mounted on the main circuit board or electrically connected to the main circuit board through a separate circuit board.

[0054] Among the electronic modules (ELM), the control module can control the overall operation of the electronic device (ED). For example, the control module can activate or deactivate the display module (DM) in response to user input. The control module may include at least one microprocessor. Among the electronic modules (ELM), the optical module may include a camera module, a proximity sensor, a biometric sensor that recognizes a part of the user's body (e.g., fingerprint, iris, or face), or a lamp that outputs light.

[0055] The housing (HAU), combined with the window (WM), can provide an internal space for accommodating a display module (DM), an electronic module (ELM), a power module (PM), and a flexible circuit board (FCB). The housing (HAU) may comprise a material having relatively high rigidity. For example, the housing (HAU) may comprise glass, plastic, or metal, or may comprise a plurality of frames and / or plates composed of a combination thereof. The housing (HAU) can protect the components of the electronic device (ED) housed in the housing (HAU) by absorbing external shocks or preventing foreign substances / moisture from penetrating from the outside.

[0056] FIG. 5 is a cross-sectional view of a display module according to one embodiment of the present invention.

[0057] Referring to FIG. 5, the display module (DM) may include a display panel (DP) and an input detection unit (ISP). The input detection unit (ISP) may be placed on the display panel (DP). For example, the input detection unit (ISP) may be placed directly on the display panel (DP). In this embodiment, “the input detection unit (ISP) is placed directly on the display panel (DP)” means that the input detection unit (ISP) is formed on the display panel (DP) through a continuous process, so that the input detection unit (ISP) and the display panel (DP) are combined without a separate adhesive layer. That is, the components of the input detection unit (ISP) may be formed on the base surface provided by the display panel (DP).

[0058] A display panel (DP) can display an image according to an electrical signal. A display panel (DP) according to one embodiment may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel (DP) may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of an inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0059] The display panel (DP) may include a base substrate (BS), a circuit element layer (CL), a light-emitting element layer (LEL), and an encapsulation layer (ECL) sequentially stacked along a third direction (DR3).

[0060] The base substrate (BS) may be a rigid substrate or a flexible substrate capable of bending, folding, or rolling. For example, the base substrate (BS) may be a glass substrate, a metal substrate, or a polymer substrate. The base substrate (BS) may provide a base surface on which a circuit element layer (CL) is placed.

[0061] The base substrate (BS) may include an inorganic layer, an organic layer, or a composite material layer. The base substrate (BS) may have a single-layer or multi-layer structure. For example, a base substrate (BS) with a multi-layer structure may include synthetic resin layers and a multi-layer or single-layer inorganic layer disposed between the synthetic resin layers. The synthetic resin layers may include acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, or perylene resin, but the material of the synthetic resin layers is not limited thereto.

[0062] A circuit element layer (CL) may be disposed on a base substrate (BS). The circuit element layer (CL) may include at least one insulating layer, a semiconductor pattern, and a conductive pattern. The insulating layer, semiconductor pattern, and conductive pattern included in the circuit element layer (CL) may form driving elements such as transistors, signal lines, and pads.

[0063] A light-emitting element layer (LEL) may be disposed on a circuit element layer (CL). The light-emitting element layer (LEL) may include light-emitting elements, each of which emits light. For example, the light-emitting elements may include organic light-emitting elements, inorganic light-emitting elements, micro LEDs, or nano LEDs. The light-emitting elements of the light-emitting element layer (LEL) are electrically connected to driving elements of the circuit element layer (CL) so as to emit light according to electrical signals provided by the driving elements.

[0064] An encapsulation layer (ECL) is disposed on a light-emitting element layer (LEL) to seal the light-emitting elements. The encapsulation layer (ECL) may include at least one thin film to improve the optical efficiency of the light-emitting element layer (LEL) or to protect the light-emitting element layer (LEL). For example, the encapsulation layer (ECL) may include at least one of an inorganic film and an organic film. The inorganic film of the encapsulation layer (ECL) can protect the light-emitting elements from moisture / oxygen. The organic film of the encapsulation layer (ECL) can protect the light-emitting elements from foreign substances such as dust particles.

[0065] The input detection unit (ISP) can detect an external input and provide an input signal containing information about the external input so that the display panel (DP) can display an image corresponding to the external input. The input detection unit (ISP) can be driven in various ways, such as capacitive, resistive, infrared, acoustic, or pressure methods, and the driving method of the input detection unit (ISP) is not limited to any one of these as long as it can detect an external input. In this embodiment, the input detection unit (ISP) is described as an input detection panel driven by a capacitive method.

[0066] The input sensing unit (ISP) may include a base layer (IL1), a first sensing conductive layer (CL1), a first sensing insulating layer (IL2), a second sensing conductive layer (CL2), and a second sensing insulating layer (IL3) sequentially stacked along a third direction (DR3). The base layer (IL1) of the input sensing unit (ISP) may be in contact with the encapsulation layer (ECL). However, the embodiments are not limited thereto, and at least one of the base layer (IL1) or the second sensing insulating layer (IL3) may be omitted.

[0067] Each of the first sensing conductive layer (CL1) and the second sensing conductive layer (CL2) may have a single-layer or multi-layer structure. The conductive layer of the multi-layer structure may include at least two of transparent conductive layers and metal layers. The conductive layer of the multi-layer structure may include metal layers containing different metals. The transparent conductive layer may include at least one of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT, metal nanowires, and graphene. The metal layer may include at least one of molybdenum, silver, titanium, copper, aluminum, and alloys thereof. For example, each of the first sensing conductive layer (CL1) and the second sensing conductive layer (CL2) may have a two-layer structure, e.g., an ITO / copper two-layer structure, or, not limited thereto, a three-layer structure of titanium / aluminum / titanium.

[0068] Each of the first sensing conductive layer (CL1) and the second sensing conductive layer (CL2) may include sensing conductive patterns. The sensing conductive patterns of the first sensing conductive layer (CL1) and the second sensing conductive layer (CL2) may form sensing electrodes and sensing lines connected thereto that constitute an input sensing unit (ISP).

[0069] Each of the base layer (IL1), the first sensing insulating layer (IL2), and the second sensing insulating layer (IL3) may comprise at least one of an inorganic film and an organic film. For example, the inorganic film may comprise at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide, and the organic film may comprise at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin. However, the materials of the inorganic film and the organic film are not limited to the above examples. In one embodiment, the base layer (IL1) may comprise an inorganic film, and the first sensing insulating layer (IL2) and the second sensing insulating layer (IL3) may comprise an organic film, but the embodiment is not limited thereto.

[0070] FIG. 6 is a plan view of a display panel according to one embodiment of the present invention.

[0071] Referring to FIG. 6, the display panel (DP) may include a base substrate (BS), pixels (PX), signal lines (SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL) electrically connected to the pixels (PX), a scan driver (SDV), an emission driver (EDV), a data driver (DDV), and display pads (D-PD).

[0072] A base substrate (BS) can provide a base surface on which electrical components, lines, etc. of a display panel (DP) are arranged. The base substrate (BS) may include a first base region (AA1), a bending region (BA), and a second base region (AA2) separated in a second direction (DR2). The bending region (BA) may extend from the first base region (AA1) in the second direction (DR2). The second base region (AA2) may extend from the bending region (BA) in the second direction (DR2). Accordingly, the first base region (AA1) and the second base region (AA2) may be spaced apart with the bending region (BA) in between.

[0073] The first base area (AA1) may include a display area (DA). The display area (DA) may be an area where light-emitting elements of pixels (PX) are arranged. Accordingly, pixels (PX) can display an image through the display area (DA). The display area (DA) may correspond to the active area (AA, see FIG. 4) of a display module (DM, see FIG. 4) and may overlap with the transparent area (TA, see FIG. 4) of a window (WM, see FIG. 4).

[0074] The remaining first base area (AA1), bending area (BA), and second base area (AA2), excluding the display area (DA), may be defined as a non-display area (NDA). The non-display area (NDA) may be an area adjacent to the display area (DA) where no image is displayed. The non-display area (NDA) may surround the display area (DA). In the non-display area (NDA), a scanning driver (SDV), an emitting driver (EDV), a driving chip (DDV) for driving pixels (PX), and display pads (D-PD) electrically connected to signal lines (SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL) may be disposed. Signal lines (SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL) electrically connected to the pixels (PX) may be extended and disposed on the non-display area (NDA).

[0075] The bending area (BA) may be an area that is bent around a bending axis extended in the first direction (DR1). That is, the bending area (BA) may be bent toward the back surface of the display panel (DP) corresponding to the first base area (AA1). A second base area (AA2) extended from one side of the bending area (BA) may overlap with the first base area (AA1) in a plane according to the bending of the bending area (BA). That is, the second base area (AA2) may be placed on the back surface of the display panel (DP) corresponding to the first base area (AA1).

[0076] In the first direction (DR1), the width of each of the bending area (BA) and the second base area (AA2) may be smaller than the width of the first base area (AA1). By having a smaller width of the bending area (BA) than the first base area (AA1) in a direction parallel to the bending axis, the bending area (BA) can be easily bent. However, this is illustrated as an example, and at least one of the widths of the bending area (BA) and the second base area (AA2) in the first direction (DR1) may be equal to the width of the first base area (AA1), and is not limited to either one.

[0077] The second base region (AA2) may be a flat region located below the first base region (AA1) by bending the bending region (BA). The second base region (AA2) may be a region where signal lines extending toward the display pads (D-PD) via the bending region (BA) among the signal lines (SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL) and a driving chip (DDV) are placed.

[0078] The area where the display pads (D-PD) are placed and the area where the inspection pads (T-PD) are placed can be divided into a display pad area (PD-A) and an inspection pad area (TPD-A), respectively. FIG. 6 illustrates, by way of example, that the display pad area (PD-A) and the inspection pad area (TPD-A) are separated in the first direction (DR1). For example, the inspection pad area (TPD-A) may be provided adjacent to both sides of the second base area (AA2) in the first direction (DR1), and the display pad area (PD-A) may be provided in the central part. However, the embodiment is not necessarily limited thereto, and the placement positions of the display pads (D-PD) and inspection pads (T-PD) may be varied. The defect status of pixels (PX) can be inspected through the inspection pads (T-PD).

[0079] The display panel (DP) of the present invention may further include an inspection unit (IP). The inspection unit (IP) may include inspection pads (T-PD) disposed in an inspection pad area (TPD-A), electrostatic discharge protection diodes (EBD), and a plurality of connection lines (CNL). Each of the plurality of connection lines (CNL) may include switching transistors (STR). The switching transistors (STR) and electrostatic discharge protection diodes (EBD) may be electrically connected to signal lines (DL1~DLn, CSL1, CSL2, PL).

[0080] Switching transistors (STR) and electrostatic protection diodes (EBD) can be electrically connected to test pads (T-PD). For example, switching transistors (STR) and electrostatic protection diodes (EBD) can be electrically connected to test pads (T-PD) through a plurality of connection wires (CNL). They can be connected to first and second control lines (CSL1, CSL2), data lines (DL1~DLn), and power line (PL) through a plurality of connection wires (CNL).

[0081] Electrostatic protection diodes (EBDs) can prevent external static electricity from damaging the test pads (T-PDs). For example, the electrostatic protection diodes (EBDs) can be TVS (Transient Voltage Suppressors) diodes. The electrostatic protection diodes (EBDs) turn on when an external overvoltage is applied and consume pulse current within the electrostatic protection diodes (EBDs), thereby protecting the test pads (T-PDs) from static electricity.

[0082] Switching transistors (STR) can regulate the current flowing into electrostatic discharge protection diodes (EBD) and test pads (T-PD). For example, when test pads (T-PD) apply a test signal to pixels (PX), the switching transistors (STR) are turned on, and when test pads (T-PD) do not apply a test signal to pixels (PX) and signals (e.g., control signal, data signal, and power voltage) are applied to pixels (PX) by the first and second control lines (CSL1, CSL2), data lines (DL1~DLn), and power line (PL), the switching transistors (STR) can be turned off. A detailed explanation thereof will be provided later.

[0083] A flexible circuit board (FCB, see FIG. 4) may be placed on a second base area (AA2) on which display pads (D-PD) are arranged and may be electrically connected to the display pads (D-PD). A flexible circuit board (FCB, see FIG. 4) placed adjacent to the bottom of the second base area (AA2) may be positioned on the back of the display panel (DP) according to the bending of the bending area (BA). As the second base area (AA2) and the flexible circuit board (FCB, see FIG. 4) are positioned below the first base area (AA1) on the front of the electronic device (ED, see FIG. 4), the bezel area of ​​the electronic device (ED, see FIG. 4) may be reduced.

[0084] Each pixel (PX) may include a pixel driving circuit composed of transistors (e.g., a driving transistor) and at least one capacitor, and a light-emitting element electrically connected to the pixel driving circuit. The pixels (PX) may generate light in response to an electrical signal applied to each pixel (PX) and may display an image through a display area (DA). According to an embodiment, some of the pixels (PX) may include a transistor placed in a non-display area (NDA), but are not limited to any one.

[0085] The scanning driver (SDV) and the light-emitting driver (EDV) may be placed in a non-display area (NDA) corresponding to a first base area (AA1). The driver chip (DDV) may be placed in a non-display area (NDA) corresponding to a second base area (AA2). In one embodiment, the driver chip (DDV) may be provided in the form of an integrated circuit chip mounted within the non-display area (NDA) of the display panel (DP). However, not limited thereto, the driver chip (DDV) may be mounted on a flexible circuit board (FCB, see FIG. 4).

[0086] The signal lines (SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL) may include scanning lines (SL1~SLm), data lines (DL1~DLn), light emission lines (EL1~ELm), first and second control lines (CSL1, CSL2), and a power line (PL). Here, m and n represent natural numbers.

[0087] Data lines (DL1–DLn) are insulated from and can intersect with scanning lines (SL1–SLm) and light emission lines (EL1–ELm). For example, scanning lines (SL1–SLm) can be extended in a first direction (DR1) and electrically connected to a scanning driver (SDV). Data lines (DL1–DLn) can be extended in a second direction (DR2) and electrically connected to a driver chip (DDV). Light emission lines (EL1–ELm) can be extended in a first direction (DR1) and electrically connected to a light emission driver (EDV).

[0088] The power line (PL) may include a portion extending in a first direction (DR1) and a portion extending in a second direction (DR2). The portion of the power line (PL) extending in the first direction (DR1) and the portion extending in the second direction (DR2) may be placed on different layers or integrally placed on the same layer. The portion of the power line (PL) extending in the first direction (DR1) may be electrically connected to pixels (PX) and the portion extending in the second direction (DR2). The portion of the power line (PL) extending in the second direction (DR2) may be placed in a non-display area (NDA) and may be electrically connected to display pads (D-PD) via a bending area (BA) and a second base area (AA2) from a first base area (AA1). The power line (PL) may provide power voltage to the pixels (PX).

[0089] The first control line (CSL1) is electrically connected to the scanning drive unit (SDV) and can be extended toward the bottom of the second base area (AA2) via the bending area (BA). The second control line (CSL2) is electrically connected to the light-emitting drive unit (EDV) and can be extended toward the bottom of the second base area (AA2) via the bending area (BA).

[0090] Display pads (D-PDs) may be positioned adjacent to the bottom of the second base area (AA2). On the second base area (AA2), display pads (D-PDs) may be positioned closer to the bottom of the base substrate (BS) than to the driver chip (DDV). Display pads (D-PDs) may be spaced apart along the first direction (DR1). The power line (PL), the first control line (CSL1), and the second control line (CSL2) may each be electrically connected to the corresponding display pad (D-PD) among the display pads (D-PDs). The data lines (DL1 to DLn) may each be electrically connected to the corresponding display pad (D-PD) among the display pads (D-PDs) through the driver chip (DDV).

[0091] Display pads (D-PDs) can be electrically connected to a flexible circuit board (FCB, see FIG. 4) through an adhesive layer, and electrical signals provided from the flexible circuit board (FCB, see FIG. 4) can be transmitted to a display panel (DP) through the display pads (D-PDs). However, the method of connecting the display pads (D-PDs) and the flexible circuit board (FCB, see FIG. 4) is not limited to this.

[0092] The scanning driver (SDV) can generate scanning signals in response to a scanning control signal. The scanning signals can be applied to pixels (PX) through scanning lines (SL1 to SLm). The driving chip (DDV) can generate data voltages corresponding to image signals in response to a data control signal. The data voltages can be applied to pixels (PX) through data lines (DL1 to DLn). The light emission driver (EDV) can generate light emission signals in response to a light emission control signal. The light emission signals can be applied to pixels (PX) through light emission lines (EL1 to ELm).

[0093] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can generate an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals. The light emission time of the pixels (PX) can be controlled by the light emission signals.

[0094] FIG. 7 is a plan view of an input sensing unit according to an embodiment of the present invention. FIG. 7 briefly illustrates the configurations of an input sensing unit (ISP) disposed on the aforementioned base substrate (BS) for convenience of explanation.

[0095] In one embodiment, the input sensing unit (ISP) may be driven in a mutual-capacitance type. Referring to FIG. 7, the input sensing unit (ISP) may include first sensing electrodes (TEX: TEX1~TEX6), second sensing electrodes (TEY: TEY1~TEY4), first sensing lines (TLX1~TLX6), second sensing lines (TLY1~TLY4), and sensing pads (I-PD). However, not limited thereto, the input sensing unit (ISP) may be driven in a self-capacitance type.

[0096] Each of the first sensing electrodes (TEX) extends along a first direction (DR1), and the first sensing electrodes (TEX) may be arranged along a second direction (DR2). FIG. 7 illustrates six first sensing electrodes (TEX1 to TEX6) as an example. However, the number of first sensing electrodes (TEX) included in the input sensing unit (ISP) is not limited thereto. One first sensing electrode (TEX) may include first sensing patterns (SP1) arranged along the first direction (DR1) and first connecting patterns (BP1) connecting them.

[0097] Each of the second sensing electrodes (TEY) extends along the second direction (DR2), and the second sensing electrodes (TEY) may be arranged along the first direction (DR1). FIG. 7 illustrates four second sensing electrodes (TEY1 to TEY4) as an example. However, the number of second sensing electrodes (TEY) included in the input sensing unit (ISP) is not limited thereto. One second sensing electrode (TEY) may include second sensing patterns (SP2) arranged along the second direction (DR2) and second connecting patterns (BP2) connecting them.

[0098] The first sensing electrodes (TEX) and the second sensing electrodes (TEY) can be electrically insulated. An input sensing unit (ISP) can detect an external input through a change in capacitance between the first sensing electrodes (TEX) and the second sensing electrodes (TEY). The first sensing electrodes (TEX) and the second sensing electrodes (TEY) can be placed in an area corresponding to the display area (DA) of the base substrate (BS). Accordingly, the electronic device (ED, see FIG. 3) can display an image through the display area (DA) while simultaneously detecting an external input applied to the display area (DA).

[0099] The first sensing lines (TLX1 to TLX6) may be placed on the non-display area (NDA) and electrically connected to the first sensing electrodes (TEX1 to TEX6), respectively. Some of the first sensing lines (TLX1 to TLX6) may be placed on the left side of the non-display area (NDA), and the remaining parts may be placed on the right side of the non-display area (NDA). For example, the first sensing lines (TLX1, TLX3, TLX5) connected to the first sensing electrodes (TEX1, TEX3, TEX5) placed in odd rows may be connected to the left sides of the first sensing electrodes (TEX1, TEX3, TEX5), respectively, and the first sensing lines (TLX2, TLX4, TLX6) connected to the first sensing electrodes (TEX2, TEX4, TEX6) placed in even rows may be connected to the right sides of the first sensing electrodes (TEX2, TEX4, TEX6), respectively. However, the arrangement of the first detection lines (TLX1~TLX6) is not limited thereto, and the first detection lines (TLX1~TLX6) may all be arranged to the left of the non-display area (NDA), or the first detection lines (TLX1~TLX6) may all be arranged to the right of the non-display area (NDA).

[0100] Each of the first sensing lines (TLX1–TLX6) may extend from the first base area (AA1) toward the second base area (AA2) via the bending area (BA). Each of the first sensing lines (TLX1–TLX6) may be electrically connected to sensing pads (I-PD) disposed on the second base area (AA2).

[0101] The second sensing lines (TLY1~TLY4) may be positioned on the non-display area (NDA) and electrically connected to the second sensing electrodes (TEY1~TEY4), respectively. Some of the second sensing lines (TLY1~TLY4) may be positioned adjacent to the left side of the non-display area (NDA), and the remaining parts may be positioned adjacent to the right side of the non-display area (NDA). For example, the second sensing lines (TLY1, TLY2) electrically connected to the second sensing electrodes (TEY1, TEY2) positioned on the left side of the second sensing electrodes (TEY1~TEY4) in the first direction (DR1) may be positioned adjacent to the left side of the first base area (AA1), and the second sensing lines (TLY3, TLY4) electrically connected to the second sensing electrodes (TEY3, TEY4) positioned on the right side may be positioned adjacent to the right side of the first base area (AA1). However, the arrangement of the second detection lines (TLY1~TLY4) is not limited to this.

[0102] Each of the second sensing lines (TLY1–TLY4) may extend from an area adjacent to the bottom of the first base area (AA1) toward the second base area (AA2) via a bending area (BA). Each of the second sensing lines (TLY1–TLY4) may be electrically connected to sensing pads (I-PD) disposed on the second base area (AA2).

[0103] Some of the sensing pads (I-PD) may be placed in an area adjacent to the left of the second base area (AA2) in the first direction (DR1), and some of the remaining may be placed in an area adjacent to the right of the second base area (AA2). For example, the sensing pads (I-PD) may be divided into two groups spaced apart with the display pad area (PD-A) in between. However, the placement of the sensing pads (I-PD) is not limited thereto.

[0104] The sensing pads (I-PD) may be placed on the same layer as the display pads (D-PD, see FIG. 6). The sensing pads (I-PD) may be placed on a different layer from the first and second sensing lines (TLX1–TLX6, TLY1–TLY4) and connected through contact holes. However, not limited thereto, the sensing pads (I-PD) may also be placed on a different layer from the display pads (D-PD, see FIG. 6). For example, the sensing pads (I-PD) may be integrally formed on the same layer as the first and second sensing lines (TLX1–TLX6, TLY1–TLY4).

[0105] The first and second sensing lines (TLX1–TLX6, TLY1–TLY4) may be positioned above the components of the display panel (DP, see FIG. 6) on an area corresponding to the non-display area (NDA) of the base substrate (BS). Accordingly, the first and second sensing lines (TLX1–TLX6, TLY1–TLY4) may overlap with the components of the display panel (DP, see FIG. 6) on the bending area (BA) and the second base area (AA2).

[0106] FIG. 8 is a cross-sectional view of a display module according to an embodiment of the present invention. FIG. 8 exemplarily illustrates a cross-section of a pixel (PX, see FIG. 6) placed in a display area (DA).

[0107] Referring to FIG. 8, the display module (DM) may include a display panel (DP) and an input sensing unit (ISP) disposed on the display panel (DP). The above description may apply equally to each of the components.

[0108] As described above in FIG. 5, the display panel (DP) may include a base substrate (BS), a circuit element layer (CL), a light-emitting element layer (LEL), and an encapsulation layer (ECL).

[0109] The base substrate (BS) has insulating properties and can provide a base surface on which components of the display module (DM) are placed. The base substrate (BS) may have flexibility to be bendable. As described above, the base substrate (BS) may include a first base region (AA1, see FIG. 6), a bending region (BA, see FIG. 6), and a second base region (AA2, see FIG. 6), and the bending region (BA, see FIG. 6) of the base substrate (BS) may be bent to a predetermined curvature.

[0110] The circuit element layer (CL) may include insulating layers (10 to 60) disposed on a base substrate (BS), a transistor (TR) of a pixel (PX, see FIG. 6), an upper electrode (UE), and connecting electrodes (CN1, CN2). The insulating layers (10 to 60) may include first to sixth insulating layers (10 to 60) sequentially stacked along the thickness direction on the base substrate (BS). However, embodiments of the insulating layers (10 to 60) included in the circuit element layer (CL) are not limited thereto and may be changed depending on the configuration or manufacturing process of the circuit element layer (CL).

[0111] The first insulating layer (10) may be disposed on a base substrate (BS). The first insulating layer (10) may be provided as a barrier layer and / or buffer layer that prevents foreign substances from entering from the outside. The first insulating layer (10) may improve the bonding strength between the base substrate (BS) and the semiconductor pattern (SM) and / or conductive pattern of the circuit element layer (CL). The first insulating layer (10) may include at least one of a silicon oxide layer and a silicon nitride layer. In one embodiment, the first insulating layer (10) may include alternatingly stacked silicon oxide layers and silicon nitride layers.

[0112] A pixel (PX, see FIG. 6) may be placed on a base substrate (BS). A pixel (PX, see FIG. 6) may be placed corresponding to a display area (DA). A pixel (PX, see FIG. 6) may include a transistor (TR) and a light-emitting element (OLED).

[0113] A transistor (TR) may include a semiconductor pattern (SM) and a gate electrode (GE). The semiconductor pattern (SM) may be disposed on a first insulating layer (10). The semiconductor pattern (SM) may include a channel (S1), a source (S2), and a drain (S3). The semiconductor pattern (SM) may include a silicon semiconductor, and may include a single-crystal silicon semiconductor, a polysilicon semiconductor, or an amorphous silicon semiconductor. Not limited thereto, the semiconductor pattern (SM) may include an oxide semiconductor. The semiconductor pattern (SM) according to one embodiment of the present invention may be formed of various materials that have semiconductor properties and is not limited to any one embodiment.

[0114] The semiconductor pattern (SM) may include multiple regions with different electrical properties depending on whether it is doped or reduced. For example, the semiconductor pattern (SM) may include regions that are doped or have reduced metal oxides and have high conductivity, and these highly conductive regions may serve as electrodes or signal lines of the transistor (TR). This may correspond to the source (S2) and drain (S3) of the transistor (TR). The semiconductor pattern (SM) may include regions that are undoped and have relatively low conductivity, and these may correspond to the channel (S1) (or active) of the transistor (TR).

[0115] A second insulating layer (20) may be disposed on the first insulating layer (10) to cover a semiconductor pattern (SM). A gate electrode (GE) may be disposed on the second insulating layer (20). The second insulating layer (20) may be disposed between the semiconductor pattern (SM) of the transistor (TR) and the gate electrode (GE). The gate electrode (GE) may overlap the channel (S1) of the semiconductor pattern (SM) on a plane. The gate electrode (GE) may function as a mask in the process of doping the semiconductor pattern (SM). The gate electrode (GE) may include heat-resistant molybdenum (Mo), an alloy containing molybdenum, titanium (Ti), an alloy containing titanium, etc., but is not limited thereto.

[0116] The structure of the transistor (TR) illustrated in FIG. 8 is exemplary, and the source (S2) or drain (S3) of the transistor (TR) may be electrodes formed independently from the semiconductor pattern (SM). In this case, the source (S2) and drain (S3) may be connected to the semiconductor pattern (SM) by contacting the semiconductor pattern (SM) or by penetrating an insulating layer. Additionally, the gate electrode (GE) may be positioned below the semiconductor pattern (SM). A transistor (TR) according to one embodiment of the present invention may be formed in various structures and is not limited to any one embodiment.

[0117] Meanwhile, the second insulating layer (20) and the third to sixth insulating layers (30 to 60) to be described later may include at least one of an inorganic layer and an organic layer. For example, the inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin.

[0118] The third insulating layer (30) is disposed on the second insulating layer (20) and can cover the gate electrode (GE). The upper electrode (UE) can be disposed on the third insulating layer (30). The upper electrode (UE) can overlap the gate electrode (GE) in a plane, and the gate electrode (GE) and the upper electrode (UE) overlapping each other can form a capacitor.

[0119] A fourth insulating layer (40) is disposed on a third insulating layer (30) and can cover an upper electrode (UE). Connecting electrodes (CN1, CN2) may include a first connecting electrode (CN1) and a second connecting electrode (CN2). The first connecting electrode (CN1) may be disposed on the fourth insulating layer (40). A fifth insulating layer (50) may be disposed on the fourth insulating layer (40) and can cover the first connecting electrode (CN1). The second connecting electrode (CN2) may be disposed on the fifth insulating layer (50). A sixth insulating layer (60) may be disposed on the fifth insulating layer (50) and can cover the second connecting electrode (CN2). In one embodiment, at least one of the fifth insulating layer (50) and the sixth insulating layer (60) may include an organic layer and may cover a step difference between the components disposed below and provide a flat upper surface.

[0120] The first connecting electrode (CN1) can be electrically connected to the semiconductor pattern (SM) through a contact hole penetrating the second to fourth insulating layers (20 to 40). The second connecting electrode (CN2) can be electrically connected to the first connecting electrode (CN1) through a contact hole penetrating the fifth insulating layer (50).

[0121] Each of the first connecting electrode (CN1) and the second connecting electrode (CN2) may include a conductive material. Each of the first connecting electrode (CN1) and the second connecting electrode (CN2) may include gold, silver, copper, aluminum, platinum, molybdenum, titanium, and alloys thereof. At least one of the first connecting electrode (CN1) and the second connecting electrode (CN2) may include conductive layers of a multilayer structure. For example, at least one of the first connecting electrode (CN1) and the second connecting electrode (CN2) may have a three-layer structure of titanium / aluminum / titanium. However, the embodiments are not limited thereto.

[0122] According to an embodiment of the circuit element layer (CL), at least one of the first connecting electrode (CN1) and the second connecting electrode (CN2) may be omitted. Alternatively, according to an embodiment of the circuit element layer (CL), an additional connecting electrode connecting the transistor (TR) and the light-emitting element (OLED) may be further disposed. Depending on the number of insulating layers disposed between the light-emitting element (OLED) and the transistor (TR), the method of electrical connection between the light-emitting element (OLED) and the transistor (TR) may be varied and is not limited to any one embodiment.

[0123] The light-emitting element layer (LEL) may include a light-emitting element (OLED) and a pixel defining film (PDL). The light-emitting element (OLED) and the pixel defining film (PDL) may be disposed on the sixth insulating layer (60). The light-emitting element (OLED) may include a first electrode (AE), a light-emitting layer (EML), and a second electrode (CE).

[0124] The first electrode (AE) can be electrically connected to the second connecting electrode (CN2) through a contact hole penetrating the sixth insulating layer (60). The first electrode (AE) can be electrically connected to the transistor (TR) through the first and second connecting electrodes (CN1, CN2).

[0125] A pixel defining film (PDL) may be defined with a pixel opening (PX-OP) that exposes at least a portion of a first electrode (AE). A portion of the first electrode (AE) exposed from the pixel defining film (PDL) may correspond to a light-emitting region. The pixel defining film (PDL) may include an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the pixel defining film (PDL) may further include a black pigment or a black dye.

[0126] The light-emitting layer (EML) may be disposed on the first electrode (AE). The light-emitting layer (EML) may provide light of a predetermined color. The light-emitting layer (EML) may be disposed corresponding to a pixel opening (PX-OP) defined in a pixel defining film (PDL). A plurality of light-emitting elements (OLEDs) and pixel openings (PX-OPs) may be provided, and the light-emitting layers (EMLs) of the light-emitting elements (OLEDs) may be disposed corresponding to each pixel opening (PX-OP) and provided in a pattern form spaced apart from each other. However, not limited thereto, the light-emitting layers (EMLs) of the light-emitting elements (OLEDs) may be formed as a single common layer.

[0127] The second electrode (CE) may be disposed on the light-emitting layer (EML) and the pixel defining layer (PDL). The second electrode (CE) may be provided as a common electrode disposed in common to the pixels (PX, see FIG. 6).

[0128] Meanwhile, the light-emitting element (OLED) may further include at least one of a hole control region disposed between the first electrode (AE) and the light-emitting layer (EML) and an electronic control region disposed between the light-emitting layer (EML) and the second electrode (CE). The hole control region may include at least one of a hole generation layer, a hole transport layer, and an electron blocking layer, and the electronic control region may include at least one of an electron generation layer, an electron transport layer, and a hole blocking layer.

[0129] An encapsulation layer (ECL) may be disposed on a light-emitting element layer (LEL). The encapsulation layer (ECL) may be disposed on a light-emitting element (OLED) and a pixel definition film (PDL) to seal the light-emitting element (OLED). The encapsulation layer (ECL) may include at least one of an inorganic film and an organic film. In the present embodiment, the encapsulation layer (ECL) may include a first inorganic film (EN1), a second inorganic film (EN3), and an organic film (EN2) disposed between the first and second inorganic films (EN1, EN3). However, the configuration of the encapsulation layer (ECL) is not limited thereto as long as it can seal the light-emitting element (OLED).

[0130] The first inorganic film (EN1) may be disposed on the second electrode (CE), and the organic film (EN2) and the second inorganic film (EN3) may be sequentially disposed on the first inorganic film (EN1) in the thickness direction of the display panel (DP). The first and second inorganic films (EN1, EN3) can protect the light-emitting element (OLED) from moisture or oxygen introduced from the outside. For example, each of the first and second inorganic films (EN1, EN3) may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. However, the materials of the first and second inorganic films (EN1, EN3) are not limited to the above examples. The organic film (EN2) can prevent foreign substances from entering the light-emitting element (OLED) and can cover the step difference of the components disposed below the organic film (EN2). For example, the organic film (EN2) may include an acrylic-based organic material. However, the material of the organic film (EN2) is not limited to the above examples.

[0131] An input sensing unit (ISP) may be placed on a display panel (DP). The input sensing unit (ISP) may include a base layer (IL1), a first sensing insulating layer (IL2), a first sensing conductive layer (CL1), and a second sensing conductive layer (CL2). The input sensing unit (ISP) may further include a second sensing insulating layer (IL3, see FIG. 5) as illustrated in FIG. 5. The above description may apply equally to each of the components.

[0132] The base layer (IL1) may come into contact with the uppermost layer of the encapsulation layer (ECL). For example, the base layer (IL1) may come into contact with the second inorganic film (EN3) of the encapsulation layer (ECL). The base layer (IL1) of the input sensing unit (ISP) may be formed directly on the base surface provided by the encapsulation layer (ECL). However, it is not limited thereto, and depending on the embodiment, the base layer (IL1) may be omitted, in which case the first sensing conductive layer (CL1) of the input sensing unit (ISP) may come into contact with the encapsulation layer (ECL).

[0133] A first sensing conductive layer (CL1) may be disposed on a base layer (IL1), and a second sensing conductive layer (CL2) may be disposed on a first sensing insulating layer (IL2). The first sensing conductive layer (CL1) and the second sensing conductive layer (CL2) may form a sensing electrode (TE). The sensing electrode (TE) may correspond to any one of the first and second sensing electrodes (TEX, TEY, see FIG. 7) described above. For example, the first sensing conductive layer (CL1) may include a connection pattern (BP) of the sensing electrode (TE), and the second sensing conductive layer (CL2) may include a sensing pattern (SP) of the sensing electrode (TE). However, it is not limited thereto, and the first sensing conductive layer (CL1) may include a sensing pattern (SP), and the second sensing conductive layer (CL2) may include a connection pattern (BP).

[0134] The connection pattern (BP) may correspond to the first connection pattern (BP1, see FIG. 7) or the second connection pattern (BP2, see FIG. 7) described above, and the detection pattern (SP) may correspond to the first detection pattern (SP1, see FIG. 7) or the second detection pattern (SP2, see FIG. 7) described above. The connection pattern (BP) may be placed on a different layer from the detection pattern (SP) and connected through a contact hole penetrating the first detection insulating layer (IL2). However, it is not limited thereto, and the connection pattern (BP) and the detection pattern (SP) may be placed on the same layer and formed integrally.

[0135] The sensing electrode (TE) may be a mesh-shaped pattern and may be positioned corresponding to an area where a pixel defining film (PDL) is placed. However, it is not limited thereto, and the sensing electrode (TE) may be provided as a single-shaped pattern that overlaps with the light-emitting element (OLED), in which case the sensing electrode (TE) may include a transparent conductive material.

[0136] FIG. 9 is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 9 briefly illustrates some configurations of an electronic device (ED) arranged corresponding to a second base region (AA2).

[0137] The second base area (AA2) corresponds to a portion of the non-display area (NDA, see FIG. 6). As illustrated in FIG. 9, the area of ​​the non-display area (NDA) or the second base area (AA2) where the driving chip (DDV) is bonded is defined as the first pad area (PA1), and the area where the flexible circuit board (FCB) is bonded can be defined as the second pad area (PA2). The second pad area (PA2) can be referred to as the display pad area.

[0138] A driving chip (DDV) can be bonded to a first pad region (PA1) through a first adhesive layer (CF1), and a flexible circuit board (FCB) can be bonded to a second pad region (PA2) through a second adhesive layer (CF2). Each of the first adhesive layer (CF1) and the second adhesive layer (CF2) may include a synthetic resin having adhesive properties. Each of the first adhesive layer (CF1) and the second adhesive layer (CF2) may be an anisotropic conductive film. For example, each of the first adhesive layer (CF1) and the second adhesive layer (CF2) may include an adhesive resin and conductive particles dispersed in the adhesive resin.

[0139] The first adhesive layer (CF1) can overlap with the first pad region (PA1). The first adhesive layer (CF1) can overlap with the driving chip (DDV). The second adhesive layer (CF2) can overlap with the second pad region (PA2). The second adhesive layer (CF2) can overlap with the flexible circuit board (FCB).

[0140] A display panel (DP) may include a plurality of pads (PD). The plurality of pads (PD) may include first signal pads (PD1), second signal pads (PD2), and display pads (D-PD). The first signal pads (PD1), second signal pads (PD2), and display pads (D-PD) may be pads placed in a signal transmission path.

[0141] The first signal pads (PD1) are positioned corresponding to the output pads of the driving chip (DDV) and may be input pads that receive a signal from the driving chip (DDV). The second signal pads (PD2) are positioned corresponding to the input pads of the driving chip (DDV) and may be output pads that output a signal to the driving chip (DDV). The display pads (D-PD) may be panel input pads that receive a signal from the flexible circuit board (FCB).

[0142] Each of the first signal pads (PD1) can be electrically connected to the pixels (PX, see FIG. 6) of the display panel (DP) via a signal line and can transmit and receive signals to and from the pixels (PX, see FIG. 6). Each of the second signal pads (PD2) can be electrically connected to the corresponding display pad (D-PD) among the display pads (D-PD) via a signal line, and the display pads (D-PD) and the second signal pads (PD2) that are electrically connected to each other can transmit and receive signals.

[0143] The first pad area (PA1) may include a first sub-pad area (PA1-1) and a second sub-pad area (PA1-2). The first sub-pad area (PA1-1) may be defined as an area where the first signal pads (PD1) are placed. The second sub-pad area (PA1-2) may be defined as an area where the second signal pads (PD2) are placed.

[0144] The first signal pads (PD1) may be arranged along a first direction (DR1) and a second direction (DR2) within a first sub-pad area (PA1-1). Among the first signal pads (PD1), the first signal pads (PD1) arranged along the first direction (DR1) may be defined as pad rows. FIG. 9 illustrates, by way of example, five pad rows arranged along the second direction (DR2). The arrangement of the first signal pads (PD1) is not limited to this.

[0145] The second signal pads (PD2) may be arranged along the first direction (DR1) within the second sub-pad area (PA1-2). The second signal pads (PD2) may be arranged in a single row of pads. However, the arrangement of the second signal pads (PD2) is not limited thereto.

[0146] According to one embodiment of the present invention, the display panel (DP) may further include test pads (T-PD). The test pads (T-PD) are pads for testing the operation of the display panel (DP) before attaching circuit components (e.g., a driving chip, a flexible circuit board, etc.) for driving the display panel (DP). The test pads (T-PD) are connected to the internal circuit of the display panel (DP), so that when a driving signal is applied to the test pads (T-PD), the display panel (DP) can be driven.

[0147] Inspection pads (T-PDs) may be spaced apart in a first direction (DR1) from a second pad area (PA2) where display pads (D-PDs) are placed. The area where the inspection pads (T-PDs) are placed may be defined as a third pad area (PA3). The third pad area (PA3) may be referred to as an inspection pad area. However, FIG. 9 is exemplary, and the location where the inspection pads (T-PDs) are placed is not limited thereto.

[0148] Although not illustrated, the electronic device (ED) of one embodiment may further include a conductive tape. The conductive tape is placed on the driving chip (DDV) and the flexible circuit board (FCB) to prevent noise caused by electromagnetic waves or static electricity.

[0149] FIGS. 10 and 11 are drawings for explaining the operation of the inspection pads of the present invention. For example, FIGS. 10 and 11 are enlarged drawings of a portion of the second base area (AA2, see FIG. 6). In FIG. 10, an inspection driving unit (P-DP) is shown. The inspection driving unit (P-DP) may be configured to apply an inspection signal to inspection pads (T-PD) to inspect whether pixels (PX, see FIG. 6) are defective before forming the display panel (DP, see FIG. 6) of the present invention. The following descriptions identical to those previously described will be omitted.

[0150] Referring to FIG. 10, the inspection drive unit (P-DP) may include inspection drive pads (ID-PD) and switching pads (S-PD). The number of inspection drive pads (ID-PD) may be equal to the number of inspection pads (T-PD).

[0151] The test drive pads (ID-PD) can be electrically connected to the test pads (T-PD). For example, the test drive pads (ID-PD) can apply a test signal to the test pads (T-PD). The test signal can be applied to pixels (PX, see FIG. 6) through electrostatic discharge protection diodes (EBD) and switching transistors (STR).

[0152] According to one embodiment of the present invention, a switching pad (S-PD) may be connected to at least one of display pads (D-PD). The connected display pad (D-PD) may be electrically connected to a pad (PD) disposed in a first pad area (PA1). The pad (PD) may be electrically connected to each of the switching transistors (STR). For example, the pad (PD) may be electrically connected to the gate of the switching transistors (STR). That is, the switching transistors (STR) may be electrically connected to the switching pad (S-PD).

[0153] The switching pad (S-PD) can adjust the gate voltage of the switching transistors (STR). In this embodiment, the switching pad (S-PD) can lower the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) on.

[0154] FIG. 11 is a diagram showing a portion of a display panel (DP, see FIG. 6) in which the test driving unit (P-DP) in FIG. 10 is removed and a driving chip (DDV) is bonded to a first pad area (PA1). Referring to FIG. 11, the switching transistors (STR) of the present invention can be electrically connected to each other with the driving chip (DDV). The driving chip (DDV) may include a switching circuit (SPDV). The switching transistors (STR) can be electrically connected to each other with the switching circuit (SPDV) of the driving chip (DDV).

[0155] The switching circuit (SPDV) can adjust the gate voltage of the switching transistors (STR). In this embodiment, the switching circuit (SPDV) can turn the switching transistors (STR) off by increasing the gate voltage of the switching transistors (STR). Alternatively, the switching circuit (SPDV) can turn the switching transistors (STR) off by maintaining a high voltage (high level). Or, the switching transistors (STR) can be turned off by directly connecting them to a dummy pad instead of the switching circuit (SPDV).

[0156] The display pad (D-PD) may be a floating electrode. In this embodiment, the display pad (D-PD) is shown as being electrically connected to the switching circuit (SPDV), but the present invention is not limited thereto, and the display pad (D-PD) may not be electrically connected to the switching circuit (SPDV).

[0157] Referring again to FIG. 10, the test driving pads (ID-PD) can apply a test signal to the test pads (T-PD). The state of applying a test signal to the test pads (T-PD) can be referred to as the first mode. That is, in the first mode, a test signal can be applied to the pixels through the test pads (T-PD). In the first mode, the switching pad (S-PD) can lower the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) on. As a result, the test signals applied by the test driving pads (ID-PD) can be applied to the pixels (PX, see FIG. 6) through the connection wires (CNL).

[0158] Referring to FIG. 6 and FIG. 11 together, the inspection drive unit (P-DP) is removed, and signals (e.g., control signal, data signal, and power voltage) can be applied to pixels (PX) through the first and second control lines (CSL1, CSL2), data lines (DL1~DLn), and power line (PL) via the display pads (D-PD). The state in which signals (e.g., control signal, data signal, and power voltage) are applied to pixels (PX) via the first and second control lines (CSL1, CSL2), data lines (DL1~DLn), and power line (PL) can be referred to as the second mode. In the second mode, the switching circuit (SPDV) can increase the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) off. When the switching transistors (STR) are turned off, no current flows through the electrostatic protection diodes (EBD) and test pads (T-PD) connected to the connection wires (CNL), and no potential difference may be generated in the electrostatic protection diodes (EBD) and test pads (T-PD). As a result, corrosion caused by the potential difference in the electrostatic protection diodes (EBD) and test pads (T-PD) is prevented, and a reliable display device (DD, see FIG. 4) can be provided.

[0159] FIGS. 12a and 12b are enlarged drawings of a portion of a display panel according to an embodiment of the present invention. For example, FIGS. 12a and 12b are drawings for explaining switching transistors (STR) in the second mode of FIG. 11.

[0160] Referring to FIG. 12a, the switching transistors (STR) of the present invention can be electrically connected to a switching circuit (SPDV) through one of the display pads (D-PD). That is, the switching circuit (SPDV) can increase the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) off.

[0161] Referring to FIG. 12a and FIG. 12b together, the display panel (DP, see FIG. 6) of the present invention may further include a dummy pad (M-PD). The dummy pad (M-PD) may be placed between the display pads (D-PD) and the test pads (T-PD). As shown in FIG. 12b, the switching transistors (STR) of the present invention may be electrically connected to a switching circuit (SPDV) through the dummy pad (M-PD).

[0162] FIGS. 13a and FIGS. 13b are drawings for explaining the operation of the inspection pads of the present invention.

[0163] Referring to FIG. 13a, an inspection driving unit (P-DP) is illustrated as in FIG. 10. The inspection driving unit (P-DP) may be configured to apply an inspection signal to inspection pads (T-PD) to inspect whether pixels (PX, see FIG. 6) are defective before forming the display panel (DP, see FIG. 6) of the present invention.

[0164] A switching pad (S-PD) can be connected to at least one of the display pads (D-PD). The switching pad (S-PD) can be electrically connected to each of the switching transistors (STR) through the connected display pad (D-PD).

[0165] The switching pad (S-PD) can adjust the gate voltage of the switching transistors (STR). In this embodiment, the switching pad (S-PD) can lower the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) on.

[0166] Referring to FIG. 6 and FIG. 13b together, the inspection drive unit (P-DP) is removed, and signals (e.g., control signal, data signal, and power voltage) can be applied to pixels (PX) through the first and second control lines (CSL1, CSL2), data lines (DL1~DLn), and power line (PL) via the display pads (D-PD).

[0167] As illustrated in FIG. 13b, the flexible circuit board (FCB) can be bonded to the second pad area (PA2). The flexible circuit board (FCB) may include a switching circuit (SPDVa). The switching transistors (STR) of the present invention may be electrically connected to each other with the switching circuit (SPDVa) of the flexible circuit board (FCB).

[0168] The switching circuit (SPDV) can increase the gate voltage of the switching transistors (STR) to turn the switching transistors (STR) off. When the switching transistors (STR) are turned off, no current flows through the electrostatic protection diodes (EBD) and test pads (T-PD) connected to the connection wires (CNL), and no potential difference may occur in the electrostatic protection diodes (EBD) and test pads (T-PD).

[0170] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0171] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0172] ED: Electronic device DD: Display device DP: Display panel D-PD: Display pad CSL1, CLS2: Signal lines DDV: Driver chip IP: Inspection Department T-PD: Inspection pad CNL: Connection wiring STR: Switching transistor

Claims

Claim 1 A display panel comprising a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area; a plurality of display pads arranged in a pad area within the non-display area; a plurality of signal lines connected to the plurality of pixels; a driving chip electrically connected to the plurality of signal lines; and a test unit arranged adjacent to the driving chip, wherein the test unit comprises a plurality of test pads spaced apart from the plurality of display pads in a first direction; and a plurality of connecting wires extending in a second direction intersecting the first direction and connecting the plurality of test pads and the plurality of signal lines, wherein the plurality of connecting wires each comprise a plurality of switching transistors electrically connected to the plurality of test pads and the plurality of signal lines. Claim 2 In claim 1, the switching transistors are a display device electrically connected to the driving chip. Claim 3 In claim 2, the driving chip is a display device comprising a switching circuit that controls the gate voltage of the switching transistors. Claim 4 In claim 3, a display device in which the switching transistors are in an off state by the switching circuit. Claim 5 In claim 3, at least one of the plurality of display pads is electrically connected to the switching transistors and the switching circuit in a display device. Claim 6 In claim 3, the display device further comprises a dummy pad disposed between the plurality of display pads and the plurality of test pads, wherein the dummy pad is electrically connected to the switching transistors and the switching circuit. Claim 7 A display device according to claim 1, further comprising a circuit board electrically connected to the display panel through the plurality of display pads, and the switching transistors electrically connected to the circuit board. Claim 8 In claim 7, the circuit board comprises a display device including a switching circuit that controls the gate voltage of the switching transistors. Claim 9 In claim 8, the switching transistors are a display device that is turned on or off by the switching circuit included in the circuit board. Claim 10 In claim 9, at least one of the plurality of display pads is electrically connected to the switching transistors and the switching circuit in a display device. Claim 11 A display device according to claim 1, further comprising a plurality of pads overlapping with the driving chip. Claim 12 In claim 1, the inspection unit further comprises an electrostatic protection diode disposed between the switching transistor and the plurality of inspection pads with respect to the second direction. Claim 13 In claim 1, the switching transistor is a display device disposed between the plurality of test pads and the plurality of signal lines with respect to the second direction. Claim 14 A display device comprising: a display panel including a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area; a plurality of display pads arranged in a pad area within the non-display area; a plurality of signal lines connected to the plurality of pixels; and an inspection unit arranged adjacent to the plurality of display pads, wherein the inspection unit includes a plurality of inspection pads spaced apart from the plurality of display pads in a first direction; and a plurality of connecting wires connecting the plurality of inspection pads and the plurality of signal lines, wherein the plurality of connecting wires include a plurality of switching transistors that are turned on in a first mode of the display panel and turned off in a second mode different from the first mode of the display panel. Claim 15 A display device according to claim 14, further comprising a driving chip including a switching circuit electrically connected to the switching transistors and controlling the gate voltage of the switching transistors. Claim 16 In claim 15, at least one of the plurality of display pads is electrically connected to the switching transistors and the switching circuit in a display device. Claim 17 In claim 14, the display device further comprises a circuit board electrically connected to the display panel through the plurality of display pads, and the switching transistor is electrically connected to the circuit board. Claim 18 In claim 17, the circuit board is a display device comprising a switching circuit that controls the gate voltage of the switching transistor. Claim 19 An electronic device comprising: a display device for displaying images; and a processor for providing image data to the display device, wherein the display device comprises: a display panel including a display area in which a plurality of pixels are arranged and a non-display area surrounding the display area; a plurality of display pads arranged in a pad area within the non-display area; a plurality of signal lines connected to the plurality of pixels; a driving chip electrically connected to the plurality of signal lines; and a test unit arranged adjacent to the driving chip, wherein the test unit comprises: a plurality of test pads spaced apart from the plurality of display pads in a first direction; and a plurality of connecting wires extending in a second direction intersecting the first direction and connecting the plurality of test pads and the plurality of signal lines, wherein the plurality of connecting wires each comprise a plurality of switching transistors electrically connected to the plurality of test pads and the plurality of signal lines. Claim 20 In claim 19, the electronic device further comprises a circuit board electrically connected to the display panel through the plurality of display pads, and the switching transistors electrically connected to the circuit board.

Images