Display device and electronic apparatus including the same

Abstract

A display device and an electronic device including the same are provided. The display device comprises: a substrate having a display area in which light-emitting regions are arranged; a circuit layer disposed on the substrate; and a device layer comprising light-emitting elements disposed in the light-emitting regions on the circuit layer. The circuit layer includes light-emitting pixel drivers arranged in a first direction and a second direction in the display area and electrically connected to the light-emitting elements. Among the light-emitting regions, eight light-emitting elements disposed in eight mutually adjacent light-emitting regions in the first direction, the second direction, and a diagonal direction intersecting the first direction and the second direction are electrically connected to eight light-emitting pixel drivers arranged in a first direction among the light-emitting pixel drivers.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat display device such as a Liquid Crystal Display Device, a Field Emission Display Device, or a Light Emitting Display Device. Here, the light emitting display device may include an organic light emitting display device comprising an organic light emitting element, an inorganic light emitting display device comprising an inorganic light emitting element such as an inorganic semiconductor, and a micro light emitting display device comprising a micro light emitting element.

[0004] Organic light-emitting display devices display images using light-emitting elements, each comprising a light-emitting layer of an organic light-emitting material. As such, since organic light-emitting display devices implement image display using self-emissive elements, they can possess relatively superior performance compared to other display devices in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0005] Among the display devices, the light-emitting surface may include a display area where an image is displayed and a non-display area surrounding the display area. In the display area, light-emitting regions that emit light with respective brightness and color may be arranged. The problem to be solved

[0006] The display device may include light-emitting pixel drivers that deliver driving current to light-emitting elements.

[0007] As the width of the light-emitting pixel drivers decreases, the number of light-emitting pixel drivers that can be placed in the display area can increase, which can be advantageous for increasing the resolution of the display device.

[0008] Accordingly, the problem that the present invention aims to solve is to provide a display device and an electronic device including the same, which can be advantageous for achieving high resolution by reducing the width of the light-emitting pixel driving units.

[0009] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0010] A display device according to one embodiment for solving the above problem comprises: a substrate including a display area in which light-emitting regions are arranged; a circuit layer disposed on the substrate; and a device layer including light-emitting elements disposed in the light-emitting regions on the circuit layer. The circuit layer includes light-emitting pixel drivers that are arranged in a first direction and a second direction in the display area and are electrically connected to the light-emitting elements. Among the light-emitting regions, eight light-emitting elements disposed in eight mutually adjacent light-emitting regions in the first direction, the second direction, and a diagonal direction intersecting the first direction and the second direction are electrically connected to eight light-emitting pixel drivers arranged in a first direction among the light-emitting pixel drivers.

[0011] The circuit layer may further include a first power wiring that transmits a first power supply; and a power connection transistor electrically connected between the first power wiring and two light-emitting pixel drivers adjacent in the first direction among the light-emitting pixel drivers. Each of the light-emitting pixel drivers may include a first transistor that is electrically connected between the power connection transistor and a first node and generates a driving current. A first electrode of the first transistor may be electrically connected to the power connection transistor. The first node may be electrically connected to a second electrode of the first transistor.

[0012] The circuit layer may include a first semiconductor layer disposed on the substrate; a first interlayer insulating layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the first interlayer insulating layer and comprising an oxide semiconductor material. The channel, first electrode, and second electrode of the first transistor may be disposed on the second semiconductor layer. The channel, first electrode, and second electrode of the power connection transistor may be disposed on the first semiconductor layer.

[0013] The eight light-emitting regions may include: a first light-emitting region; a second light-emitting region adjacent to the first light-emitting region in the diagonal direction; a third light-emitting region adjacent to the first light-emitting region in the first direction; a fourth light-emitting region adjacent to the third light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the first direction; a fifth light-emitting region adjacent to the first light-emitting region in the second direction; a sixth light-emitting region adjacent to the fifth light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the second direction; a seventh light-emitting region adjacent to the fifth light-emitting region in the first direction and adjacent to the third light-emitting region in the second direction; and an eighth light-emitting region adjacent to the seventh light-emitting region in the diagonal direction, adjacent to the sixth light-emitting region in the first direction, and adjacent to the fourth light-emitting region in the second direction. The eight light-emitting pixel drivers may include a first light-emitting pixel driver electrically connected to a light-emitting element of the first light-emitting region; It may include a second light-emitting pixel driver electrically connected to a light-emitting element of the second light-emitting region; a third light-emitting pixel driver electrically connected to a light-emitting element of the third light-emitting region; a fourth light-emitting pixel driver electrically connected to a light-emitting element of the fourth light-emitting region; a fifth light-emitting pixel driver electrically connected to a light-emitting element of the fifth light-emitting region; a sixth light-emitting pixel driver electrically connected to a light-emitting element of the sixth light-emitting region; a seventh light-emitting pixel driver electrically connected to a light-emitting element of the seventh light-emitting region; and an eighth light-emitting pixel driver electrically connected to a light-emitting element of the eighth light-emitting region.

[0014] Each of the first light-emitting region and the seventh light-emitting region can emit light in a first wavelength band. Each of the second light-emitting region, the fourth light-emitting region, the sixth light-emitting region, and the eighth light-emitting region can emit light in a second wavelength band that is lower than the first wavelength band. Each of the third light-emitting region and the fifth light-emitting region can emit light in a third wavelength band that is lower than the second wavelength band.

[0015] The first electrode and channel of the first transistor of the first light-emitting pixel driver may be symmetrical to the first electrode and channel of the first transistor of the second light-emitting pixel driver with respect to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. The first electrode of the first transistor of the first light-emitting pixel driver and the first electrode of the first transistor of the second light-emitting pixel driver may be interconnected.

[0016] Each of the above-mentioned light-emitting pixel drivers may further include a node connecting electrode that electrically connects the second electrode of the first transistor and the first electrode of the fifth transistor. The second electrode of the first transistor of the second light-emitting pixel driver may extend to one side of the second direction. The second electrode of the first transistor of the third light-emitting pixel driver may extend to the other side of the second direction. The node connecting electrode of the third light-emitting pixel driver may extend to the second direction.

[0017] Each of the above-described light-emitting pixel driving units may further include: a second transistor electrically connected between a data wiring that transmits a data signal and the gate electrode of the first transistor; a third transistor electrically connected between a reference voltage wiring that transmits a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage wiring that transmits an initialization voltage and a second node; a fifth transistor electrically connected between the first node and the second node; a first capacitor electrically connected between the gate electrode of the first transistor and the first node; and a second capacitor electrically connected between the first node and the first power wiring. The second node may be electrically connected to one of the light-emitting elements.

[0018] The first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may intersect with two scan-write wires that transmit different scan-write signals, one reset-control wire that transmits a reset-control signal, one initialization-control wire that transmits an initialization-control signal, one first light-emitting control wire that transmits a first light-emitting control signal, and one second light-emitting control wire that transmits a second light-emitting control signal. The gate electrode of the second transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver may be electrically connected to one of the two scan-write wires. The gate electrode of the second transistor of each of the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the other of the two scan-write wires. The gate electrode of the third transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the single reset control wire. The gate electrode of the fourth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the single initialization control wire.The gate electrodes of four power connection transistors electrically connected to the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver can be electrically connected to the one first light-emitting control wire. The gate electrode of the fifth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver can be electrically connected to the one second light-emitting control wire.

[0019] One of the first light-emitting pixel driver and the third light-emitting pixel driver may intersect with a data line and be electrically connected to the data line. The other of the first light-emitting pixel driver and the third light-emitting pixel driver may be electrically connected to the data line through a first data extension line extending in the first direction. One of the second light-emitting pixel driver and the fourth light-emitting pixel driver may intersect with another data line and be electrically connected to the other data line. The other of the second light-emitting pixel driver and the fourth light-emitting pixel driver may be electrically connected to the other data line through a second data extension line extending in the first direction.

[0020] The circuit layer may further include constant voltage auxiliary wirings that extend in the second direction and transmit a constant voltage. The first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may intersect with a first initialization voltage wiring that extends in the first direction and transmits a first initialization voltage, and a second initialization voltage wiring that extends in the first direction and transmits a second initialization voltage different from the first initialization voltage. The first initialization voltage wiring may be electrically connected to the first electrode of a fourth transistor of some of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver. The second initialization voltage wiring may be electrically connected to the first electrode of the fourth transistor of the other remaining portion among the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver. The constant voltage auxiliary wiring may include a first power auxiliary wiring that transmits the first power, a reference voltage auxiliary wiring that transmits the reference voltage, a first initialization voltage auxiliary wiring that transmits the first initialization voltage, and a second initialization voltage auxiliary wiring that transmits the second initialization voltage.The second electrode of the first transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may overlap with one of the constant voltage auxiliary wirings in a third direction.

[0021] The circuit layer may further include data lines extending in the second direction and transmitting a data signal; first auxiliary lines extending in the first direction; and second auxiliary lines extending in the second direction. Two adjacent data lines among the data lines may intersect the first light-emitting pixel driver and the second light-emitting pixel driver, respectively. Two adjacent second auxiliary lines among the second auxiliary lines may intersect the third light-emitting pixel driver and the fourth light-emitting pixel driver, respectively.

[0022] The above may further include a display driving circuit that supplies data signals to the data lines. The substrate may further include a non-display area disposed around the display area. The circuit layer may further include data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit. A bypass area on one side of the display area may include a bypass middle area, a first bypass side area parallel to the bypass middle area in the first direction and in contact with the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area. The data supply lines may extend to the bypass middle area and the second bypass side area. The data lines may include a first data line disposed in the first bypass side area and a second data line disposed in the second bypass side area. The first auxiliary lines may include a first bypass auxiliary line electrically connected to the first data line. The second auxiliary wirings may include a second bypass auxiliary wiring adjacent to the second data wiring, which is electrically connected to the first bypass auxiliary wiring. Among the data supply wirings, the first data supply wiring that transmits the data signal of the first data wiring may be electrically connected to the first data wiring through the first bypass auxiliary wiring and the second bypass auxiliary wiring. Among the data supply wirings, the second data supply wiring that transmits the data signal of the second data wiring may be directly electrically connected to the second data wiring.

[0023] An electronic device according to one embodiment for solving the above problem includes: a display device for displaying an image; a memory for storing an application; a processor for executing the application and transmitting an image data signal and an input control signal to the display device; and a power module for transmitting power to the display device. The display device includes a substrate comprising a display area in which light-emitting regions are arranged; a circuit layer disposed on the substrate; and an element layer disposed on the circuit layer. The circuit layer includes light-emitting pixel drivers that are arranged in a first direction and a second direction in the display area and are electrically connected to the light-emitting elements. The light-emitting regions include: a first light-emitting region; a second light-emitting region adjacent to the first light-emitting region in a diagonal direction; a third light-emitting region adjacent to the first light-emitting region in the first direction; a fourth light-emitting region adjacent to the third light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the first direction; a fifth light-emitting region adjacent to the first light-emitting region in the second direction; and a sixth light-emitting region adjacent to the fifth light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the second direction. It includes a seventh light-emitting region adjacent to the fifth light-emitting region in the first direction and adjacent to the third light-emitting region in the second direction; and an eighth light-emitting region adjacent to the seventh light-emitting region in the diagonal direction, adjacent to the sixth light-emitting region in the first direction and adjacent to the fourth light-emitting region in the second direction.The light-emitting pixel drivers include: a first light-emitting pixel driver electrically connected to a light-emitting element of the first light-emitting region; a second light-emitting pixel driver electrically connected to a light-emitting element of the second light-emitting region; a third light-emitting pixel driver electrically connected to a light-emitting element of the third light-emitting region; a fourth light-emitting pixel driver electrically connected to a light-emitting element of the fourth light-emitting region; a fifth light-emitting pixel driver electrically connected to a light-emitting element of the fifth light-emitting region; a sixth light-emitting pixel driver electrically connected to a light-emitting element of the sixth light-emitting region; a seventh light-emitting pixel driver electrically connected to a light-emitting element of the seventh light-emitting region; and an eighth light-emitting pixel driver electrically connected to a light-emitting element of the eighth light-emitting region.

[0024] The circuit layer may further include a first power wiring that transmits a first power supply; and a power connection transistor electrically connected between the first power wiring and two light-emitting pixel drivers adjacent in the first direction among the light-emitting pixel drivers. Each of the light-emitting pixel drivers may include a first transistor that is electrically connected between the power connection transistor and a first node and generates a driving current. The first node may be electrically connected to the second electrode of the first transistor. The first electrode of the power connection transistor may be electrically connected to the first power wiring. The first electrode and channel of the first transistor of the first light-emitting pixel driver may be symmetrical to the first electrode and channel of the first transistor of the second light-emitting pixel driver with respect to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. The first electrode of the first transistor of the first light-emitting pixel driver and the first electrode of the first transistor of the second light-emitting pixel driver are interconnected and may be electrically connected to the second electrode of a single power connection transistor.

[0025] Each of the above-mentioned light-emitting pixel drivers may further include a node connecting electrode that electrically connects the second electrode of the first transistor and the first electrode of the fifth transistor. The second electrode of the first transistor of the second light-emitting pixel driver may extend to one side of the second direction. The second electrode of the first transistor of the third light-emitting pixel driver may extend to the other side of the second direction. The node connecting electrode of the third light-emitting pixel driver may extend to the second direction.

[0026] Each of the above-described light-emitting pixel driving units may further include: a second transistor electrically connected between a data wiring that transmits a data signal and the gate electrode of the first transistor; a third transistor electrically connected between a reference voltage wiring that transmits a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage wiring that transmits an initialization voltage and a second node; and a fifth transistor electrically connected between the first node and the second node; a first capacitor electrically connected between the gate electrode of the first transistor and the first node; and a second capacitor electrically connected between the first node and the first power wiring. The first electrode of the first transistor may be electrically connected to the power connection transistor. The second node may be electrically connected to one of the light-emitting elements. The circuit layer may include a first semiconductor layer disposed on the substrate; a first interlayer insulating layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the first interlayer insulating layer and comprising an oxide semiconductor material. The channel, first electrode, and second electrode of the first transistor may be disposed in the second semiconductor layer. The channel, first electrode, and second electrode of the power connection transistor may be disposed in the first semiconductor layer.

[0027] One of the first light-emitting pixel driver and the third light-emitting pixel driver may intersect with a data line and be electrically connected to the data line. The other of the first light-emitting pixel driver and the third light-emitting pixel driver may be electrically connected to the data line through a first data extension line extending in the first direction. One of the second light-emitting pixel driver and the fourth light-emitting pixel driver may intersect with another data line and be electrically connected to the other data line. The other of the second light-emitting pixel driver and the fourth light-emitting pixel driver may be electrically connected to the other data line through a second data extension line extending in the first direction.

[0028] The first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may intersect with two scan-write wires that transmit different scan-write signals, one reset-control wire that transmits a reset-control signal, one initialization-control wire that transmits an initialization-control signal, one first light-emitting control wire that transmits a first light-emitting control signal, and one second light-emitting control wire that transmits a second light-emitting control signal. The gate electrode of the second transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver may be electrically connected to one of the two scan-write wires. The gate electrode of the second transistor of each of the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the other of the two scan-write wires. The gate electrode of the third transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the single reset control wire. The gate electrode of the fourth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver may be electrically connected to the single initialization control wire.The gate electrodes of four power connection transistors electrically connected to the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver can be electrically connected to the one first light-emitting control wire. The gate electrode of the fifth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver can be electrically connected to the one second light-emitting control wire.

[0029] The circuit may further include a display driving circuit that supplies data signals to the data lines. The substrate may further include a non-display area disposed around the display area. The circuit layer may further include data lines extending in the second direction and transmitting data signals; first auxiliary lines extending in the first direction; second auxiliary lines extending in the second direction; and data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit. A bypass area on one side of the display area may include a bypass middle area, a first bypass side area parallel to the bypass middle area in the first direction and in contact with the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area. The data supply lines may extend to the bypass middle area and the second bypass side area. The data lines may include a first data line disposed in the first bypass side area and a second data line disposed in the second bypass side area. The first auxiliary wirings may include a first bypass auxiliary wiring that is electrically connected to the first data wiring. The second auxiliary wirings may include a second bypass auxiliary wiring that is electrically connected to the first bypass auxiliary wiring and adjacent to the second data wiring. Among the data supply wirings, the first data supply wiring that transmits a data signal of the first data wiring may be electrically connected to the first data wiring through the first bypass auxiliary wiring and the second bypass auxiliary wiring. Among the data supply wirings, the second data supply wiring that transmits a data signal of the second data wiring may be directly electrically connected to the second data wiring.Among the above data lines, two adjacent data lines may intersect the first light-emitting pixel driver and the second light-emitting pixel driver, respectively. Among the above second auxiliary lines, two adjacent second auxiliary lines may intersect the third light-emitting pixel driver and the fourth light-emitting pixel driver, respectively.

[0030] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0031] A display device according to one embodiment includes a substrate, a circuit layer disposed on the substrate, and a device layer disposed on the circuit layer.

[0032] The substrate may include a display area in which light-emitting regions are arranged.

[0033] The circuit layer may include light-emitting pixel drivers arranged side by side in a first direction and a second direction in a display area.

[0034] The device layer may include light-emitting devices disposed in light-emitting regions.

[0035] According to one embodiment, eight light-emitting elements arranged in eight mutually adjacent light-emitting regions in a first direction, a second direction, and a diagonal direction intersecting therewith among the light-emitting regions can be electrically connected to eight light-emitting pixel drivers arranged in a mutually parallel manner in the first direction among the light-emitting pixel drivers.

[0036] That is, since the eight light-emitting pixel drivers electrically connected to the eight light-emitting elements placed in the eight light-emitting regions are not arranged in the first direction and the second direction, but are arranged only in the first direction, at least one of the wires electrically connected to the eight light-emitting pixel drivers and extending in the first direction is arranged as only one instead of two, so the number of wires in the first direction can be reduced.

[0037] Accordingly, the width of the area intersecting with the wiring of the first direction among each light-emitting pixel driving unit can be reduced, which can be advantageous for increasing the resolution of the display device.

[0038] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0039] FIG. 1 is a perspective view showing an electronic device according to one embodiment. Figure 2 is an exploded perspective view of the electronic device shown in Figure 1. Figure 3 is a plan view showing the display device of Figure 2. Figure 4 is a cross-sectional view showing A-A' of Figure 3. Figure 5 is a schematic diagram showing part B of Figure 3. Figure 6 is a block diagram showing the display device of Figure 2. FIG. 7 is an equivalent circuit diagram showing the light-emitting pixel driving unit of FIG. 6 according to one embodiment. FIG. 8 is a cross-sectional view showing the first transistor, second transistor, fifth transistor, first capacitor, second capacitor, and light-emitting element of FIG. 7. FIG. 9 is a schematic diagram showing some light-emitting pixel driving units according to one embodiment of FIG. 5. FIG. 10 is a plan view showing the substrate of FIG. 4 according to one embodiment. Figure 11 is a schematic diagram showing part C of Figure 10. Figure 12 is a schematic diagram showing part D of Figure 10. Figure 13 is a cross-sectional view showing E-E' of Figure 11. FIGS. 14, FIGS. 15, FIGS. 16, FIGS. 17, and FIGS. 18 are each plan views showing different parts of the light-emitting pixel driving units of FIG. 9 according to one embodiment. FIG. 19 is a block diagram of an electronic device according to one embodiment. FIG. 20 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention

[0040] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0041] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0042] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0043] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0044] Specific embodiments will be described below with reference to the attached drawings.

[0045] FIG. 1 is a perspective view showing an electronic device according to one embodiment. FIG. 2 is an exploded perspective view of the electronic device shown in FIG. 1.

[0046] Referring to FIG. 1, an electronic device (10) according to one embodiment is a device having the function of displaying an image in a display area. The electronic device (10) can provide portability. For example, the electronic device (10) may be a portable electronic device such as a mobile phone, a smartphone, a tablet PC (tablet personal computer), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a PMP (portable multimedia player), a navigation system, a UMPC (Ultra Mobile PC), etc.

[0047] However, the electronic device (10) according to one embodiment is not limited to a portable electronic device and may be a large device such as a television, laptop, monitor, billboard, or Internet of Things (IOT).

[0048] An electronic device (10) according to one embodiment may include a cover window (11) and a lower cover (12) provided as a housing that protects a display device (100 of FIG. 2).

[0049] Referring to FIG. 2, the electronic device (10) may further include a display device (100) housed between a cover window (11) and a lower cover (12), a bracket (13), and a main circuit board (14).

[0050] A display device (100) may include a display area (DA) where image display is implemented, a main area (MA) including a non-display area (NDA) surrounding the display area (DA), and a sub-area (SBA) protruding from one side of the main area (MA).

[0051] The display device (100) may further include a display driving circuit (200) disposed in a sub-area (SBA), a display circuit board (300) bonded to one side of the sub-area (SBA), a touch driving circuit (400) mounted on the display circuit board (300), and a cable (600) extending from one side of the display circuit board (300).

[0052] In this specification, the first direction (DR1) may be a direction parallel to the short side of the electronic device (10) on a plane, i.e., the horizontal direction of the electronic device (10). The second direction (DR2) may be a direction parallel to the long side of the electronic device (10) on a plane, i.e., the vertical direction of the electronic device (10). The third direction (DR3) may be the thickness direction of the electronic device (10).

[0053] The electronic device (10) may be formed in a shape close to a rectangle on a plane. For example, the electronic device (10) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the electronic device (10) is not limited to a rectangle and may be formed in other polygons, circles, or ellipses.

[0054] A cover window (11) may be placed on the upper surface of a display device (100) to cover the upper surface of the display device (100). The cover window (11) may serve to protect the upper surface of the display device (100).

[0055] The cover window (11) may include a transparent light-transmitting part and an opaque light-blocking part.

[0056] The light-emitting part may overlap with the display area (DA) of the display device (100) in the third direction (DR3), and the light-blocking part may overlap with the non-display area (NDA) of the display device (100) in the third direction (DR3).

[0057] The cover window (11) may include an upper surface portion forming the upper surface of the electronic device (10), a left side portion forming the left side of the electronic device (10), and a right side portion forming the right side of the electronic device (10). The left side portion of the cover window (11) may extend from the left side of the upper surface portion, and the right side portion may extend from the right side of the upper surface portion.

[0058] Each of the top, left, and right sides of the cover window (11) may include a light-transmitting part and a light-blocking part.

[0059] The light-emitting portion of the cover window (11) can be placed on most of the upper surface, left side, and right side of the cover window (11).

[0060] The light-blocking portion of the cover window (11) may be positioned at the upper edge and lower edge of the upper surface portion of the cover window (11), the upper edge, left edge, and lower edge of the left side portion of the cover window (11), and the upper edge, right edge, and lower edge of the right side portion of the cover window (11).

[0061] The display device (100) can be placed at the bottom of the cover window (11).

[0062] That is, the cover window (11) can be placed on the display device (100).

[0063] The display device (100) may include an upper surface facing the upper surface of the cover window (11), a left side facing the left side of the cover window (11), and a right side facing the right side of the cover window (11). The left side of the display device (100) may extend from the left side of the upper surface, and the right side may extend from the right side of the upper surface.

[0064] The display device (100) may include a main area (MA) that serves as a display surface and a sub-area (SBA) that protrudes from at least a portion of one side of the main area (MA).

[0065] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA).

[0066] The display area (DA) can be placed over most of the main area (MA). The display area (DA) can be placed in the center of the main area (MA).

[0067] In other words, the top surface, left side, and right side of the display device (100) may each include a display area (DA) and a non-display area (NDA).

[0068] The display area (DA) can be placed on most of the top surface, left side, and right side of the display device (100).

[0069] The non-display area (NDA) may be placed outside the display area (DA). The non-display area (NDA) may be an edge area of ​​the main area (MA).

[0070] The non-display area (NDA) may be positioned at the upper edge and lower edge of the upper surface portion of the display device (100), the upper edge, left edge, and lower edge of the left side portion of the display device (100), and the upper edge, right edge, and lower edge of the right side portion of the display device (100).

[0071] The sub-region (SBA) can protrude in a second direction (DR2) from one side of the main region (MA).

[0072] The length of the first direction (DR1) of the sub-region (SBA) may be less than or equal to the length of the first direction (DR1) of the main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be smaller than the length of the second direction (DR2) of the main region (MA), but is not limited thereto.

[0073] As part of the sub-region (SBA) is deformed into a bent shape, another part of the sub-region (SBA) can overlap with the main region (MA) in the third direction (DR3).

[0074] A display driving circuit (200) is mounted in the sub-area (SBA), and a display circuit board (300) can be attached.

[0075] One end of the display circuit board (300) can be attached to pads placed on the lower edge of a sub-region (SBA) of the display device (100) using an anisotropic conductive film.

[0076] The display circuit board (300) may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that maintains a flat shape, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0077] The display driving circuit (200) can transmit the data signal (Vdata in FIG. 7) of each of the light-emitting pixel drivers (EPDs in FIG. 6) of the display area (DA) to the data lines (DLs in FIG. 6) based on the control signals, power supplies, and voltages supplied through the display circuit board (300).

[0078] The display driving circuit (200) is provided as an integrated circuit (IC) and can be mounted in a sub-region (SBA) of the display device (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic method. However, this is merely an example and is not limited thereto. For example, the display driving circuit (200) may be mounted on a display circuit board (300).

[0079] According to one embodiment, a touch driving circuit (400) may be further mounted in a sub-region (SBA) of the display device (100).

[0080] Alternatively, as shown in FIG. 2, the touch driving circuit (400) may be mounted on the display circuit board (300).

[0081] The touch driving circuit (400) can be electrically connected to the touch sensor layer (150 in FIG. 4) of the display device (100).

[0082] As shown in Fig. 2, the bracket (13) can be placed at the bottom of the display device (100).

[0083] The bracket (13) may be made of plastic or metal. The bracket (13) may include a first camera hole (CMH1) into which a camera device (16) is inserted, a battery hole (BH) into which a battery (18) is placed, and a cable hole (CAH) through which a cable (600) connected to a display circuit board (300) passes.

[0084] A main circuit board (14) and a battery (18) can be placed at the bottom of the bracket (13).

[0085] The main circuit board (14) may be a printed circuit board or a flexible printed circuit board.

[0086] The main circuit board (14) may include a main processor (15), a camera device (16), and a main connector (17). The main processor (15) may be formed as an integrated circuit.

[0087] The camera device (16) may be placed on both the upper and lower surfaces of the main circuit board (14), the main processor (15) may be placed on the upper surface of the main circuit board (14), and the main connector (17) may be placed on the lower surface of the main circuit board (14).

[0088] The main processor (15) can control all functions of the electronic device (10).

[0089] For example, the main processor (15) can output digital video data to the display driving circuit (200) through the display circuit board (300) so that the display device (100) displays an image. Additionally, the main processor (15) can receive touch data including the user's touch coordinates from the touch driving circuit (400), determine whether the user has touched or is in proximity, and then execute an action corresponding to the user's touch input or proximity input. For example, the main processor (15) can execute an application indicated by the icon touched by the user or perform an action.

[0090] The main processor (15) may be an application processor, a central processing unit, or a system chip made of an integrated circuit.

[0091] The camera device (16) processes image frames, such as still images or video, obtained by an image sensor in camera mode and outputs them to the main processor (15).

[0092] A cable (600) passing through the cable hole (CAH) of the bracket (13) can be connected to the main connector (17). As a result, the main circuit board (14) can be electrically connected to the display circuit board (300).

[0093] The battery (18) can be positioned so as not to overlap with the main circuit board (14) in the third direction (DR3). The battery (18) can overlap with the battery hole (BH) of the bracket (13) in the third direction (DR3).

[0094] In addition, the main circuit board (14) may be further equipped with a mobile communication module capable of transmitting and receiving wireless signals with at least one of a base station, an external terminal, or a server on a mobile communication network. The wireless signal may include various forms of data such as voice signals, video call signals, or text / multimedia message transmission and reception.

[0095] The lower cover (12) may be placed on the lower side of the main circuit board (14) and the battery (18). The lower cover (12) may be secured by being fastened to a bracket (13). The lower cover (12) may form the upper side, lower side, and lower surface of the electronic device (10). The lower cover (12) may include plastic, metal, or both plastic and metal.

[0096] The lower cover (12) may include a second camera hole (CMH2) through which the lower surface of the camera device (16) is exposed. The position of the camera device (16) and the positions of the first camera hole (CMH1) and the second camera hole (CMH2) corresponding to the camera device (16) are not limited by the illustration in FIG. 2.

[0097] Next, a display device (100) according to one embodiment will be described.

[0098] FIG. 3 is a plan view showing the display device of FIG. 2. FIG. 4 is a cross-sectional view showing A-A' of FIG. 3.

[0099] Referring to FIGS. 3 and 4, a display device (100) according to one embodiment is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0100] The display device (100) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the description will focus on the case where the display device (100) is an organic light-emitting display device. However, the present invention is not limited thereto and may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0101] The display device (100) may be formed flat, but is not limited thereto. For example, the display device (100) may include a curved surface formed at the left and right ends, having a constant curvature or a changing curvature. In addition, the display device (100) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0102] Referring to FIG. 3, at least one surface of the display device (100) includes a main area (MA) from which light for image display is emitted.

[0103] The display area (DA) may be formed as a rectangular plane having a short side of the first direction (DR1) and a long side of the second direction (DR2) that intersects the first direction (DR1). The corner where the short side of the first direction (DR1) and the long side of the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display area (DA) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses.

[0104] The display area (DA) can be placed in most of the main area (MA). The display area (DA) can be placed in the center of the main area (MA).

[0105] Referring to FIG. 4, the display device (100) may further include a sub-region (SBA) protruding in a second direction (DR2) from at least a portion of one side of the main area (MA).

[0106] As a part of the sub-region (SBA) is deformed into a bent shape, another part of the sub-region (SBA) can be placed on the back surface of the display device (100).

[0107] According to one embodiment, a display device (100) includes a substrate (110), a circuit layer (120) disposed on the substrate (110), and a component layer (130) disposed on the circuit layer (120).

[0108] The display device (100) may further include a sealing layer (140) disposed on the element layer (130) and a touch sensor layer (150) disposed on the sealing layer (140).

[0109] The display device (100) may further include a polarizing layer (160) disposed on the touch sensor layer (150) to reduce external light reflection.

[0110] The substrate (110) may include a main area (MA) corresponding to a display surface and a sub-area (SBA) protruding in a second direction (DR2) from at least a portion of one side of the main area (MA).

[0111] The main area (MA) of the substrate (110) may include a display area (DA) where light is emitted, and a non-display area (NDA) placed around the display area (DA).

[0112] According to one embodiment, the element layer (130) may include light-emitting elements (LEs in FIG. 7 and FIG. 8) respectively disposed in light-emitting regions (EAs in FIG. 5).

[0113] The circuit layer (120) may include light-emitting pixel drivers (EPDs in FIG. 5) electrically connected to light-emitting elements (LEs), and data wiring (DLs in FIG. 6 and 7) that transmit data signals (Vdata in FIG. 7) of the light-emitting pixel drivers (EPDs in FIG. 5).

[0114] The sealing layer (140) can cover the device layer (130). The sealing layer (140) may include a structure in which two or more inorganic films and at least one organic film are alternately stacked.

[0115] The touch sensor layer (150) is disposed on the sealing layer (140) and may correspond to the main area (MA). The touch sensor layer (150) may include touch electrodes for detecting touch by a person or object.

[0116] The polarization layer (160) is intended to prevent a decrease in the visibility of an image due to external light reflection by blocking external light reflected from the touch sensor layer (150), sealing layer (140), device layer (130), circuit layer (120), and the interfaces thereof.

[0117] Meanwhile, as a portion of the sub-region (SBA) is deformed into a bending shape, the display driving circuit (200) mounted on the sub-region (SBA) and the display circuit board (300) connected to one side of the sub-region (SBA) can be placed under the substrate (110).

[0118] The display driving circuit (200) can be electrically connected to the data lines (DLs in FIG. 6 and FIG. 7) of the circuit layer (120). Based on control signals and power voltages supplied from the display circuit board (300), the display driving circuit (200) can transmit data signals (Vdata in FIG. 7) of the light-emitting pixel drivers (EPDs in FIG. 5) through the data lines (DLs).

[0119] The display driving circuit (200) is provided as an integrated circuit (IC) and can be mounted in a sub-region (SBA) of the display device (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic method. However, this is merely an example and is not limited thereto. For example, the display driving circuit (200) may be mounted on a display circuit board (300).

[0120] One end of the display circuit board (300) can be attached to pads placed on one edge of a sub-region (SBA) of the display device (100) using an anisotropic conductive film.

[0121] The display circuit board (300) may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that maintains a flat shape, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0122] The display circuit board (300) can be connected to signal pads (SPDs of FIG. 10) placed on one side of the sub-region (SBA).

[0123] A touch driving circuit (400) can be mounted on the display circuit board (300).

[0124] The touch driving circuit (400) can be electrically connected to the touch sensor layer (150) of the display device (100).

[0125] The touch driving circuit (400) can apply a touch driving signal to the driving wires of the touch sensor layer (150) and receive a touch detection signal from the sensing wires. Then, the touch driving circuit (400) can determine whether a user touches and whether they are in close proximity by detecting the change in charge of the capacitances based on the touch detection signal.

[0126] User touch refers to an object, such as a user's finger or pen, directly contacting the upper surface of a cover window placed on a touch sensor layer. User proximity refers to an object, such as a user's finger or pen, hovering away from the upper surface of the cover window.

[0127] The touch driving circuit (400) can output touch data including the user's touch coordinates to the main processor (15 in FIG. 2).

[0128] Figure 5 is a schematic diagram showing part B of Figure 3.

[0129] As shown in FIG. 5, the display area (DA) may include light-emitting regions (EA) where light is emitted, and a non-light-emitting region (NEA) that is a spaced area between the light-emitting regions (EA) and where light is not emitted.

[0130] Each of the light-emitting regions (EA) may be a unit region that emits light of a wavelength band corresponding to one of two or more different colors with a brightness corresponding to an image signal.

[0131] Each of the light-emitting regions (EA) can be arranged in a square shape. For example, as illustrated in FIG. 5, each of the light-emitting regions (EA) may have a rhombus shape. However, this is merely an example, and the planar shape of the light-emitting regions (EA) according to one embodiment is not limited to the illustration in FIG. 5. That is, in addition to a rhombus, the light-emitting regions (EA) may have a planar shape that is a polygon such as a rectangle, square, hexagon, octagon, etc., a circle, or an ellipse.

[0132] According to one embodiment, light-emitting regions (EA) may be arranged side by side in a first direction (DR1), a second direction (DR2), and diagonal directions (DR4, DR5) intersecting therefrom.

[0133] The diagonal directions (DR4, DR5) may include a first diagonal direction (DR4) between the lower left and upper right and a second diagonal direction (DR5) between the lower right and upper left. For a brief and easy explanation of one example, the second diagonal direction (DR5) may be referred to as the diagonal direction (DR4, DR5).

[0134] According to one embodiment, the light-emitting regions (EA) may include eight mutually adjacent light-emitting regions (EA1-EA8) in a first direction (DR1), a second direction (DR2), and diagonal directions (DR4, DR5) intersecting therefrom.

[0135] The eight light-emitting regions (EA1-EA8) comprise a first light-emitting region (EA1), a second light-emitting region (EA2) adjacent to the first light-emitting region (EA1) in the diagonal direction (DR5), a third light-emitting region (EA3) adjacent to the first light-emitting region (EA1) in the first direction (DR1), a fourth light-emitting region (EA4) adjacent to the third light-emitting region (EA3) in the diagonal direction (DR5) and adjacent to the second light-emitting region (EA2) in the first direction (DR1), a fifth light-emitting region (EA5) adjacent to the first light-emitting region (EA1) in the second direction (DR2), a sixth light-emitting region (EA6) adjacent to the fifth light-emitting region (EA5) in the diagonal direction (DR5) and adjacent to the second light-emitting region (EA2) in the second direction (DR2), a seventh light-emitting region (EA7) adjacent to the fifth light-emitting region (EA5) in the first direction (DR1) and adjacent to the third light-emitting region (EA3) in the second direction (DR2), and a diagonal It may include an 8th light-emitting region (EA8) adjacent to the 7th light-emitting region (EA7) in the direction (DR5), adjacent to the 6th light-emitting region (EA6) in the 1st direction (DR1), and adjacent to the 4th light-emitting region (EA4) in the 2nd direction (DR2).

[0136] According to one embodiment, the light-emitting regions (EA) may include first color light-emitting regions (R_EA) that emit light of a first wavelength band, second color light-emitting regions (G_EA) that emit light of a second wavelength band lower than the first wavelength band, and third color light-emitting regions (B_EA) that emit light of a third wavelength band lower than the second wavelength band.

[0137] For example, the first wavelength band is about 600 nm to about 750 nm and may correspond to red. The second wavelength band is about 480 nm to about 560 nm and may correspond to green. The third wavelength band is about 370 nm to about 460 nm and may correspond to blue.

[0138] However, this is merely an example, and the first wavelength band, second wavelength band, and third wavelength band according to one embodiment are not limited thereto.

[0139] As the light-emitting regions (EA) include a first color light-emitting region (R_EA), a second color light-emitting region (G_EA), and a third color light-emitting region (B_EA), unit pixels (PX) can each be provided by a combination of one or more mutually adjacent first color light-emitting regions (R_EA), one or more second color light-emitting regions (G_EA), and one or more third color light-emitting regions (B_EA) among the light-emitting regions (EA).

[0140] Each unit pixel (PX) can be a unit that displays various colors, including white. That is, the various colors of light displayed in each unit pixel (PX) can be realized by mixing light emitted from two or more light-emitting regions (EA) included in each unit pixel (PX).

[0141] The third color emission region (B_EA) may have a wider width than the first color emission region (R_EA), and the first color emission region (R_EA) may have a wider width than the second color emission region (G_EA). However, this is merely an example, and the width of each of the emission regions (EA) is not limited to the illustration in FIG. 5.

[0142] According to one embodiment, each of the first light-emitting region (EA1) and the seventh light-emitting region (EA7) may be a first color light-emitting region (R_EA) that emits light of a first wavelength band.

[0143] Each of the second light-emitting region (EA2), the fourth light-emitting region (EA4), the sixth light-emitting region (EA6), and the eighth light-emitting region (EA8) may be a second color light-emitting region (G_EA) that emits light of the second wavelength band.

[0144] Each of the third light-emitting region (EA3) and the fifth light-emitting region (EA5) may be a third color light-emitting region (B_EA) that emits light of the third wavelength band.

[0145] According to one embodiment, the circuit layer (120) may include light-emitting pixel drivers (EPDs) arranged in a first direction (DR1) and a second direction (DR2) in a display area (DA in FIG. 3).

[0146] The light-emitting pixel drivers (EPDs) can be electrically connected to the light-emitting elements (LEs in FIG. 7 and FIG. 8) of the element layer (130 in FIG. 4) placed in the light-emitting regions (EA).

[0147] According to one embodiment, light-emitting elements (LE) placed in eight mutually adjacent light-emitting regions (EA1-EA8) in a first direction (DR1), a second direction (DR2), and diagonal directions intersecting them (DR4, DR5) can be electrically connected to eight light-emitting pixel drivers (EPD1-EPD8) arranged in the first direction (DR1) among the light-emitting pixel drivers (EPD) of the circuit layer (120).

[0148] In other words, in the first direction (DR1), the second direction (DR2) and the diagonal directions (DR4, DR5) intersecting therewith, eight light-emitting pixel drivers (EPD1-EPD8) electrically connected to light-emitting elements (LE) placed in eight mutually adjacent light-emitting regions (EA1-EA8) are not arranged in the first direction (DR1) and the second direction (DR2) like the eight light-emitting regions (EA1-EA8), but are arranged only in the first direction (DR1).

[0149] In this way, as described below with reference to FIG. 9, at least one of the wirings (hereinafter referred to as "wirings of the first direction (DR1)" that are electrically connected to the eight light-emitting pixel drivers (EPD1-EPD8) and extend in the first direction (DR1) can be arranged as only one instead of two, so the number of wirings in the first direction (DR1) can be reduced.

[0150] For example, according to one embodiment of FIG. 9, the wiring of the first direction (DR1) may include a scan write wiring (GWL), a reset control wiring (GRL), an initialization control wiring (GIL), a first light emission control wiring (ECL1), a second light emission control wiring (ECL2), a reference voltage wiring (VRL), a first power wiring (VDL), a first initialization voltage wiring (VAIL1) and a second initialization voltage wiring (VAIL2).

[0151] As described above, according to one embodiment, in the first direction (DR1), the second direction (DR2), and the diagonal directions (DR4, DR5) intersecting therewith, eight light-emitting pixel drivers (EPD1-EPD8) electrically connected to light-emitting elements (LE) placed in eight mutually adjacent light-emitting regions (EA1-EA8) are arranged only in the first direction (DR1), thereby reducing the number of wirings in the first direction (DR1) electrically connected to the eight light-emitting pixel drivers (EPD1-EPD8). Accordingly, in each of the light-emitting pixel drivers (EPD), the width of the region intersecting with the wirings in the first direction (DR1) can be reduced, which is advantageous for increasing the resolution of the display device (100).

[0152] Figure 6 is a block diagram showing the display device of Figure 2.

[0153] Referring to FIG. 6, a circuit layer (120) of a display device (100) according to one embodiment may include light-emitting pixel drivers (EPDs) electrically connected to light-emitting elements (LEs in FIG. 7) placed in light-emitting regions (EAs in FIG. 5), and data lines (DLs) that transmit data signals (Vdatas in FIG. 7) to the light-emitting pixel drivers (EPDs).

[0154] The circuit layer (120) may further include one or more gate wires (GL) that transmit one or more gate signals to light-emitting pixel drivers (EPDs).

[0155] According to one embodiment, the display device (100) may further include a display driving circuit (200) that outputs data signals (Vdata in FIG. 7) of light-emitting pixel drivers (EPDs) to data lines (DL) to control the brightness of each of the light-emitting elements (LEs in FIG. 7).

[0156] According to one embodiment, the display device (100) may further include a gate driver (GTDR) that outputs gate signals to gate wires (GL), a power supply unit (700) that supplies power and voltages to light-emitting pixel drivers (EPDs), and a timing control unit (800) that controls the driving timing of each of the display driving circuit (200) and the gate driver (GTDR).

[0157] The timing control unit (800) receives a video signal supplied from outside the display device (100).

[0158] The timing control unit (800) can output image data (DATA) and a data control signal (DCS) to the display driving circuit (200).

[0159] The timing control unit (800) can generate a scan control signal (SCS) to control the operation timing of the gate driver (GTDR).

[0160] The display driving circuit (200) can convert image data (DATA) into analog data voltages and output them to data wires (DL).

[0161] The gate driver (GTDR) can generate gate signals according to the scan control signal (SCS) and sequentially output the gate signals to the gate wires (GL).

[0162] The gate wires (GL) may include a scan write wire (GWL) that transmits a scan write signal (GW in FIG. 7), a reset control wire (GRL) that transmits a reset control signal (GR in FIG. 7), an initialization control wire (GIL) that transmits an initialization control signal (GI in FIG. 7), a first light emission control wire (ECL1) that transmits a first light emission control signal (EC1 in FIG. 7), and a second light emission control wire (ECL2) that transmits a second light emission control signal (EC2 in FIG. 7).

[0163] The gate signals may have pulses that vary to a first gate level voltage or a second gate level voltage.

[0164] The power supply unit (700) can supply various power sources and voltages required for driving the light-emitting pixel driving units (EPDs).

[0165] For example, the power supply unit (700) can supply a first power supply (ELVDD in FIG. 7) and a second power supply (ELVSS in FIG. 7) for generating a driving signal to be transmitted to the light-emitting elements (LE), a reference voltage (VREF in FIG. 7) for initializing the light-emitting pixel driving units (EPDs), and an initialization voltage (VINT in FIG. 7) for initializing the light-emitting elements (LEs in FIG. 7).

[0166] FIG. 7 is an equivalent circuit diagram showing the light-emitting pixel driving unit of FIG. 6 according to one embodiment.

[0167] Referring to FIG. 7, the circuit layer (120 of FIG. 4) may include a first power line (VDL) that transmits a first power (ELVDD) to light-emitting pixel drivers (EPDs), a second power line (VSL) that transmits a second power (ELVSS) to light-emitting elements (LEs), a reference voltage line (VRL) that transmits a reference voltage (VREF) to light-emitting pixel drivers (EPDs), and an initialization voltage line (VAIL) that transmits an initialization voltage (VAINT).

[0168] The light-emitting elements (LE) of the element layer (130 in FIG. 4) can be electrically connected between the light-emitting pixel drivers (EPDs) and the second power supply (ELVSS).

[0169] That is, one of the light-emitting elements (LE) can be electrically connected between one of the light-emitting pixel drivers (EPD) of the circuit layer (120) and the second power supply (ELVSS).

[0170] The second power source (ELVSS) may be at a lower voltage level than the first power source (ELVDD).

[0171] That is, the anode electrode of the light-emitting element (LE) is electrically connected to the light-emitting pixel driver (EPD), and the cathode electrode of the light-emitting element (LE) can be electrically connected to the second power wiring (VSL) that transmits the second power supply (ELVSS).

[0172] The capacitor (Cel) connected in parallel with the light-emitting element (LE) represents the parasitic capacitance between the anode electrode and the cathode electrode.

[0173] The circuit layer (120) may include a scan write wire (GWL) that transmits a scan write signal (GW), a reset control wire (GRL) that transmits a reset control signal (GR), an initialization control wire (GIL) that transmits an initialization control signal (GI), a first light emission control wire (ECL1) that transmits a first light emission control signal (EC1), and a second light emission control wire (ECL2) that transmits a second light emission control signal (EC2).

[0174] According to one embodiment, the circuit layer (120) may include a power connection transistor (TPC) that is electrically connected between two mutually adjacent light-emitting pixel drivers (EPDs) in a first direction (DR1) among the light-emitting pixel drivers (EPDs) and a first power line (VDL).

[0175] Each of the light-emitting pixel drivers (EPDs) may include a first transistor (T1) that is electrically connected between a power connection transistor (TPC) and a first node (N1) and generates a driving current for driving a light-emitting element (LE).

[0176] The first electrode of the power connection transistor (TPC) is electrically connected to the first power wiring (VDL), and the second electrode of the power connection transistor (TPC) can be electrically connected to the first electrode of the first transistor (T1) of each of two mutually adjacent light-emitting pixel drivers (EPDs).

[0177] According to one embodiment, each of the light-emitting pixel driving units (EPDs) of the circuit layer (120) may further include two or more transistors (T2 to T5) electrically connected to the first transistor (T1) or light-emitting element (LE) and one or more capacitors (C1, C2).

[0178] That is, each of the light-emitting pixel drivers (EPDs) may further include a second transistor (T2) electrically connected between the data line (DL) and the gate electrode of the first transistor (T1), a third transistor (T3) electrically connected between the reference voltage line (VRL) and the gate electrode of the first transistor (T1), a fourth transistor (T4) electrically connected between the initialization voltage line (VAIL) and the second node (N2), a fifth transistor (T5) electrically connected between the first node (N1) and the second node (N2), a first capacitor (C1) electrically connected between the gate electrode of the first transistor (T1) and the first node (N1), and a second capacitor (C2) electrically connected between the first node (N1) and the first power line (VDL).

[0179] The first node (N1) can be electrically connected to the second electrode of the first transistor (T1).

[0180] The second node (N2) can be electrically connected to the light-emitting element (LE).

[0181] The second transistor (T2) can be turned on by the scan write signal (GW) of the scan write wiring (GWL).

[0182] When the second transistor (T2) is turned on, the data signal (Vdata) of the data wiring (DL) can be transmitted to the gate electrode of the first transistor (T1).

[0183] When the voltage difference between the gate electrode of the first transistor (T1) and the second electrode of the first transistor (T1) becomes greater than the threshold voltage of the first transistor (T1) due to the data signal (Vdata) applied to the gate electrode of the first transistor (T1), the first transistor (T1) can be turned on. Accordingly, the drain-source current of the first transistor (T1) can be generated with a magnitude corresponding to the data signal (Vdata).

[0184] The third transistor (T3) can be turned on by the reset control signal (GR) of the reset control wiring (GRL).

[0185] When the third transistor (T3) is turned on, the potential of the gate electrode of the first transistor (T1) can be reset to the reference voltage (VREF) of the reference voltage wiring (VRL).

[0186] The fourth transistor (T4) can be turned on by the initialization control signal (GI) of the initialization control wiring (GIL).

[0187] When the fourth transistor (T4) is turned on, the potential of the anode electrode of the light-emitting element (LE) can be initialized to the initial voltage (VAINT) of the initial voltage wiring (VAIL).

[0188] The first transistor (T1) can be electrically connected to the first power wiring (VDL in FIG. 7) through a power connection transistor (TPC).

[0189] The power connection transistor (TPC) can be turned on by the first light emission control signal (EC1) of the first light emission control wiring (ECL1).

[0190] When the power connection transistor (TPC) is turned on, the first power (ELVDD) of the first power wiring (VDL) can be delivered to the first electrode of the first transistor (T1).

[0191] The fifth transistor (T5) can be turned on by the second light emission control signal (EC2) of the second light emission control wiring (ECL2).

[0192] When the fifth transistor (T5) is turned on, the drain-source current of the first transistor (T1), which is generated with a size corresponding to the data signal (Vdata), can be delivered to the light-emitting element (LE) through the fifth transistor (T5) as a driving current.

[0193] Thus, the light-emitting element (LE) can emit light of a brightness corresponding to the data signal (Vdata).

[0194] The first capacitor (C1) can be electrically connected between the gate electrode of the first transistor (T1) and the second electrode of the first transistor (T1).

[0195] Accordingly, the first capacitor (C1) can be filled with a data signal (Vdata) applied to the gate electrode of the first transistor (T1), and due to the voltage filled in the first capacitor (C1), the turn-on of the first transistor (T1) can be maintained for a predetermined period.

[0196] The second capacitor (C2) can be electrically connected between the second electrode of the first transistor (T1) and the first power line (VDL).

[0197] The voltage of the first capacitor (C1) corresponds to the potential difference between the gate electrode of the first transistor (T1) and the second electrode of the first transistor, and can be varied by the data signal (Vdata).

[0198] Additionally, the voltage of the first capacitor (C1) can be divided by the second capacitor (C2). Thus, the potential difference between the gate electrode of the first transistor (T1) and the second electrode of the first transistor can be maintained at a magnitude corresponding to the data signal (Vdata).

[0199] According to one embodiment, the first transistor (T1) may include a gate electrode and a gate addition electrode facing each other on both sides of the channel.

[0200] The gate electrode of the first transistor (T1) can be electrically connected to the second transistor (T2).

[0201] The gate additional electrode of the first transistor (T1) can be electrically connected to the second electrode of the first transistor (T1).

[0202] Accordingly, when a data signal (Vdata) is applied to the gate electrode of the first transistor (T1) and the first transistor (T1) is turned on, the other part of the channel of the first transistor (T1) adjacent to the gate electrode may not be activated compared to the part of the channel of the first transistor (T1) adjacent to the gate electrode.

[0203] Therefore, since the electron mobility of the channel of the first transistor (T1) is reduced, the slope of the current curve representing the relationship between the voltage of the gate electrode and the source-drain current of the first transistor (T1) can be made gentler. Consequently, the driving voltage range of the first transistor (T1) can be widened, thereby improving the ease of brightness control.

[0204] As shown in Fig. 7, the first transistor (T1) may be an N-type MOSFET.

[0205] Similar to the first transistor (T1), the second to fifth transistors (T2 to T5) and the power connection transistor (TPC) may also be N-type MOSFETs.

[0206] Alternatively, as shown in FIG. 7, at least some of the second to fifth transistors (T2 to T5) and the power connection transistor (TPC) may be P-type MOSFETs.

[0207] For example, the power connection transistor (TPC) and the fifth transistor (T5) may be P-type MOSFETs, and the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may be N-type MOSFETs.

[0208] Accordingly, according to one embodiment, the circuit layer (120) may include a first semiconductor layer (SEL1 in FIG. 8) for forming a P-type MOSFET and a second semiconductor layer (SEL2 in FIG. 8) for forming an N-type MOSFET.

[0209] FIG. 8 is a cross-sectional view showing the first transistor, second transistor, sixth transistor, first capacitor, second capacitor, and light-emitting element of FIG. 7.

[0210] Referring to FIG. 8, a display device (100) according to one embodiment may include a substrate (110), a circuit layer (120) on the substrate (110), and a device layer (130) on the circuit layer (120).

[0211] The display device (100) may further include a sealing layer (140) on the element layer (130).

[0212] According to one embodiment, the circuit layer (120) may include a first semiconductor layer (SEL1) disposed on a substrate (110), a first interlayer insulating layer (124) disposed on the first semiconductor layer (SEL1), and a second semiconductor layer (SEL2) disposed on the first interlayer insulating layer (124).

[0213] The circuit layer (120) comprises a first gate insulating layer (122) covering a first semiconductor layer (SEL1), a first gate conductive layer (GCDL1) disposed on the first gate insulating layer (122), a second gate insulating layer (123) covering the first gate conductive layer (GCDL1), a second gate conductive layer (GCDL2) disposed between the second gate insulating layer (123) and the first interlayer insulating layer (124), a third gate insulating layer (125) covering the second semiconductor layer (SEL2), a third gate conductive layer (GCDL3) disposed on the third gate insulating layer (125), a second interlayer insulating layer (126) covering the third gate conductive layer (GCDL3), a first source drain conductive layer (SDCDL1) disposed on the second interlayer insulating layer (126), a first flattening layer (127) covering the first source drain conductive layer (SDCDL1), and the first flattening layer (127). It may further include a second source drain conductive layer (SDCDL2) disposed on top, and a second flattening layer (128) covering the second source drain conductive layer (SDCDL2).

[0214] However, the circuit layer (120) illustrated in FIG. 8 is merely an example, and the circuit layer (120) of the display device (100) according to one embodiment is not limited to the illustration in FIG. 8. For example, the circuit layer (120) may further include one or more additional gate insulating layers disposed on the second gate conductive layer (GCDL2), and one or more additional gate conductive layers disposed on the one or more additional gate insulating layers and covered by the first interlayer insulating layer (124).

[0215] According to one embodiment, the circuit layer (120) may further include a buffer layer (121) covering the substrate (110). In this case, the first semiconductor layer (SEL1) may be placed on the buffer layer (121).

[0216] The circuit layer (120) may include light-emitting pixel drivers (EPDs) that are electrically connected to the light-emitting elements (LEs) of the element layer (130).

[0217] According to one embodiment of FIG. 7, the circuit layer (120) may include light-emitting pixel drivers (EPDs) and a power connection transistor (TPC) electrically connected between two light-emitting pixel drivers (EPDs) adjacent to each other in a first direction (DR1) and a first power line (VDL).

[0218] Each of the light-emitting pixel driving units (EPD) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a first capacitor (C1), and a second capacitor (C2).

[0219] Each of the first transistor (T1), second transistor (T2), third transistor (T3), fourth transistor (T4), fifth transistor (T5), and power connection transistor (TPC) may include a gate electrode, a channel overlapping with the gate electrode, a first electrode connected to one side of the channel, and a second electrode connected to the other side of the channel.

[0220] According to one embodiment, the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may be N-type MOSFETs, and the fifth transistor (T5) and the power connection transistor (TPC) may be P-type MOSFETs.

[0221] The channel, first electrode, and second electrode of a P-type MOSFET may be placed in a first semiconductor layer (SEL1), and the channel, first electrode, and second electrode of an N-type MOSFET may be placed in a second semiconductor layer (SEL2).

[0222] That is, the channels, first electrodes, and second electrodes of each of the first transistor (T1), second transistor (T2), third transistor (T3), and fourth transistor (T4) may be placed in the second semiconductor layer (SEL2), and the channels, first electrodes, and second electrodes of each of the fifth transistor (T5) and power connection transistor (TPC) may be placed in the first semiconductor layer (SEL1).

[0223] As shown in FIG. 8, the fifth transistor (T5) may include a channel (CH5) disposed in a first semiconductor layer (SEL1), a first electrode (E15) disposed in the first semiconductor layer (SEL1) and connected to one side of the channel (CH5), a second electrode (E25) disposed in the first semiconductor layer (SEL1) and connected to the other side of the channel (CH5), and a gate electrode (G5) disposed in a first gate conductive layer (GCDL1) and overlapping with the channel (CH5).

[0224] The first semiconductor layer (SEL1) may include a silicon semiconductor material such as polysilicon or amorphous silicon.

[0225] The first semiconductor layer (SEL1) may include a first capacitor electrode (CAE1).

[0226] The first capacitor electrode (CAE1) can be electrically connected to the gate electrode (G1) of the first transistor (T1).

[0227] Since the power connection transistor (TPC) is a P-type MOSFET identical to the fifth transistor (T5), redundant explanations are omitted below.

[0228] Each of the first transistor (T1) and the second transistor (T2) may include a channel (CH1, CH2) disposed in the second semiconductor layer (SEL2), a first electrode (E11, E12) disposed in the second semiconductor layer (SEL2) and connected to one side of the channel (CH1, CH2), a second electrode (E21, E22) disposed in the second semiconductor layer (SEL2) and connected to the other side of the channel (CH1, CH2), and a gate electrode (G1, G2) disposed in the third gate conductive layer (GCDL3) and overlapping with the channel (CH1, CH2).

[0229] The second semiconductor layer (SEL2) may include an oxide semiconductor material.

[0230] The first gate conductive layer (GCDL1) may include a second capacitor electrode (CAE2) that overlaps with the first capacitor electrode (CAE1).

[0231] The second capacitor electrode (CAE2) can be electrically connected to the second electrode (E21) of the first transistor (T1).

[0232] Accordingly, a first capacitor (C1) can be formed by a first capacitor electrode (CAE1) and a second capacitor electrode (CAE2) that overlap each other in the third direction (DR3), and a first gate insulating layer (122) interposed between them.

[0233] The second gate conductive layer (GCDL2) may include a third capacitor electrode (CAE3) that overlaps with the second capacitor electrode (CAE2).

[0234] The third capacitor electrode (CAE3) can be electrically connected to the first power wiring (VDL in Fig. 7).

[0235] Accordingly, a second capacitor (C2) can be formed by a second capacitor electrode (CAE2) and a third capacitor electrode (CAE3) that overlap each other in the third direction (DR3), and a second gate insulating layer (123) interposed between them.

[0236] The upper surface of the channel (CH1) of the first transistor (T1) may face the gate electrode (G1).

[0237] And, the lower surface of the channel (CH1) of the first transistor (T1) can face the second capacitor electrode (CAE2).

[0238] That is, the second capacitor electrode (CAE2) may be the gate additional electrode of the first transistor (T1).

[0239] The first source drain conductive layer (SDCDL1) may include a first node connection electrode (NCE1), a second node connection electrode (NCE2), a data connection electrode (DCE), and a first anode connection electrode (ANCE1).

[0240] The second source drain conductive layer (SDCDL2) may include a second anode connection electrode (ANCE2), a data line (DL), and a constant voltage auxiliary line (CVAL).

[0241] According to one embodiment, a constant voltage auxiliary wiring (CVAL) can transmit one of a first power source (ELVDD in FIG. 7), a reference voltage (VREF in FIG. 7), and a first initialization voltage (VAINT in FIG. 7).

[0242] The first electrode (E12) of the second transistor (T2) can be electrically connected to the data wiring (DL) through the data connection electrode (DCE).

[0243] The data connection electrode (DCE) is placed on the first source drain conductive layer (SDCDL1) and can be electrically connected to the first electrode (E12) of the second transistor (T2) through the first data connection hole (DCH1).

[0244] The first data connection hole (DCH1) can penetrate the second interlayer insulation layer (126) and the third gate insulation layer (125).

[0245] The data wiring (DL) is placed in the second source drain conductive layer (SDCDL2) and can be electrically connected to the data connection electrode (DCE) through the second data connection hole (DCH2) penetrating the first flattening layer (127).

[0246] The second electrode (E22) of the second transistor (T2) can be electrically connected to the gate electrode (G1) and the first capacitor electrode (CAE1) of the first transistor (T1) through the first node connection electrode (NCE1).

[0247] The first node connecting electrode (NCE1) can be electrically connected to the gate electrode (G1) of the first transistor (T1) through the first node connecting hole (NCH1), electrically connected to the first capacitor electrode (CAE1) through the second node connecting hole (NCH2), and electrically connected to the second electrode (E22) of the second transistor (T2) through the third node connecting hole (NCH3).

[0248] The second electrode (E21) of the first transistor (T1) can be electrically connected to the first electrode (E15) and the second capacitor electrode (CAE2) of the fifth transistor (T5) through the second node connection electrode (NCE2).

[0249] The second node connecting electrode (NCE2) can be electrically connected to the second electrode (E21) of the first transistor (T1) through the fourth node connecting hole (NCH4), electrically connected to the second capacitor electrode (CAE2) through the fifth node connecting hole (NCH5), and electrically connected to the first electrode (E15) of the fifth transistor (T5) through the sixth node connecting hole (NCH6).

[0250] The second electrode (E25) of the fifth transistor (T5) can be electrically connected to the anode electrode (131) of the light-emitting element (LE) through the first anode connection electrode (ANCE1) and the second anode connection electrode (ANCE2).

[0251] The first anode connection electrode (ANCE1) can be electrically connected to the second electrode (E25) of the fifth transistor (T5) through the first anode connection hole (ANCH1).

[0252] The first anode connection hole (ANCH1) can penetrate the second interlayer insulating layer (126), the third gate insulating layer (125), the first interlayer insulating layer (124), the second gate insulating layer (123), and the first gate insulating layer (122).

[0253] The second anode connecting electrode (ANCE2) can be electrically connected to the first anode connecting electrode (ANCE1) through the second anode connecting hole (ANCH2) penetrating the first flattening layer (127).

[0254] The anode electrode (131) is placed on the second flattening layer (128) and can be electrically connected to the second anode connecting electrode (ANCE2) through the third anode connecting hole (ANCH3).

[0255] The element layer (130) is disposed on the circuit layer (120) and may include light-emitting elements (LE) corresponding to each of the light-emitting regions (EA).

[0256] Each of the light-emitting elements (LE) may include an anode electrode (131) and a cathode electrode (134) facing each other, and a light-emitting layer (133) disposed between them.

[0257] That is, the device layer (130) may include an anode electrode (131) disposed in light-emitting regions (EA), a pixel defining layer (132) disposed in a non-light-emitting region (NEA) and covering the edge of the anode electrode (131), a light-emitting layer (133) disposed on the anode electrode (131), and a cathode electrode (134) disposed on the light-emitting layer (133) and the pixel defining layer (132).

[0258] The pixel definition layer (132) may include a first pixel definition layer (1321) disposed on the second flattening layer (128), a second pixel definition layer (1322) disposed on the first pixel definition layer (1321), and a spacer layer (1323) disposed on a part of the second pixel definition layer (1322).

[0259] For example, the first pixel definition layer (1321) may include a light-absorbing insulating material that absorbs light or a light-blocking insulating material that blocks light.

[0260] Alternatively, each of the light-emitting elements (LE) may further include a first common layer disposed between the anode electrode (131) and the light-emitting layer (133), and a second common layer disposed between the light-emitting layer (133) and the cathode electrode (134).

[0261] The anode electrode (131) is placed in the light-emitting region (EA) and can be electrically connected to the light-emitting pixel driver (EPD). This anode electrode (131) may be referred to as a pixel electrode.

[0262] The light-emitting layer (133) may include an organic light-emitting material that converts electron-hole pairs into light.

[0263] A cathode electrode (134) may be placed in a display area (DA in FIG. 3) including light-emitting regions (EA). The cathode electrode (134) may be part of a second power wiring (VSL in FIG. 7) that carries a second power source (ELVSS in FIG. 7) or may be electrically connected to the second power wiring (VSL). Such a cathode electrode (134) may be referred to as a common electrode.

[0264] The sealing layer (140) is placed on the circuit layer (120) and can cover the element layer (130).

[0265] For example, the sealing layer (140) may include a first sealing layer disposed on the element layer (130) and made of an inorganic insulating material, a second sealing layer disposed on the first sealing layer and overlapping with the element layer (130) and made of an organic insulating material, and a third sealing layer disposed on the first sealing layer, covering the second sealing layer and made of an inorganic insulating material.

[0266] FIG. 9 is a schematic diagram showing some light-emitting pixel driving units according to one embodiment of FIG. 5.

[0267] Referring to FIG. 9, the light-emitting pixel driving units (EPDs) of the circuit layer (120) of the display device (100) according to one embodiment may be arranged in a first direction (DR1) and a second direction (DR2).

[0268] The light-emitting pixel drivers (EPDs) may include a first light-emitting pixel driver (EPD1), a second light-emitting pixel driver (EPD2), a third light-emitting pixel driver (EPD3), a fourth light-emitting pixel driver (EPD4), a fifth light-emitting pixel driver (EPD5), a sixth light-emitting pixel driver (EPD6), a seventh light-emitting pixel driver (EPD7), and an eighth light-emitting pixel driver (EPD8) arranged in parallel with each other in a first direction (DR1).

[0269] As shown in FIG. 5, the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to light-emitting elements (LEs in FIG. 7 and FIG. 8) arranged in eight light-emitting regions (EA1-EA8) adjacent to the first direction (DR1), the second direction (DR2), and the diagonal direction (DR5).

[0270] As shown in FIG. 9, the circuit layer (120) may include wiring in the first direction (DR1) that transmits different signals or voltages and extends in the first direction (DR1).

[0271] The wiring of the first direction (DR1) may include a scan write wiring (GWL), a reset control wiring (GRL), an initialization control wiring (GIL), a first light emission control wiring (ECL1), a second light emission control wiring (ECL2), a reference voltage wiring (VRL), a first power wiring (VDL), a first initialization voltage wiring (VAIL1), and a second initialization voltage wiring (VAIL2).

[0272] According to one embodiment, the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) may intersect with two scan writing wires (GWLA, GWLB) that transmit different scan writing signals (GW in FIG. 7), one reset control wire (GRL) that transmits a reset control signal (GR in FIG. 7), one initialization control wire (GIL) that transmits an initialization control signal (GI in FIG. 7), one first light-emitting control wire (ECL1) that transmits a first light-emitting control signal (EC1 in FIG. 7), and one second light-emitting control wire (ECL2) that transmits a second light-emitting control signal (EC2 in FIG. 7).

[0273] Each of the two scan write wires (GWLA, GWLB), one reset control wire (GRL), one initialization control wire (GIL), one first light emission control wire (ECL1), and one second light emission control wire (ECL2) can be extended in a first direction (DR1).

[0274] The first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), and the fourth light-emitting pixel driver (EPD4) can be electrically connected to four light-emitting elements (LE) placed in the first light-emitting region (EA1), the second light-emitting region (EA2), the third light-emitting region (EA3), and the fourth light-emitting region (EA4).

[0275] In addition, the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to four light-emitting elements (LE) placed in the fifth light-emitting region (EA5), the sixth light-emitting region (EA6), the seventh light-emitting region (EA7), and the eighth light-emitting region (EA8) adjacent to the first light-emitting region (EA1), the second light-emitting region (EA2), the third light-emitting region (EA3), and the fourth light-emitting region (EA4) in the second direction (DR2).

[0276] Accordingly, the gate electrode of the second transistor (T2) of each of the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), and the fourth light-emitting pixel driver (EPD4) can be electrically connected to one of the two scan write wires (GWLA, GWLB) scan write wire (GWLA).

[0277] The gate electrode of the second transistor (T2) of each of the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to the other scan write wire (GWLB) among the two scan write wires (GWLA, GWLB).

[0278] The gate electrode of the third transistor (T3) of each of the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to a single reset control wire (GRL).

[0279] The gate electrode of the fourth transistor (T4) of each of the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to a single initialization control wire (GIL).

[0280] The gate electrodes of four power connection transistors (TPCs) electrically connected to two light-emitting pixel drivers adjacent in the first direction (DR1) among the first light-emitting pixel driver (EPD1), second light-emitting pixel driver (EPD2), third light-emitting pixel driver (EPD3), fourth light-emitting pixel driver (EPD4), fifth light-emitting pixel driver (EPD5), sixth light-emitting pixel driver (EPD6), seventh light-emitting pixel driver (EPD7) and eighth light-emitting pixel driver (EPD8) can be electrically connected to one first light-emitting control wire (ECL1).

[0281] The gate electrode of the fifth transistor (T5) of each of the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to one second light-emitting control wire (ECL2).

[0282] According to one embodiment, the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) may intersect with one first power line (VDL) that transmits the first power supply (ELVDD), one reference voltage line (VRL) that transmits the reference voltage (VREF), and one initialization voltage line (VAIL) that transmits the initialization voltage (VAINT in FIG. 7).

[0283] In this case, the light-emitting elements (LE) placed in the light-emitting regions (EA in Fig. 5) of the display area (DA in Fig. 3 and 4) can be initialized with an initial voltage by the initial voltage wiring (VAIL).

[0284] The gate electrode of the first transistor (T1) of each of the light-emitting pixel driving units (EPDs of FIG. 7 and 8) of the circuit layer (120) can be initialized to a reference voltage (VREF).

[0285] Alternatively, as illustrated in FIG. 9, according to one embodiment, the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) may be crossed with one first power line (VDL) that transmits a first power supply (ELVDD), one reference voltage line (VRL) that transmits a reference voltage (VREF), one first initialization voltage line (VAIL1) that transmits a first initialization voltage, and one second initialization voltage line (VAIL2) that transmits a second initialization voltage different from the first initialization voltage.

[0286] Each of the first power line (VDL), the reference voltage line (VRL), the first initialization voltage line (VAIL1), and the second initialization voltage line (VAIL2) can be extended in the first direction (DR1).

[0287] The first electrode of the third transistor (T3) of each of the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to a single reference voltage line (VRL).

[0288] According to one embodiment, a light-emitting element (LE) placed in a first color light-emitting region (R_EA in FIG. 5) is initialized with a first initialization voltage by a first initialization voltage wiring (VAIL1), and light-emitting elements (LE) placed in a second color light-emitting region (G_EA in FIG. 5) and a third color light-emitting region (B_EA in FIG. 5) can be initialized with a second initialization voltage by a second initialization voltage wiring (VAIL2).

[0289] Among the eight light-emitting regions (EA1-EA8), the first light-emitting region (EA1) and the seventh light-emitting region (EA7) may be included in the first color light-emitting region (R_EA).

[0290] In this case, the first electrode of the fourth transistor (T4) of each of the first light-emitting pixel driver (EPD1) and the seventh light-emitting pixel driver (EPD7) can be electrically connected to one first initialization voltage wire (VAIL1).

[0291] The first electrode of the fourth transistor (T4) of each of the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to one second initialization voltage wire (VAIL2).

[0292] The first electrode and the second capacitor (C2) of four power connection transistors (TPCs) electrically connected to two light-emitting pixel drivers adjacent in the first direction (DR1) among the first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) can be electrically connected to one first power line (VDL).

[0293] The first light-emitting pixel driver (EPD1), the second light-emitting pixel driver (EPD2), the third light-emitting pixel driver (EPD3), the fourth light-emitting pixel driver (EPD4), the fifth light-emitting pixel driver (EPD5), the sixth light-emitting pixel driver (EPD6), the seventh light-emitting pixel driver (EPD7), and the eighth light-emitting pixel driver (EPD8) are arranged only in the first direction (DR1), rather than in the first direction (DR1) and the second direction (DR2).

[0294] Accordingly, the wiring of the first direction (DR1) required to drive the light-emitting elements (LEs in FIG. 7 and FIG. 8) arranged in eight light-emitting regions (EA1-EA8) adjacent to the first direction (DR1), second direction (DR2) and diagonal direction (DR5) may include one reset control wiring (GRL), one initialization control wiring (GIL), one first light-emitting control wiring (ECL1) and one second light-emitting control wiring (ECL2).

[0295] And, the wiring of the first direction (DR1) required for driving light-emitting elements (LEs in FIG. 7 and FIG. 8) arranged in eight light-emitting regions (EA1-EA8) adjacent to the first direction (DR1), second direction (DR2) and diagonal direction (DR5) may further include one first power wiring (VDL), one reference voltage wiring (VRL), one first initialization voltage wiring (VAIL1) and one second initialization voltage wiring (VAIL2).

[0296] Thus, at least some of the wiring in the first direction (DR1) required to drive the light-emitting elements (LEs in FIG. 7 and FIG. 8) arranged in eight light-emitting regions (EA1-EA8) adjacent to the first direction (DR1), second direction (DR2) and diagonal direction (DR5) can be reduced by half, which is advantageous for increasing the resolution of the display device (100).

[0297] According to one embodiment, the circuit layer (120) may include data wires (DL) that extend in a second direction (DR2) and transmit a data signal (Vdata of FIG. 7).

[0298] Data wires (DL) can be arranged in a two-to-two adjacent configuration in the first direction (DR1).

[0299] One of the two adjacent data lines (DLA, DLB) in the first direction (DR1) can transmit data signals (Vdata) for driving a light-emitting element (LE) placed in a light-emitting region of the first color (R_EA in FIG. 5) and a light-emitting element (LE) placed in a light-emitting region of the third color (B_EA in FIG. 5).

[0300] And, among the two adjacent data lines (DLA, DLB) in the first direction (DR1), the other data line (DLB) can transmit data signals (Vdata) to drive a light-emitting element (LE) placed in the light-emitting region of the second color (G_EA in FIG. 5).

[0301] As shown in the example of FIG. 5, a first light-emitting pixel driver (EPD1) may be electrically connected to a light-emitting element (LE) placed in a light-emitting region of a first color (R_EA in FIG. 5), and a third light-emitting pixel driver (EPD3) may be electrically connected to a light-emitting element (LE) placed in a light-emitting region of a third color (B_EA in FIG. 5). Additionally, a second light-emitting pixel driver (EPD2) and a fourth light-emitting pixel driver (EPD4) may each be electrically connected to a light-emitting element (LE) placed in a light-emitting region of a second color (G_EA in FIG. 5).

[0302] In this case, one of the two adjacent data lines (DLA, DLB) in the first direction (DR1) can be electrically connected to the first light-emitting pixel driver (EPD1) and the third light-emitting pixel driver (EPD3).

[0303] One of the first light-emitting pixel driver (EPD1) and the third light-emitting pixel driver (EPD3) can be crossed with one data line (DLA).

[0304] The other of the first light-emitting pixel driver (EPD1) and the third light-emitting pixel driver (EPD3) can be electrically connected to one data line (DLA) through a first data extension line (DEXL1) extending in a first direction (DR1).

[0305] And, among the two adjacent data lines (DLA, DLB) in the first direction (DR1), the other data line (DLB) can be electrically connected to the second light-emitting pixel driver (EPD2) and the fourth light-emitting pixel driver (EPD4).

[0306] One of the second light-emitting pixel driver (EPD2) and the fourth light-emitting pixel driver (EPD4) can be crossed with another data line (DLB).

[0307] One of the second light-emitting pixel driver (EPD2) and the other of the fourth light-emitting pixel driver (EPD4) can be electrically connected to another data line (DLB) through a second data extension line (DEXL2) that extends in the first direction (DR1).

[0308] For example, in the first direction (DR1), one of the two mutually adjacent data lines (DLA, DLB) may intersect with the first light-emitting pixel driver (EPD1), and the other data line (DLB) may intersect with the second light-emitting pixel driver (EPD2).

[0309] As another example, in the first direction (DR1), one of the two mutually adjacent data lines (DLA, DLB) may intersect with the third light-emitting pixel driver (EPD3), and the other data line (DLB) may intersect with the second light-emitting pixel driver (EPD2). In this case, the first light-emitting pixel driver (EPD1) may be electrically connected to one of the data lines (DLA) through the first data extension line (DEXL1).

[0310] As another example, in the first direction (DR1), one of the two mutually adjacent data lines (DLA, DLB) may intersect with the third light-emitting pixel driver (EPD3), and the other data line (DLB) may intersect with the fourth light-emitting pixel driver (EPD4). In this case, the first light-emitting pixel driver (EPD1) may be electrically connected to one data line (DLA) through the first data extension line (DEXL1), and the second light-emitting pixel driver (EPD2) may be electrically connected to the other data line (DLB) through the second data extension line (DEXL2).

[0311] As shown in the example of FIG. 5, the fifth light-emitting pixel driver (EPD5) may be electrically connected to a light-emitting element (LE) placed in a light-emitting region of the third color (B_EA in FIG. 5), and the seventh light-emitting pixel driver (EPD7) may be electrically connected to a light-emitting element (LE) placed in a light-emitting region of the first color (R_EA in FIG. 5). Additionally, the sixth light-emitting pixel driver (EPD6) and the eighth light-emitting pixel driver (EPD8) may each be electrically connected to a light-emitting element (LE) placed in a light-emitting region of the second color (G_EA in FIG. 5).

[0312] In this case, one of the two adjacent data lines (DLA, DLB) in the first direction (DR1) can be electrically connected to the fifth light-emitting pixel driver (EPD5) and the seventh light-emitting pixel driver (EPD7).

[0313] One of the fifth light-emitting pixel driver (EPD5) and the seventh light-emitting pixel driver (EPD7) can be crossed with one data line (DLA).

[0314] The other of the fifth light-emitting pixel driver (EPD5) and the seventh light-emitting pixel driver (EPD7) can be electrically connected to one data line (DLA) through a first data extension line (DEXL1) extending in a first direction (DR1).

[0315] And, among the two adjacent data lines (DLA, DLB) in the first direction (DR1), the other data line (DLB) can be electrically connected to the sixth light-emitting pixel driver (EPD6) and the eighth light-emitting pixel driver (EPD8).

[0316] One of the 6th light-emitting pixel driver (EPD6) and the 8th light-emitting pixel driver (EPD8) can be crossed with another data line (DLB).

[0317] One of the 6th light-emitting pixel driver (EPD6) and the other of the 8th light-emitting pixel driver (EPD8) can be electrically connected to another data line (DLB) through a second data extension line (DEXL2) that extends in the first direction (DR1).

[0318] In this way, even if eight light-emitting pixel drivers (EPD1-EPD8) electrically connected to light-emitting elements (LEs in FIG. 7 and 8) arranged in eight light-emitting regions (EA1-EA8) adjacent to the first direction (DR1), second direction (DR2), and diagonal direction (DR5) are arranged only in the first direction (DR1), the number of data lines (DL) may not be doubled.

[0319] This makes it advantageous to increase the resolution of the display device (100).

[0320] FIG. 10 is a plan view showing the substrate of FIG. 4 according to one embodiment.

[0321] Referring to FIG. 10, a substrate (110) of a display device (100) according to one embodiment includes a main area (MA) corresponding to a display surface and a sub area (SBA) protruding from a part of one side of the main area (MA).

[0322] The main area (MA) includes a display area (DA) positioned in most of the center and a non-display area (NDA) positioned at the edges and surrounding the display area (DA).

[0323] The display area (DA) may include a bypass area (BYA) positioned on one side adjacent to the sub-area (SBA), and a general area (GA) positioned in the remaining area excluding the bypass area (BYA).

[0324] The bypass area (BYA) may include a bypass middle area (BMA) positioned at the center of the first direction (DR1), a first bypass side area (BSA1) parallel to the bypass middle area (BMA) in the first direction (DR1) and adjacent to the non-display area (NDA), and a second bypass side area (BSA2) positioned between the bypass middle area (BMA) and the first bypass side area (BSA1).

[0325] The first bypass side region (BSA1) may be positioned adjacent to the bent edge of the substrate (110) relative to the bypass middle region (BMA) and the second bypass side region (BSA2).

[0326] The first bypass side area (BSA1) and the second bypass side area (BSA2) may be positioned between each of the two sides of the first direction (DR1) of the bypass middle area (BMA) and the non-display area (NDA).

[0327] The general area (GA) may include a general middle area (GMA) connected to the bypass middle area (BMA) of the bypass area (BYA) in the second direction (DR2), a first general side area (GSA1) connected to the first bypass side area (BSA1) of the bypass area (BYA) in the second direction (DR2), and a second general side area (GSA2) connected to the second bypass side area (BSA2) of the bypass area (BYA) in the second direction (DR2).

[0328] The non-display area (NDA) may include a gate driving circuit area (GDRA) where the gate driving circuit (GTDR of FIG. 6) is placed.

[0329] The gate driving circuit area (GDRA) may face one side of the display area (DA) extending in the second direction (DR2). However, this is merely an example, and the gate driving circuit area (GDRA) may be divided and placed in the display area (DA) rather than the non-display area (NDA).

[0330] The gate driving circuit (GTDR) of the gate driving circuit region (GDRA) can transmit gate signals to the gate wires.

[0331] The gate wires may include a scan write wire (GWL in FIG. 7), a reset control wire (GRL in FIG. 7), an initialization control wire (GBL in FIG. 7), a first light emission control wire (ECL1 in FIG. 7), and a second light emission control wire (ECL2 in FIG. 7).

[0332] A sub-region (SBA) may include a bending region (BA) that is deformed into a bending shape, a first sub-region (SB1) positioned between one side of the bending region (BA) and the main region (MA), and a second sub-region (SB2) connected to the other side of the bending region (BA).

[0333] When the bending region (BA) is deformed into a bending shape, the second sub-region (SB2) is placed below the substrate (110) and overlaps with the main region (MA).

[0334] The display driving circuit (200) can be placed in the second sub-region (SB2).

[0335] Signal pads (SPDs) bonded to the circuit board (300 in FIG. 3) can be arranged on one edge of the second sub-region (SB2).

[0336] FIG. 11 is a schematic diagram showing part C of FIG. 10. FIG. 12 is a schematic diagram showing part D of FIG. 10. FIG. 13 is a cross-sectional view showing E-E' of FIG. 11.

[0337] Referring to FIGS. 11 and 12, a circuit layer (120) of a display device (100) according to one embodiment may include light-emitting pixel drivers (EPDs) arranged in parallel in a first direction (DR1) and a second direction (DR2), data lines (DL) extending in the second direction (DR2) and transmitting a data signal (Vdata of FIG. 7) to the light-emitting pixel drivers (EPDs), first auxiliary lines (ASL1) extending in the first direction (DR1), and second auxiliary lines (ASL2) extending in the second direction (DR2).

[0338] According to one embodiment, some of the light-emitting pixel drivers (EPDs) may intersect with data lines (DL), and the remaining parts may intersect with second auxiliary lines (ASL2).

[0339] In this way, each of the light-emitting pixel drivers (EPDs) does not cross both the data line (DL) and the second auxiliary line (ASL2), so it can be advantageous for increasing the resolution of the display device (100).

[0340] According to one embodiment, the circuit layer (120) may further include data supply lines (DSPL) that are placed in a non-display area (NDA) and electrically connected between the display driving circuit (200) and the data lines (DL).

[0341] Data supply lines (DSPLs) can be extended to a bypass middle area (BMA) and a second bypass side area (BSA2).

[0342] Data supply lines (DSPLs) may include a first data supply line (DSPL1) that transmits a data signal of a first data line (DL1), and a second data supply line (DSPL2) that transmits a data signal of a second data line (DL2).

[0343] Data lines (DL) may include a first data line (DL1) placed in a first bypass side area (BSA1) adjacent to a non-display area (NDA) in a first direction (DR1), and a second data line (DL2) placed in a second bypass side area (BSA2) between the first bypass side area (BSA1) and a bypass middle area (BMA).

[0344] The first auxiliary wiring (ASL1) may include a first bypass auxiliary wiring (BASL1) electrically connected to the first data wiring (DL1).

[0345] The second auxiliary wiring (ASL2) may include a second bypass auxiliary wiring (BASL2) that is electrically connected to the first bypass auxiliary wiring (BASL1).

[0346] The first bypass auxiliary wiring (BASL1) can electrically connect the first data wiring (DL1) and the second bypass auxiliary wiring (BASL2).

[0347] The second bypass auxiliary wiring (BASL2) can electrically connect the first bypass auxiliary wiring (BASL1) and the first data supply wiring (DSPL1).

[0348] That is, the first data supply line (DSPL1) extends to the second bypass auxiliary line (BASL2) of the second bypass side area (BSA2) and can be electrically connected to the first data line (DL1) through the second bypass auxiliary line (BASL2) and the first bypass auxiliary line (BASL1).

[0349] On the other hand, the second data supply line (DSPL2) can be extended to the second bypass side area (BSA2) and directly electrically connected to the second data line (DL2).

[0350] In this way, the first data supply line (DSPL1) is extended to the second bypass auxiliary line (BASL2) of the second bypass side area (BSA2) rather than to the first data line (DL1) of the first bypass side area (BSA1), so the extension length of the first data supply line (DSPL1) can be shortened. As a result, the width of the area required for the placement of the data supply lines (DSPL) can be reduced, and thus the width of the non-display area (NDA) can be reduced.

[0351] Additionally, since the data supply lines (DSPL) are not placed in a portion of the non-display area (NDA) adjacent to the folded corner of the substrate (110), the width of the non-display area (NDA) can be further reduced.

[0352] The data lines (DL) may further include a third data line (DL3) placed in the bypass middle area (BMA). And, the data supply lines (DSPL) may further include a third data supply line (DSPL3) that transmits the data signal of the third data line (DL3).

[0353] The third data supply line (DSPL3) extends to the bypass middle area (BMA) and can be directly electrically connected to the third data line (DL3).

[0354] The first auxiliary wiring (ASL1) may further include the first transmission auxiliary wiring (TASL1), which is the remainder excluding the first bypass auxiliary wiring (BASL1).

[0355] The second auxiliary lines (ASL2) may further include the second transmission auxiliary lines (TASL2), which are the remainder excluding the second bypass auxiliary lines (BASL2).

[0356] The first bypass auxiliary wiring (BASL1) can be placed between the first data wiring (DL1) and the second bypass auxiliary wiring (BASL2).

[0357] The second bypass auxiliary wiring (BASL2) can be placed between the first data supply wiring (DSPL1) and the first bypass auxiliary wiring (BASL1) of the non-display area (NDA).

[0358] In this way, the first bypass auxiliary wiring (BASL1) and the second bypass auxiliary wiring (BASL2) are placed exclusively in the bypass area (BYA), and the ends of the first bypass auxiliary wiring (BASL1) and the end of the second bypass auxiliary wiring (BASL2) are placed in the display area (DA), so the visibility of the first bypass auxiliary wiring (BASL1) and the second bypass auxiliary wiring (BASL2) can be increased.

[0359] However, according to one embodiment, the first auxiliary wiring (ASL1) further includes first transmission auxiliary wiring (TASL1) in addition to the first bypass auxiliary wiring (BASL1), and the second auxiliary wiring (ASL2) further includes second transmission auxiliary wiring (TASL2) in addition to the second bypass auxiliary wiring (BASL2).

[0360] Accordingly, the visibility of the first bypass auxiliary wiring (BASL1) and the second bypass auxiliary wiring (BASL2) may be reduced.

[0361] Two of the first transmission auxiliary wirings (TASL1) can be extended into the non-marked area (NDA) at both ends of the first bypass auxiliary wiring (BASL1).

[0362] One of the second transmission auxiliary wirings (TASL2) may extend from one end of the second bypass auxiliary wiring (BASL2) to the non-marked area (NDA) in a direction away from the sub-area (SBA).

[0363] Since the second bypass auxiliary wiring (BASL2) is placed only in the second bypass side area (BSA2), the first data wiring (DL1) of the first bypass side area (BSA1) and the third data wiring (DL3) of the bypass middle area (BMA) can each be adjacent to the second transmission auxiliary wiring (TASL2) overall.

[0364] According to one embodiment, each of the first transmission auxiliary wiring (TASL1) and the second transmission auxiliary wiring (TASL2) may be electrically connected to one of the following: a first power wiring (VDL in FIG. 7) that transmits a first power supply (ELVDD in FIG. 7), a second power wiring (VSL in FIG. 7) that transmits a second power supply (ELVSS in FIG. 7), a first initialization voltage wiring (VAIL1 in FIG. 9) that transmits a first initialization voltage, a second initialization voltage wiring (VAIL2 in FIG. 9) that transmits a second initialization voltage, and a reference voltage wiring (VRL in FIG. 7) that transmits a reference voltage (VREF in FIG. 7). By doing so, the resistance of the path through which the power supply or constant voltage is transmitted can be lowered by the first transmission auxiliary wiring (TASL1) and the second transmission auxiliary wiring (TASL2), so that the voltage level of the power supply or constant voltage can be maintained more stably. Accordingly, the display quality of the display device (100) can be improved.

[0365] According to one embodiment, the circuit layer (120) may further include a first power supply line (VDSPL) and a second power supply line (VSSPL) that are placed in a non-display area (NDA) and extend to a sub-area (SBA).

[0366] The first power supply wire (VDSPL) transmits the first power (ELVDD in FIG. 7), and the second power supply wire (VSSPL) transmits the second power (ELVSS in FIG. 7).

[0367] The first power supply wiring (VDSPL) can be electrically connected to the first power pad for transmitting the first power (ELVDD of FIG. 7) among the signal pads (SPD of FIG. 9) placed in the second sub-region (SB2).

[0368] The second power supply wiring (VSSPL in FIG. 7) can be electrically connected to the second power pad for transmitting the second power (ELVSS in FIG. 7) among the signal pads (SPD in FIG. 9) placed in the second sub-region (SB2).

[0369] For example, at least some of the first transmission auxiliary wiring (TASL1) may be electrically connected to the second power supply wiring (VSSPL).

[0370] And, at least some of the second transmission auxiliary wiring (TASL2) can be electrically connected to at least some of the first transmission auxiliary wiring (TASL1) and the second power supply wiring (VSSPL).

[0371] As shown in Fig. 11, in the general area (GA), the first transmission auxiliary wiring (TASL1) among the first auxiliary wirings (ASL1) and the second transmission auxiliary wiring (TASL2) among the second auxiliary wirings (ASL2) may be arranged.

[0372] Each of the first transmission auxiliary wirings (TASL1) can be electrically connected to at least some of the second transmission auxiliary wirings (TASL2).

[0373] As illustrated in FIGS. 11 and 12, according to one embodiment, the first auxiliary wiring (ASL1) may be adjacent to each other in two directions (DR2).

[0374] Among the first auxiliary wirings (ASL1), two first auxiliary wirings (ASL1) adjacent in the second direction (DR2) can be positioned adjacent to the boundary between two light-emitting pixel drivers (EPDs) adjacent in the second direction (DR2).

[0375] That is, according to one embodiment, the first auxiliary wiring (ASL1) is not arranged one by one at equal intervals, but is arranged in pairs, so the width of the area that must be secured for the arrangement of the first auxiliary wiring (ASL1) can be reduced.

[0376] As shown in FIG. 13, according to one embodiment, the first auxiliary wiring (ASL1) may be placed on the first source-drain conductive layer (SDCDL1 in FIG. 8) on the second interlayer insulating layer (126), and the data wiring (DL) and the second auxiliary wiring (ASL2) may be placed on the second source-drain conductive layer (SDCDL2 in FIG. 8) on the first flattening layer (127) covering the first source-drain conductive layer (SDCDL1 in FIG. 8).

[0377] The first bypass auxiliary wiring (BASL1) can be electrically connected to the first data wiring (DL1) through a connection hole and can be electrically connected to the second bypass auxiliary wiring (BASL2) through a connection hole.

[0378] FIGS. 14, FIGS. 15, FIGS. 16, FIGS. 17, and FIGS. 18 are each plan views showing different parts of the light-emitting pixel driving units of FIG. 9 according to one embodiment.

[0379] As shown in FIG. 14, according to one embodiment, one of two mutually adjacent data lines (DLA, DLB) may be intersected by a first light-emitting pixel driver (EPD1) and the other data line (DLB) may be intersected by a second light-emitting pixel driver (EPD2).

[0380] The data connection electrode (DCE) of the first light-emitting pixel driver (EPD1) may overlap with a protrusion extending from one data line (DLA) in the third direction (DR3) and one side of the first data extension line (DEXL1).

[0381] The data connection electrode (DCE) of the first light-emitting pixel driver (EPD1) is electrically connected to one data wire (DLA) through the second data connection hole (DCH2) and can be electrically connected to the first electrode of the second transistor (T2 in FIG. 9) through the first data connection hole (DCH1).

[0382] The data connection electrode (DCE) of the first light-emitting pixel driver (EPD1) can be electrically connected to the first data extension wiring (DEXL1) through the data connection auxiliary hole (DCAH).

[0383] The first data extension wiring (DEXL1) extends in the first direction (DR1) and can intersect with the second light-emitting pixel driver (EPD2).

[0384] And, the other side of the first data extension wiring (DEXL1) can overlap with the data connection electrode (DCE) of the third light-emitting pixel driver (EPD3) in the third direction (DR3).

[0385] The data connection electrode (DCE) of the third light-emitting pixel driver (EPD3) can be electrically connected to the first data extension wiring (DEXL1) through the data connection auxiliary hole (DCAH).

[0386] Thus, the first light-emitting pixel driver (EPD1) and the third light-emitting pixel driver (EPD3) can be electrically connected to a single data line (DLA).

[0387] The data connection electrode (DCE) of the second light-emitting pixel driver (EPD2) may overlap with a protrusion extending from another data wiring (DLB) in the third direction (DR3) and one side of the second data extension wiring (DEXL2).

[0388] The data connection electrode (DCE) of the second light-emitting pixel driver (EPD2) can be electrically connected to another data wiring (DLB) through the second data connection hole (DCH2) and electrically connected to the first electrode of the second transistor (T2 in FIG. 9) through the first data connection hole (DCH1).

[0389] The data connection electrode (DCE) of the second light-emitting pixel driver (EPD2) can be electrically connected to the second data extension wiring (DEXL2) through the data connection auxiliary hole (DCAH).

[0390] The second data extension wiring (DEXL2) extends in the first direction (DR1) and can intersect with the third light-emitting pixel driver (EPD3).

[0391] And, the other side of the second data extension wiring (DEXL2) can overlap with the data connection electrode (DCE) of the fourth light-emitting pixel driver (EPD4) in the third direction (DR3).

[0392] The data connection electrode (DCE) of the fourth light-emitting pixel driver (EPD4) can be electrically connected to the second data extension wiring (DEXL2) through the data connection auxiliary hole (DCAH).

[0393] Thus, the second light-emitting pixel driver (EPD2) and the fourth light-emitting pixel driver (EPD4) can be electrically connected to another data line (DLB).

[0394] According to one embodiment, the first gate conductive layer (GCDL1) may include a second initialization voltage wiring (VAIL2) and a second data extension wiring (DEXL2).

[0395] The second gate conductive layer (GCDL2) may include a first data extension wire (DEXL1).

[0396] The first source drain conductive layer (SDCDL1) may include a scan write wire (GWLB), a first auxiliary wire (ASL1), and a data connection electrode (DCE).

[0397] The second source drain conductive layer (SDCDL2) may include a data wire (DL), a second auxiliary wire (ASL2), a constant voltage auxiliary wire (CVAL), and a second anode connection electrode (ANCE2).

[0398] As shown in FIG. 15, according to one embodiment, the first transistor (T1) may include a channel (CH1) disposed in a second semiconductor layer (SEL2), a first electrode (E11) and a second electrode (E21), and a gate electrode (G1) disposed in a third gate conductive layer (GCDL3).

[0399] The first electrode (E11) and channel (CH1) of the first transistor (T1) of the first light-emitting pixel driver (EPD1) can be symmetrical to the first electrode (E11) and channel (CH1) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) with respect to the boundary between the first light-emitting pixel driver (EPD1) and the second light-emitting pixel driver (EPD2).

[0400] According to one embodiment, the first electrode (E11) of the first transistor (T1) of the first light-emitting pixel driver (EPD1) and the first electrode (E11) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) can be interconnected.

[0401] According to one embodiment, the second electrode (E21) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) may be extended to one side of the second direction (DR2) (upper side in FIG. 15), and the second electrode (E21) of the first transistor (T1) of the third light-emitting pixel driver (EPD3) may be extended to the other side of the second direction (DR2) (lower side in FIG. 15).

[0402] For example, the second electrode (E21) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) can be point-symmetric with respect to the second electrode (E21) of the first transistor (T1) of the third light-emitting pixel driver (EPD3).

[0403] By doing this, the volume ratio of each light-emitting pixel driver (EPD) can be improved, which can be advantageous for increasing the resolution of the display device (100).

[0404] The first transistor (T1), data wiring (DL), and second auxiliary wiring (ASL2) according to one embodiment of FIG. 16 are substantially identical or similar to one embodiment of FIG. 14 or one embodiment of FIG. 15, so redundant descriptions are omitted below.

[0405] As shown in FIG. 16, according to one embodiment, the circuit layer (120) may include constant voltage auxiliary wiring (CVAL) that extends in a second direction (DR2) and transmits a constant voltage.

[0406] The second source drain conductive layer (SDCDL2) may include data lines (DL), second auxiliary lines (ASL2), and constant voltage auxiliary lines (CVAL).

[0407] Each of the constant voltage auxiliary wirings (CVAL) can be placed between two data wirings (DL) and two second auxiliary wirings (ASL2) in the first direction (DR1).

[0408] The constant voltage auxiliary wiring (CVAL) may include a first power auxiliary wiring (VDAL) that transmits a first power source (ELVDD), a reference voltage auxiliary wiring (VRAL) that transmits a reference voltage (VREF), a first initialization voltage auxiliary wiring (VAIAL1) that transmits a first initialization voltage, and a second initialization voltage auxiliary wiring (VAIAL2) that transmits a second initialization voltage.

[0409] The first power auxiliary wiring (VDAL) can be arranged alternately with the reference voltage auxiliary wiring (VRAL), the first initial voltage auxiliary wiring (VAIAL1) that transmits the first initial voltage, and the second initial voltage auxiliary wiring (VAIAL2) that transmits the second initial voltage, respectively, in the first direction (DR1).

[0410] According to one embodiment, the second electrode (E21) of the first transistor (T1) of each of the first light-emitting pixel driver (EPD1), second light-emitting pixel driver (EPD2), third light-emitting pixel driver (EPD3), fourth light-emitting pixel driver (EPD4), fifth light-emitting pixel driver (EPD5), sixth light-emitting pixel driver (EPD6), seventh light-emitting pixel driver (EPD7) and eighth light-emitting pixel driver (EPD8) may overlap with one of the constant voltage auxiliary wirings (CVAL).

[0411] In this way, the output of the first transistor (T1) is protected from failure in which it is coupled with the data signal (Vdata) of the data line (DL) by the constant voltage auxiliary line (CVAL), so it can be maintained relatively stably. Accordingly, the display quality of the display device (100) can be improved.

[0412] Since the first transistor (T1) according to one embodiment of FIG. 17 is substantially the same or similar to one embodiment of FIG. 15, redundant descriptions below will be omitted.

[0413] As shown in FIG. 17, according to one embodiment, the circuit layer (120) may include a first power wiring (VDL in FIG. 9) that transmits a first power supply and a power connection transistor (TPC) that is electrically connected between two light-emitting pixel drivers (EPD1, EPD2) adjacent in a first direction (DR1).

[0414] The power connection transistor (TPC) may include a channel (CHPC) disposed in a first semiconductor layer (SEL1), a first electrode (E1PC) and a second electrode (E2PC), and a gate electrode (GPC) disposed in a first gate conductive layer (GCDL1).

[0415] The first electrode (E1PC) of the power connection transistor (TPC) can be electrically connected to the first power wiring (VDL) through the power connection electrode (VDCE).

[0416] The power connection electrode (VDCE) can be placed on the first source drain conductive layer (SDCDL1).

[0417] The light-emitting pixel drivers (EPDs) of the circuit layer (120) may include a first light-emitting pixel driver (EPD1) and a second light-emitting pixel driver (EPD2) adjacent to each other in a first direction (DR1).

[0418] The second electrode (E2PC) of the power connection transistor (TPC) can be electrically connected to the first electrode (E11) of the first transistor (T1) of the first light-emitting pixel driver (EPD1) and the first electrode (E11) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) through the third node connection electrode (NCE3).

[0419] The third node connecting electrode (NCE3) can be placed on the first source drain conductive layer (SDCDL1).

[0420] The gate electrode (GPC) of the power connection transistor (TPC) may be a part that overlaps with the channel (CHPC) of the power connection transistor (TPC) in the third direction (DR3) of the first light-emitting control wiring (ECL1).

[0421] The first light-emitting control wiring (ECL1) can be placed on the first gate conductive layer (GCDL1).

[0422] Each of the first light-emitting pixel driver (EPD1) and the second light-emitting pixel driver (EPD2) may include a fifth transistor (T5) electrically connected between the second electrode (E21) of the first transistor (T1) and the second node (N2 in FIG. 9).

[0423] The fifth transistor (T5) may include a channel (CH5) disposed in the first semiconductor layer (SEL1), a first electrode (E15) and a second electrode (E25), and a gate electrode (G5) disposed in the first gate conductive layer (GCDL1).

[0424] The first electrode (E15) of the fifth transistor (T5) can be electrically connected to the second electrode (E21) of the first transistor (T1) through the second node connection electrode (NCE2).

[0425] The second electrode (E25) of the fifth transistor (T5) can be electrically connected to the first anode connection electrode (ANCE1 in FIG. 8).

[0426] The gate electrode (G5) of the fifth transistor (T5) may be a part that overlaps with the channel (CH5) of the fifth transistor (T5) in the third direction (DR3) of the second light-emitting control wiring (ECL2).

[0427] The second light-emitting control wiring (ECL2) can be placed on the first gate conductive layer (GCDL1).

[0428] The second node connecting electrode (NCE2) can be placed on the first source drain conductive layer (SDCDL1).

[0429] The second node connecting electrode (NCE2) can be electrically connected to the second electrode (E21) of the first transistor (T1) through the fourth node connecting hole (NCH4), electrically connected to the second capacitor electrode (CAE2) through the fifth node connecting hole (NCH5), and electrically connected to the first electrode (E15) of the fifth transistor (T5) through the sixth node connecting hole (NCH6).

[0430] The second capacitor electrode (CAE2) is placed on the first gate conductive layer (GCDL1) and can overlap with the first capacitor electrode (CAE1) in the third direction (DR3).

[0431] The first capacitor electrode (CAE1) can be placed on the first semiconductor layer (SEL1).

[0432] The first source drain conductive layer (SDCDL1) may further include a reference voltage connection electrode (VRCE).

[0433] A portion of the reference voltage connection electrode (VRCE) may be symmetrical with respect to a portion of the power connection electrode (VDCE) with respect to the boundary between the first light-emitting pixel driver (EPD1) and the second light-emitting pixel driver (EPD2).

[0434] According to one embodiment of FIG. 18, the power connection transistor (TPC), the first transistor (T1), the fifth transistor (T5), the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), the second node connection electrode (NCE2), and the third node connection electrode (NCE3) are substantially identical or similar to those in one embodiment of FIG. 17, so redundant descriptions are omitted below.

[0435] As shown in FIG. 15, according to one embodiment, the second electrode (E21) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) may be extended to one side of the second direction (DR2) (upper side in FIG. 15), and the second electrode (E21) of the first transistor (T1) of the third light-emitting pixel driver (EPD3) may be extended to the other side of the second direction (DR2) (lower side in FIG. 15).

[0436] As shown in FIG. 18, the second light-emitting control wiring (ECL2) that intersects the second light-emitting pixel driver (EPD2) and the third light-emitting pixel driver (EPD3) may be placed on one side (upper side of FIG. 18) of the second direction (DR2) of the first transistor (T1) of each of the second light-emitting pixel driver (EPD2) and the third light-emitting pixel driver (EPD3).

[0437] In this case, the second electrode (E21) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) is extended to one side of the second direction (DR2) (upper side in FIG. 18), so that a part of the second electrode (E21) of the first transistor (T1) of the second light-emitting pixel driver (EPD2) can be positioned adjacent to the first electrode (E15) of the fifth transistor (T5).

[0438] On the other hand, the second electrode (E21) of the first transistor (T1) of the third light-emitting pixel driver (EPD3) extends to the other side of the second direction (DR2) (the lower side of FIG. 18), so it can be spaced relatively far from the first electrode (E15) of the fifth transistor (T5) of the third light-emitting pixel driver (EPD3).

[0439] According to one embodiment, the second electrode (E21) of the first transistor (T1) of the third light-emitting pixel driver (EPD3) can be electrically connected to the first electrode (E15) of the fifth transistor (T5) of the third light-emitting pixel driver (EPD3) through a second node connection electrode (NCE2) extending in a second direction (DR2).

[0440] Hereinafter, for convenience of explanation, the second node connecting electrode (NCE2) extending in the second direction (DR2) may be referred to as the node connecting electrode.

[0441] In other words, the second node connecting electrode (NCE2) of the second light-emitting pixel driver (EPD2) is in a form where no separate extension direction is visible, whereas the second node connecting electrode (NCE2) of the third light-emitting pixel driver (EPD3) may be in a form that extends to one side of the second direction (DR2) (upper side of FIG. 18).

[0442] The display device (100) of each embodiment as described above can be applied to various electronic devices.

[0443] An electronic device (10) according to one embodiment may include the display device (100) described above.

[0444] In addition, the electronic device (10) according to one embodiment may further include a module or device having other additional functions in addition to the display device (100).

[0445] FIG. 19 is a block diagram of an electronic device according to one embodiment.

[0446] Referring to FIG. 19, an electronic device (10) according to one embodiment may include a display module (21), a processor (22), a memory (23), and a power module (24).

[0447] The display module (21) may include a display device (100) that displays an image.

[0448] The processor (22) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0449] The memory (15) may store data information necessary for the operation of the processor (22) or the display module (21). When the processor (22) executes an application stored in the memory (23), a video data signal and / or an input control signal are transmitted to the display module (21), and the display module (21) can process the received signal and output video information through a display screen.

[0450] The power module (24) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0451] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device (100), while others may be provided separately from the display device (100). For example, the display device (100) may include a display module (21), and the processor (22), memory (23), and power module (24) may be provided in the form of other devices within the electronic device (10) other than the display device (100).

[0452] FIG. 20 is a schematic diagram of an electronic device according to various embodiments.

[0453] Referring to FIG. 20, electronic devices (10) according to embodiments may include image display electronic devices such as a smartphone (10_1a), tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), as well as wearable electronic devices such as smart glasses (10_2a), head-mounted display (10_2b), and smart watch (10_2c), and automotive electronic devices (10_3) such as a center information display (CID) and room mirror display of a car instrument panel, center fascia, and dashboard.

[0454] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0455] 10: Electronic devices 100: Display device 110: Substrate 120: Circuit layer 130: Device layer DA: Display area EA: Luminous area EPD: Light-emitting pixel driver EA1-EA8: Eight light-emitting regions (1st-8th light-emitting regions) EPD1-EPD8: Eight light-emitting pixel drivers (1st-8th light-emitting pixel drivers) R_EA: First color emission region G_EA: Second color luminescence region B_EA: Third color emission region TPC: Power connection transistor T1-5: 1st-5th transistors C1, C2: 1st and 2nd capacitors DL: Data wiring ASL1, ASL2: 1st and 2nd auxiliary wiring

Claims

Claim 1 A display device comprising: a substrate including a display area in which light-emitting regions are arranged; a circuit layer disposed on the substrate; and a device layer including light-emitting elements disposed in the light-emitting regions on the circuit layer, wherein the circuit layer includes light-emitting pixel drivers arranged in mutually parallel to each other in a first direction and a second direction in the display area and electrically connected to the light-emitting elements, and wherein eight light-emitting elements disposed in mutually adjacent light-emitting regions in the first direction, the second direction, and a diagonal direction intersecting the first direction and the second direction among the light-emitting regions are electrically connected to eight light-emitting pixel drivers arranged in mutually parallel to each other in the first direction among the light-emitting pixel drivers. Claim 2 In claim 1, the circuit layer further comprises: a first power wiring that transmits a first power supply; and a power connection transistor electrically connected between two light-emitting pixel drivers adjacent in the first direction among the light-emitting pixel drivers and the first power wiring, wherein each of the light-emitting pixel drivers includes a first transistor that is electrically connected between the power connection transistor and a first node and generates a driving current, the first electrode of the first transistor is electrically connected to the power connection transistor, and the first node is electrically connected to the second electrode of the first transistor. Claim 3 A display device according to claim 2, wherein the circuit layer comprises: a first semiconductor layer disposed on the substrate; a first interlayer insulating layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the first interlayer insulating layer and comprising an oxide semiconductor material, wherein the channel, first electrode, and second electrode of the first transistor are disposed on the second semiconductor layer, and the channel, first electrode, and second electrode of the power connection transistor are disposed on the first semiconductor layer. Claim 4 In claim 2, the eight light-emitting regions comprise: a first light-emitting region; a second light-emitting region adjacent to the first light-emitting region in the diagonal direction; a third light-emitting region adjacent to the first light-emitting region in the first direction; a fourth light-emitting region adjacent to the third light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the first direction; a fifth light-emitting region adjacent to the first light-emitting region in the second direction; a sixth light-emitting region adjacent to the fifth light-emitting region in the diagonal direction and adjacent to the second light-emitting region in the second direction; and a seventh light-emitting region adjacent to the fifth light-emitting region in the first direction and adjacent to the third light-emitting region in the second direction. A display device comprising an eighth light-emitting region adjacent to the seventh light-emitting region in the diagonal direction, adjacent to the sixth light-emitting region in the first direction, and adjacent to the fourth light-emitting region in the second direction, wherein the eight light-emitting pixel drivers include: a first light-emitting pixel driver electrically connected to a light-emitting element of the first light-emitting region; a second light-emitting pixel driver electrically connected to a light-emitting element of the second light-emitting region; a third light-emitting pixel driver electrically connected to a light-emitting element of the third light-emitting region; a fourth light-emitting pixel driver electrically connected to a light-emitting element of the fourth light-emitting region; a fifth light-emitting pixel driver electrically connected to a light-emitting element of the fifth light-emitting region; a sixth light-emitting pixel driver electrically connected to a light-emitting element of the sixth light-emitting region; a seventh light-emitting pixel driver electrically connected to a light-emitting element of the seventh light-emitting region; and an eighth light-emitting pixel driver electrically connected to a light-emitting element of the eighth light-emitting region. Claim 5 A display device according to claim 4, wherein each of the first light-emitting region and the seventh light-emitting region emits light of a first wavelength band, each of the second light-emitting region, the fourth light-emitting region, the sixth light-emitting region, and the eighth light-emitting region emits light of a second wavelength band lower than the first wavelength band, and each of the third light-emitting region and the fifth light-emitting region emits light of a third wavelength band lower than the second wavelength band. Claim 6 In claim 4, the first electrode and channel of the first transistor of the first light-emitting pixel driving unit are symmetrical to the first electrode and channel of the first transistor of the second light-emitting pixel driving unit with respect to the boundary between the first light-emitting pixel driving unit and the second light-emitting pixel driving unit, and the first electrode of the first transistor of the first light-emitting pixel driving unit and the first electrode of the first transistor of the second light-emitting pixel driving unit are interconnected in a display device. Claim 7 In claim 4, each of the light-emitting pixel driving units further comprises a node connecting electrode that electrically connects the second electrode of the first transistor and the first electrode of the fifth transistor, wherein the second electrode of the first transistor of the second light-emitting pixel driving unit extends to one side of the second direction, the second electrode of the first transistor of the third light-emitting pixel driving unit extends to the other side of the second direction, and the node connecting electrode of the third light-emitting pixel driving unit extends to the second direction. Claim 8 In claim 4, each of the light-emitting pixel driving units further comprises: a second transistor electrically connected between a data wiring that transmits a data signal and the gate electrode of the first transistor; a third transistor electrically connected between a reference voltage wiring that transmits a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage wiring that transmits an initialization voltage and a second node; and a fifth transistor electrically connected between the first node and the second node; a first capacitor electrically connected between the gate electrode of the first transistor and the first node; and a second capacitor electrically connected between the first node and the first power wiring, wherein the second node is electrically connected to one of the light-emitting elements. Claim 9 In claim 8, the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver intersect with two scan-write wires that transmit different scan-write signals, one reset control wire that transmits a reset control signal, one initialization control wire that transmits an initialization control signal, one first light-emitting control wire that transmits a first light-emitting control signal, and one second light-emitting control wire that transmits a second light-emitting control signal; the gate electrode of the second transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver is electrically connected to one of the two scan-write wires, and the gate electrode of the second transistor of each of the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the other of the two scan-write wires, and the first The gate electrode of the third transistor of each of the light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one reset control wire, and the gate electrode of the fourth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one initialization control wire, and the first light-emitting pixel driver, the second light-emitting pixel driver,A display device in which the gate electrodes of four power connection transistors electrically connected to the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver are electrically connected to the one first light-emitting control wire, and the gate electrode of the fifth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one second light-emitting control wire. Claim 10 A display device according to claim 8, wherein one of the first light-emitting pixel driver and the third light-emitting pixel driver is intersected with one data line and electrically connected to the one data line, and the other of the first light-emitting pixel driver and the third light-emitting pixel driver is electrically connected to the one data line through a first data extension line extending in the first direction, and one of the second light-emitting pixel driver and the fourth light-emitting pixel driver is intersected with another data line and electrically connected to the other data line, and the other of the second light-emitting pixel driver and the fourth light-emitting pixel driver is electrically connected to the other data line through a second data extension line extending in the first direction. Claim 11 In claim 10, the circuit layer further comprises constant voltage auxiliary wirings that extend in the second direction and transmit a constant voltage, and the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver are intersected by a first initialization voltage wiring that extends in the first direction and transmits a first initialization voltage, and a second initialization voltage wiring that extends in the first direction and transmits a second initialization voltage different from the first initialization voltage, and the first initialization voltage wiring is electrically connected to the first electrode of a fourth transistor of some of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver, and the second initialization voltage wiring is the first light-emitting pixel driver, the second light-emitting A pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver are electrically connected to the first electrode of the fourth transistor of the other remaining portion, and the constant voltage auxiliary wirings include a first power auxiliary wiring that transmits the first power, a reference voltage auxiliary wiring that transmits the reference voltage, a first initialization voltage auxiliary wiring that transmits the first initialization voltage, and a second initialization voltage auxiliary wiring that transmits the second initialization voltage, and the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver,A display device in which the second electrode of the first transistor of each of the seventh light-emitting pixel driver and the eighth light-emitting pixel driver overlaps with one of the constant voltage auxiliary wirings in a third direction. Claim 12 In claim 4, the circuit layer further comprises data lines extending in the second direction and transmitting a data signal; first auxiliary lines extending in the first direction; and second auxiliary lines extending in the second direction, wherein two adjacent data lines among the data lines intersect the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, and two adjacent second auxiliary lines among the second auxiliary lines intersect the third light-emitting pixel driver and the fourth light-emitting pixel driver, respectively. Claim 13 In claim 12, the display driving circuit further comprises a data signal supplying to the data lines, and the substrate further comprises a non-display area disposed around the display area, and the circuit layer further comprises data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit, and a bypass area on one side of the display area comprises a bypass middle area, a first bypass side area parallel to the bypass middle area in the first direction and in contact with the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area, and the data supply lines extend to the bypass middle area and the second bypass side area, and the data lines comprise a first data line disposed in the first bypass side area and a second data line disposed in the second bypass side area, and the first auxiliary lines comprise a first bypass auxiliary line electrically connected to the first data line, and the second auxiliary lines comprise a second bypass auxiliary line electrically connected to the first bypass auxiliary line and adjacent to the second data line. A display device comprising wiring, wherein a first data supply wiring among the data supply wirings that transmits a data signal of the first data wiring is electrically connected to the first data wiring through the first bypass auxiliary wiring and the second bypass auxiliary wiring, and a second data supply wiring among the data supply wirings that transmits a data signal of the second data wiring is directly electrically connected to the second data wiring. Claim 14 A display device for displaying images; a memory for storing an application; a processor for executing the application and transmitting an image data signal and an input control signal to the display device; and a power module for transmitting power to the display device, wherein the display device comprises: a substrate including a display area in which light-emitting regions are arranged; and a circuit layer disposed on the substrate. and includes a device layer disposed on the circuit layer, wherein the circuit layer includes light-emitting pixel drivers arranged in a first direction and a second direction in the display area and electrically connected to the light-emitting elements, and the light-emitting areas include: a first light-emitting area; a second light-emitting area adjacent to the first light-emitting area in a diagonal direction; a third light-emitting area adjacent to the first light-emitting area in the first direction; a fourth light-emitting area adjacent to the third light-emitting area in the diagonal direction and adjacent to the second light-emitting area in the first direction; a fifth light-emitting area adjacent to the first light-emitting area in the second direction; a sixth light-emitting area adjacent to the fifth light-emitting area in the diagonal direction and adjacent to the second light-emitting area in the second direction; and a seventh light-emitting area adjacent to the fifth light-emitting area in the first direction and adjacent to the third light-emitting area in the second direction. and includes an eighth light-emitting region adjacent to the seventh light-emitting region in the diagonal direction, adjacent to the sixth light-emitting region in the first direction, and adjacent to the fourth light-emitting region in the second direction, wherein the light-emitting pixel drivers include: a first light-emitting pixel driver electrically connected to a light-emitting element of the first light-emitting region; a second light-emitting pixel driver electrically connected to a light-emitting element of the second light-emitting region; a third light-emitting pixel driver electrically connected to a light-emitting element of the third light-emitting region; a fourth light-emitting pixel driver electrically connected to a light-emitting element of the fourth light-emitting region; a fifth light-emitting pixel driver electrically connected to a light-emitting element of the fifth light-emitting region; and a sixth light-emitting pixel driver electrically connected to a light-emitting element of the sixth light-emitting region.An electronic device comprising: a seventh light-emitting pixel driving unit electrically connected to a light-emitting element of the seventh light-emitting region; and an eighth light-emitting pixel driving unit electrically connected to a light-emitting element of the eighth light-emitting region. Claim 15 In claim 14, the circuit layer further comprises: a first power wiring that transmits a first power supply; and a power connection transistor electrically connected between two light-emitting pixel drivers adjacent in the first direction among the light-emitting pixel drivers and the first power wiring, wherein each of the light-emitting pixel drivers comprises a first transistor that is electrically connected between the power connection transistor and a first node and generates a driving current, wherein the first node is electrically connected to a second electrode of the first transistor, and the first electrode of the power connection transistor is electrically connected to the first power wiring, and the first electrode and channel of the first transistor of the first light-emitting pixel driver are symmetrical to the first electrode and channel of the first transistor of the second light-emitting pixel driver with respect to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and the first electrode of the first transistor of the first light-emitting pixel driver and the first electrode of the first transistor of the second light-emitting pixel driver are interconnected and electrically connected to the second electrode of one power connection transistor. Claim 16 In claim 15, each of the light-emitting pixel driving units further comprises a node connecting electrode electrically connecting the second electrode of the first transistor and the first electrode of the fifth transistor, wherein the second electrode of the first transistor of the second light-emitting pixel driving unit extends to one side of the second direction, the second electrode of the first transistor of the third light-emitting pixel driving unit extends to the other side of the second direction, and the node connecting electrode of the third light-emitting pixel driving unit extends to the second direction. Claim 17 In claim 14, each of the light-emitting pixel driving units further comprises: a second transistor electrically connected between a data wiring that transmits a data signal and the gate electrode of the first transistor; a third transistor electrically connected between a reference voltage wiring that transmits a reference voltage and the gate electrode of the first transistor; a fourth transistor electrically connected between an initialization voltage wiring that transmits an initialization voltage and the second node; and a fifth transistor electrically connected between the first node and the second node; a first capacitor electrically connected between the gate electrode of the first transistor and the first node; and a second capacitor electrically connected between the first node and the first power wiring, wherein the first electrode of the first transistor is electrically connected to the power connection transistor, and the second node is electrically connected to one of the light-emitting elements, and the circuit layer comprises: a first semiconductor layer disposed on the substrate; and a first interlayer insulating layer disposed on the first semiconductor layer. An electronic device comprising a second semiconductor layer disposed on the first interlayer insulating layer and including an oxide semiconductor material, wherein the channel, first electrode, and second electrode of the first transistor are disposed on the second semiconductor layer, and the channel, first electrode, and second electrode of the power connection transistor are disposed on the first semiconductor layer. Claim 18 An electronic device according to claim 17, wherein one of the first light-emitting pixel driver and the third light-emitting pixel driver is intersected with one data line and electrically connected to the one data line, and the other of the first light-emitting pixel driver and the third light-emitting pixel driver is electrically connected to the one data line through a first data extension line extending in the first direction, and one of the second light-emitting pixel driver and the fourth light-emitting pixel driver is intersected with another data line and electrically connected to the other data line, and the other of the second light-emitting pixel driver and the fourth light-emitting pixel driver is electrically connected to the other data line through a second data extension line extending in the first direction. Claim 19 In claim 17, the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver are intersected by two scan-write wires that transmit different scan-write signals, one reset control wire that transmits a reset control signal, one initialization control wire that transmits an initialization control signal, one first light-emitting control wire that transmits a first light-emitting control signal, and one second light-emitting control wire that transmits a second light-emitting control signal; the gate electrode of the second transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, and the fourth light-emitting pixel driver is electrically connected to one of the two scan-write wires, and the gate electrode of the second transistor of each of the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the other of the two scan-write wires. The gate electrode of the third transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one reset control wire, and the gate electrode of the fourth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one initialization control wire, and the first light-emitting pixel driver, the second light-emitting pixel driver,An electronic device in which the gate electrodes of four power connection transistors electrically connected to the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver are electrically connected to the one first light-emitting control wire, and the gate electrode of the fifth transistor of each of the first light-emitting pixel driver, the second light-emitting pixel driver, the third light-emitting pixel driver, the fourth light-emitting pixel driver, the fifth light-emitting pixel driver, the sixth light-emitting pixel driver, the seventh light-emitting pixel driver, and the eighth light-emitting pixel driver is electrically connected to the one second light-emitting control wire. Claim 20 In claim 14, the display driving circuit for supplying data signals to the data lines further comprises, the substrate further comprises a non-display area disposed around the display area, and the circuit layer comprises: data lines extending in the second direction and transmitting data signals; first auxiliary lines extending in the first direction; and second auxiliary lines extending in the second direction.and further include data supply lines disposed in the non-display area and electrically connected between the data lines and the display driving circuit, wherein a bypass area on one side of the display area includes a bypass middle area, a first bypass side area adjacent to the bypass middle area in the first direction and in contact with the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area, wherein the data supply lines extend to the bypass middle area and the second bypass side area, and the data lines include a first data line disposed in the first bypass side area and a second data line disposed in the second bypass side area, wherein the first auxiliary lines include a first bypass auxiliary line electrically connected to the first data line, and the second auxiliary lines include a second bypass auxiliary line electrically connected to the first bypass auxiliary line and adjacent to the second data line, and among the data supply lines, the first data supply line that transmits the data signal of the first data line is through the first bypass auxiliary line and the second bypass auxiliary line An electronic device that is electrically connected to the first data line and, among the data supply lines, has a second data supply line that transmits a data signal of the second data line, is directly electrically connected to the second data line, two mutually adjacent data lines among the data lines intersect the first light-emitting pixel driver and the second light-emitting pixel driver, respectively, and two mutually adjacent second auxiliary lines among the second auxiliary lines intersect the third light-emitting pixel driver and the fourth light-emitting pixel driver, respectively.

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