Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device comprises a substrate, a device layer disposed on the substrate and including a light-emitting element and a light-receiving element, and a circuit layer disposed between the substrate and the device layer and including a light-emitting transistor electrically connected to the light-emitting element and a light-receiving transistor electrically connected to the light-receiving element. The circuit layer comprises a first stack including the light-emitting transistor, a first wiring stack disposed on the first stack and including a first wiring electrically connected to the light-emitting transistor, a second stack disposed on the first wiring stack and including the light-receiving transistor, and a second wiring stack disposed on the second stack and including a second wiring electrically connected to at least one of the light-emitting transistor and the light-receiving transistor.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a Liquid Crystal Display Device, a Field Emission Display Device, or an Organic Light Emitting Display Device. Among these flat panel display devices, the light-emitting display device includes a light-emitting element in which each pixel of the display panel can emit light on its own, thereby enabling the display of an image without a backlight unit that provides light to the display panel.

[0004] The display device may include a detection sensor that detects light embedded in a display panel that displays an image. The detection sensor may include a light-receiving element capable of collecting light. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a high-resolution display device including a light-emitting element and a light-receiving element, and an electronic device including the same.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to one embodiment for solving the above problem comprises a substrate, a device layer disposed on the substrate and including a light-emitting element and a light-receiving element, and a circuit layer disposed between the substrate and the device layer and including a light-emitting transistor electrically connected to the light-emitting element and a light-receiving transistor electrically connected to the light-receiving element, wherein the circuit layer comprises a first stack including the light-emitting transistor, a first wiring stack disposed on the first stack and including a first wiring electrically connected to the light-emitting transistor, a second stack disposed on the first wiring stack and including the light-receiving transistor, and a second wiring stack disposed on the second stack and including a second wiring electrically connected to at least one of the light-emitting transistor and the light-receiving transistor.

[0008] The above photodetector can be non-overlapping with the light-emitting transistor in a horizontal direction perpendicular to the thickness direction of the substrate.

[0009] The above photoreceiving transistor can overlap with the light-emitting transistor in the thickness direction of the substrate.

[0010] The second wiring above may include a common application wiring that is electrically connected to both the light-emitting transistor and the light-receiving transistor.

[0011] The above common application wiring may include one end adjacent to the light-emitting transistor, the other end adjacent to the light-receiving transistor, and a connection portion connecting the one end and the other end.

[0012] The circuit layer further includes a first contact hole penetrating the insulating film of each of the second stack and the first wiring stack, and a second contact hole penetrating the insulating film of the second stack, wherein the first contact hole electrically connects the one end and the light-emitting transistor, and the second contact hole electrically connects the other end and the light-receiving transistor, and the connecting portion may be disposed between the first contact hole and the second contact hole.

[0013] The above common application wiring may include at least one of a reference voltage line, an initialization voltage line, a scan write line, and a low voltage power line.

[0014] The photoreceiving transistor may not be placed in the first stack, and the light-emitting transistor may not be placed in the second stack.

[0015] A display device according to another embodiment for solving the above problem comprises a substrate, a device layer disposed on the substrate and including a light-emitting element and a light-receiving element, and a circuit layer disposed between the substrate and the device layer, wherein the circuit layer comprises a first active layer disposed on the substrate, a first gate layer disposed on the first active layer, a first source-drain layer disposed on the first gate layer, a second active layer disposed on the first source-drain layer, a second gate layer disposed on the second active layer, a second source-drain layer disposed on the second gate layer, a light-emitting transistor electrically connected to the light-emitting element and comprising a semiconductor region disposed on the first active layer, a first electrode and a second electrode, and a gate electrode disposed on the first gate layer, a light-receiving transistor electrically connected to the light-receiving element and comprising a semiconductor region disposed on the second active layer, a first electrode and a second electrode, and a gate electrode disposed on the second gate layer, a first wiring disposed on the first source-drain layer and electrically connected to the light-emitting transistor, and on the second source-drain layer It includes a second wiring that is positioned and electrically connected to at least one of the light-emitting transistor and the light-receiving transistor.

[0016] The above photodetector can be non-overlapping with the light-emitting transistor in a horizontal direction perpendicular to the thickness direction of the substrate.

[0017] The above photoreceiving transistor can overlap with the light-emitting transistor in the thickness direction of the substrate.

[0018] The second wiring above may include a common application wiring that is electrically connected to both the light-emitting transistor and the light-receiving transistor.

[0019] The above common application wiring may include one end adjacent to the light-emitting transistor, the other end adjacent to the light-receiving transistor, and a connection portion connecting the one end and the other end.

[0020] The above common application wiring can be placed in the second source drain layer.

[0021] The circuit layer further comprises a first connecting electrode disposed in the first source drain layer, a first contact hole penetrating insulating films disposed between the first source drain layer and the second source drain layer, and a second contact hole penetrating insulating films disposed between the second active layer and the second source drain layer, wherein the first contact hole electrically connects the one end and the light-emitting transistor, and the second contact hole electrically connects the other end and the photoreceiving transistor, and the connecting portion may be disposed between the first contact hole and the second contact hole.

[0022] The above common application wiring may include at least one of a reference voltage line, an initialization voltage line, a scan write line, and a low voltage power line.

[0023] The photoreceiving transistor may not be placed in the first stack, and the light-emitting transistor may not be placed in the second stack.

[0024] The circuit layer may further include a first lower conductive layer disposed between the substrate and the first active layer, and a second lower conductive layer disposed between the first source drain layer and the second active layer.

[0025] The light-emitting transistor may further include a lower gate electrode disposed in the first lower conductive layer, and the light-receiving transistor may further include a lower gate electrode disposed in the second lower conductive layer.

[0026] An electronic device according to one embodiment for solving the above problem comprises a display device for displaying an image, a processor for providing an image driving signal to the display device, and a power module for supplying power to the display device and the processor. The display device comprises a substrate, a device layer disposed on the substrate and comprising a light-emitting element and a light-receiving element, and a circuit layer disposed between the substrate and the device layer and comprising a light-emitting transistor electrically connected to the light-emitting element and a light-receiving transistor electrically connected to the light-receiving element. The circuit layer comprises a first stack comprising the light-emitting transistor, a first wiring stack disposed on the first stack and comprising a first wiring electrically connected to the light-emitting transistor, a second stack disposed on the first wiring stack and comprising the light-receiving transistor, and a second wiring stack disposed on the second stack and comprising a second wiring electrically connected to at least one of the light-emitting transistor and the light-receiving transistor. Effects of the invention

[0027] According to one embodiment of the present invention, a display device and an electronic device including the same may have a high resolution including a light-emitting element and a light-receiving element.

[0028] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0029] FIG. 1 is a perspective view showing a display device according to one embodiment. Figure 2 is a plan view showing the display device of Figure 1. Figure 3 is a cross-sectional view taken along X1-X1' of Figure 2. FIG. 4 is a plan view showing a light-emitting pixel, a sensing pixel, various driving parts, and various wirings of a display device according to one embodiment. FIG. 5 is a block diagram showing a light-emitting pixel, a sensing pixel, various driving units, and various wirings of a display device according to one embodiment. FIG. 6 is a plan view showing the display area of ​​a display device according to one embodiment. FIG. 7 is an equivalent circuit diagram showing a light-emitting pixel according to one embodiment. FIG. 8 is an equivalent circuit diagram showing a sensing pixel according to one embodiment. FIG. 9 is a cross-sectional view showing a light-emitting pixel according to one embodiment. FIG. 10 is a cross-sectional view showing a sensing pixel according to one embodiment. FIG. 11 is a table showing the layer-by-layer arrangement of wirings connected to each of the light-emitting pixel and the sensing pixel, and the layer-by-layer arrangement of transistors included in each of the light-emitting pixel and the sensing pixel, according to one embodiment of a display device. FIG. 12 is a schematic layout diagram showing the display area of ​​a display device according to a comparative example and one embodiment. FIG. 13 is an equivalent circuit diagram showing connection portions connecting a light-emitting pixel, a sensing pixel, and a common applied wiring according to one embodiment. Figure 14 is a layout diagram showing a part of the display area. FIG. 15 is a layout diagram showing the first stack and the first wiring stack. FIG. 16 is a layout diagram showing the second stack and the second wiring stack. FIG. 17 is a cross-sectional view taken along X2-X2' of FIG. 14 to 16. FIG. 18 is a cross-sectional view taken along X3-X3' of FIG. 14 to 16. FIG. 19 is a block diagram of an electronic device according to one embodiment. FIG. 20 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0031] When an element or layer is referred to as being "on" another element or layer, it includes cases where another layer or element is interposed directly above or in between. Likewise, when referred to as "below," "left," and "right," it includes cases where they are interposed immediately adjacent to another element or where another layer or material is interposed in between. Throughout the specification, the same reference numerals refer to the same components.

[0032] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0033] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] Specific embodiments will be described below with reference to the attached drawings.

[0035] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a plan view showing the display device of FIG. 1. FIG. 3 is a cross-sectional view taken along X1-X1' of FIG. 2.

[0036] FIG. 1 illustrates a state in which a sub-region (SBA) of a display device (10) is unfolded, and FIG. 2 and FIG. 3 illustrate a state in which a sub-region (SBA) of a display device (10) is bent.

[0037] Referring to FIGS. 1 to 3, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0038] The display device (10) may include a display panel (100). The display panel (100) may be a light-emitting display panel such as an organic light-emitting display panel using an organic light-emitting diode, a quantum dot light-emitting display panel including a quantum dot light-emitting layer, an inorganic light-emitting display panel including an inorganic semiconductor, and a micro light-emitting display panel using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the description will focus on the case where the display panel (100) is an organic light-emitting display panel, but is not limited thereto.

[0039] The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved surface formed at the left and right ends, having a constant curvature or a changing curvature. Additionally, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0040] The display panel (100) may include a main area (MA) corresponding to the display surface of the display device (10) and a sub-area (SBA) protruding from one side of the main area (MA).

[0041] The main area (MA) may include a display area (DA) positioned in most of the center and a non-display area (NDA) positioned around the display area (DA). The display area (DA) may be formed as a rectangular plane having a short side in the first direction (DR1) and a long side in the second direction (DR2). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. However, the planar shape of the display area (DA) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The non-display area (NDA) may be positioned at the edge of the main area (MA) to surround the display area (DA).

[0042] In the illustrated drawing, the first direction (DR1) and the second direction (DR2) each intersect each other as horizontal directions. For example, the first direction (DR1) and the second direction (DR2) may be mutually orthogonal. Additionally, the third direction (DR3) intersects the first direction (DR1) and the second direction (DR2), and may be, for example, an orthogonal vertical direction. Unless otherwise defined, in this specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) may be referred to as one side, and the opposite direction may be referred to as the other side. Furthermore, in this specification, “up,” “upper side,” “top,” “top,” and “upper surface” refer to the direction in which the arrow of the drawing points among the third direction (DR3) based on the drawing, and “lower,” “lower side,” “lower,” “bottom,” and “lower surface” refer to the direction opposite to the direction in which the arrow of the third direction (DR3) points based on the drawing.

[0043] The sub-region (SBA) may be a region extending in the second direction (DR2) from a portion of one side of the main region (MA) extending in the first direction (DR1). The sub-region (SBA) may include a bending region that is deformed into a curved shape.

[0044] As illustrated in FIG. 3, the sub-region (SBA) may include a bending area that is deformed into a bending shape, a first sub-region positioned between one side of the main area (MA) and one side of the bending area, and a second sub-region extending from the other side of the bending area. When the bending area is deformed into a bending shape, the second sub-region may be positioned on the back surface of the display device (10) and may overlap with the main area (MA). A display driving circuit (200) provided as an integrated circuit chip (IC) may be mounted in the second sub-region. A circuit board (300) may be bonded to one side of the second sub-region. A touch driving circuit (400) provided as an integrated circuit chip (IC) may be mounted on the circuit board (300).

[0045] As illustrated in FIG. 3, the display panel (100) of the display device (10) according to the embodiments may include a substrate (SUB), a circuit layer (TFTL), a device layer (EML), a sealing layer (TFEL), a touch sensor layer (SENL), and a polarizing layer (POL).

[0046] The substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. Alternatively, the substrate (SUB) may be made of an insulating material such as glass.

[0047] The device layer (EML) may include light-emitting elements (LE) (see FIG. 7) respectively disposed in light-emitting regions (EA) (see FIG. 6) and light-receiving elements (PD) (see FIG. 9) respectively disposed in sensing regions (PDA) (see FIG. 6).

[0048] The circuit layer (TFTL) may include light-emitting pixel drivers (EPDs) (see FIG. 7) that are electrically connected to light-emitting elements (LEs) (see FIG. 7) of the device layer (EML) and sensing pixel drivers (OPDs) (see FIG. 9) that are electrically connected to light-receiving elements (PDs) (see FIG. 9) of the device layer (EML).

[0049] The sealing layer (TFEL) is disposed on the device layer (EML) and may have a structure in which at least one organic film is interposed between two or more inorganic films.

[0050] The touch sensor layer (SENL) may include touch electrodes for detecting a signal that varies according to the touch of a person or object and for sensing the point where the touch of the person or object occurs within the main area (MA).

[0051] The polarization layer (POL) can prevent the deterioration of image visibility caused by external light reflection by blocking external light reflected from the touch sensor layer (SENL), sealing layer (TFEL), device layer (EML), circuit layer (TFTL), and the interfaces between them.

[0052] According to the embodiments, the display device (10) may further include a display driving circuit (200) which is provided as an integrated circuit chip (IC) and mounted in a sub-region (SBA).

[0053] The display driving circuit (200) can supply digital video data (DATA) (see FIG. 5) to the data lines (DL) (see FIG. 4) of the circuit layer (TFTL).

[0054] According to embodiments, the display device (10) may further include a circuit board (300) mounted in a sub-region (SBA). The circuit board (300) may be bonded to pads placed in the sub-region (SBA) using an anisotropic conductive film or the like.

[0055] According to embodiments, the display device (10) may further include a touch driving circuit (400) mounted on a circuit board (300). When the touch sensor layer (SENL) includes capacitive touch electrodes and sensing electrodes, the touch driving circuit (400) may detect a touch based on whether there is a change in capacitance. However, this is merely an example, and the touch sensor layer (SENL) and the touch driving circuit (400) of FIG. 3 may be provided with a touch sensing method other than the capacitive method.

[0056] FIG. 4 is a plan view showing a light-emitting pixel, a sensing pixel, various driving units, and various wirings of a display device according to one embodiment. FIG. 5 is a block diagram showing a light-emitting pixel, a sensing pixel, various driving units, and various wirings of a display device according to one embodiment.

[0057] Referring to FIGS. 4 and 5, the display panel (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a light-emitting pixel (PX), a sensing pixel (OPX), a power line (VL), a data line (DL), a read-out line (ROL), a gate line (GL), and a light-emitting control line (ECL).

[0058] Each of the plurality of light-emitting pixels (PX) can be connected to a gate line (GL), a light-emitting control line (ECL), a data line (DL), and a power line (VL). Each of the plurality of light-emitting pixels (PX) may include a plurality of transistors, light-emitting elements, and capacitors.

[0059] Each of the plurality of sensing pixels (OPX) can be connected to a gate line (GL), a power line (VL), and a read-out line (ROL). Each of the plurality of sensing pixels (OPX) may include a plurality of transistors and photodetectors.

[0060] The gate lines (GL) can be extended in a first direction (DR1) and can be spaced apart from each other in a second direction (DR2) that intersects the first direction (DR1). The gate lines (GL) can sequentially supply gate signals to the light-emitting pixels (PX) and the sensing pixels (OPX).

[0061] The light emission control lines (ECLs) can be extended in a first direction (DR1) and spaced apart from each other in a second direction (DR2). The light emission control lines (ECLs) can sequentially supply light emission signals to light emission pixels (PX).

[0062] Data lines (DL) can be extended in a second direction (DR2) and can be spaced apart from each other in a first direction (DR1). The data lines (DL) can supply data voltage to light-emitting pixels (PX). The data voltage can determine the brightness of each light-emitting pixel (PX).

[0063] The power line (VL) can be extended in a second direction (DR2) and separated from each other in a first direction (DR1). The power line (VL) can supply power voltage to light-emitting pixels (PX) and sensing pixels (OPX). Here, the power voltage may be a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage may be a high potential voltage for driving the light-emitting pixel (PX), and the common voltage may be a low potential voltage for driving the light-emitting pixel (PX) and the sensing pixel (OPX).

[0064] A non-display area (NDA) may surround a display area (DA). The non-display area (NDA) may include a gate driver (610), a light emission control driver (620), fan-out lines (FL), a first gate control line (GSL1), and a second gate control line (GSL2).

[0065] Fan-out lines (FL) can extend from the display driving circuit (200) to the display area (DA). The fan-out lines (FL) can supply data voltage received from the display driving circuit (200) to the data line (DL), supply power voltage received from the display driving circuit (200) to the power line (VL), and supply a sensing signal received from the read-out line (ROL) to the display driving circuit (200). Accordingly, the display driving circuit (200) can drive the light-emitting pixel (PX) and the sensing pixel (OPX).

[0066] The first gate control line (GSL1) may extend from the display driving circuit (200) to the gate driving unit (610). The first gate control line (GSL1) may supply a gate control signal (GCS) received from the display driving circuit (200) to the gate driving unit (610).

[0067] The second gate control line (GSL2) can be extended from the display driving circuit (200) to the light emission control driving unit (620). The second gate control line (GSL2) can supply a light emission control signal (ECS) received from the display driving circuit (200) to the light emission control driving unit (620).

[0068] A sub-region (SBA) may extend from one side of a non-display area (NDA). The sub-region (SBA) may include a display driving circuit (200) and a pad portion (DP). The pad portion (DP) may be positioned adjacent to one edge of the sub-region (SBA) than the display driving circuit (200). The pad portion (DP) may be electrically connected to a circuit board (300) through an anisotropic conductive film (ACF).

[0069] The display driving circuit (200) may include a timing control unit (210) and a data driving unit (220).

[0070] The timing control unit (210) can receive digital video data (DATA) and timing signals from the circuit board (300). The timing control unit (210) can generate a data control signal (DCS) based on the timing signals and supply the digital video data (DATA) and the data control signal (DCS) to the data driver (220) to control the operation timing of the data driver (220). The timing control unit (210) can generate a gate control signal (GCS) and supply it to the gate driver (610) and control the operation timing of the gate driver (610). The timing control unit (210) can generate a light emission control signal (ECS) and supply it to the light emission control driver (620) and control the operation timing of the light emission control driver (620).

[0071] The data driver (220) can convert digital video data (DATA) into analog data voltages and supply them to data lines (DL) through fan-out lines (FL). The gate signals of the gate driver (610) can select light-emitting pixels (PX) to which the data voltage is supplied, and the selected light-emitting pixels (PX) can receive the data voltage through the data lines (DL). The data driver (220) can supply the received sensing signal to the main processor through the read-out line (ROL).

[0072] The power supply unit (500) is positioned on the circuit board (300) and can supply power voltage to the display driving circuit (200) and the display panel (100). The power supply unit (500) can generate power voltage and supply it to the power line (VL), and generate a common voltage and supply it to the common electrode common to the light-emitting pixels (PX) and the sensing pixels (OPX). The power supply unit (500) can generate an initialization voltage and supply it to the initialization voltage line, generate a reference voltage and supply it to the reference voltage line, generate a bias voltage and supply it to the bias voltage line, and generate a reset voltage and supply it to the reset voltage line.

[0073] The gate driver (610) may be positioned on one side outside the display area (DA) or on one side of the non-display area (NDA), and the light emission control driver (620) may be positioned on the other side outside the display area (DA) or on the other side of the non-display area (NDA), but is not limited thereto. As another example, the gate driver (610) and the light emission control driver (620) may be positioned on either one side or the other side of the non-display area (NDA).

[0074] The gate driver (610) may include a plurality of transistors that generate gate signals based on a gate control signal (GCS). The light emission control driver (620) may include a plurality of transistors that generate light emission signals based on a light emission control signal (ECS). For example, the transistors of the gate driver (610) and the transistors of the light emission control driver (620) may be formed on the same layer as the transistors of each light-emitting pixel (PX). The gate driver (610) may supply gate signals to gate lines (GL), and the light emission control driver (620) may supply light emission signals to light emission control lines (ECL).

[0075] FIG. 6 is a plan view showing the display area of ​​a display device according to one embodiment.

[0076] Referring to FIG. 6, the display area (DA) may include light-emitting areas (EA) and non-light-emitting areas (NEA).

[0077] The light-emitting regions (EA) can emit light from the light-emitting elements (LE) (see FIG. 7), and the light-emitting elements (LE) (see FIG. 7) may not be placed in the non-light-emitting regions (NEA). The non-light-emitting regions (NEA) may be regions other than the light-emitting regions (EA).

[0078] The light-emitting regions (EA) may include first to third light-emitting regions (EA1, EA2, EA3). For example, the first light-emitting region (EA1) may emit light of a first color or red light, the second light-emitting region (EA2) may emit light of a second color or green light, and the third light-emitting region (EA3) may emit light of a third color or blue light, but is not limited thereto.

[0079] A single light-emitting pixel (PX) may express a white gradation by including a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3), but the configuration of the light-emitting pixel (PX) is not limited thereto. The white gradation may be expressed by a combination of light emitted from a first light-emitting region (EA1), light emitted from a second light-emitting region (EA2), and light emitted from a third light-emitting region (EA3).

[0080] The areas of the first to third light-emitting regions (EA1, EA2, EA3) may differ from each other. For example, the area of ​​the third light-emitting region (EA3) may be larger than the area of ​​the second light-emitting region (EA2), and the area of ​​the second light-emitting region (EA2) may be larger than the area of ​​the first light-emitting region (EA1), but is not limited thereto. As another example, the areas of the first to third light-emitting regions (EA1, EA2, EA3) may be the same.

[0081] The display area (DA) may further include sensing areas (PDA). The sensing areas (PDA) may be placed in a non-luminous area (NEA). The sensing areas (PDA) may be spaced apart from each other with at least one luminous area (EA) in between.

[0082] The sensing area (PDA) may be surrounded by first to third light-emitting areas (EA1, EA2, EA3). The sensing area (PDA) may be positioned between the first light-emitting areas (EA1) in a diagonal direction defined by the first direction (DR1) and the second direction (DR2), may be positioned between the second light-emitting areas (EA2) in the first direction (DR1), and may be positioned between the third light-emitting areas (EA3) in the second direction (DR2).

[0083] The sensing pixel (OPX) can receive light incident on the sensing area (PDA).

[0084] FIG. 7 is an equivalent circuit diagram showing a light-emitting pixel according to one embodiment.

[0085] Referring to FIG. 7, the light-emitting pixel (PX) can be connected to a light-emitting pixel driver (EPD) to a scan write line (GWL) that transmits a scan write signal (GW), a reset control line (GRL) that transmits a reset control signal (GR), a bias control line (GBL) that transmits a bias control signal (GB), a first light-emitting control line (ECL1) that transmits a first light-emitting control signal (EC1), a second light-emitting control line (ECL2) that transmits a second light-emitting control signal (EC2), a first power line (VDL) that transmits a first power supply (ELVDD), a second power line (VSL) that transmits a second power supply (ELVSS), a reference voltage line (VRL) that transmits a reference voltage (VREF), an initialization voltage line (VAIL) that transmits an initialization voltage (VAINT), and a data line (DL) that transmits digital video data (DATA).

[0086] The light-emitting pixel (PX) may include a light-emitting element (LE) and a light-emitting pixel driver (EPD) that drives the light-emitting element (LE).

[0087] Light-emitting elements (LEs) can be electrically connected between light-emitting pixel drivers (EPDs) and a second power line (VSL). One of the light-emitting elements (LEs) can be electrically connected between one of the light-emitting pixel drivers (EPDs) and a second power line (VSL).

[0088] The second power supply (ELVSS) may be at a lower voltage level than the first power supply (ELVDD). The anode electrode of the light-emitting element (LE) is electrically connected to the light-emitting pixel driver (EPD), and the second power supply (ELVSS) at a lower voltage level than the first power supply (ELVDD) may be applied to the cathode electrode of the light-emitting element (LE).

[0089] The light-emitting capacitor (Cel) connected in parallel with the light-emitting element (LE) represents the parasitic capacitance between the anode electrode and the cathode electrode.

[0090] The light-emitting pixel driver (EPD) may include a first transistor (T1) that generates a driving current for driving a light-emitting element (LE), two or more transistors (T2 to T6) electrically connected to the first transistor (T1), and one or more capacitors (C1, C2).

[0091] The second transistor (T2) can be electrically connected between the gate electrode of the first transistor (T1) and the data line (DL). The second transistor (T2) can be turned on by the scan write signal (GW) of the scan write line (GWL). When the second transistor (T2) is turned on, digital video data (DATA) of the data line (DL) can be transmitted to the gate electrode of the first transistor (T1).

[0092] When the voltage difference between the gate electrode of the first transistor (T1) and the second electrode (e.g., source electrode) of the first transistor (T1) becomes greater than the threshold voltage of the first transistor (T1) due to digital video data (DATA) applied to the gate electrode of the first transistor (T1), the first transistor (T1) can be turned on. Accordingly, the drain-source current of the first transistor (T1) can be generated with a magnitude corresponding to the digital video data (DATA).

[0093] The third transistor (T3) can be electrically connected between the gate electrode of the first transistor (T1) and the reference voltage line (VRL). The third transistor (T3) can be turned on by the reset control signal (GR) of the reset control line (GRL). When the third transistor (T3) is turned on, the potential of the gate electrode of the first transistor (T1) can be reset to the reference voltage (VREF) of the reference voltage line (VRL).

[0094] The fourth transistor (T4) can be electrically connected between the light-emitting element (LE) and the initialization voltage line (VAIL). The fourth transistor (T4) can be turned on by the bias control signal (GB) of the bias control line (GBL). When the fourth transistor (T4) is turned on, the potential of the anode electrode of the light-emitting element (LE) can be initialized to the initialization voltage (VAINT) of the initialization voltage line (VAIL).

[0095] The fifth transistor (T5) can be electrically connected between the first electrode (e.g., drain electrode) of the first transistor (T1) and the first power line (VDL). The fifth transistor (T5) can be turned on by the first light emission control signal (EC1) of the first light emission control line (ECL1). When the fifth transistor (T5) is turned on, the first power (ELVDD) of the first power line (VDL) can be delivered to the first electrode of the first transistor (T1).

[0096] The sixth transistor (T6) can be electrically connected between the second electrode (e.g., source electrode) of the first transistor (T1) and the light-emitting element (LE). The sixth transistor (T6) can be turned on by the second light-emitting control signal (EC2) of the second light-emitting control line (ECL2). When the sixth transistor (T6) is turned on, the drain-source current of the first transistor (T1), which is generated with a magnitude corresponding to the digital video data (DATA), can be transmitted to the light-emitting element (LE) through the sixth transistor (T6). Thus, the light-emitting element (LE) can emit light with a brightness corresponding to the digital video data (DATA).

[0097] The first capacitor (C1) can be electrically connected between the gate electrode of the first transistor (T1) and the second electrode (e.g., source electrode) of the first transistor (T1).

[0098] Accordingly, the first capacitor (C1) can be filled with digital video data (DATA) applied to the gate electrode of the first transistor (T1), and due to the voltage filled in the first capacitor (C1), the turn-on of the first transistor (T1) can be maintained for a predetermined period.

[0099] The second capacitor (C2) can be electrically connected between the second electrode (e.g., source electrode) of the first transistor (T1) and the first power line (VDL).

[0100] The voltage of the first capacitor (C1) corresponds to the potential difference between the gate electrode of the first transistor (T1) and the second electrode (e.g., source electrode) of the first transistor (T1), is varied by digital video data (DATA), and can be divided into the second capacitor (C2). Accordingly, the threshold voltage of the first transistor (T1) can be compensated, and stable operation can be achieved by compensating for fluctuations in the threshold voltage of the first transistor (T1).

[0101] In one embodiment, as shown in FIG. 7, the first to sixth transistors (T1 to T6) may be N-type MOSFETs. However, this is not limited thereto, and at least one of the first to sixth transistors (T1 to T6) may be a P-type MOSFET.

[0102] FIG. 8 is an equivalent circuit diagram showing a sensing pixel according to one embodiment.

[0103] Referring to FIG. 8, the sensing pixel (OPX) can be connected to the sensing pixel driver (OPD) to a reset signal line (GSL) that transmits a reset signal (GS), a scan write line (GWL) that transmits a scan write signal (GW), a second power line (VSL) that transmits a second power supply (ELVSS), a reference voltage line (VRL) that transmits a reference voltage (VREF), and an initialization voltage line (VAIL) that transmits an initialization voltage (VAINT).

[0104] The sensing pixel (OPX) may include a light receiving element (PD) and a sensing pixel driver (OPD) that drives the light receiving element (PD).

[0105] The photodetectors (PDs) can be electrically connected between the sensing pixel drivers (OPDs) and the second power line (VSL). One of the photodetectors (PDs) can be electrically connected between one of the sensing pixel drivers (OPDs) and the second power line (VSL).

[0106] The second power supply (ELVSS) may be a voltage level lower than the initialization voltage (VAINT) and reference voltage (VREF). The anode electrode of the photodetector (PD) is electrically connected to the sensing pixel driver (OPD), and the second power supply (ELVSS) may be applied to the cathode electrode of the photodetector (PD).

[0107] The detection pixel driver (OPD) may include first to third sensor transistors (PT1, PT2, PT3).

[0108] The first sensor transistor (PT1) may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first sensor transistor (PT1) may be connected to a sensor node (NS), the first electrode may be connected to a third sensor transistor (PT3), and the second electrode may be connected to a reference voltage line (VRL). The first sensor transistor (PT1) can control a source-drain current (Isd, hereinafter referred to as "sensing current") based on the voltage of the sensor node (NS), which is the first electrode of the photodetector (PD). The sensing current flowing through the channel of the first sensor transistor (PT1) may be proportional to the square of the difference between the voltage (Vsg) between the source electrode and the gate electrode of the first sensor transistor (PT1) and the threshold voltage (Vth) (Isd = k' × (Vsg - Vth)²). Here, k' represents a proportionality constant determined by the structure and physical characteristics of the first sensor transistor (PT1), Vsg represents the source-gate voltage of the first sensor transistor (PT1), and Vth represents the threshold voltage of the first sensor transistor (PT1). The first electrode of the first sensor transistor (PT1) may be the source electrode and the second electrode may be the drain electrode, but is not limited thereto.

[0109] The second sensor transistor (PT2) can be turned on by the reset signal (GS) of the reset signal line (GSL) to discharge the voltage of the sensor node (NS) to the reset voltage. The gate electrode of the second sensor transistor (PT2) may be connected to the reset signal line (GSL), the first electrode may be connected to the sensor node (NS), and the second electrode may be connected to the initialization voltage line (VAIL). The first electrode of the second sensor transistor (PT2) may be connected to the first electrode of the photodetector (PD) and the gate electrode of the first sensor transistor (PT1) through the sensor node (NS). The first electrode of the second sensor transistor (PT2) may be the drain electrode and the second electrode may be the source electrode, but is not limited thereto.

[0110] The third sensor transistor (PT3) can be turned on by the scan write signal (GW) of the scan write line (GWL) to electrically connect the first electrode and the read out line (ROL) of the first sensor transistor (PT1).

[0111] A photodetector (PD) can receive light and convert light energy into an electrical signal. The first electrode of the photodetector (PD) is connected to a sensor node (NS), which is the gate electrode of a first sensor transistor (PT1), and the second electrode can be connected to a second power line (VSL). The second electrode of the photodetector (PD) can receive a second power supply (ELVSS) from the second power line (VSL). For example, the first electrode of the photodetector (PD) may be a sensor electrode and the second electrode may be a common electrode, but is not limited thereto.

[0112] When an object is positioned on the display panel (100), light emitted from the light-emitting element (LE) can be reflected by the object, and the light-receiving element (PD) can receive the reflected light. The light-receiving element (PD) can convert the energy of the light into an electrical signal (current or voltage) formed between the first electrode and the second electrode, and the converted electrical signal can flow from the second power line (VSL) to the sensor node (NS) as a reverse bias current. For example, when the light-receiving element (PD) receives light and an electric field is formed between the first electrode and the second electrode of the light-receiving element (PD), current can flow through the light-receiving element (PD) in proportion to the amount of light, and the voltage of the sensor node (NS) can increase. Therefore, when the light-receiving element (PD) receives light, the voltage of the sensor node (NS) can increase, and the magnitude of the sensing current (or source-drain current) of the first sensor transistor (PT1) can decrease. The sensing current of the first sensor transistor (PT1) can be applied to the display driving circuit (200) as a sensing signal through the third sensor transistor (PT3) and the read-out line (ROL).

[0113] FIG. 9 is a cross-sectional view showing a light-emitting pixel according to one embodiment. FIG. 10 is a cross-sectional view showing a sensing pixel according to one embodiment.

[0114] Referring to FIGS. 9 and 10 in addition to FIGS. 7 and 8, the display panel (100) may include a substrate (SUB), a circuit layer (TFTL), and a device layer (EML).

[0115] The light-emitting pixel (PX) may include a light-emitting pixel driver (EPD) and a light-emitting element (LE). The light-emitting pixel driver (EPD) may include a light-emitting transistor (TFT_P), and the light-emitting transistor (TFT_P) may be placed in a circuit layer (TFTL). The light-emitting transistor (TFT_P) may include the first to sixth transistors (T1 to T6) described with reference to FIG. 7. The light-emitting element (LE) may be placed in a device layer (EML).

[0116] A sensing pixel (OPX) may include a sensing pixel driver (OPD) and a light receiving element (PD). The sensing pixel driver (OPD) may include a light receiving transistor (TFT_O), and the light receiving transistor (TFT_O) may be placed in a circuit layer (TFTL). The light receiving transistor (TFT_O) may include first to third sensor transistors (PT1, PT2, PT3) described with reference to FIG. 8. The light receiving element (PD) may be placed in a device layer (EML).

[0117] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide, but is not limited thereto. As another example, the substrate (SUB) may include a glass material or a metal material.

[0118] The circuit layer (TFTL) may include a barrier layer (BR), a first lower conductive layer (BML1), a first buffer layer (BF1), a first active layer (ACTL1), a first gate insulating layer (GI1), a first gate layer (GTL1), a first interlayer insulating layer (ILD1), a first source drain layer (SDL1), a second interlayer insulating layer (ILD2), a second lower conductive layer (BML2), a second buffer layer (BF2), a second active layer (ACTL2), a second gate insulating layer (GI2), a second gate layer (GTL2), a third interlayer insulating layer (ILD3), a second source drain layer (SDL2), a first via layer (VIA1), a third source drain layer (SDL3), and a second via layer (VIA2).

[0119] The barrier layer (BR) may be a film for protecting the transistors of the circuit layer (TFTL) and the light-emitting layer (EL) and light-receiving layer (RCL) of the device layer (EML) from moisture penetrating through a substrate (SUB) that is susceptible to moisture permeability. The barrier layer (BR) may be composed of a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the barrier layer (BR) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0120] The first lower conductive layer (BML1) may be disposed on the barrier layer (BR). The first lower conductive layer (BML1) may be disposed overlapping the semiconductor region (ACT_P) of the light-emitting transistor (TFT_P) in the third direction (DR3) to prevent light from being incident on the semiconductor region (ACT_P) of the light-emitting transistor (TFT_P) and causing leakage current. The first lower conductive layer (BML1) may include the lower gate electrode (BGE_P) of the light-emitting transistor (TFT_P). Accordingly, the quality of the light-emitting transistor (TFT_P) may be improved. The first lower conductive layer (BML1) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0121] The first buffer layer (BF1) may be disposed on the first lower conductive layer (BML1). The first buffer layer (BF1) may prevent the penetration of air or moisture. The first buffer layer (BF1) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the first buffer layer (BF1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0122] A first active layer (ACTL1) may be disposed on a first buffer layer (BF1). The first active layer (ACTL1) may include a semiconductor material. For example, the first active layer (ACTL1) may include a silicon-based semiconductor material, such as low-temperature polycrystalline silicon (LTPS), or an oxide-based semiconductor material. The first active layer (ACTL1) may include a semiconductor region (ACT_P) of a light-emitting transistor (TFT_P), a first electrode (DE_P), and a second electrode (SE_P).

[0123] A first gate insulating layer (GI1) may be disposed on a first active layer (ACTL1). The first gate insulating layer (GI1) may insulate the first active layer (ACTL1) from the first gate layer (GTL1). The first gate insulating layer (GI1) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the first gate insulating layer (GI1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0124] A first gate layer (GTL1) may be disposed on a first gate insulating layer (GI1). The first gate layer (GTL1) may include a gate line (GL_P) and a gate electrode (GE_P) of a light-emitting transistor (TFT_P). The gate line (GL_P) may include a scan write line (GWL), a reset control line (GRL), a bias control line (GBL), a first light-emitting control line (ECL1), and a second light-emitting control line (ECL2) as described with reference to FIG. 7. The gate electrode (GE_P) of the light-emitting transistor (TFT_P) may be a part of the gate line (GL_P). The first gate layer (GTL1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0125] The first interlayer insulating layer (ILD1) may be disposed on the first gate layer (GTL1). The first interlayer insulating layer (ILD1) may insulate the first gate layer (GTL1) from the first source drain layer (SDL1). The first interlayer insulating layer (ILD1) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the first interlayer insulating layer (ILD1) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0126] The first source drain layer (SDL1) may be disposed on the first interlayer insulating layer (ILD1). The first source drain layer (SDL1) may include a first anode connection electrode (ANCE1) and a data line (DL). When the light-emitting transistor (TFT_P) is the sixth transistor (T6), the first anode connection electrode (ANCE1) may electrically connect the second electrode (SE_P) and the second anode connection electrode (ANCE2) of the light-emitting transistor (TFT_P). Although not shown in the drawing, when the light-emitting transistor (TFT_P) is the second transistor (T2), the data line (DL) may be electrically connected to the first electrode (DE_P) of the light-emitting transistor (TFT_P). The first source drain layer (SDL1) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0127] The second interlayer insulating layer (ILD2) may be disposed on the first source-drain layer (SDL1). The second interlayer insulating layer (ILD2) may insulate the first source-drain layer (SDL1) from the second lower conductive layer (BML2). The second interlayer insulating layer (ILD2) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the second interlayer insulating layer (ILD2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0128] The second lower conductive layer (BML2) may be disposed on the second interlayer insulating layer (ILD2). The second lower conductive layer (BML2) may be disposed overlapping the semiconductor region (ACT_O) of the photodetector (TFT_O) in the third direction (DR3) to prevent leakage current from occurring when light is incident on the semiconductor region (ACT_O) of the photodetector (TFT_O). The second lower conductive layer (BML2) may include the lower gate electrode (BGE_O) of the photodetector (TFT_O). Accordingly, the quality of the photodetector (TFT_O) may be improved. The second lower conductive layer (BML2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0129] The second buffer layer (BF2) may be disposed on the second lower conductive layer (BML2). The second gate insulating layer (GI2) may insulate the second lower conductive layer (BML2) from the second active layer (ACTL2). The second buffer layer (BF2) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the second buffer layer (BF2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0130] The second active layer (ACTL2) may be disposed on the second buffer layer (BF2). The second active layer (ACTL2) may include a semiconductor material. For example, the second active layer (ACTL2) may include a silicon-based semiconductor material, such as low-temperature polycrystalline silicon (LTPS), or an oxide-based semiconductor material. The second active layer (ACTL2) may include a semiconductor region (ACT_O) of a photodetector transistor (TFT_O), a first electrode (DE_O), and a second electrode (SE_O).

[0131] The second gate insulating layer (GI2) may be disposed on the second active layer (ACTL2). The second gate insulating layer (GI2) may insulate the second active layer (ACTL2) from the second gate layer (GTL2). The second gate insulating layer (GI2) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the second gate insulating layer (GI2) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0132] The second gate layer (GTL2) may be disposed on the second gate insulating layer (GI2). The second gate layer (GTL2) may include a scan write line (GWL) and a gate electrode (GE_O) of a photodetector (TFT_O). If the photodetector (TFT_O) is a third sensor transistor (PT3), the gate electrode (GE_O) of the photodetector (TFT_O) may be part of the scan write line (GWL) or electrically connected to the scan write line (GWL). The second gate layer (GTL2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0133] The third interlayer insulating layer (ILD3) may be disposed on the second gate layer (GTL2). The third interlayer insulating layer (ILD3) may insulate the second gate layer (GTL2) from the second source drain layer (SDL2). The third interlayer insulating layer (ILD3) may include a single layer of inorganic film or a plurality of inorganic films stacked alternately. For example, the third interlayer insulating layer (ILD3) may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0134] The second source drain layer (SDL2) may be disposed on the third interlayer insulating layer (ILD3). The second source drain layer (SDL2) may include a second anode connection electrode (ANCE2), an initialization voltage line (VAIL), a first power line (VDL), and a reference voltage line (VRL) in the light-emitting pixel (PX), and may include a first sensor connection electrode (PNCE1), an initialization voltage line (VAIL), and a reference voltage line (VRL) in the sensing pixel (OPX). The second source drain layer (SDL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0135] If the light-emitting transistor (TFT_P) is the sixth transistor (T6), the second anode connection electrode (ANCE2) can electrically connect the first anode connection electrode (ANCE1) and the third anode connection electrode (ANCE3). Although not shown in the drawing, if the light-emitting transistor (TFT_P) is the third transistor (T3), the reference voltage line (VRL) can be electrically connected to the first electrode (DE_P) of the light-emitting transistor (TFT_P). Although not shown in the drawing, if the light-emitting transistor (TFT_P) is the fourth transistor (T4), the initialization voltage line (VAIL) can be electrically connected to the second electrode (SE_P) of the light-emitting transistor (TFT_P). Although not shown in the drawing, if the light-emitting transistor (TFT_P) is the fifth transistor (T5), the first power line (VDL) can be electrically connected to the first electrode (DE_P) of the light-emitting transistor (TFT_P).

[0136] If the photodetector (TFT_O) is the second sensor transistor (PT2), the first sensor connection electrode (PNCE1) can electrically connect the second electrode (SE_O) of the photodetector (TFT_O) and the second sensor connection electrode (PNCE2). If the photodetector (TFT_O) is the second sensor transistor (PT2), the initialization voltage line (VAIL) can be electrically connected to the first electrode (DE_O) of the photodetector (TFT_O). Although not shown in the drawing, if the photodetector (TFT_O) is the first sensor transistor (PT1), the reference voltage line (VRL) can be electrically connected to the first electrode (DE_O) of the photodetector (TFT_O).

[0137] A first via layer (VIA1) may be disposed on a second source-drain layer (SDL2). The first via layer (VIA1) may insulate the second source-drain layer (SDL2) and the third source-drain layer (SDL3). The upper surface of the first via layer (VIA1) may be flat. The first via layer (VIA1) may include an organic insulating material such as polyimide.

[0138] A third source drain layer (SDL3) may be disposed on a first via layer (VIA1). The third source drain layer (SDL3) may include a third anode connection electrode (ANCE3) in a light-emitting pixel (PX), and a second sensor connection electrode (PNCE2), a reset signal line (GSL), and a read-out line (ROL) in a sensing pixel (OPX). The third source drain layer (SDL3) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0139] When the light-emitting transistor (TFT_P) is the sixth transistor (T6), the third anode connection electrode (ANCE3) can electrically connect the second anode connection electrode (ANCE2) and the pixel electrode (AE) of the light-emitting element (LE).

[0140] If the photodetector (TFT_O) is the second sensor transistor (PT2), the second sensor connection electrode (PNCE2) can electrically connect the first sensor connection electrode (PNCE1) and the sensor electrode (PE) of the photodetector (PD). If the photodetector (TFT_O) is the second sensor transistor (PT2), the reset signal line (GSL) can be electrically connected to the gate electrode (GE_O) of the photodetector (TFT_O). Although not shown in the drawing, if the photodetector (TFT_O) is the third sensor transistor (PT3), the read-out line (ROL) can be electrically connected to the second electrode (SE_O) of the photodetector (TFT_O).

[0141] The second via layer (VIA2) may be disposed on the third source drain layer (SDL3). The second via layer (VIA2) may insulate the pixel electrode (AE) of the light-emitting element (LE) from the third source drain layer (SDL3) and may insulate the sensor electrode (PE) of the light-emitting element (LE) from the third source drain layer (SDL3). The upper surface of the second via layer (VIA2) may be flat. The second via layer (VIA2) may include an organic insulating material such as polyimide.

[0142] The device layer (EML) may include a pixel defining layer (PDL), a light-emitting element (LE), and a light-receiving element (PD).

[0143] A pixel defining film (PDL) may be disposed on the pixel electrode (AE) and the second via layer (VIA2) of a light-emitting element (LE). The pixel defining film (PDL) may define a plurality of light-emitting regions (EA). The pixel defining film (PDL) may include an organic insulating material such as polyimide, but is not limited thereto.

[0144] The light-emitting element (LE) may include a pixel electrode (AE), a hole transport layer (HTL), a light-emitting layer (EL), an electron transport layer (ETL), and a common electrode (CAT).

[0145] A pixel electrode (AE) can be placed on a second via layer (VIA2). The pixel electrode (AE) can overlap with one of a plurality of light-emitting regions (EA) defined by a pixel defining film (PDL). The pixel electrode (AE) can receive a driving current from a light-emitting pixel driver (EPD) of a light-emitting pixel (PX).

[0146] The hole transport layer (HTL) may be placed on the pixel electrode (AE) in the light-emitting region (EA) and on the pixel defining film (PDL) in a region other than the light-emitting region (EA). The hole transport layer (HTL) may not be separated by light-emitting pixels (PX) but may be implemented as a common layer for all light-emitting pixels (PX) and sensing pixels (OPX).

[0147] The emitting layer (EL) may be disposed on the hole transport layer (HTL) in the emitting region (EA). For example, the emitting layer (EL) may be an organic emitting layer made of an organic material, but is not limited thereto.

[0148] The electron transport layer (ETL) may be placed on the emitting layer (EL) in the emitting region (EA) and on the hole transport layer (HTL) in a region other than the emitting region (EA). The electron transport layer (ETL) may not be separated by emitting pixels (PX) but may be implemented as a common layer for all emitting pixels (PX) and sensing pixels (OPX).

[0149] A common electrode (CAT) may be placed on an electron transport layer (ETL). For example, the common electrode (CAT) may be implemented in the form of an electrode common to all light-emitting pixels (PX) and sensing pixels (OPX) without being separated by light-emitting pixels (PX). The common electrode (CAT) may be a transparent electrode and may transmit light. The common electrode (CAT) may be electrically connected to a second power line (VSL) and may receive a second voltage (ELVSS) (or low potential voltage, common voltage, or cathode voltage).

[0150] When the light-emitting layer (EL) corresponds to an organic light-emitting layer, the light-emitting pixel driving unit (EPD) of the light-emitting pixel (PX) applies a predetermined voltage to the pixel electrode (AE), and when the common electrode (CAT) receives a common voltage or a cathode voltage, holes can move to the light-emitting layer (EL) through the hole transport layer (HTL), electrons can move to the light-emitting layer (EL) through the electron transport layer (ETL), and holes and electrons can combine with each other in the light-emitting layer (EL) to emit light.

[0151] The photodetector (PD) may include a sensor electrode (PE), a hole transport layer (HTL), a photodetector layer (RCL), an electron transport layer (ETL), and a common electrode (CAT).

[0152] The sensor electrode (PE) is placed on the second via layer (VIA2) and can be placed on the same layer as the pixel electrode (AE) of the light-emitting element (LE). The sensor electrode (PE) can overlap with one of a plurality of sensing regions (PDA) defined by the pixel defining film (PDL).

[0153] The hole transport layer (HTL) may be placed on the sensor electrode (PE) in the sensing region (PDA) and on the pixel defining film (PDL) in a region other than the sensing region (PDA). The hole transport layer (HTL) may not be separated by sensing pixel (OPX) but may be implemented as a common layer for the entire emitting pixel (PX) and the sensing pixel (OPX).

[0154] The photoreceiving layer (RCL) can be placed on the hole transport layer (HTL) in the sensing region (PDA). The photoreceiving layer (RCL) can receive light emitted from the emission region (EA) and reflected by an object, or receive light introduced from the outside. Light emitted from the light-emitting element (LE) in the emission region (EA) is reflected by the object, and the reflected light can reach the photoreceiving layer (RCL). Alternatively, light introduced from the outside after being reflected by the object can reach the photoreceiving layer (RCL).

[0155] The electron transport layer (ETL) may be placed on the photoreceiving layer (RCL) in the sensing area (PDA) and on the hole transport layer (HTL) in an area other than the sensing area (PDA). The electron transport layer (ETL) may not be separated by sensing pixel (OPX) but may be implemented as a common layer for the entire emitting pixel (PX) and the sensing pixel (OPX).

[0156] A common electrode (CAT) may be placed on an electron transport layer (ETL). For example, the common electrode (CAT) may be implemented in the form of an electrode common to all light-emitting pixels (PX) and sensing pixels (OPX) without being separated by sensing pixels (OPX). The common electrode (CAT) may be a transparent electrode and may transmit light. The common electrode (CAT) may be electrically connected to a second power line (VSL) and may receive a second voltage (ELVSS) (or low potential voltage, common voltage, or cathode voltage).

[0157] When the photoreceiving layer (RCL) corresponds to an organic photoreceiving layer, the photoreceiving element (PD) can convert the energy of light into an electrical signal (current or voltage) formed between the sensor electrode (PE) and the common electrode (CAT), and the converted electrical signal can flow to the sensor node (NS) of FIG. 8 as a reverse bias current. For example, when the photoreceiving element (PD) receives light and an electric field is formed between the sensor electrode (PE) and the common electrode (CAT) of the photoreceiving element (PD), a current can flow to the photoreceiving element (PD) in proportion to the amount of light.

[0158] A sealing layer (TFEL) may be placed on a common electrode (CAT) to cover a light-emitting element (LE) and a light-receiving element (PD). The sealing layer (TFEL) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element (LE) and the light-receiving element (PD). The encapsulation layer (TFEL) may include at least one organic film to protect the light-emitting element (LE) and the light-receiving element (PD) from foreign substances such as dust.

[0159] FIG. 11 is a table showing the layer-by-layer arrangement of wirings connected to each of the light-emitting pixel and the sensing pixel, and the layer-by-layer arrangement of transistors included in each of the light-emitting pixel and the sensing pixel, of a display device according to one embodiment. FIG. 12 is a schematic layout diagram showing the display area of ​​a display device according to a comparative embodiment and one embodiment.

[0160] Referring to FIGS. 11 and FIGS. 12 in addition to FIGS. 9 and 10, in a display device (10) according to the present embodiment, the circuit layer (TFTL) may include a first stack (TSTK1), a first wiring stack (BSTK1), a second stack (TSTK2), and a second wiring stack (BSTK2).

[0161] The first stack (TSTK1) may be disposed on a substrate (SUB) (or barrier layer (BR)). The first stack (TSTK1) may include a first lower conductive layer (BML1), a first buffer layer (BF1), a first active layer (ACTL1), a first gate insulating layer (GI1), a first gate layer (GTL1), and a first interlayer insulating layer (ILD1). The first stack (TSTK1) may include a light-emitting transistor (TFT_P). The first stack (TSTK1) may include wirings electrically connected to a light-emitting pixel driver (EPD). For example, the first stack (TSTK1) may include a scan write line (GWL), a reset control line (GRL), a bias control line (GBL), a first light-emitting control line (ECL1), and a second light-emitting control line (ECL2).

[0162] A first wiring stack (BSTK1) may be placed on a first stack (TSTK1). The first wiring stack (BSTK1) may include a first source drain layer (SDL1) and a second interlayer insulation layer (ILD2). The first wiring stack (BSTK1) may include wirings electrically connected to an emitting pixel driver (EPD). For example, the first wiring stack (BSTK1) may include a data line (DL).

[0163] A second stack (TSTK2) may be placed on a first wiring stack (BSTK1). The second stack (TSTK2) may include a second lower conductive layer (BML2), a second buffer layer (BF2), a second active layer (ACTL2), a second gate insulating layer (GI2), a second gate layer (GTL2), and a third interlayer insulating layer (ILD3). The second stack (TSTK2) may include a photodetector (TFT_O). The second stack (TSTK2) may include wirings electrically connected to a sensing pixel driver (OPD). For example, the second stack (TSTK2) may include a scan write line (GWL).

[0164] A second wiring stack (BSTK2) may be disposed on the second stack (TSTK2). The second wiring stack (BSTK2) may include a second source drain layer (SDL2), a first via layer (VIA1), a third source drain layer (SDL3), and a second via layer (VIA2). The second wiring stack (BSTK2) may include wirings electrically connected to an emitting pixel driver (EPD). For example, the second wiring stack (BSTK2) may include a reference voltage line (VRL), an initialization voltage line (VAIL), and a first power line (VDL). The second wiring stack (BSTK2) may include wirings electrically connected to a sensing pixel driver (OPD). For example, the second stack (TSTK2) may include a reference voltage line (VRL), an initialization voltage line (VAIL), a reset signal line (GSL), and a read-out line (ROL).

[0165] According to the display device (10) of the present embodiment, the number of light-emitting pixels (PX) and detection pixels (OPX) placed in the display area (DA) can be increased. That is, a high-resolution display device (10) can be provided.

[0166] For example, FIG. 12 is a drawing showing a portion of a display area (DA) containing the same number of light-emitting pixels (PX) and detection pixels (OPX) in each of the display device (10') according to the comparative embodiment and the display device (10) according to the present embodiment.

[0167] In the display device (10') according to the comparative embodiment, transistors of the light-emitting pixel driver (EPD) and transistors of the sensing pixel driver (OPD) may be arranged within a single stack without distinction between the first stack (TSTK1) and the second stack (TSTK2). For example, the display device (10') according to the comparative embodiment may include a substrate (SUB), a stack disposed on the substrate (SUB) and including transistors of the light-emitting pixel driver (EPD) and transistors of the sensing pixel driver (OPD), and a wiring stack disposed on the stack.

[0168] In one embodiment, the stack of the display device (10') according to the comparative embodiment includes a first lower conductive layer (BML1), a first active layer (ACTL1), and a first gate layer (GTL1), and may be stacked in order. The wiring stack of the display device (10') according to the comparative embodiment may include at least one layer among the first to third source drain layers (SDL1, SDL2, SDL3).

[0169] Unlike the display device (10) according to the present embodiment, the display device (10') according to the comparative embodiment has the light-emitting transistors (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving transistors (TFT_O) of the detection pixel driver (OPD) arranged together in the lower part of the wiring stack without stack separation, so additional space is required to arrange the light-receiving transistors (TFT_O) between the light-emitting transistors (TFT_P).

[0170] For example, in one embodiment, when the stack of the display device (10') according to the comparative embodiment includes a first lower conductive layer (BML1), a first active layer (ACTL1), and a first gate layer (GTL1), since the semiconductor region (ACT_P) of the light-emitting transistors (TFT_P) and the semiconductor region (ACT_O) of the light-receiving transistors (TFT_O) are placed in the same first active layer (ACTL1), additional space is required to place the light-receiving transistors (TFT_O) between the light-emitting transistors (TFT_P).

[0171] Accordingly, as illustrated in FIG. 12, when the length of a display area (DA) containing the same number of light-emitting pixels (PX) and detection pixels (OPX) is referred to as the unit display length, the unit display length (L_DA) in the display device (10) according to the present embodiment may be smaller than the unit display length (L_DA') in the display device (10') according to the comparative embodiment. Accordingly, the display device (10) according to the present embodiment may include a greater number of light-emitting pixels (PX) and detection pixels (OPX) within the same size display area (DA) than the display device (10') according to the comparative embodiment.

[0172] Accordingly, according to the display device (10) of the present embodiment, the number of light-emitting pixels (PX) and detection pixels (OPX) placed in the display area (DA) can be increased. That is, a high-resolution display device (10) can be provided.

[0173] FIG. 13 is an equivalent circuit diagram showing connection portions connecting a light-emitting pixel, a sensing pixel, and a common applied wiring according to one embodiment. FIG. 14 is a layout diagram showing a part of a display area. FIG. 15 is a layout diagram showing a first stack and a first wiring stack. FIG. 16 is a layout diagram showing a second stack and a second wiring stack. FIG. 17 is a cross-sectional view taken along X2-X2' of FIG. 14 to 16. FIG. 18 is a cross-sectional view taken along X3-X3' of FIG. 14 to 16.

[0174] Referring to FIGS. 13 to 18 in addition to FIGS. 9 to 11, in a display device (10) according to the present embodiment, a light-emitting pixel driver (EPD) and a light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) may be placed in a first stack (TSTK1), and a light-receiving pixel driver (OPD) and a light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) may be placed in a second stack (TSTK2). In some embodiments, the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) may include first to sixth transistors (T1 to T6), and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) may include first to third sensor transistors (PT1 to PT3). However, the number of transistors and sensor transistors of each of the light-emitting pixel driver (EPD) and the light-receiving pixel driver (OPD) is not limited thereto.

[0175] Since the light-emitting pixel driver (EPD) and the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) are placed in different stacks and stacked together, the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) can overlap at least partially with the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-emitting pixel driver (EPD) in the third direction (DR3). For example, as shown in FIGS. 14 to 16, the first sensor transistor (PT1) can overlap with the second transistor (T2) in the third direction (DR3).

[0176] Since the light-emitting pixel driver (EPD) and the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) are placed in different stacks and stacked together, the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) can be non-overlapping with the light-emitting pixel driver (EPD) and the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) in a horizontal direction perpendicular to the third direction (DR3) (e.g., a plane defined by the first direction (DR1) and the second direction (DR2)).

[0177] In some embodiments, as shown in FIG. 13, the reference voltage line (VRL), initialization voltage line (VAIL), scan write line (GWL), and second power line (ELVSS) may be electrically connected to both the light-emitting pixel driver (EPD) and the sensing pixel driver (OPD). The wiring electrically connected to both the light-emitting pixel driver (EPD) and the sensing pixel driver (OPD) may be referred to as common application wiring.

[0178] The scan write line (GWL) is a common power supply line, but as illustrated in FIGS. 11 and 13, it may be provided in the first stack (TSTK1) and the second stack (TSTK2), respectively, rather than the wiring stacks (BSTK1, BSTK2). For example, the scan write line (GWL) connected to the light-emitting pixel driver (EPD) may be placed in the first stack (TSTK1), and the wiring connected to the sensing pixel driver (OPD) may be placed in the second stack (TSTK2). However, it is not limited thereto, and the scan write line (GWL), like other common power supply lines, may also be provided in common to the light-emitting pixel driver (EPD) and the sensing pixel driver (OPD) and placed in the second wiring stack (BSTK2).

[0179] The common authorization wiring may include connecting portions that connect one end adjacent to the light-emitting pixel driver (EPD) and the other end adjacent to the sensing pixel driver (OPD).

[0180] For example, the reference voltage line (VRL) may include a first connection (CEP1) connecting one end adjacent to the light-emitting pixel driver (EPD) and the other end adjacent to the detection pixel driver (OPD). The initialization voltage line (VAIL) may include a second connection (CEP2) connecting one end adjacent to the light-emitting pixel driver (EPD) and the other end adjacent to the detection pixel driver (OPD). The second power line (ELVSS) may include a third connection (CEP3) connecting one end adjacent to the light-emitting pixel driver (EPD) and the other end adjacent to the detection pixel driver (OPD). Although not shown in the drawings, if the scan write line (GWL) is provided in common for the light-emitting pixel driver (EPD) and the detection pixel driver (OPD), the scan write line (GWL) may include a fourth connection (CEP4) connecting one end adjacent to the light-emitting pixel driver (EPD) and the other end adjacent to the detection pixel driver (OPD).

[0181] The first connection part (CEP1) and the second connection part (CEP2) will be described with reference to FIGS. 14 to 18.

[0182] First, as illustrated in FIGS. 14 to 16 and FIG. 17, a reference voltage line (VRL) may be placed in the second source-drain layer (SDL2) of the second wiring stack (BSTK2). The reference voltage line (VRL) may be electrically connected to the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving transistor (TFT_O) of the detection pixel driver (OPD).

[0183] For example, one end of the reference voltage line (VRL) can be electrically connected to a light-emitting transistor (TFT_P) (e.g., a third transistor (T3)) through a first contact hole (CNT1) and a first connecting electrode (CCE1). The first contact hole (CNT1) can penetrate the second interlayer insulating layer (ILD2), the second buffer layer (BF2), and the third interlayer insulating layer (ILD3). The first connecting electrode (CCE1) can be placed in the first source-drain layer (SDL1).

[0184] The other end of the reference voltage line (VRL) can be electrically connected to a photodetector (TFT_O) (e.g., a first sensor transistor (PT1)) through a second contact hole (CNT2). The second contact hole (CNT2) can penetrate the third interlayer insulating layer (ILD3).

[0185] The reference voltage line (VRL) may include a first connection portion (CEP1) connecting one end of the reference voltage line (VRL) adjacent to the light-emitting transistor (TFT_P) and the other end of the reference voltage line (VRL) adjacent to the photodetector (TFT_O). The first connection portion (CEP1) may be disposed in the second source-drain layer (SDL2). The first connection portion (CEP1) may be disposed between the first contact hole (CNT1) and the second contact hole (CNT2).

[0186] Next, as illustrated in FIGS. 14 to 16 and FIG. 18, the initialization voltage line (VAIL) may be placed in the second source-drain layer (SDL2) of the second wiring stack (BSTK2). The initialization voltage line (VAIL) may be electrically connected to the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving transistor (TFT_O) of the detection pixel driver (OPD).

[0187] For example, one end of the initialization voltage line (VAIL) can be electrically connected to a light-emitting transistor (TFT_P) (e.g., a fourth transistor (T4)) through a third contact hole (CNT3) and a second connecting electrode (CCE2). The third contact hole (CNT3) can penetrate the second interlayer insulating layer (ILD2), the second buffer layer (BF2), and the third interlayer insulating layer (ILD3). The second connecting electrode (CCE2) can be placed in the first source drain layer (SDL1).

[0188] The other end of the initialization voltage line (VAIL) can be electrically connected to a photodetector (TFT_O) (e.g., a second sensor transistor (PT2)) through a fourth contact hole (CNT4). The fourth contact hole (CNT4) can penetrate the third interlayer insulating layer (ILD3).

[0189] The initialization voltage line (VAIL) may include a second connection portion (CEP2) connecting one end of the initialization voltage line (VAIL) adjacent to the light-emitting transistor (TFT_P) and the other end of the initialization voltage line (VAIL) adjacent to the photodetector (TFT_O). The second connection portion (CEP2) may be disposed in the second source-drain layer (SDL2). The second connection portion (CEP2) may be disposed between the first contact hole (CNT1) and the second contact hole (CNT2).

[0190] In the display device (10) according to the present embodiment, the light-emitting pixel driver (EPD) and the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) are placed in the first stack (TSTK1), and the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) are placed in the second stack (TSTK2). Therefore, a common application wiring that is commonly connected to the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD) and the light-receiving pixel driver (OPD) can be placed in the second wiring stack (BSTK2). In addition, the common application wiring includes connection parts, contact holes, and connection electrodes for connecting them, so that, despite the distinction between the first stack (TSTK1) and the second stack (TSTK2), the common application wiring can be commonly connected to the light-emitting pixel driver (EPD) and the light-emitting transistor (TFT_P) of the light-emitting pixel driver (EPD), and the light-receiving pixel driver (OPD) and the light-receiving transistor (TFT_O) of the light-receiving pixel driver (OPD).

[0191] The display device (10) according to the above-described embodiments can be applied to various electronic devices (1). An electronic device (1) according to one embodiment includes the above-described display device (10) and may further include a module or device having additional functions other than the display device (10).

[0192] FIG. 19 is a block diagram of an electronic device according to one embodiment.

[0193] Referring to FIG. 19, an electronic device (1) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0194] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0195] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal are transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen.

[0196] The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (1).

[0197] At least one of each component of the electronic device (1) described above may be included in the display device (10) according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device (10), while others may be provided separately from the display device (10). For example, the display device (10) may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (1) other than the display device (10).

[0198] FIG. 20 is a schematic diagram of an electronic device according to various embodiments.

[0199] Referring to FIG. 20, various electronic devices (1) to which a display device (10) according to embodiments is applied may include not only image display electronic devices (1) such as a smartphone (1_1a), tablet PC (1_1b), laptop (1_1c), TV (1_1d), and desk monitor (1_1e), but also wearable electronic devices (1) including display modules such as smart glasses (1_2a), head-mounted display (1_2b), and smart watch (1_2c), and automotive electronic devices (1_3) including display modules such as a CID (Center Information Display) and room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0200] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0201] 1: Electronic device 10: Display device 100: Display panel PX: Light-emitting pixel OPX: Detect pixel EPD: Light-emitting pixel driver OPD: Detection pixel driver TFT_P: Light Emitting Transistor TFT_O: Photodetector TSTK1, TSTK2: 1st and 2nd stacks BSTK1, BSTK2: 1st and 2nd wiring stacks CEP1, CEP2, CEP3: 1st to 3rd connecting parts CNT1, CNT2, CNT3, CNT4: 1st to 4th contact holes CCE1, CCE2: First and second connecting electrodes

Claims

Claim 1 A display device comprising: a substrate; a device layer disposed on the substrate and including a light-emitting element and a light-receiving element; and a circuit layer disposed between the substrate and the device layer and including a light-emitting transistor electrically connected to the light-emitting element and a light-receiving transistor electrically connected to the light-receiving element, wherein the circuit layer comprises: a first stack including the light-emitting transistor; a first wiring stack disposed on the first stack and including a first wiring electrically connected to the light-emitting transistor; a second stack disposed on the first wiring stack and including the light-receiving transistor; and a second wiring stack disposed on the second stack and including a second wiring electrically connected to at least one of the light-emitting transistor and the light-receiving transistor. Claim 2 In claim 1, the light-receiving transistor is a display device that does not overlap with the light-emitting transistor in a horizontal direction perpendicular to the thickness direction of the substrate. Claim 3 In claim 1, the light-receiving transistor is a display device that overlaps with the light-emitting transistor in the thickness direction of the substrate. Claim 4 A display device according to claim 1, wherein the second wiring comprises a common application wiring electrically connected to both the light-emitting transistor and the light-receiving transistor. Claim 5 In paragraph 4, the common applied wiring comprises one end adjacent to the light-emitting transistor, the other end adjacent to the light-receiving transistor, and a connecting portion connecting the one end and the other end, forming a display device. Claim 6 In claim 5, the circuit layer further comprises a first contact hole penetrating the insulating film of each of the second stack and the first wiring stack, and a second contact hole penetrating the insulating film of the second stack, wherein the first contact hole electrically connects the first end and the light-emitting transistor, and the second contact hole electrically connects the other end and the light-receiving transistor, and the connecting portion is disposed between the first contact hole and the second contact hole. Claim 7 In paragraph 4, the common applied wiring comprises at least one of a reference voltage line, an initialization voltage line, a scan write line, and a low voltage power line, in a display device. Claim 8 A display device according to claim 1, wherein the light receiving transistor is not placed in the first stack and the light emitting transistor is not placed in the second stack. Claim 9 A substrate; a device layer disposed on the substrate and comprising a light-emitting element and a light-receiving element; and a circuit layer disposed between the substrate and the device layer, wherein the circuit layer comprises: a first active layer disposed on the substrate; a first gate layer disposed on the first active layer; a first source-drain layer disposed on the first gate layer; a second active layer disposed on the first source-drain layer; a second gate layer disposed on the second active layer; a second source-drain layer disposed on the second gate layer; a light-emitting transistor electrically connected to the light-emitting element and comprising a semiconductor region disposed on the first active layer, a first electrode, a second electrode, and a gate electrode disposed on the first gate layer; a light-receiving transistor electrically connected to the light-receiving element and comprising a semiconductor region disposed on the second active layer, a first electrode, a second electrode, and a gate electrode disposed on the second gate layer; and a first wiring disposed on the first source-drain layer and electrically connected to the light-emitting transistor. A display device comprising a second wiring disposed in the second source drain layer and electrically connected to at least one of the light-emitting transistor and the light-receiving transistor. Claim 10 In claim 9, the light-receiving transistor is a display device that does not overlap with the light-emitting transistor in a horizontal direction perpendicular to the thickness direction of the substrate. Claim 11 In claim 9, the light-receiving transistor is a display device that overlaps with the light-emitting transistor in the thickness direction of the substrate. Claim 12 In claim 9, the second wiring comprises a common application wiring electrically connected to both the light-emitting transistor and the light-receiving transistor, forming a display device. Claim 13 In claim 12, the common applied wiring comprises one end adjacent to the light-emitting transistor, the other end adjacent to the light-receiving transistor, and a connecting portion connecting the one end and the other end, forming a display device. Claim 14 In Clause 13, the common authorization wiring is a display device disposed in the second source drain layer. Claim 15 In claim 13, the circuit layer further comprises: a first connecting electrode disposed in the first source drain layer; a first contact hole penetrating insulating films disposed between the first source drain layer and the second source drain layer; and a second contact hole penetrating insulating films disposed between the second active layer and the second source drain layer, wherein the first contact hole electrically connects the one end and the light-emitting transistor, and the second contact hole electrically connects the other end and the light-receiving transistor, and the connecting portion is disposed between the first contact hole and the second contact hole. Claim 16 In paragraph 12, the common applied wiring comprises at least one of a reference voltage line, an initialization voltage line, a scan write line, and a low voltage power line, in a display device. Claim 17 A display device according to claim 9, wherein the light receiving transistor is not placed in the first stack and the light emitting transistor is not placed in the second stack. Claim 18 In claim 9, the circuit layer further comprises a first lower conductive layer disposed between the substrate and the first active layer, and a second lower conductive layer disposed between the first source drain layer and the second active layer. Claim 19 A display device according to claim 18, wherein the light-emitting transistor further comprises a lower gate electrode disposed in the first lower conductive layer, and the light-receiving transistor further comprises a lower gate electrode disposed in the second lower conductive layer. Claim 20 An electronic device comprising: a display device for displaying an image; a processor for providing an image driving signal to the display device; and a power module for supplying power to the display device and the processor, wherein the display device comprises: a substrate; a device layer disposed on the substrate and comprising a light-emitting element and a light-receiving element; and a circuit layer disposed between the substrate and the device layer and comprising a light-emitting transistor electrically connected to the light-emitting element and a light-receiving transistor electrically connected to the light-receiving element, wherein the circuit layer comprises: a first stack comprising the light-emitting transistor; a first wiring stack disposed on the first stack and comprising a first wiring electrically connected to the light-emitting transistor; a second stack disposed on the first wiring stack and comprising the light-receiving transistor; and a second wiring stack disposed on the second stack and comprising a second wiring electrically connected to at least one of the light-emitting transistor and the light-receiving transistor.

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