Display device, and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device comprises: a substrate including a display area in which light-emitting regions are arranged and a non-display area disposed around the display area; a device layer including light-emitting elements disposed in the light-emitting regions on the substrate; a sealing layer covering the device layer; a light path control layer disposed on the sealing layer; a first dam portion disposed in the non-display area and surrounding the display area; and a second dam portion disposed in the non-display area and surrounding the first dam portion. The non-display area includes a valley area disposed between the first dam portion and the second dam portion; and a softening area disposed around the second dam portion. The width of the softening area is greater than the width of the valley area.

Description

Technology Field

[0001] The present invention relates to a display device and an electronic device including the same. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat display device such as a Liquid Crystal Display Device, a Field Emission Display Device, or a Light Emitting Display Device. Here, the light emitting display device may include an organic light emitting display device comprising an organic light emitting element, an inorganic light emitting display device comprising an inorganic light emitting element such as an inorganic semiconductor, and a micro light emitting display device comprising a micro light emitting element.

[0004] Organic light-emitting display devices display images using light-emitting elements, each comprising a light-emitting layer of an organic light-emitting material. As such, since organic light-emitting display devices implement image display using self-emissive elements, they can possess relatively superior performance compared to other display devices in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle.

[0005] Among the display devices, the light-emitting display surface may include a display area where an image is displayed and a non-display area surrounding the display area. In the display area, light-emitting regions that emit light with respective brightness and color may be arranged. The problem to be solved

[0006] Electronic devices including display devices may include automotive electronic devices such as a Center Information Display (CID) installed on the dashboard of a vehicle.

[0007] Since automotive electronic devices must selectively provide information and / or content to the driver and / or passenger depending on the driving conditions of the vehicle, a display device embedded in the automotive electronic device may include an optical path control layer for controlling the viewing angle.

[0008] The optical path control layer may include a plurality of organic insulating layers.

[0009] Each of the multiple organic insulating layers can be prepared through a process of dropping and diffusing a liquid organic insulating material.

[0010] To prevent damage to the circuit layer, device layer, and sealing layer placed beneath the optical path control layer, monitoring of the placement status of the multiple organic insulating layers is necessary, as the placement process of the multiple organic insulating layers is difficult to include a process for selectively removing diffused organic insulating material.

[0011] Accordingly, the problem that the present invention aims to solve is to provide a display device capable of relatively easily inspecting the arrangement state of a plurality of organic insulating layers provided in an optical path control layer, and an electronic device including the same.

[0012] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0013] A display device according to one embodiment for solving the above problem comprises: a substrate including a display area in which light-emitting regions are arranged and a non-display area disposed around the display area; a device layer including light-emitting elements disposed in the light-emitting regions on the substrate; a sealing layer covering the device layer; a light path control layer disposed on the sealing layer; a first dam portion disposed in the non-display area and surrounding the display area; and a second dam portion disposed in the non-display area and surrounding the first dam portion. The non-display area includes a valley area disposed between the first dam portion and the second dam portion; and a softening area disposed around the second dam portion. The width of the softening area is greater than the width of the valley area.

[0014] The light path control layer may include two or more light output control layers that overlap with the display area in the thickness direction of the substrate; and at least one inspection mark disposed in the non-display area and adjacent to at least some of the edges of the substrate. Each of the two or more light output control layers may include light-shielding portions that overlap with the display area and are spaced apart from each other; a sub-insulating layer covering the light-shielding portions; and a main insulating layer disposed on the sub-insulating layer and comprising an organic insulating material. The at least one inspection mark may include two or more spaced-apart mark groups. Each of the two or more mark groups may include at least one valley mark disposed in the valley area; and one or more main marks disposed in the smoothing area. Each of the at least one valley mark and the one or more main marks may include spaced-apart intaglio portions. Each of the intaglio portions may be formed concavely in the sub-insulating layer.

[0015] Each of the above two or more light output control layers may further include a sub-insulating layer disposed between the light-blocking portions and the main insulating layer. Each of the sub-insulating layer and the main insulating layer may extend into the non-display area. The above two or more mark groups may be disposed in the sub-insulating layers of the above two or more light output control layers. The light path control layer may further include non-display light-blocking portions that overlap the non-display area and are disposed in the same layer as the light-blocking portions of each of the above two or more light output control layers. The non-display light-blocking portions and the main insulating layers of the above two or more light output control layers may extend into the non-display area.

[0016] The edge of the substrate may include two first sides facing in a first direction, two second sides facing in a second direction, and corners where one of the two first sides and one of the two second sides meet. One of the at least one inspection mark may be positioned adjacent to a part of the two first sides and one of the two second sides.

[0017] The edge of the substrate may include two first sides facing in a first direction, two second sides facing in a second direction, and corners where one of the two first sides and one of the two second sides meet. One of the at least one mark may be positioned adjacent to at least a part of one of the corners.

[0018] The above at least one inspection mark may be arranged in the form of a frame surrounding the periphery of the display area.

[0019] The optical path control layer may include two or more optical output control layers that overlap with the display area in the thickness direction of the substrate. The two or more optical output control layers may include a first optical output control layer disposed on the sealing layer; a second optical output control layer disposed on the first optical output control layer; and a third optical output control layer disposed on the second optical output control layer. The first optical output control layer may include first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer. The second optical output control layer may include second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; a second sub-insulating layer covering the second light-blocking portions; and a second main insulating layer disposed on the second sub-insulating layer. The third light output control layer may include third light-blocking portions that overlap with and are spaced apart from the first light-blocking portions and the second light-blocking portions, respectively; a third sub-insulating layer covering the third light-blocking portions; and a third main insulating layer disposed on the third sub-insulating layer. The first sub-insulating layer may cover the first dam and the second dam of the non-display area and extend into the smoothing area. In the smoothing area, the thickness of the first main insulating layer may gradually decrease as it approaches the edge of the substrate.

[0020] The optical path control layer may further include at least one inspection mark disposed in the non-display area and adjacent to at least a portion of the edges of the substrate. The at least one inspection mark may include a first mark group disposed in the first sub-insulating layer; a second mark group disposed in the second sub-insulating layer; and a third mark group disposed in the third sub-insulating layer. In one direction parallel to a portion of the edges of the substrate, the first mark group, the second mark group, and the third mark group may be spaced apart from each other. The first mark group may include at least one first valley mark disposed in the valley area and one or more first main marks disposed in the smoothing area. The second mark group may include at least one second valley mark disposed in the valley area and one or more second main marks disposed in the smoothing area. The third mark group may include at least one third valley mark disposed in the valley area and one or more third main marks disposed in the smoothing area. Each of the at least one first valley mark and each of the one or more first main marks may be formed concavely in the first sub-insulating layer. Each of the at least one second valley mark and each of the one or more second main marks may be formed concavely in the second sub-insulating layer. Each of the at least one third valley mark and each of the one or more third main marks may be formed concavely in the third sub-insulating layer.

[0021] The optical path control layer may further include: one or more first auxiliary dam layers arranged between the first sub-insulating layer and the edge of the substrate and disposed in the same layer as the first sub-insulating layer; one or more second auxiliary dam layers arranged between the second sub-insulating layer and the edge of the substrate and disposed in the same layer as the second sub-insulating layer; and one or more third auxiliary dam layers disposed in the same layer as the third sub-insulating layer and disposed in the same layer as the second sub-insulating layer. The at least one inspection mark may further include one or more first auxiliary marks disposed on the one or more first auxiliary dam layers; one or more second auxiliary marks disposed on the one or more second auxiliary dam layers; and one or more third auxiliary marks disposed on the one or more third auxiliary dam layers. The one or more first auxiliary marks, the one or more second auxiliary marks, and the one or more third auxiliary marks may be spaced apart from each other. Each of the above one or more first auxiliary marks, the above one or more second auxiliary marks, and the above one or more third auxiliary marks may include mutually spaced intaglio portions.

[0022] The optical path control layer may further include: one or more first auxiliary dam layers arranged between the first sub-insulating layer and the edge of the substrate and disposed in the same layer as the first sub-insulating layer; one or more second auxiliary dam layers arranged between the second sub-insulating layer and the edge of the substrate and disposed in the same layer as the second sub-insulating layer; and one or more third auxiliary dam layers disposed in the same layer as the third sub-insulating layer and the second sub-insulating layer. The one or more first auxiliary dam layers may be disposed on the sealing layer. The second sub-insulating layer may cover at least one of the one or more first auxiliary dam layers. The one or more second auxiliary dam layers may be disposed on the sealing layer. The third sub-insulating layer and the one or more third auxiliary dam layers may be disposed on the second main insulating layer.

[0023] The second sub-insulating layer and the one or more second auxiliary dam layers may be disposed on the first main insulating layer. The third sub-insulating layer and the one or more third auxiliary dam layers may be disposed on the second main insulating layer.

[0024] The light path control layer may include a first clad layer disposed on the sealing layer; a first light output control layer disposed on the first clad layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer. The first light output control layer may include first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer. The second light output control layer may include second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; a second sub-insulating layer covering the second light-blocking portions; and a second main insulating layer disposed on the second sub-insulating layer. The third light output control layer may include third light-blocking portions that overlap with and are spaced apart from the first light-blocking portions and the second light-blocking portions, respectively; It may include a second clad layer covering the third light-blocking portions; a lens layer disposed on the second clad layer; and a third main insulating layer covering the lens layer.

[0025] The light path control layer may further include: a first non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the first light-blocking parts; a second non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the second light-blocking parts; and a third non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the third light-blocking parts. The first main insulating layer may extend into the non-display area and may be in contact with the first non-display light-blocking part in the softening area. The second main insulating layer may extend into the non-display area and may be in contact with the second non-display light-blocking part in the softening area. The third main insulating layer may extend into the non-display area and overlap with the third non-display light-blocking part.

[0026] An electronic device according to one embodiment for solving the above problem includes: a display device for displaying an image; a memory for storing an application; a processor that executes the application and transmits an image data signal and an input control signal to the display device; and a power module that transmits power to the display device. The display device includes a substrate comprising a display area in which light-emitting regions are arranged and a non-display area disposed around the display area; a device layer comprising light-emitting elements disposed in the light-emitting regions on the substrate; a sealing layer covering the device layer; an optical path control layer disposed on the sealing layer; a first dam portion disposed in the non-display area and surrounding the display area; and a second dam portion disposed in the non-display area and surrounding the first dam portion. The optical path control layer includes two or more optical output control layers that overlap with the display area in the thickness direction of the substrate. The non-display area includes a valley area disposed between the first dam portion and the second dam portion; and a smoothing area disposed around the second dam portion. The width of the smoothing area is greater than the width of the valley area.

[0027] The above two or more light output control layers may include a first light output control layer disposed on the sealing layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer. The first light output control layer may include first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer. The second light output control layer may include second light-blocking portions that overlap with the first light-blocking portions; a second sub-insulating layer covering the second light-blocking portions; and a second main insulating layer disposed on the second sub-insulating layer. The third light output control layer may include third light-blocking portions that overlap with the first light-blocking portions and the second light-blocking portions; a third sub-insulating layer covering the third light-blocking portions; and a third main insulating layer disposed on the third sub-insulating layer. The first sub-insulating layer may cover the first dam and the second dam in the non-display area and extend into the smoothing area. In the smoothing area, the thickness of the first main insulating layer may gradually decrease as it approaches the edge of the substrate.

[0028] The optical path control layer may further include at least one inspection mark disposed in the non-display area and adjacent to at least a portion of the edges of the substrate. The at least one inspection mark may include a first mark group disposed in the first sub-insulating layer; a second mark group disposed in the second sub-insulating layer; and a third mark group disposed in the third sub-insulating layer. In one direction parallel to a portion of the edges of the substrate, the first mark group, the second mark group, and the third mark group may be spaced apart from each other. The first mark group may include at least one first valley mark disposed in the valley area between the first dam portion and the second dam portion, and one or more first main marks disposed in the smoothing area. The second mark group may include at least one second valley mark disposed in the valley area, and one or more second main marks disposed in the smoothing area. The third mark group may include at least one third valley mark disposed in the valley area, and one or more third main marks disposed in the smoothing area. Each of the at least one first valley mark and each of the one or more first main marks may be formed concavely in the first sub-insulating layer. Each of the at least one second valley mark and each of the one or more second main marks may be formed concavely in the second sub-insulating layer. Each of the at least one third valley mark and each of the one or more third main marks may be formed concavely in the third sub-insulating layer.

[0029] The light path control layer may include a first clad layer disposed on the sealing layer; a first light output control layer disposed on the first clad layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer. The first light output control layer may include first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer. The second light output control layer may include second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; a second sub-insulating layer covering the second light-blocking portions; and a second main insulating layer disposed on the second sub-insulating layer. The third light output control layer may include third light-blocking portions that overlap with and are spaced apart from the first light-blocking portions and the second light-blocking portions, respectively; It may include a second clad layer covering the third light-blocking portions; a lens layer disposed on the second clad layer; and a third main insulating layer covering the lens layer.

[0030] The light path control layer may further include: a first non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the first light-blocking parts; a second non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the second light-blocking parts; and a third non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the third light-blocking parts. The first main insulating layer may extend into the non-display area and may be in contact with the first non-display light-blocking part in the softening area. The second main insulating layer may extend into the non-display area and may be in contact with the second non-display light-blocking part in the softening area. The third main insulating layer may extend into the non-display area and overlap with the third non-display light-blocking part.

[0031] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0032] A display device according to one embodiment may include a device layer disposed on a substrate, a sealing layer covering the device layer, a light path control layer disposed on the sealing layer, and a first dam and a second dam that are disposed in a non-display area of ​​the substrate.

[0033] The substrate may include a display area where light-emitting regions are arranged, and a non-display area disposed around the display area.

[0034] The device layer may include light-emitting elements disposed in light-emitting regions on the substrate.

[0035] The non-displayed area may include a valley area positioned between the first dam section and the second dam section, and a softening area positioned around the second dam section.

[0036] The optical path control layer may include two or more optical output control layers that overlap with a display area in the thickness direction of the substrate, and at least one inspection mark disposed in a non-display area and adjacent to at least a portion of the edges of the substrate.

[0037] Each of the two or more light output control layers may include light-shielding portions that overlap with and are spaced apart from the display area, a sub-insulating layer covering the light-shielding portions and comprising an inorganic insulating material, and a main insulating layer disposed on the sub-insulating layer and comprising an organic insulating material.

[0038] At least one inspection mark may include two or more mark groups formed on the sub-insulating layer of each of two or more optical output control layers.

[0039] Each of the two or more mark groups may include at least one valley mark placed in the valley area and one or more main marks placed in the smoothing area.

[0040] Each of at least one valley mark and one or more main marks may include mutually spaced intaglio portions.

[0041] In this way, during the placement process of the main insulating layer, the engraved portions of the main mark hinder the diffusion of the liquid organic insulating material, so the edge of the main insulating layer may include a curvature caused by the main mark.

[0042] Thus, the visibility of the edges of the main insulating layers of two or more light output control layers can be improved by at least one inspection mark.

[0043] In addition, according to one embodiment, since the diffusion of the liquid organic insulating material is easily stopped in the softened region of the non-display area, the edges of the main insulating layers of two or more light output control layers can be arranged in a form that does not overlap each other.

[0044] Therefore, since the arrangement status of two or more main insulating layers provided in two or more optical output control layers can be easily inspected, the quality reliability of the display device can be improved and the defect rate can be reduced.

[0045] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0046] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a plan view showing a display device according to one embodiment. FIG. 3 is a schematic diagram of an electronic device according to one embodiment. Figure 4 is a cross-sectional view showing A-A' of Figure 2. FIGS. 5 and 6 are schematic diagrams showing part B of FIG. 2 according to one embodiment. FIG. 7 is a block diagram showing a display device according to one embodiment. FIG. 8 is an equivalent circuit diagram showing the light-emitting pixel driving unit of FIG. 7 according to one embodiment. FIG. 9 is a cross-sectional view showing C-C' of FIG. 6 according to one embodiment. FIG. 10 is a schematic diagram showing the viewing angle of a display device according to one embodiment. FIG. 11 is a plan view showing a display device according to one embodiment. FIG. 12 is a cross-sectional view showing D-D' of FIG. 11 according to one embodiment. FIGS. 13, FIGS. 14, FIGS. 15 and FIGS. 16 are plan views showing portion E of FIG. 11 according to one embodiment. Figure 17 is an enlarged view showing part F of Figure 15. Fig. 18 is a cross-sectional view showing G-G' of Fig. 17. FIGS. 19, FIGS. 20, FIGS. 21, FIGS. 22, and FIGS. 23 are each plan views showing a display device according to one embodiment. FIGS. 24 and FIGS. 25 are each cross-sectional views showing D-D' of FIGS. 11 according to one embodiment. FIG. 26 is a cross-sectional view showing C-C' of FIG. 6 according to one embodiment. FIG. 27 is a cross-sectional view showing D-D' of FIG. 11 according to one embodiment. FIG. 28 is a block diagram of an electronic device according to one embodiment. FIG. 29 is a schematic diagram of an electronic device according to various embodiments. Specific details for implementing the invention

[0047] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0048] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0049] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0050] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0051] Specific embodiments will be described below with reference to the attached drawings.

[0052] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a plan view showing a display device according to one embodiment.

[0053] Referring to FIGS. 1 and 2, a display device (10) according to one embodiment is a device for displaying video or still images, and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0054] The display device (10) may be any one of an organic light-emitting display device, a liquid crystal display device, a plasma display device, a field emission display device, an electrophoretic display device, an electrowetting display device, a quantum dot light-emitting display device, and a micro LED display device. In the following description, the display device (10) is described with an organic light-emitting display device, but the present invention is not limited thereto.

[0055] The display device (10) may include a flat-panel display panel (100) that emits light for image display, a display driving circuit (200) that generates data signals (Vdata of FIG. 8) corresponding to image signals, a circuit board (300) connected to pads of the display panel (100), and a touch driving circuit (500) that collects a detection signal for touch sensing.

[0056] The display panel (100) may include a rectangular side. However, this is merely an example, and the shape of the display panel (100) is not limited to the depiction in FIG. 1 and FIG. 2. That is, the display panel (100) according to one embodiment may include a side of various polygons, circles, and ellipses in addition to a rectangular side. Alternatively, at least part of the display panel (100) may be in an unfolded form and then deformed into a bent, curved, folded, or rolled form.

[0057] The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved surface formed at the left and right ends, having a constant curvature or a changing curvature.

[0058] In the illustrated drawings, the first direction (DR1) and the second direction (DR2) each intersect each other as horizontal directions. For example, the first direction (DR1) and the second direction (DR2) may be mutually orthogonal. Additionally, the third direction (DR3) intersects the first direction (DR1) and the second direction (DR2), and may be, for example, an orthogonal vertical direction. In this specification, the direction indicated by the first to third directions (DR1, DR2, DR3) in the drawings may be referred to as one side, and the opposite direction may be referred to as the other side; unless otherwise specified, both sides may be included. Unless otherwise defined, in this specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) may be referred to as one side, and the opposite direction may be referred to as the other side. Additionally, in this specification, “upper,” “upper side,” “top,” “top,” and “upper surface” refer to the direction in which the arrow of the drawing points among the third direction (DR3) based on the drawing, and “lower,” “lower side,” “lower,” “bottom,” and “lower surface” refer to the direction opposite to the direction in which the arrow of the third direction (DR3) points based on the drawing.

[0059] One side of the display panel (100) may include a display area (DA) from which light for image display is emitted, and a main area (MA) including a non-display area (NDA) placed around the display area (DA).

[0060] The display area (DA) can be placed in most of the main area (MA).

[0061] In the display area (DA), light-emitting areas (EA) that emit light with respective brightness and color may be arranged.

[0062] The non-display area (NDA) may be in the form of a frame surrounding the display area (DA) and does not emit light for image display. For example, the non-display area (NDA) may be maintained in a specific color, such as black.

[0063] The display panel (100) may include a protruding area (PA) extending from a portion of the edge of the main area (MA).

[0064] According to one embodiment, the protruding region (PA) may protrude from the lower side of the main region (MA). The length of the first direction (DR1) of the protruding region (PA) may be smaller than the length of the first direction (DR1) of the main region (MA).

[0065] The protruding area (PA) may include a bending area (BA) and a pad area (PDA).

[0066] The bending area (BA) is positioned between the main area (MA) and the pad area (PDA) and can be deformed into a bending shape.

[0067] When the bending area (BA) takes the form of a bend, the pad area (PDA) is placed on the back surface of the display panel (100) and can overlap with the main area (MA) in the third direction (DR3).

[0068] The display driving circuit (200) can be mounted on the pad area (PDA).

[0069] Pads to which the circuit board (300) is connected may be arranged in the pad area (PDA).

[0070] The display driving circuit (200) outputs signals and voltages for driving the display panel (100). For example, the display driving circuit (200) can supply data voltages to data lines (DL in FIG. 7 and FIG. 8).

[0071] The display driving circuit (200) is formed as an integrated circuit (IC) and can be mounted on the pad area (PDA) of the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method.

[0072] Alternatively, the display driving circuit (200) can be mounted on the circuit board (300).

[0073] The circuit board (300) can be attached to the pads using an anisotropic conductive film. As a result, the lead lines of the circuit board (300) can be electrically connected to the pads of the display panel (100). The circuit board (300) may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0074] The touch driving circuit (400) can be electrically connected to the touch sensor layer (150 in FIG. 4) of the display panel (100).

[0075] According to one embodiment, the touch driving circuit (400) can apply driving signals to the touch electrodes of the touch sensor layer (150 in FIG. 4) and measure the capacitance values ​​of the touch electrodes. The driving signal may be a signal having a plurality of driving pulses. The touch driving circuit (400) can determine whether a touch input is made based on the capacitance values, and can also calculate the touch coordinates where the touch is input.

[0076] The touch driving circuit (400) can be formed as an integrated circuit (IC) and mounted on the circuit board (300).

[0077] Alternatively, the touch driving circuit (400) can be embedded in the circuit board (300).

[0078] According to one embodiment, the display device (10) may include an optical path control layer (LCL) disposed on a display panel (100).

[0079] The optical path control layer (LCL) may include non-transmitting regions (LSA) that overlap with and are spaced apart from the display region (DA), and a transmitting region (OA) between the non-transmitting regions (LSA).

[0080] Light emitted from the display panel (100) can be selectively blocked by non-transmitting regions (LSA) and output to the outside through a transmitting region (OA).

[0081] Thus, the range in which light from the display panel (100) is visible (hereinafter referred to as "viewing angle") can be limited by the light path control layer (LSL).

[0082] FIGS. 1 and 2 illustrate a case where the non-transmitting regions (LSA) are rectangular and the transmitting regions (OA) are formed in the shape of slits. However, this is merely an example, and the transmitting regions (OA) may have a circular, elliptical, or polygonal shape in planar form.

[0083] The non-transparent regions (LSA) may extend in a first direction (DR1) or a second direction (DR2). For example, as illustrated in FIG. 1, the non-transparent regions (LSA) may extend in the first direction (DR1) and be positioned along the second direction (DR2). For another example, the non-transparent regions (LSA) may extend in the second direction (DR2) and be positioned along the first direction (DR1). For yet another example, some of the non-transparent regions (LSA) may extend in the first direction (DR1) and be positioned along the second direction (DR2), while the remaining portion of the non-transparent regions (LSA) may extend in the second direction (DR2) and be positioned along the first direction (DR1).

[0084] In one embodiment, as illustrated in FIG. 1, when non-transparent regions (LSA) are arranged along a second direction (DR2), the viewing angle can be controlled in the second direction (DR2). In another embodiment, when non-transparent regions (LSA) are arranged along a first direction (DR1), the viewing angle can be controlled in the first direction (DR1). In the display device (10) according to the present embodiment, the arrangement and shape of the transparent regions (OA) and non-transparent regions (LSA) can be varied according to the required viewing angle control direction.

[0085] Meanwhile, in the drawings, the transparent region (OA) is depicted as being arranged to surround the non-transparent region (LSA), but is not limited thereto. In some embodiments, the transparent region (OA) includes a plurality of transparent regions (OA), and the plurality of transparent regions (OA) extend in the same direction as the non-transparent regions (LSA), so that the plurality of transparent regions (OA) and non-transparent regions (LSA) may be arranged alternately. For example, as in FIG. 1, when the non-transparent regions (LSA) extend in a first direction (DR1), the plurality of transparent regions (OA) may extend in the first direction (DR1) and be arranged alternately with the non-transparent regions (LSA) in a second direction (DR2).

[0086] According to one embodiment, the light path control layer (LCL) can be placed directly on the display panel (100). By doing so, the thickness of the display device (10) can be reduced, and the manufacturing process of the display device (10) can be made relatively easier.

[0087] Alternatively, the light path control layer (LCL) may be provided in the form of a film and attached to the display panel (100) through a separate adhesive layer.

[0088] FIG. 3 is a schematic diagram of an electronic device according to one embodiment.

[0089] Referring to FIG. 3, an electronic device (20) according to one embodiment may be a device mounted on a vehicle.

[0090] The vehicle may include a vehicle body forming the exterior of the vehicle and an interior space defined by said vehicle body. said vehicle body may include a windshield (W) that protects the driver (PS1) and passenger (PS2) from the outside and provides a view to the driver (PS1). A display device (10) may be provided in said interior space as shown in the drawing.

[0091] According to one embodiment, the electronic device (20) may be placed on the dashboard in the interior space of the vehicle.

[0092] An electronic device (20) according to one embodiment may extend from a dashboard located in front of the driver's seat to a dashboard located in front of the passenger seat. That is, the electronic device (10) may be an integrated display connected from a dashboard located in front of the driver's seat to a dashboard located in front of the passenger seat.

[0093] In this case, the display area (DA) of the electronic device (10) may include a first display area (DA1) located in front of the driver's seat and a second display area (DA2) located in front of the passenger seat.

[0094] The first display area (DA1) is positioned on the dashboard in front of the driver's seat and can provide the driver (PS1) with vehicle operation information and navigation information, etc.

[0095] The second display area (DA2) is positioned on the dashboard in front of the passenger seat and can provide entertainment information, etc. to the passenger (PS2).

[0096] The electronic device (20) may further include a third display area positioned between the first display area (DA1) and the second display area (DA2).

[0097] According to another embodiment, the electronic device (20) may include a first display device positioned on the dashboard in front of the driver's seat and a second display device positioned on the dashboard in front of the passenger seat.

[0098] The driver (PS1) can recognize (or see) light (LGT0_1) emitted from the first display area (DA1) in front of the driver's seat toward the driver (PS1).

[0099] Meanwhile, some of the light (LGT1) emitted from the first display area (DA1) in front of the driver's seat may be reflected onto the surrounding windshield (W). In this case, the image reflected on the windshield (W) may interfere with the driving of the driver (PS1).

[0100] However, the display device (10) according to one embodiment includes a light path control layer (LCL) that limits the viewing angle, so that the emission direction of light (LGT0_1) emitted from a first display area (DA1) in front of the driver's seat can be limited to a front direction (a direction facing the driver (PS1)).

[0101] For example, the vertical viewing angle of light (LGT0_1) emitted from a first display area (DA1) in front of the driver's seat can be limited by the light path control layer (LCL), so that some of the light (LGT1) emitted from the first display area (DA1) in front of the driver's seat does not go toward the surrounding windshield (W). Accordingly, driver convenience can be improved.

[0102] The passenger (PS2) can perceive (or see) light (LGT0_2) emitted from the second display area (DA2) in front of the passenger seat toward the passenger (PS2). However, some of the light (LGT2) emitted from the second display area (DA2) in front of the passenger seat may be provided toward the driver (PS1). In this case, when the vehicle is in operation, the light (LGT0_2) emitted from the second display area (DA2) in front of the passenger seat interferes with the driver (PS1)'s control of the vehicle, so it is necessary to restrict the driver (PS1)'s viewing of the second display area (DA2).

[0103] A display device (10) according to one embodiment includes a light path control layer (LCL), so that the emission direction of light (LGT0_2) emitted from a second display area (DA2) in front of the passenger seat can be limited to a front direction (a direction facing the passenger (PS2)).

[0104] For example, the left and right viewing angles of the light (LGT0_2) emitted from the second display area (DA2) in front of the passenger seat can be limited by the light path control layer (LCL), so that the light (LGT0_2) emitted from the second display area (DA2) in front of the passenger seat may not be directed toward the driver. Therefore, a decrease in the safety of the vehicle caused by the electronic device (20) can be prevented.

[0105] The operation of the electronic device (20) of FIG. 3 is merely an example, and an embodiment is not limited to the illustration of FIG. 3. For example, the electronic device (20) may adjust the left and right viewing angles of light (LGT0_1) emitted from a first display area (DA1) in front of the driver's seat and the up and down viewing angles of light (LGT0_2) emitted from a second display area (DA2) in front of the passenger seat. For another example, the electronic device (20) may adjust both the up and down viewing angles and the left and right viewing angles of the first display area (DA1) and the second display area (DA2), respectively.

[0106] According to one embodiment, when a virtual line extending in a direction perpendicular to the display surface of the display device (10) and facing the driver (PS1) or passenger (PS2) is used as the normal, the viewing angle may be an angle within 35° from the normal. According to another embodiment, an angle within 35° from the normal may be defined as the effective viewing angle, but is not limited thereto.

[0107] Figure 4 is a cross-sectional view showing A-A' of Figure 2.

[0108] Referring to FIG. 4, a display device (10) according to one embodiment may include a substrate (110) including a display area (DA) and a non-display area (NDA), a device layer (130) disposed on the substrate (110), a sealing layer (140) covering the device layer (130), and an optical path control layer (LCL) disposed on the sealing layer (140).

[0109] A display device (10) according to one embodiment may further include a circuit layer (120) disposed on a substrate (110) and a touch sensor layer (150) disposed on a sealing layer (140). A device layer (130) may be disposed on the circuit layer (120), and an optical path control layer (LCL) may be disposed on the sealing layer (140).

[0110] Alternatively, the display device (10) may include a display panel (100) and an optical path control layer (LCL) disposed on the display panel (100).

[0111] And, the display panel (100) may include a substrate (110) including a display area (DA) and a non-display area (NDA), a circuit layer (120) disposed on the substrate (110), a device layer (130) disposed on the circuit layer (120), a sealing layer (140) covering the device layer (130), and a touch sensor layer (150) disposed on the sealing layer (140).

[0112] In the display area (DA), light-emitting areas (EA of FIG. 1) can be arranged.

[0113] The element layer (130) may include light-emitting elements (LEs in FIG. 8 and 9) disposed in light-emitting regions (EAs in FIG. 1) on the substrate (110).

[0114] The circuit layer (120) may include at least one semiconductor layer, two or more conductive layers, and insulating layers covering each of them.

[0115] The sealing layer (140) may have a structure comprising two or more inorganic insulating layers and at least one organic layer interposed between them.

[0116] Since the organic light-emitting material of the light-emitting elements (LE) of the element layer (130) can be sealed by the sealing layer (140), the deterioration of the light-emitting elements (LE) due to oxygen or moisture can be delayed or prevented.

[0117] The touch sensor layer (150) may include touch electrodes for detecting a user's touch in a capacitive manner and touch lines connecting the pads and the touch electrodes. For example, the touch sensor layer (150) may detect a user's touch in a self-capacitance manner or a mutual capacitance manner.

[0118] The touch electrodes of the touch sensor layer (150) can be placed in a touch sensor area that overlaps with the display area (DA). The touch lines of the touch sensor layer (150) can be placed in a touch peripheral area that overlaps with the non-display area (NDA).

[0119] The optical path control layer (LCL) can be superimposed on the display area (DA).

[0120] The light path control layer (LCL) can transmit some of the light emitted from the element layer (130) of the display panel (100) within a predetermined viewing angle range, and absorb or block the remaining light. Accordingly, the viewing angle of the display device (10) can be limited to a predetermined range by the light path control layer (LCL).

[0121] A display device (10) according to one embodiment may further include a cover window.

[0122] A cover window may be placed on an optical path control layer (LCL), in which case the optical path control layer (LCL) and the cover window may be attached by a transparent adhesive member such as an optically clear adhesive (OCA) film.

[0123] FIGS. 5 and 6 are schematic diagrams showing part B of FIG. 2 according to one embodiment.

[0124] As shown in FIG. 5, the display area (DA) may include light-emitting regions (EA) where light is emitted, and a non-light-emitting region (NEA) that is a spaced area between the light-emitting regions (EA) and where light is not emitted.

[0125] Each of the light-emitting regions (EA) may be a unit region that emits light of a wavelength band corresponding to one of two or more different colors with a brightness corresponding to an image signal.

[0126] Each of the light-emitting regions (EA) can be arranged in a square shape.

[0127] However, this is merely an example, and the planar shape of the light-emitting regions (EA) according to one embodiment is not limited to that shown in FIG. 5. That is, the light-emitting regions (EA) may have planar shapes other than rhombuses, such as polygons like rectangles, squares, hexagons, octagons, etc., as well as circular or elliptical shapes.

[0128] The light-emitting regions (EA) may include first light-emitting regions (EA1) that emit light of a first wavelength band, second light-emitting regions (EA2) that emit light of a second wavelength band lower than the first wavelength band, and third light-emitting regions (EA3) that emit light of a third wavelength band lower than the second wavelength band.

[0129] For example, the first wavelength band is about 600 nm to about 750 nm and may correspond to red. The second wavelength band is about 480 nm to about 560 nm and may correspond to green. The third wavelength band is about 370 nm to about 460 nm and may correspond to blue.

[0130] However, this is merely an example, and the first wavelength band, second wavelength band, and third wavelength band according to one embodiment are not limited thereto.

[0131] As the light-emitting regions (EA) include a first light-emitting region (EA1), a second light-emitting region (EA2), and a third light-emitting region (EA3), unit pixels can be provided by a combination of one or more mutually adjacent first light-emitting regions (EA1), one or more second light-emitting regions (EA2), and one or more third light-emitting regions (EA3) among the light-emitting regions (EA).

[0132] Each unit pixel can be a unit that displays various colors, including white. That is, the various colors of light displayed in each unit pixel can be realized by mixing light emitted from two or more light-emitting regions (EA) included in each unit pixel.

[0133] The third light-emitting region (EA3) may have a wider width than the first light-emitting region (EA1), and the first light-emitting region (EA1) may have a wider width than the second light-emitting region (EA2). However, this is merely an example, and the width of each of the light-emitting regions (EA) is not limited to the illustration in FIG. 5.

[0134] According to one embodiment, the circuit layer (120) may include light-emitting pixel drivers (EPDs) arranged in a first direction (DR1) and a second direction (DR2) in a display area (DA).

[0135] The device layer (130 in FIG. 4) may include light-emitting elements (LE in FIG. 8 and FIG. 9) respectively disposed in light-emitting regions (EA).

[0136] The light-emitting pixel drivers (EPDs) can be electrically connected to the light-emitting elements (LEs in FIG. 8 and FIG. 9), respectively.

[0137] As illustrated in FIG. 6, according to one embodiment, the light path control layer (LCL) may include non-transmitting regions (LSA) that overlap with and are spaced apart from each other and block light, a transmitting region (OA) that is positioned between the non-transmitting regions (LSA) and passes light, and light-blocking portions (LS) that overlap with the non-transmitting regions (LSA).

[0138] In other words, the transmission area (OA) may be an area that does not overlap with the light-blocking areas (LS).

[0139] A portion of each of the light-emitting regions (EA) overlaps with at least one of the non-transmitting regions (LSA) in the third direction (DR3), and another portion of each of the light-emitting regions (EA) may overlap with a transmitting region (OA) in the third direction (DR3).

[0140] FIG. 7 is a block diagram showing a display device according to one embodiment.

[0141] As illustrated in FIG. 7, a display device (10) according to one embodiment may include a display panel (100), a data driver (DTDR) that supplies data signals (Vdata in FIG. 8) to data lines (DL) of the display panel (100), a gate driver (GTDR) that supplies gate signals to gate lines (GL) of the display panel (100), a power supply unit (700) that supplies power and voltages to the display panel (100), and a timing control unit (800) that controls the driving timing of each of the data driver (DTDR) and the gate driver (GTDR).

[0142] The display panel (100) may include light-emitting pixel drivers (EPDs) electrically connected to light-emitting elements (LEs in FIG. 8 and 9) of the element layer (130 in FIG. 4), gate wiring (GLs) that transmit gate signals to the light-emitting pixel drivers (EPDs), and data wiring (DLs) that transmit data signals (Vdata in FIG. 8) to the light-emitting pixel drivers (EPDs).

[0143] Each of the gate signals is intended to control the turn-on-turn-off operation of at least one of two or more transistors each provided in the light-emitting pixel drivers (EPDs).

[0144] The data signals (Vdata) are intended to control the brightness of the light-emitting elements (LE) placed in the light-emitting regions (EA), respectively.

[0145] The timing control unit (800) receives a video signal supplied from outside the display device (10).

[0146] The timing control unit (800) can output image data (DATA) and a data control signal (DCS) to the data driving unit (DTDR).

[0147] The data driver (DTDR) can convert image data (DATA) into analog data voltages according to the data control signal (DCS) and output data signals (Vdata) to the data lines (DL).

[0148] The data driving unit (DTDR) can be embedded in a display driving circuit (200 in FIG. 1 and FIG. 2) formed by an integrated circuit (IC).

[0149] The timing control unit (800) can generate a scan control signal (SCS) to control the operation timing of the gate driver (GTDR).

[0150] The gate driver (GTDR) can generate gate signals according to the scan control signal (SCS) and output the gate signals to the gate wires (GL).

[0151] The gate signals may have pulses that vary to a first gate level voltage or a second gate level voltage.

[0152] The power supply unit (700) can supply various power sources and voltages required for driving the light-emitting pixel driving units (EPDs).

[0153] FIG. 8 is an equivalent circuit diagram showing the light-emitting pixel driving unit of FIG. 7 according to one embodiment.

[0154] As shown in FIG. 8, the light-emitting pixel driver (EPD) can be electrically connected between a first power line (VDL) that transmits a first power source (ELVDD) and one end of a light-emitting element (LE). The other end of the light-emitting element (LE) can be electrically connected to a second power line (VSL) that transmits a second power source (ELVSS).

[0155] The second power source (ELVSS) may have a lower voltage level than the first power source (ELVDD).

[0156] That is, the anode electrode of the light-emitting element (LE) is electrically connected to the light-emitting pixel driver (EPD), and the cathode electrode of the light-emitting element (LE) can be electrically connected to the second power source (ELVSS).

[0157] The light-emitting element (LE) may be an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (Quantum Dot LED) including a quantum dot light-emitting layer, a micro light-emitting diode (Micro LED), or an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor.

[0158] The light-emitting pixel driver (EPD) may include a first transistor (ST1) that generates a driving current for a light-emitting element (LE), one or more transistors (ST2, ST3) electrically connected to the first transistor (ST1), and one or more capacitors (C1).

[0159] The first transistor (ST1) can be electrically connected between the first power line (VDL) and the light-emitting element (LE).

[0160] The first electrode of the first transistor (ST1) can be electrically connected to the first power wiring (VDL).

[0161] The second electrode of the first transistor (ST1) can be electrically connected to the second node (N2) and the anode electrode of the light-emitting element (LE).

[0162] The first gate electrode of the first transistor (ST1) can be electrically connected to the first node (N1) and the second transistor (ST2).

[0163] The second gate electrode of the first transistor (ST1) can be electrically connected to the second node (N2).

[0164] The second transistor (ST2) can be electrically connected between the data line (DL) and the first node (N1).

[0165] The gate electrode of the second transistor (ST2) can be electrically connected to the scan write wire (GWL). That is, the second transistor (ST2) can be turned on by the scan write signal of the scan write wire (GWL).

[0166] When the second transistor (ST2) is turned on, the data signal (Vdata) of the data wiring (DL) can be transmitted to the first node (N1).

[0167] Due to the data signal (Vdata) transmitted to the first node (N1), the voltage difference between the gate electrode of the first transistor (ST1) and the first electrode of the first transistor (ST1), that is, the gate-source voltage difference, becomes the voltage difference between the first power supply (ELVDD) and the data signal (Vdata), and thus can become greater than the threshold voltage of the first transistor (ST1). Accordingly, as the first transistor (ST1) is turned on, a source-drain current of a magnitude corresponding to the data signal (Vdata) can be generated between the first electrode and the second electrode of the first transistor (ST1). And, the source-drain current of the first transistor (ST1) can be supplied as a driving current to the light-emitting element (LE).

[0168] Thus, since a driving current of a size corresponding to the data signal (Vdata) is supplied to the light-emitting element (LE), the light-emitting element (LE) can emit light of a brightness corresponding to the data signal (Vdata).

[0169] The first capacitor (C1) can be electrically connected between the first node (N1) and the second node (N2).

[0170] The first capacitor (C1) can be filled by a data signal (Vdata) transmitted to the first node (N1) through the turned-on second transistor (ST2).

[0171] Thus, due to the voltage filled in the first capacitor (C1), the potential of the first node (N1) can be maintained for a predetermined period.

[0172] The third transistor (ST3) can be electrically connected between the initialization voltage wiring (VIL) and the second node (N2).

[0173] The gate electrode of the third transistor (ST3) can be electrically connected to the scan initialization wire (GIL). That is, the third transistor (ST3) can be turned on by the scan initialization signal (GI) of the scan initialization wire (GIL).

[0174] When the third transistor (ST3) is turned on, the potential of the second node (N2), that is, the potential of the anode electrode of the light-emitting element (LE), can be initialized to the initial voltage (VINT) of the initial voltage wiring (VIL).

[0175] As shown in FIG. 8, according to one embodiment, each of the first, second, and third transistors (ST1, ST2, ST3) may be an N-type MOSFET. However, this is merely an example, and at least one of the first, second, and third transistors (ST1, ST2, ST3) may be a P-type MOSFET.

[0176] The light-emitting pixel driving unit (EPD) of the display device (10) according to one embodiment is not limited to the illustration in FIG. 8.

[0177] FIG. 9 is a cross-sectional view showing C-C' of FIG. 6 according to one embodiment.

[0178] As shown in FIG. 9, a display panel (100) of a display device (10) according to one embodiment may include a substrate (110), a circuit layer (120) disposed on the substrate (110), a device layer (130) disposed on the circuit layer (120), a sealing layer (140) disposed on the device layer (130), and a touch sensor layer (150) disposed on the sealing layer (140).

[0179] The substrate (110) may include a first base layer (111) and a second base layer (112) stacked in a third direction (DR3).

[0180] Each of the first base layer (111) and the second base layer (112) may be made of an insulating material such as glass, quartz, or polymer resin. Examples of polymer materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate may include a metal material.

[0181] The substrate (110) may further include a substrate buffer layer (113) disposed between the first base layer (111) and the second base layer (112).

[0182] The substrate buffer layer (113) is intended to block moisture or oxygen penetrating through the first base layer (111) and the second base layer (112).

[0183] The substrate buffer layer (113) may include a plurality of inorganic films stacked alternately. For example, each of the inorganic films of the substrate buffer layer (113) may be one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0184] The circuit layer (120) comprises a lower metal layer (BML) disposed on a substrate (110), a buffer layer (121) covering the lower metal layer (BML), a semiconductor layer disposed on the buffer layer (121) (including a channel portion (CH1) of a first transistor (ST1), a first electrode portion (E11) and a second electrode portion (E21)), a gate insulating layer (GI) covering the channel portion (CH1) of the semiconductor layer, a first gate conductive layer disposed on the gate insulating layer (GI) (including a first gate electrode (G1) of the first transistor (ST1)), a first interlayer insulating layer (122) covering the semiconductor layer and the first gate conductive layer, a second gate conductive layer (including a capacitor electrode (CAE)) disposed on the first interlayer insulating layer (122), a second interlayer insulating layer (123) covering the second gate conductive layer, and a first source-drain conductive layer (first anode connection) disposed on the second interlayer insulating layer (123). It may include an electrode (ANCE1), a first flattening layer (124) covering a first source-drain conductive layer, a second source-drain conductive layer (including a second anode connection electrode (ANCE2)) disposed on the first flattening layer (124), and a second flattening layer (125) covering the second source-drain conductive layer.

[0185] Each of the buffer layer (121), gate insulating layer (GI), first interlayer insulating layer (122), and second interlayer insulating layer (123) may include an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0186] Each of the lower metal layer (BML), the first gate conductive layer (including the first gate electrode (G1) of the first transistor (ST1)), and the second gate conductive layer (including the capacitor electrode (CAE)) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0187] The lower metal layer (BML) is intended to prevent leakage current from occurring in the channel portion (CH1) of the first transistor (ST1) due to light incident through the substrate (110). The lower metal layer (BML) may overlap with the channel portion (CH1) of the first transistor (ST1) in a third direction (DR3).

[0188] The semiconductor layer (including the channel portion (CH1) of the first transistor (ST1), the first electrode portion (E11) and the second electrode portion (E21)) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0189] The channel portion (CH1) of the first transistor (ST1) among the semiconductor layers is overlapped with the gate insulating layer (GI) and the first gate electrode (G1) to maintain semiconductor properties, and the remainder excluding the channel portion (CH1) of the first transistor (ST1) can have conductivity through impurity or ion doping.

[0190] That is, the first electrode portion (E11) and the second electrode portion (E21) of the first transistor (ST1) in the semiconductor layer may have conductivity.

[0191] The first gate electrode (G1) of the first transistor (ST1) placed on the first gate conductive layer can overlap with the channel portion (CH1) of the first transistor (ST1) in the third direction (DR3).

[0192] The capacitor electrode (CAE) placed on the second gate conductive layer can overlap with the first gate electrode (G1) of the first transistor (ST1) in the third direction (DR3).

[0193] Each of the first source-drain conductive layer (including the first anode connecting electrode (ANCE1)) and the second source-drain conductive layer (including the second anode connecting electrode (ANCE2)) disposed on the first flattening layer (124) may be formed as a multilayer including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0194] Each of the first flattening layer (124) and the second flattening layer (125) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0195] The first anode connection electrode (ANCE1) disposed on the first source drain conductive layer can be electrically connected to the second electrode portion (E21) of the first transistor (ST1) through the first anode connection hole (ANCH1).

[0196] The second anode connecting electrode (ANCE2) disposed on the second source drain conductive layer can be electrically connected to the first anode connecting electrode (ANCE1) through the second anode connecting hole (ANCH2).

[0197] The element layer (130) can be placed on the second flattening layer (125).

[0198] The device layer (130) may include first electrodes (131) disposed in light-emitting regions (EA), a pixel defining layer (132) disposed in a non-light-emitting region (NEA) and covering the edges of the first electrodes (131), light-emitting layers (133) disposed on the first electrodes (131), and a second electrode (134) disposed on the pixel defining layer (132) and the light-emitting layers (133).

[0199] Each of the light-emitting elements (LE) of the light-emitting regions (EA) can be formed with a structure in which a light-emitting layer (134) is interposed between mutually opposing first electrode (131) and second electrode (134).

[0200] The first electrode (131) is placed on the second flattening layer (125) and can be electrically connected to the second anode connecting electrode (ANCE2) through the third anode connecting hole (ANCH3).

[0201] Thus, the first electrode (131) can be electrically connected to the second electrode portion (E21) of the first transistor (ST1) through the first anode connection electrode (ANCE1) and the second anode connection electrode (ANCE2).

[0202] The first electrodes (131) are each placed in the light-emitting regions (EA) and are each electrically connected to the light-emitting pixel drivers (EPDs), so they can be referred to as pixel electrodes or anode electrodes.

[0203] The second electrode (134) may be placed over the entire display area (DA), including light-emitting regions (EA) and non-light-emitting regions (NEA), and may be referred to as a common electrode or cathode electrode since it is shared with light-emitting elements (LE). Alternatively, the second electrode (134) may be part of the second power wiring (VSL in FIG. 8).

[0204] The device layer (130) may further include a first common layer disposed between the first electrode (131) and the light-emitting layer (133), and a second common layer disposed between the light-emitting layer (133) and the second electrode (134).

[0205] The first common layer may include a hole transport layer. Alternatively, the first common layer may further include a hole injection layer.

[0206] The second common layer may include an electron transport layer. Alternatively, the second common layer may further include an electron injection layer.

[0207] Each of the light-emitting layers (133) may include an organic light-emitting material.

[0208] The pixel definition layer (132) may include an organic insulating material.

[0209] The sealing layer (140) may include a first sealing layer (141) disposed on the element layer (130) and comprising an inorganic insulating material, a second sealing layer (142) disposed on the first sealing layer (141) and comprising an organic insulating material, and a third sealing layer (143) covering the second sealing layer (142) and comprising an inorganic insulating material.

[0210] For example, the first sealing layer (141) and the third sealing layer (143) may each be formed as a single layer or a multilayer including at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0211] The second sealing layer (142) may include a polymer-based organic insulating material. Polymer-based materials may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.) or any combination thereof.

[0212] The touch sensor layer (150) may be disposed on the sealing layer (140). The touch sensor layer (150) may include touch electrodes for detecting a signal that varies according to the touch of a person or object and for sensing the point on the display surface where the touch of the person or object occurred.

[0213] The touch sensor layer (150) may include a first touch insulating layer (151) disposed on a sealing layer (140), a first touch electrode (REL) disposed on the first touch insulating layer (151), a second touch insulating layer (152) covering the first touch electrode (REL), a second touch electrode (TEL) disposed on the second touch insulating layer (152), a third touch insulating layer (153) covering the second touch electrode (TEL), and a touch flattening layer (154) covering the third touch insulating layer (153).

[0214] Each of the first touch insulating layer (151), the second touch insulating layer (152), and the third touch insulating layer (153) may comprise an inorganic insulating material. However, this is merely an example, and at least one of the first touch insulating layer (151), the second touch insulating layer (152), and the third touch insulating layer (153) may comprise an organic insulating material.

[0215] The touch flattening layer (154) may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0216] According to one embodiment, the optical path control layer (LCL) may include two or more optical output control layers (160) that overlap with the display area (DA in FIG. 4) in the third direction (DR3).

[0217] Each of the two or more light output control layers (160) may include light-blocking portions (LS) that overlap with and are spaced apart from the display area (DA), a sub-insulating layer (SBI) covering the light-blocking portions (LS), and a main insulating layer (MNI) disposed on the sub-insulating layer (SBI).

[0218] According to one embodiment, the sub-insulating layer (SBI) may include an inorganic insulating material.

[0219] Alternatively, the sub-insulating layer (SBI) and the main insulating layer (MNI) may each include an organic insulating material.

[0220] For example, a sub-insulating layer (SBI) can be placed through a process of partially etching the organic insulating material stacked by vapor deposition.

[0221] According to one embodiment, the main insulating layer (MNI) can be placed through a process of diffusing an organic insulating material dropped by an inkjet printing method.

[0222] According to one embodiment, two or more light output control layers (160) may include a first light output control layer (161) disposed on a sealing layer (140) of a display panel (100), a second light output control layer (162) disposed on the first light output control layer (161), and a third light output control layer (163) disposed on the second light output control layer (162).

[0223] The first light output control layer (161) may include first light-blocking portions (1611) that overlap with and are spaced apart from the display area (DA), a first sub-insulating layer (1612) covering the first light-blocking portions (1611), and a first main insulating layer (1613) disposed on the first sub-insulating layer (1612).

[0224] The second light output control layer (162) may include second light-blocking sections (1621) that overlap with the first light-blocking sections (1611), a second sub-insulating layer (1622) covering the second light-blocking sections (1621), and a second main insulating layer (1623) disposed on the second sub-insulating layer (1622).

[0225] The third light output control layer (163) may include third light-blocking sections (1631) that overlap with the first light-blocking sections (1611) and the second light-blocking sections (1621), a third sub-insulating layer (1632) covering the third light-blocking sections (1631), and a third main insulating layer (1633) disposed on the third sub-insulating layer (1632).

[0226] In other words, when two or more light output control layers (160) include a first light output control layer (161), a second light output control layer (162), and a third light output control layer (163), the light-blocking portions (LS) of the two or more light output control layers (160) may include first light-blocking portions (1611), second light-blocking portions (1621), and third light-blocking portions (1631).

[0227] And, the sub-insulating layers (SBI) of the two or more optical output control layers (160) include a first sub-insulating layer (1612), a second sub-insulating layer (1622), and a third sub-insulating layer (1632), and the main insulating layers (MNI) of the two or more optical output control layers (160) may include a first main insulating layer (1613), a second main insulating layer (1623), and a third main insulating layer (1633).

[0228] The light-blocking sections (LS) overlap with non-transmitting regions (LSA) and may include a material that blocks or absorbs light.

[0229] For example, each of the light-blocking parts (LS) may include an organic black pigment, such as carbon black, as a photosensitive resin.

[0230] The sub-insulating layers (SBI) may include inorganic insulating materials such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0231] The main insulating layers (MNI) may include at least one organic insulating material selected from propylene glycol methyl ether acetate, methacrylic acid-benzylmethacrylic acid copolymer, multi-functional acrylate, and photoinitiator.

[0232] As another example, the sub-insulating layers (SBI) and the main insulating layers (MNI) each may comprise at least one organic insulating material selected from propylene glycol methyl ether acetate, methacrylic acid-benzylmethacrylic acid copolymer, multi-functional acrylate, and photoinitiator.

[0233] According to one embodiment, the optical path control layer (LCL) may further include at least one clad layer (CLD) disposed on the display panel (100).

[0234] At least one of the clad layers (CLD) can be disposed between two or more light output control layers (160) and the display panel (100). That is, two or more light output control layers (160) can be disposed on one clad layer (CLD).

[0235] At least one clad layer (CLD) may include an inorganic insulating material.

[0236] For example, at least one clad layer (CLD) may include an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide.

[0237] According to one embodiment, the optical path control layer (LCL) may further include an overcoat layer (OC) covering two or more optical output control layers (160).

[0238] The overcoat layer (OC) contains an organic insulating material and can be laid relatively flat.

[0239] Alternatively, to improve the light efficiency of the display device (10), the overcoat layer (OC) of the light path control layer (LCL) may be omitted.

[0240] FIG. 10 is a schematic diagram showing the viewing angle of a display device according to one embodiment.

[0241] As shown in Fig. 10, light generated by the element layer (130) of the display panel (100) can be emitted at a light emission angle (θ1) corresponding to the width of the light emission area (EA), etc.

[0242] According to one embodiment, the display device (10) includes an optical path control layer (LCL) disposed on a display panel (100).

[0243] The optical path control layer (LCL) includes two or more sequentially stacked optical output control layers (161, 162, 163), and each of the two or more optical output control layers (161, 162, 163) includes light-blocking portions (LS) superimposed on a non-transmitting region (LSA).

[0244] Accordingly, since light emitted from the element layer (130) of the display panel (100) can be selectively transmitted through the transmission area (OA) between the non-transmission area (LSA), the viewing angle of the display device (10) can be limited to a range corresponding to the width of the transmission area (OA) and the spacing between two or more light output control layers (161, 162, 163).

[0245] Thus, the viewing angle of the display device (10) can be smaller than the light emission angle (θ1).

[0246] According to one embodiment, the viewing angle of the display device (10) may be about 15 degrees or less.

[0247] According to one embodiment, the process of placing main insulating layers (MNI) may include a process of dropping a liquid organic insulating material through an inkjet printing process or the like, and a process of widely spreading the dropped liquid organic insulating material.

[0248] If the amount of liquid organic insulating material dropped is excessive, the main insulating layers (MNI) overlap with the cutting line for individual separation of the device, so the quality reliability of the display device (10) may be reduced.

[0249] In addition, to prevent unnecessary damage to the display panel (100), the process of placing the main insulating layers (MNI) is difficult to include a process of selectively removing organic insulating material that has diffused beyond a critical range.

[0250] Therefore, a monitoring process for the placement status of the main insulation layers (MNI) needs to be carried out.

[0251] Accordingly, each of the following embodiments provides a display device (10) in which visibility of the edges of the main insulating layers (MNI) can be improved so as to relatively easily inspect the arrangement state of the main insulating layers (MNI).

[0252] FIG. 11 is a plan view showing a display device according to one embodiment.

[0253] As illustrated in FIG. 11, a display device (10) according to one embodiment may include an optical path control layer (LCL) disposed on a display panel (100), a first damper (DM1) disposed in a non-display area (NDA) and surrounding a display area (DA), and a second damper (DM2) surrounding the first damper (DM1).

[0254] The first dam portion (DM1) and the second dam portion (DM2) are intended to limit the placement range of the second sealing layer (142 in FIG. 9) of the sealing layer (140 in FIG. 9).

[0255] The light path control layer (LCL) may include light-blocking sections (LS) placed in non-transmitting regions (LSA).

[0256] According to one embodiment, the optical path control layer (LCL) may include at least one inspection mark (TID) disposed in a non-display area (NDA) and adjacent to at least a portion of the edges of the substrate (110).

[0257] For reference, in this specification, the edge of the substrate (110) may refer to the edge of the main region (MA) of the substrate (110).

[0258] According to one embodiment, the edge of the substrate (110) may include two first sides (SD1) facing in a first direction (DR1), two second sides (SD2) facing in a second direction (DR2), and corners (CRN) where one of the two first sides (SD1) and one of the two second sides (SD2) meet.

[0259] According to one embodiment, the corners (CRN) may be curved.

[0260] According to one embodiment of FIG. 11, at least one inspection mark (TID) may be placed adjacent to a part of each of the two first sides (SD1).

[0261] FIG. 12 is a cross-sectional view showing D-D' of FIG. 11 according to one embodiment.

[0262] Referring to FIG. 12, a display device (10) according to one embodiment may include a substrate (110) including a display area (DA in FIG. 11) and a non-display area (NDA), a device layer (130) disposed on the substrate (110), a sealing layer (140) covering the device layer (130), an optical path control layer (LCL) disposed on the sealing layer (140), a first damper (DM1) disposed in the non-display area (NDA) and surrounding the display area (DA), and a second damper (DM2) disposed in the non-display area (NDA) and surrounding the first damper (DM1).

[0263] According to one embodiment, the optical path control layer (LCL) may include two or more optical output control layers (160) that overlap with the display area (DA in FIG. 4) in the third direction (DR3).

[0264] Two or more light output control layers (160) may include a first light output control layer (161) disposed on a sealing layer (140) of a display panel (100), a second light output control layer (162) disposed on the first light output control layer (161), and a third light output control layer (163) disposed on the second light output control layer (162).

[0265] The first light output control layer (161) may include a first sub-insulating layer (1612) covering the first light-blocking portions (1611 in FIG. 9), and a first main insulating layer (1613) disposed on the first sub-insulating layer (1612).

[0266] The second light output control layer (162) may include a second sub-insulating layer (1622) covering the second light-blocking portions (1621 in FIG. 9), and a second main insulating layer (1623) disposed on the second sub-insulating layer (1622).

[0267] The third light output control layer (163) may include a third sub-insulating layer (1632) covering the third light-blocking portions (1631 in FIG. 9), and a third main insulating layer (1633) disposed on the third sub-insulating layer (1632).

[0268] According to one embodiment, the optical path control layer (LCL) may further include one or more first auxiliary dam layers (ADL1) arranged between the first sub-insulating layer (1612) and the edge of the substrate (110) (i.e., the first side (SD1)) and disposed in the same layer as the first sub-insulating layer (1612), one or more second auxiliary dam layers (ADL2) arranged between the second sub-insulating layer (1622) and the edge of the substrate (110) (the first side (SD1) in FIG. 11) and disposed in the same layer as the second sub-insulating layer (1622), and one or more third auxiliary dam layers (ADL3) arranged between the third sub-insulating layer (1632) and the edge of the substrate (110) (the first side (SD1) in FIG. 11) and disposed in the same layer as the third sub-insulating layer (1632).

[0269] According to one embodiment, the non-display area (NDA) may include a valley area (VLA) positioned between the first dam section (DM1) and the second dam section (DM2), and a softening area (SLDA) positioned around the second dam section (DM2).

[0270] According to one embodiment, the first sub-insulating layer (1612) may cover the first dam (DM1) and the second dam (DM2) of the non-display area (NDA) and extend into the softened area (SLDA).

[0271] That is, the first sub-insulating layer (1612) can overlap with the valley region (VLA) and the softened region (SLDA).

[0272] The thickness of the first main insulating layer (1613) on the first sub-insulating layer (1612) is primarily reduced in the valley region (VLA) and gradually reduced as it approaches the edge of the substrate (110) in the smoothing region (SLDA) so as to converge to a minimum thickness.

[0273] The softened region (SLDA) can be spaced apart from the edge of the substrate (110) (i.e., the first side (SD1)).

[0274] For example, the easing zone (SLDA) may be spaced apart from one or more first auxiliary dam layers (ADL1).

[0275] According to one embodiment, the width (W1) of the smoothed region (SLDA) may be larger than the width (W2) of the valley region (VLA).

[0276] For example, the width (W1) of the softened region (SLDA) may be about 80 μm or more.

[0277] In this way, during the process of widely diffusing the liquid organic insulating material while laying the main insulating layers (MNI), the diffusion of the organic insulating material is primarily slowed down in the valley region (VLA) and can be relatively easily stopped by the flat surface of the smoothing region (SLDA).

[0278] Thus, the placement range of the main insulating layers (MNI) can be relatively easily limited even if the process of placing the main insulating layers (MNI) does not include a process of selectively removing the organic insulating material.

[0279] Therefore, the quality reliability and defect rate of the display device (10) can be improved.

[0280] One or more first auxiliary dam layers (ADL1) may be auxiliary means for preventing the second main insulating layer (1623) and the third main insulating layer (1633) from coming into contact with the edge (i.e., the first side (SD1)) of the substrate (110) by forming valleys between the first sub-insulating layer (1612) and one or more first auxiliary dam layers (ADL1).

[0281] According to one embodiment, the minimum spacing (W4) between the softening area (SLDA) and one or more first auxiliary dam layers (ADL1) may be greater than the width (W3) of one of the first auxiliary dam layers (ADL1).

[0282] One or more second auxiliary dam layers (ADL2) may be auxiliary means for preventing the third main insulating layer (1633) from coming into contact with the edge of the substrate (110) (first side (SD1) in FIG. 11) by forming valleys between the second sub-insulating layer (1622) and one or more second auxiliary dam layers (ADL2). One or more third auxiliary dam layers (ADL3) may be auxiliary means for preventing the third main insulating layer (1633) from coming into contact with the edge of the substrate (110) (first side (SD1) in FIG. 11) by forming valleys between the third sub-insulating layer (1632) and one or more third auxiliary dam layers (ADL3).

[0283] According to one embodiment, one or more first auxiliary dam layers (ADL1) may be disposed on the sealing layer (140).

[0284] According to one embodiment, the second sub-insulating layer (1622) may cover at least one of the first main insulating layer (1613) and one or more first auxiliary dam layers (ADL1).

[0285] As another example, one of the one or more second auxiliary dam layers (ADL2) may be placed on the other of the one or more first auxiliary dam layers (ADL1).

[0286] According to one embodiment, the third sub-insulating layer (1632) can cover the second main insulating layer (1623).

[0287] The third sub-insulating layer (1632) may cover at least one of one or more first auxiliary dam layers (ADL1) or at least one of one or more second auxiliary dam layers (ADL2).

[0288] One of the one or more third auxiliary dam layers (ADL3) may be placed on another of the one or more first auxiliary dam layers (ADL1) or another of the one or more second auxiliary dam layers (ADL2).

[0289] According to one embodiment, the overcoat layer (OC) of the optical path control layer (LCL) can cover the third main insulating layer (1633).

[0290] FIGS. 13, FIGS. 14, FIGS. 15 and FIGS. 16 are plan views showing portion E of FIG. 11 according to one embodiment. FIG. 17 is an enlarged view showing portion F of FIG. 15. FIG. 18 is a cross-sectional view showing G-G' of FIG. 17.

[0291] FIG. 13 illustrates an example of the first light output control layer (161) and the inspection mark (TID) in part E of FIG. 11.

[0292] FIG. 14 illustrates an example of the second optical output control layer (162) and the inspection mark (TID) in part E of FIG. 11.

[0293] FIG. 15 illustrates an example of the third optical output control layer (163) and inspection mark (TID) in part E of FIG. 11.

[0294] FIG. 16 illustrates an example of the edges of the main insulating layers (MNI) in part E of FIG. 11.

[0295] As shown in FIG. 11, the light path control layer (LCL) of the display device (10) according to one embodiment may include at least one inspection mark (TID).

[0296] As illustrated in FIGS. 13, 14 and 15, at least one inspection mark (TID) may include two or more spaced-apart mark groups (MG1, MG2, MG3) disposed on the sub-insulating layers (1612, 1622, 1623) of each of two or more optical output control layers (161, 162, 163).

[0297] Each of the two or more mark groups (MG1, MG2, MG3) may include at least one valley mark (VLM1, VLM2, VLM3) placed in the valley region (VLA), and one or more main marks (MNM1, MNM2, MNM3) placed in the smoothed region (SLDA).

[0298] Each of at least one valley mark (VLM1, VLM2, VLM3) and one or more main marks (MNM1, MNM2, MNM3) may include mutually spaced intaglio portions (INT1, INT2, INT3 of FIG. 17 and FIG. 18).

[0299] Each of the intaglio portions (INT1, INT2, INT3 in FIG. 17 and FIG. 18) can be formed concavely in the sub-insulating layer (1612, 1622, 1623).

[0300] When two or more light output control layers (160) include a first light output control layer (161), a second light output control layer (162), and a third light output control layer (163), at least one inspection mark (TID) may include a first mark group (MG1 in FIG. 13, 14, and 15) disposed on the first sub-insulating layer (1612) of the first light output control layer (161), a second mark group (MG2 in FIG. 14 and 15) disposed on the second sub-insulating layer (1622) of the second light output control layer (162), and a third mark group (MG3 in FIG. 15) disposed on the third sub-insulating layer (1632) of the third light output control layer (163).

[0301] As shown in FIG. 15, in one direction (the second direction (DR2) in FIG. 15) parallel to some of the edges of the substrate (110), the first mark group (MG1), the second mark group (MG2), and the third mark group (MG3) may be spaced apart from each other.

[0302] In this way, as illustrated in FIG. 16, the deformation portion of the edge of the first main insulating layer (1613) by the first mark group (MG1), the deformation portion of the edge of the second main insulating layer (1623) by the second mark group (MG2), and the deformation portion of the edge of the third main insulating layer (1633) by the third mark group (MG3) can be spaced apart from one another in one direction (the second direction (DR2) in FIG. 15). Therefore, according to one embodiment, the identification of each of the first main insulating layer (1613), the second main insulating layer (1623), and the third main insulating layer (1633) can be facilitated by at least one inspection mark (TID).

[0303] As shown in FIG. 13, the first mark group (MG1) corresponding to the first sub-insulating layer (1612) may include at least one first valley mark (VLM1) placed in the valley region (VLA) and one or more first main marks (MNM1) placed in the smoothing region (SLDA).

[0304] At least one first valley mark (VLM1) and one or more first main marks (MNM1) may be arranged parallel to each other in one direction parallel to some of the edges of the substrate (110) (second direction (DR2) in FIG. 13) and in another direction perpendicular to it (first direction (DR1) in FIG. 13).

[0305] Since the width of the smoothed region (SLDA) (W1 in FIG. 12) is greater than the width of the valley region (VLA) (W2 in FIG. 12), the number or spacing of one or more first main marks (MNM1) may be greater than the number or spacing of at least one first valley mark (VLM1).

[0306] Since the surface tension of the first sub-insulating layer (1612) is varied by the first intaglio portions (INT1 in FIG. 17 and FIG. 18) of the first mark group (MG1), the diffusion pattern of the organic insulating material during the placement process of the first main insulating layer (1613) may include a deformation corresponding to the first mark group (MG1). Accordingly, the edge of the first main insulating layer (1613) on the first sub-insulating layer (1612) may include a deformation portion caused by the first mark group (MG1).

[0307] According to one embodiment, at least one inspection mark (TID) may further include one or more first auxiliary marks (ADM1) placed on one or more first auxiliary dam layers (ADL1).

[0308] One or more first auxiliary marks (ADM1) may be arranged in parallel with at least one first valley mark (VLM1) and one or more first main marks (MNM1) in another direction (the first direction (DR1) of FIG. 13).

[0309] As shown in FIG. 14, the second mark group (MG2) corresponding to the second sub-insulating layer (1622) may include at least one second valley mark (VLM2) placed in the valley region (VLA) and one or more second main marks (MNM2) placed in the smoothing region (SLDA).

[0310] At least one second valley mark (VLM2) and one or more second main marks (MNM2) can be arranged side by side in another direction (the first direction (DR1) of FIG. 14).

[0311] Since the width of the smoothed region (SLDA) (W1 in FIG. 12) is greater than the width of the valley region (VLA) (W2 in FIG. 12), the number or spacing of one or more second main marks (MNM2) may be greater than the number or spacing of at least one second valley mark (VLM2).

[0312] Since the surface tension of the second sub-insulating layer (1622) is varied by the second intaglio portion (INT2 in FIG. 17 and 18) of the second mark group (MG2), the edge of the second main insulating layer (1623) on the second sub-insulating layer (1622) may include a deformation portion by the second mark group (MG2).

[0313] According to one embodiment, the second sub-insulating layer (1622) may further cover at least one first auxiliary dam layer (ADL1) adjacent to the first sub-insulating layer (1612) among one or more first auxiliary dam layers (ADL1).

[0314] The second mark group (MG2) may further include at least one second sub-mark (SBM2) formed in a portion that overlaps with at least one first auxiliary dam layer (ADL1) among the second sub-insulating layers (1622).

[0315] At least one second sub-mark (SBM2) may be arranged in parallel with at least one second valley mark (VLM2) and one or more second main marks (MNM2) in another direction (the first direction (DR1) of FIG. 14).

[0316] According to one embodiment, at least one inspection mark (TID) may further include one or more second auxiliary marks (ADM2) placed on one or more second auxiliary dam layers (ADL2).

[0317] One or more second auxiliary marks (ADM2) may be arranged in parallel with at least one second valley mark (VLM2) and one or more second main marks (MNM2) in another direction (the first direction (DR1) of FIG. 14).

[0318] As shown in FIG. 15, the third mark group (MG3) corresponding to the third sub-insulating layer (1632) may include at least one third valley mark (VLM3) placed in the valley region (VLA) and one or more third main marks (MNM3) placed in the softening region (SLDA).

[0319] At least one third valley mark (VLM3) and one or more third main marks (MNM3) may be arranged side by side in another direction (third direction (DR1) of FIG. 15).

[0320] Since the width of the smoothed region (SLDA) (W1 in FIG. 12) is greater than the width of the valley region (VLA) (W2 in FIG. 12), the number or spacing of one or more third main marks (MNM3) may be greater than the number or spacing of at least one third valley mark (VLM3).

[0321] Since the surface tension of the third sub-insulating layer (1633) is varied by the third intaglio portion (INT3 in FIG. 17 and FIG. 18) of the third mark group (MG3), the edge of the third main insulating layer (1633) on the third sub-insulating layer (1612) may include a deformation portion by the third mark group (MG3).

[0322] According to one embodiment, the third sub-insulating layer (1632) may further cover at least one second auxiliary dam layer (ADL2) adjacent to the second sub-insulating layer (1622) among one or more second auxiliary dam layers (ADL2).

[0323] The third mark group (MG3) may further include at least one third sub-mark (SBM3) formed in a portion that overlaps with at least one second auxiliary dam layer (ADL2) of the third sub-insulating layer (1632).

[0324] At least one third sub-mark (SBM3) may be arranged in parallel with at least one third valley mark (VLM3) and one or more third main marks (MNM3) in another direction (the first direction (DR1) of FIG. 14).

[0325] According to one embodiment, at least one inspection mark (TID) may further include one or more third auxiliary marks (ADM3) placed on one or more third auxiliary dam layers (ADL3).

[0326] One or more third auxiliary marks (ADM3) may be arranged in parallel with at least one third valley mark (VLM3) and one or more third main marks (MNM3) in another direction (the third direction (DR1) of FIG. 15).

[0327] As shown in FIG. 16, according to one embodiment, the edges of the main insulating layers (MNI) include a modified portion by at least one inspection mark (TID), so that identification between the main insulating layers (MNI) can be facilitated.

[0328] Therefore, inspection of the arrangement status of the main insulating layers (MNI) can be made relatively easy.

[0329] As illustrated in FIGS. 17 and 18, the first indented portions (INT1) of the first mark group (MG1) may be spaced apart from each other and formed concavely in the first sub-insulating layer (1612).

[0330] The second indented portions (INT2) of the second mark group (MG2) can be spaced apart from each other and formed concavely in the second sub-insulating layer (1622).

[0331] The third indentations (INT3) of the third mark group (MG3) can be spaced apart from each other and formed concavely in the third sub-insulating layer (1632).

[0332] FIG. 17 illustrates a case where the first engraved parts (INT1), the second engraved parts (INT2), and the third engraved parts (INT3) are arranged at predetermined intervals, but this is merely an example, and the arrangement of the first engraved parts (INT1), the second engraved parts (INT2), and the third engraved parts (INT3) according to one embodiment is not limited to the illustration in FIG. 17. That is, the first engraved parts (INT1), the second engraved parts (INT2), and the third engraved parts (INT3) may be arranged at random intervals, or the interval in the first direction (DR1) and the interval in the second direction (DR2) may be regularly varied.

[0333] As with the city in Fig. 18, each of the intaglio portions of one or more first auxiliary marks (ADM1 in Fig. 13) can be formed concavely in one or more first dam layers (ADL1 in Fig. 13).

[0334] Each of the intaglio portions of one or more second auxiliary marks (ADM2 in FIG. 14) can be formed concavely in one or more second dam layers (ADL2 in FIG. 14).

[0335] Each of the intaglio portions of one or more third auxiliary marks (ADM3 in FIG. 15) can be formed concavely in one or more third dam layers (ADL3 in FIG. 15).

[0336] FIGS. 19, FIGS. 20, FIGS. 21, FIGS. 22, and FIGS. 23 are each plan views showing a display device according to one embodiment.

[0337] A display device (10) according to one embodiment of FIG. 19 is substantially identical to one embodiment shown in FIG. 11 to FIG. 18, except that at least one inspection mark (TID) is positioned adjacent to a part of each of the second sides (SD2) facing in the second direction (DR2), rather than the first sides (SD1) of the edges of the substrate (110), so redundant descriptions are omitted below.

[0338] A display device (10) according to one embodiment of FIG. 20 is substantially the same as one embodiment shown in FIG. 11 to FIG. 18, except that at least one inspection mark (TID) is placed adjacent to a part of each of the first sides (SD1) of the edge of the substrate (110) as well as a part of each of the second sides (SD2), so redundant descriptions are omitted below.

[0339] A display device (10) according to one embodiment of FIG. 21 is substantially the same as one embodiment shown in FIG. 11 to FIG. 18, except that at least one inspection mark (TID) is placed adjacent to at least a portion of each of the corners (CRN), rather than the first sides (SD1) of the edge of the substrate (110), so redundant descriptions are omitted below.

[0340] A display device (10) according to one embodiment of FIG. 22 is substantially the same as one embodiment shown in FIG. 11 to FIG. 18, except that at least one inspection mark (TID) is placed adjacent to a part of each of the first sides (SD1) of the edge of the substrate (110), as well as a part of each of the second sides (SD2) and at least a part of each of the corners (CRN), so redundant descriptions are omitted below.

[0341] The display device (10) according to one embodiment of FIG. 23 is virtually identical to one embodiment shown in FIG. 11 to FIG. 18, except that the inspection mark (TID) is arranged in a frame shape surrounding the periphery of the display area (DA), so redundant descriptions are omitted below.

[0342] In this way, the diffusion range of the main insulating layers (MNI) can be controlled not only by the softening area (SLDA) but also by the inspection mark (TID), so the quality reliability and defect rate of the display device (10) can be improved.

[0343] FIGS. 24 and FIGS. 25 are each cross-sectional views showing D-D' of FIGS. 11 according to one embodiment.

[0344] A display device (10) according to one embodiment of FIG. 24 is substantially the same as one embodiment shown in FIG. 11 to FIG. 18, except that a third sub-insulating layer (1632) and one or more third auxiliary dam layers (ADL3) are disposed on the second main insulating layer (1623), so redundant descriptions are omitted below.

[0345] According to one embodiment of FIG. 24, the third sub-insulating layer (1632) does not cover at least one of the second main insulating layer (1623) and one or more second auxiliary dam layers (ADL2), and one or more third auxiliary dam layers (ADL3) spaced apart from the third sub-insulating layer (1632) are not disposed on the sealing layer (140). Therefore, the width of the non-display area (NDA) can be reduced to the extent that the third sub-insulating layer (1632) and one or more third auxiliary dam layers (ADL3) are not disposed on the sealing layer (140) away from the second main insulating layer (1623).

[0346] A display device (10) according to one embodiment of FIG. 25 is substantially the same as one embodiment shown in FIG. 11 to FIG. 18, except that a second sub-insulating layer (1622) and one or more second auxiliary dam layers (ADL2) are disposed on the first main insulating layer (1613), so redundant descriptions are omitted below.

[0347] According to one embodiment of FIG. 25, the second sub-insulating layer (1622) does not cover at least one of the first main insulating layer (1613) and one or more first auxiliary dam layers (ADL1), and one or more second auxiliary dam layers (ADL2) spaced apart from the second sub-insulating layer (1622) are not placed on the sealing layer (140). Therefore, the width of the non-display area (NDA) can be reduced to the extent that the second sub-insulating layer (1622) and one or more second auxiliary dam layers (ADL2) are not placed on the sealing layer (140) beyond the first main insulating layer (1613).

[0348] FIG. 26 is a cross-sectional view showing C-C' of FIG. 6 according to one embodiment.

[0349] The display device (10) of one embodiment shown in FIG. 26 is substantially identical or similar to the display device (10) of one embodiment shown in FIG. 9, except that the first light output control layer (161) among the light path control layers (LCL) is disposed on the first clad layer (CLD1), the third light output control layer (163') among the light path control layers (LCL) does not include the third sub-insulating layer (1632 in FIG. 9), the second clad layer (CLD2) covering the third light-blocking portions (1631), and the lens layer (LNL) disposed between the second clad layer (CLD2) and the third main insulating layer (1633), and does not include the overcoat layer (OC in FIG. 9) covering the light output control layers (160), so redundant descriptions are omitted below.

[0350] As shown in FIG. 26, according to one embodiment, the lens layer (LNL) may include lenses disposed on the second clad layer (CLD2) and overlapping with the transmission regions (OA in FIG. 6).

[0351] The lenses of the lens layer (LNL) can be superimposed on the edges of the third light-blocking portions (1631) in the third direction (DR3).

[0352] Each of the lenses of the lens layer (LNL) may have a cross-section in the shape of a convex lens that protrudes convexly relative to the substrate (110).

[0353] In this way, the display device (10) according to one embodiment includes a lens layer (LNL) that overlaps with the transmission areas (OA), so that light loss due to total reflection can be reduced, and thus the light output efficiency and brightness of the display device (10) can be improved, and thereby the display quality of the display device (10) can be improved.

[0354] The second clad layer (CLD2) is placed on the second light output control layer (162) and can cover the third light-blocking portions (1631).

[0355] The second clad layer (CLD2) may include an inorganic insulating material.

[0356] In this way, the third light-blocking sections (1631), the first light output control layer (161), and the second light output control layer (162) can be protected by the second clad layer (CLD2), so that the organic materials provided in each of the third light-blocking sections (1631), the first light output control layer (161), and the second light output control layer (162) can be prevented and / or reduced during the placement process of the lens layer (LNL).

[0357] The third main insulating layer (1633) is placed on the second clad layer (CLD2) and can cover the lens layer (LNL).

[0358] According to one embodiment, sub-insulating layers (SBI) (i.e., a first sub-insulating layer (1612) and a second sub-insulating layer (1622)) may be disposed through a process of partially etching an organic insulating material stacked by vapor deposition and may include an organic insulating material.

[0359] For example, the sub-insulating layers (SBI) may comprise at least one organic insulating material selected from propylene glycol methyl ether acetate, methacrylic acid-benzylmethacrylic acid copolymer, multi-functional acrylate, and photoinitiator.

[0360] FIG. 27 is a cross-sectional view showing D-D' of FIG. 11 according to one embodiment.

[0361] FIG. 27 illustrates an example of a cross-section of D-D' of FIG. 11 of a display device (10) of an embodiment shown in FIG. 26.

[0362] A display device (10) of one embodiment illustrated in FIG. 27 includes a first additional damper (ADD1) and a second additional damper (ADD2) instead of a first damper (DM1 in FIG. 11) and a second damper (DM2 in FIG. 11); a light path control layer (LCL) is superimposed on a non-display area (NDA) and includes non-display light-shielding parts (i.e., a first non-display light-shielding part (1611'), a second non-display light-shielding part (1621'), and a third non-display light-shielding part (1631') which are disposed on the same layer as the light-shielding parts (LS in FIG. 9); a first diffusion barrier layer (DBL1) adjacent to a softening area (SLDA) and disposed on the same layer as the first non-display light-shielding parts (1611'); and a second diffusion barrier layer adjacent to the first diffusion barrier layer (DBL1) and disposed on the same layer as the second non-display light-shielding parts (1621'). Except for the fact that it further includes a barrier layer (DBL2) and that at least one first auxiliary dam layer (ADL1) and one or more second auxiliary dam layers (ADL2) are disposed between the second diffusion barrier layer (DBL2) and the edge of the substrate (110) (the first side (SD1) in FIG. 11), the display device (10) of one embodiment shown in FIG. 12 is substantially the same or similar, so redundant descriptions are omitted below.

[0363] According to one embodiment, the first additional dam portion (ADD1) and the second additional dam portion (ADD2) may be arranged in a ring shape that sequentially surrounds the display area (DA in FIG. 11) in the non-display area (NDA).

[0364] The first additional dam (ADD1) and the second additional dam (ADD2) are placed on the first sealing layer (141) and can be covered with a third sealing layer (143).

[0365] The first additional dam section (ADD1) and the second additional dam section (ADD2) may be separated by a valley area (VLA).

[0366] The first clad layer (CLD1) can overlap the entire substrate (110) and cover the sealing layer (140).

[0367] According to one embodiment, a first non-display light-blocking portion (1611') extending to a non-display area (NDA) is disposed on a first clad layer (CLD1) and may overlap with a first additional dam portion (ADD1), a valley area (VLA), a second additional dam portion (ADD2), and a softening area (SLDA).

[0368] According to one embodiment, the width (W1) of the smoothed region (SLDA) may be larger than the width (W2) of the valley region (VLA).

[0369] For example, the width (W1) of the softened region (SLDA) may be about 80 μm or more.

[0370] Since the diffusion of the organic insulating material for the formation of the first main insulating layer (1613) is primarily decelerated in the valley region (VLA) and then further decelerated by the flat surface of the smoothed region (SLDA), the first main insulating layer (1613) can be diffused to the smoothed region (SLDA).

[0371] According to one embodiment, the first sub-insulating layer (1612) may overlap with the first additional dam portion (ADD1) and be spaced apart from the second additional dam portion (ADD2).

[0372] In the softened area (SLDA), the first main insulating layer (1613) can be in contact with the first non-displaying light-shielding part (1611').

[0373] The first diffusion barrier layer (DBL1) can be formed in the same layer as the first non-display light-blocking portion (1611').

[0374] A display device (10) according to one embodiment may include one or more first diffusion barrier layers (DBL1) arranged between a softened region (SLDA) and the edge of a substrate (110) (i.e., the first edge (SD1) of FIG. 11).

[0375] According to one embodiment, the width (W5) of one first diffusion barrier layer (DBL1) adjacent to a softened region (SLDA) among one or more first diffusion barrier layers (DBL1) may be smaller than the width (W6) between one first diffusion barrier layer (DBL1) and the softened region (SLDA).

[0376] According to one embodiment, a second non-display light-blocking portion (1621') extending to a non-display area (NDA) may cover one of the first diffusion barrier layers (DBL1) adjacent to the softened area (SLDA) among one or more first diffusion barrier layers (DBL1).

[0377] According to one embodiment, the second sub-insulating layer (1622) may overlap with the first additional dam portion (ADD1) and be spaced apart from the second additional dam portion (ADD2).

[0378] The diffusion of the organic insulating material for the formation of the second main insulating layer (1623) is gradually slowed down in the valley region (VLA) and the softening region (SLDA), and can be further slowed down by the valley between the first non-displaying light-blocking portion (1611') and one or more first diffusion barrier layers (DBL1).

[0379] Accordingly, between the softened region (SLDA) and the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11), the second main insulating layer (1623) can be in contact with the second non-display light-blocking portion (1621').

[0380] According to one embodiment, the second diffusion barrier layer (DBL2) may overlap with another first diffusion barrier layer (DBL1) adjacent to the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11) among one or more first diffusion barrier layers (DBL1).

[0381] According to one embodiment, a third non-display light-blocking portion (1631') extending to a non-display area (NDA) can cover the second diffusion barrier layer (DBL2).

[0382] According to one embodiment, the second clad layer (CLD2) may overlap the entire substrate (110) and cover the third non-display light-blocking portion (1631').

[0383] The diffusion of the organic insulating material for the formation of the third main insulating layer (1633) is gradually slowed down in the valley region (VLA) and the saturation region (SLDA), and can be further slowed down by the valley between the second non-displaying light-shielding portion (1621') and the second diffusion barrier layer (DBL2).

[0384] Accordingly, between the softened region (SLDA) and the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11), the third main insulating layer (1633) may be placed in a limited area that overlaps with the third non-display light-blocking portion (1631'). That is, the third main insulating layer (1633) may not extend beyond the third non-display light-blocking portion (1631') to the edge of the substrate (110) (i.e., the first side (SD1)).

[0385] According to one embodiment, the first auxiliary dam layer (ADL1) is disposed on the same layer as the first sub-insulating layer (1612) and can extend to the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11).

[0386] The first auxiliary dam layer (ADL1) can cover the edge of another first diffusion barrier layer (DBL1) adjacent to the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11) among one or more first diffusion barrier layers (DBL1).

[0387] One or more second auxiliary dam layers (ADL2) are disposed on the first auxiliary dam layer (ADL1) and may be formed in the same layer as the second sub-insulating layer (1622).

[0388] According to one embodiment, the sub-insulating layers (SBI of FIG. 9, i.e., including the first sub-insulating layer (1612) and the second sub-insulating layer (1622)) extend to the first auxiliary dam portion (ADD1), and the first auxiliary dam portion (ADL1) and one or more second auxiliary dam portions (ADL2) are positioned adjacent to the edge of the substrate (110) (i.e., the first side (SD1) of FIG. 11), so that the placement of at least one inspection mark (TID of FIG. 11) may not be easy.

[0389] Accordingly, since at least one inspection mark (TID of FIG. 11) of the display device (10) according to one embodiment is formed on non-display light-blocking parts (i.e., including a first non-display light-blocking part (1611'), a second non-display light-blocking part (1621') and a third non-display light-blocking part (1631')), one or more first diffusion barrier layers (DBL1) and a second diffusion barrier layer (DBL2) instead of sub-insulating layers (SBI of FIG. 9, i.e., including a first sub-insulating layer (1612) and a second sub-insulating layer (1622)), a first auxiliary dam layer (ADL1) and one or more second auxiliary dam layers (ADL2), the description below is substantially the same or similar to the embodiments shown in FIG. 13 to 24.

[0390] That is, according to one embodiment, a first mark group (MG1 in FIG. 13, 14, and 15) may be formed in a first non-display light-shielding part (1611'), a second mark group (MG2 in FIG. 14 and 15) may be formed in a second non-display light-shielding part (1621'), and a third mark group (MG3 in FIG. 15) may be formed in a third non-display light-shielding part (1631').

[0391] One or more first auxiliary marks (ADM1 in FIG. 13, 14, 15, and 16) may be formed on one or more first diffusion barrier layers (DBL1).

[0392] A second auxiliary mark (ADM2 in FIG. 14 and FIG. 15) can be formed on the second diffusion barrier layer (DBL2).

[0393] The display device (10) of each embodiment as described above can be applied to various electronic devices (20 in FIG. 28).

[0394] An electronic device (20 in FIG. 28) according to one embodiment may include the display device (10) described above.

[0395] In addition, an electronic device (20 in FIG. 28) according to one embodiment may further include a module or device having other additional functions in addition to the display device (10).

[0396] FIG. 28 is a block diagram of an electronic device according to one embodiment.

[0397] Referring to FIG. 28, an electronic device (20) according to one embodiment may include a display module (21), a processor (22), a memory (23), and a power module (24).

[0398] The display module (21) may include a display device (10) that displays an image.

[0399] The processor (22) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0400] The memory (23) may store data information necessary for the operation of the processor (22) or the display module (21). When the processor (22) executes an application stored in the memory (23), a video data signal and / or an input control signal is transmitted to the display module (21), and the display module (21) can process the received signal and output video information through a display screen.

[0401] The power module (24) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (20).

[0402] At least one of each component of the electronic device (20) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device (10) may include a display module (21), and the processor (22), memory (23), and power module (24) may be provided in the form of other devices within the electronic device (20) other than the display device (10).

[0403] FIG. 29 is a schematic diagram of an electronic device according to various embodiments.

[0404] Referring to FIG. 29, electronic devices (20) according to embodiments may include image display electronic devices such as a smartphone (20_1a), tablet PC (20_1b), laptop (20_1c), TV (20_1d), and desk monitor (20_1e), as well as wearable electronic devices such as smart glasses (20_2a), head-mounted display (20_2b), and smart watch (20_2c), and automotive electronic devices (20_3) such as a center information display (CID) and room mirror display of a car instrument panel, center fascia, and dashboard.

[0405] According to one embodiment, the electronic device (20) may be a Center Information Display (CID) of a dashboard.

[0406] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0407] 10: Display device 20: Electronic device 100: Display panel LCL: Optical Path Control Layer DA: Display area NDA: Non-display area 110: Substrate 130: Device layer 140: Sealing layer DM1, DM2: 1st and 2nd dam sections VLA: Valley Area SLDA: Smoothing area TID: Inspection Mark 160: Two or more optical output control layers LS: Shading units SBI: Sub-insulating layers MNI: Main insulation layers 161, 162, 163: 1st, 2nd, and 3rd optical output control layers 1611, 1621, 1631: 1st, 2nd, and 3rd shading crews 1612, 1622, 1632: 1st, 2nd, and 3rd sub-insulating layers 1613, 1623, 1633: 1st, 2nd, and 3rd main insulation layers MG1, MG2, MG3: 1st, 2nd, and 3rd mark groups ADL1, ADL2, ADL3: 1st, 2nd, and 3rd auxiliary dam layers INT1, INT2, INT3: 1st, 2nd, and 3rd engraved parts 1611', 1621', 1631': 1st, 2nd, and 3rd non-marking light-shielding parts ADD1, ADD2: 1st and 2nd additional dam sections DBL1, DBL2: 1st and 2nd diffusion barrier layers

Claims

Claim 1 A display device comprising: a substrate including a display area where light-emitting regions are arranged and a non-display area disposed around the display area; a device layer including light-emitting elements disposed in the light-emitting regions on the substrate; a sealing layer covering the device layer; a light path control layer disposed on the sealing layer; a first dam portion disposed in the non-display area and surrounding the display area; and a second dam portion disposed in the non-display area and surrounding the first dam portion, wherein the non-display area includes a valley area disposed between the first dam portion and the second dam portion; and a softening area disposed around the second dam portion, and the width of the softening area is greater than the width of the valley area. Claim 2 In claim 1, the light path control layer comprises: two or more light output control layers that overlap with the display area in the thickness direction of the substrate; and at least one inspection mark disposed in the non-display area and adjacent to at least a portion of the edges of the substrate, wherein each of the two or more light output control layers comprises: light-shielding portions that overlap with the display area and are spaced apart from each other; a sub-insulating layer covering the light-shielding portions; and a main insulating layer disposed on the sub-insulating layer and comprising an organic insulating material, wherein the at least one inspection mark comprises two or more mark groups that are spaced apart from each other, and each of the two or more mark groups comprises at least one valley mark disposed in the valley area; and one or more main marks disposed in the smoothing area, and each of the at least one valley mark and the one or more main marks comprises spaced-apart intaglio portions, and each of the intaglio portions is formed concavely in the sub-insulating layer. Claim 3 In claim 2, each of the two or more light output control layers further comprises a sub-insulating layer disposed between the light-blocking portions and the main insulating layer, and each of the sub-insulating layer and the main insulating layer extends to the non-display area, and the two or more mark groups are disposed in the sub-insulating layers of the two or more light output control layers. Claim 4 In claim 2, the light path control layer further comprises non-display light-shielding portions that overlap the non-display area and are disposed in the same layer as the light-shielding portions of each of the two or more light output control layers, and the main insulating layers of the non-display light-shielding portions and the two or more light output control layers extend to the non-display area. Claim 5 In claim 2, the edges of the substrate include two first sides facing in a first direction, two second sides facing in a second direction, and corners where one of the two first sides and one of the two second sides meet, and one of the at least one inspection mark is a display device positioned adjacent to a part of the two first sides and one of the two second sides. Claim 6 In claim 2, the edge of the substrate comprises two first sides facing in a first direction, two second sides facing in a second direction, and corners where one of the two first sides and one of the two second sides meet, and the at least one mark is a display device positioned adjacent to at least a part of one of the corners. Claim 7 In claim 2, the at least one inspection mark is a display device arranged in the form of a frame surrounding the periphery of the display area. Claim 8 In claim 1, the optical path control layer comprises two or more optical output control layers that overlap with the display area in the thickness direction of the substrate, wherein the two or more optical output control layers comprise: a first optical output control layer disposed on the sealing layer; a second optical output control layer disposed on the first optical output control layer; and a third optical output control layer disposed on the second optical output control layer, wherein the first optical output control layer comprises: first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer, wherein the second optical output control layer comprises: second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; and a second sub-insulating layer covering the second light-blocking portions. A display device comprising a second main insulating layer disposed on the second sub-insulating layer, wherein the third light output control layer comprises: third light-blocking portions that overlap and are spaced apart from each other with the first light-blocking portions and the second light-blocking portions, respectively; a third sub-insulating layer covering the third light-blocking portions; and a third main insulating layer disposed on the third sub-insulating layer, wherein the first sub-insulating layer covers the first dam and the second dam of the non-display area and extends to the smoothing area, and in the smoothing area, the thickness of the first main insulating layer gradually decreases as it approaches the edge of the substrate. Claim 9 In claim 8, the optical path control layer further comprises at least one inspection mark disposed in the non-display area and adjacent to at least a portion of the edges of the substrate, wherein the at least one inspection mark comprises: a first mark group disposed in the first sub-insulating layer; and a second mark group disposed in the second sub-insulating layer. and includes a third mark group disposed on the third sub-insulating layer, wherein in one direction parallel to a portion of the edge of the substrate, the first mark group, the second mark group, and the third mark group are spaced apart from each other, the first mark group includes at least one first valley mark disposed in the valley region and one or more first main marks disposed in the smoothing region, the second mark group includes at least one second valley mark disposed in the valley region and one or more second main marks disposed in the smoothing region, the third mark group includes at least one third valley mark disposed in the valley region and one or more third main marks disposed in the smoothing region, and the intaglio portions of each of the at least one first valley mark and the one or more first main marks are formed concavely in the first sub-insulating layer, the intaglio portions of each of the at least one second valley mark and the one or more second main marks are formed concavely in the second sub-insulating layer, and the intaglio portions of each of the at least one third valley mark and the one or more third main marks are formed concavely in the third A display device formed concavely in a sub-insulating layer. Claim 10 In claim 9, the optical path control layer further comprises: one or more first auxiliary dam layers arranged between the first sub-insulating layer and the edge of the substrate and disposed in the same layer as the first sub-insulating layer; one or more second auxiliary dam layers arranged between the second sub-insulating layer and the edge of the substrate and disposed in the same layer as the second sub-insulating layer; and one or more third auxiliary dam layers disposed in the same layer as the third sub-insulating layer and disposed in the same layer as the second sub-insulating layer, and the at least one inspection mark comprises: one or more first auxiliary marks disposed on the one or more first auxiliary dam layers; and one or more second auxiliary marks disposed on the one or more second auxiliary dam layers. A display device further comprising one or more third auxiliary marks disposed on the one or more third auxiliary dam layers, wherein the one or more first auxiliary marks, the one or more second auxiliary marks and the one or more third auxiliary marks are spaced apart from each other, and each of the one or more first auxiliary marks, the one or more second auxiliary marks and the one or more third auxiliary marks includes spaced-apart engraved portions. Claim 11 In claim 8, the optical path control layer further comprises: one or more first auxiliary dam layers arranged between the first sub-insulating layer and the edge of the substrate and disposed in the same layer as the first sub-insulating layer; one or more second auxiliary dam layers arranged between the second sub-insulating layer and the edge of the substrate and disposed in the same layer as the second sub-insulating layer; and one or more third auxiliary dam layers disposed in the same layer as the third sub-insulating layer and the second sub-insulating layer and disposed in the same layer as the third sub-insulating layer, wherein the one or more first auxiliary dam layers are disposed on the sealing layer. Claim 12 A display device according to claim 11, wherein the second sub-insulating layer covers at least one of the one or more first auxiliary dam layers, the one or more second auxiliary dam layers are disposed on the sealing layer, and the third sub-insulating layer and the one or more third auxiliary dam layers are disposed on the second main insulating layer. Claim 13 A display device according to claim 11, wherein the second sub-insulating layer and the one or more second auxiliary dam layers are disposed on the first main insulating layer, and the third sub-insulating layer and the one or more third auxiliary dam layers are disposed on the second main insulating layer. Claim 14 In claim 1, the light path control layer comprises: a first clad layer disposed on the sealing layer; a first light output control layer disposed on the first clad layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer, wherein the first light output control layer comprises: first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer, and the second light output control layer comprises: second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; and a second sub-insulating layer covering the second light-blocking portions. A display device comprising a second main insulating layer disposed on the second sub-insulating layer, wherein the third light output control layer comprises: third light-blocking portions that overlap and are spaced apart from each other with the first light-blocking portions and the second light-blocking portions, respectively; a second clad layer covering the third light-blocking portions; a lens layer disposed on the second clad layer; and a third main insulating layer covering the lens layer. Claim 15 In claim 14, the light path control layer further comprises: a first non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the first light-blocking parts; a second non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the second light-blocking parts; and a third non-display light-blocking part that overlaps the non-display area and is formed in the same layer as the third light-blocking parts, wherein the first main insulating layer extends into the non-display area and contacts the first non-display light-blocking part in the softening area, the second main insulating layer extends into the non-display area and contacts the second non-display light-blocking part in the softening area, and the third main insulating layer extends into the non-display area and overlaps the third non-display light-blocking part. Claim 16 An electronic device comprising: a display device for displaying images; a memory for storing an application; a processor for executing the application and transmitting image data signals and input control signals to the display device; and a power module for transmitting power to the display device, wherein the display device comprises: a substrate including a display area in which light-emitting regions are arranged and a non-display area disposed around the display area; a device layer including light-emitting elements disposed in the light-emitting regions on the substrate; a sealing layer covering the device layer; an optical path control layer disposed on the sealing layer; a first dam portion disposed in the non-display area and surrounding the display area; and a second dam portion disposed in the non-display area and surrounding the first dam portion, wherein the optical path control layer comprises two or more optical output control layers that overlap with the display area in the thickness direction of the substrate, and the non-display area comprises a valley area disposed between the first dam portion and the second dam portion; and a smoothing area disposed around the second dam portion, wherein the width of the smoothing area is greater than the width of the valley area. Claim 17 In claim 16, the two or more light output control layers comprise: a first light output control layer disposed on the sealing layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer, wherein the first light output control layer comprises: first light-blocking portions that overlap with and are spaced apart from each other with respect to the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer, and the second light output control layer comprises: second light-blocking portions that overlap with the first light-blocking portions; a second sub-insulating layer covering the second light-blocking portions; and a second main insulating layer disposed on the second sub-insulating layer, and the third light output control layer comprises: third light-blocking portions that overlap with the first light-blocking portions and the second light-blocking portions; and a third sub-insulating layer covering the third light-blocking portions. An electronic device comprising a third main insulating layer disposed on the third sub-insulating layer, wherein the first sub-insulating layer covers the first dam and the second dam of the non-display area and extends to the smoothing area, and in the smoothing area, the thickness of the first main insulating layer gradually decreases as it approaches the edge of the substrate. Claim 18 In claim 17, the optical path control layer further comprises at least one inspection mark disposed in the non-display area and adjacent to at least a portion of the edges of the substrate, wherein the at least one inspection mark comprises: a first mark group disposed in the first sub-insulating layer; and a second mark group disposed in the second sub-insulating layer. and includes a third mark group disposed on the third sub-insulating layer, wherein in one direction parallel to a portion of the edges of the substrate, the first mark group, the second mark group, and the third mark group are spaced apart from each other, the first mark group includes at least one first valley mark disposed in a valley region between the first dam portion and the second dam portion, and one or more first main marks disposed in the smoothing region, the second mark group includes at least one second valley mark disposed in the valley region, and one or more second main marks disposed in the smoothing region, and the third mark group includes at least one third valley mark disposed in the valley region, and one or more third main marks disposed in the smoothing region, wherein each of the at least one first valley mark and the one or more first main marks is concavely formed in the first sub-insulating layer, and each of the at least one second valley mark and the one or more second main marks is concavely formed in the second sub-insulating layer, and the at least one third valley mark and the one or more third The engraved portions of each of the main marks are formed concavely in the third sub-insulating layer of the electronic device. Claim 19 In claim 16, the light path control layer comprises: a first clad layer disposed on the sealing layer; a first light output control layer disposed on the first clad layer; a second light output control layer disposed on the first light output control layer; and a third light output control layer disposed on the second light output control layer, wherein the first light output control layer comprises: first light-blocking portions that overlap with and are spaced apart from the display area; a first sub-insulating layer covering the first light-blocking portions of the display area; and a first main insulating layer disposed on the first sub-insulating layer, and the second light output control layer comprises: second light-blocking portions that overlap with and are spaced apart from the first light-blocking portions; and a second sub-insulating layer covering the second light-blocking portions. An electronic device comprising a second main insulating layer disposed on the second sub-insulating layer, wherein the third light output control layer comprises: third light-blocking portions that overlap and are spaced apart from each other with the first light-blocking portions and the second light-blocking portions, respectively; a second clad layer covering the third light-blocking portions; a lens layer disposed on the second clad layer; and a third main insulating layer covering the lens layer. Claim 20 An electronic device according to claim 19, wherein the light path control layer further comprises: a first non-display light-blocking portion that overlaps the non-display area and is formed in the same layer as the first light-blocking portions; a second non-display light-blocking portion that overlaps the non-display area and is formed in the same layer as the second light-blocking portions; and a third non-display light-blocking portion that overlaps the non-display area and is formed in the same layer as the third light-blocking portions, wherein the first main insulating layer extends into the non-display area and contacts the first non-display light-blocking portion in the softening area, the second main insulating layer extends into the non-display area and contacts the second non-display light-blocking portion in the softening area, and the third main insulating layer extends into the non-display area and overlaps the third non-display light-blocking portion.

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