Integrated circuit structures with nanoribbon transistors and source / drain contacts on opposite sides of nanoribbons

Abstract

The present invention discloses a nanoribbon transistor and an IC structure having S / D contacts on both sides of the nanoribbon, and related methods and devices. An exemplary IC structure comprises a nanoribbon and a transistor comprising a channel portion, a first S / D region, and a second S / D region within a portion of the nanoribbon, a first conductive contact that is conductively in contact with the first S / D region—the first conductive contact being on the front side of the channel portion—a second conductive contact that is conductively in contact with the second S / D region—the second conductive contact being on the rear side of the channel portion—and an insulator structure that is in contact with the first S / D region—the insulator structure being on the rear side of the channel portion—wherein in a side cross-sectional view of the IC structure, the shape at the interface with the first S / D region of the insulator structure is convex.

Description

Background Technology

[0001] Over the past few decades, scaling the features of integrated circuit (IC) structures has been the driving force behind the continuously growing semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units on the limited mounting area of ​​a semiconductor chip. For example, by reducing transistor size, a greater number of memory or logic devices can be integrated into the chip, enabling the manufacture of products with increased capacity. However, continuously increasing capacity can present challenges. The need to optimize every part of the IC structure has become increasingly important.

[0002] The source and drain regions of a transistor, particularly a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET), are two of the key terminals that play a decisive role in the operation of the transistor. The source region is the area where charge carriers (electrons or holes) are supplied to the transistor's channel. The drain region is the area where charge carriers exit the channel. As is common in the field of FETs, the naming of source and drain is often interchangeable; thus, the source and drain regions may be referred to as the first source / drain (S / D) region and the second S / D region, where one of the first and second S / D regions is the source region and the other is the drain region. Likewise, the electrical contacts for each S / D region may be referred to as the first S / D contact and the second S / D contact. Brief explanation of the drawing

[0003] The embodiments will be easily understood by combining the detailed description below with the accompanying drawings. To facilitate this description, the same reference numerals indicate similar components. In the accompanying drawings, the embodiments are examples, not limitations. FIG. 1 provides a perspective view of an exemplary IC structure having a nanoribbon transistor according to some embodiments. FIG. 2 is a flowchart of an exemplary method for manufacturing an IC structure having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIGS. 3a to 3e are side cross-sectional views illustrating exemplary IC structures after various processes of the method of FIG. 2 according to some embodiments. FIG. 4 illustrates a plan view of a wafer and a die that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIG. 5 is a side cross-sectional view of an IC device that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIG. 6 is a side cross-sectional view of an IC package that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIG. 7 illustrates a side cross-sectional view of an IC device assembly that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIG. 8 is a block diagram of an exemplary computing device that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. FIG. 9 is a block diagram of an exemplary processing device that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. Specific details for implementing the invention

[0004] The present invention discloses a nanoribbon transistor and an IC structure having S / D contacts on both sides of the nanoribbon, as well as related methods and devices. The systems, methods, and devices of the present invention each have several novel aspects, and no single aspect thereof is solely responsible for all the desirable properties disclosed herein. Details regarding one or more embodiments of the claimed subject matter described herein are provided in the following description and accompanying drawings.

[0005] For the purpose of explaining the nanoribbon transistor and the IC structure having S / D contacts on both sides of the nanoribbon proposed herein, it may be useful to first understand the phenomena that may occur during IC manufacturing. The following basic information may be considered as a basis for adequately explaining the present disclosure. Such information is provided for illustrative purposes only and should not be interpreted in any way as limiting the broad scope of the present disclosure and its potential applications.

[0006] A FET, for example a MOSFET, is a three-terminal device comprising source, drain, and gate terminals that uses an electric field to control the current flowing through the device. A FET generally comprises a semiconductor material forming a channel portion of the transistor, source and drain regions provided on both sides of the channel portion, and a gate stack comprising at least a gate electrode material and optionally may also include a gate insulator, wherein the gate stack is provided over at least a portion of the channel portion between the source and drain regions.

[0007] Recently, FETs with non-planar architectures, such as nanoribbon transistors (also called 'GAA (gate all-around) transistors'), have been extensively studied as an alternative to transistors with planar architectures. In nanoribbon transistors, a gate stack is provided around a portion of a long semiconductor structure called a 'nanoribbon', allowing gates to be formed on all sides of the nanoribbon. The 'channel' or 'channel portion' of the nanoribbon transistor is the portion of the nanoribbon wrapped by the gate stack. These transistors are often called 'GAA transistors' because, in use, a conductive channel can be formed on all 'sides' of the nanoribbon's channel portion. Source and drain regions are provided on the nanoribbon on each side of the gate stack, respectively, forming the source and drain of the nanoribbon transistor. In some settings, the terms 'nanoribbon' or 'nanosit' have been used to describe long semiconductor structures having a substantially rectangular cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), whereas the term 'nanowire' has been used to describe structures that are similar but have a substantially circular or square cross-section. In this disclosure, the term 'nanoribbon' is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as long semiconductor structures having a cross-section of any shape with a longitudinal axis parallel to the base (such as a cross-section in the shape of an ellipse or a polygon with rounded corners). If the channel of a transistor is a portion of the nanoribbon, that is, a portion that the transistor's gate stack can wrap around, the transistor may be described as a 'nanoribbon transistor'. The semiconductor material in the portion of the nanoribbon forming the channel of the transistor may be referred to as a 'channel material', and the S / D regions of the transistor are provided on both sides of this channel material.In some embodiments, the nanoribbon transistor may include a stack of nanoribbons, wherein the stack comprises two or more nanoribbons stacked together, and includes a gate electrode material (which may include a work function material) provided to the entire nanoribbon stack as a single gate stack. The description provided below regarding the nanoribbon stack is equally applicable to a single nanoribbon (i.e., a stack of only one nanoribbon).

[0008] When one of the S / D contacts is a front contact (e.g., when a conductive contact to one of the S / D regions of the nanoribbon transistor is formed from the front of the nanoribbon stack) and the other is a back contact (e.g., when a conductive contact to another of the S / D regions of the nanoribbon transistor is formed from the back of the nanoribbon stack), routing signals and power to the nanoribbon transistor can be simplified. Embodiments of the present disclosure are based on the recognition that if the material of the S / D region associated with the front S / D contact extends past the nanoribbon furthest from the front contact (referred to as the bottom nanoribbon in the stack), it can cause undesirable parasitic capacitance, thereby degrading transistor performance. Embodiments of the present disclosure are further based on the recognition that providing an insulator structure in contact with an S / D region associated with a front S / D contact on the back side of a nanoribbon stack, and allowing the insulator structure to extend to at least the level of a bottom nanoribbon into the said S / D region and / or to have a convex shape at the interface with the said S / D region can help reduce parasitic capacitance and thus improve device performance. In one embodiment, an exemplary IC structure comprises a nanoribbon, a transistor including a channel portion, a first S / D region and a second S / D region within a portion of the nanoribbon, a first conductive contact that is conductively in contact with the first S / D region—the first conductive contact being on the front side of the channel portion—a second conductive contact that is conductively in contact with the second S / D region—the second conductive contact being on the rear side of the channel portion—and an insulator structure that is in contact with the first S / D region—the insulator structure being on the rear side of the channel portion—wherein in a side cross-sectional view of the IC structure, the shape at the interface with the first S / D region of the insulator structure is convex.

[0009] An IC structure having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon may be included in one or more components associated with the IC and / or may be included among these various components. In various embodiments, the components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. The components associated with the IC may include components mounted on the IC or components connected to the IC. The IC may be analog or digital and may be used in various applications such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, the IC structure described herein may be included in a radio frequency (RF) IC (RFIC), which may be included in any component associated with the IC of an RF receiver, RF transmitter, or RF transceiver, such as for use in remote communication within a base station (BS) or user equipment (UE), for example. These components include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structures described herein may be included in a memory device or circuit. In some embodiments, the IC structures described herein may be used as part of a chipset that performs one or more related functions in a computer.

[0010] For illustrative purposes, specific numbers, materials, and configurations are described to enable a complete understanding of the exemplary implementation. However, it will be obvious to those skilled in the art that the present disclosure may be practiced without these specific details and / or with only some of the aspects described in the present disclosure. In other instances, known features are omitted or briefly described so as not to obscure the exemplary implementation.

[0011] In the detailed description that follows, various aspects of exemplary embodiments are described using terms commonly used by those skilled in the art to convey their findings to others skilled in the art. For example, in the context of the S / D contact of a transistor, the term "contact" may be used interchangeably with the term "terminal" of the transistor. As another example, the term "connected" as used herein refers to a direct electrical or magnetic connection between connected parts without any intermediate device, whereas the term "coupled" refers to a direct electrical or magnetic connection between connected parts or an indirect connection through one or more passive or active intermediate devices. The term "circuit" refers to one or more passive and / or active components arranged to cooperate with one another to provide a desired function. Where terms such as ‘oxide’, ‘carbide’, ‘nitride’, ‘sulfide’ are used, they refer to compounds containing oxygen, carbon, nitrogen, sulfur, etc., respectively, and the term ‘high-k dielectric’ refers to a material having a dielectric constant (k) higher than silicon oxide, whereas the term ‘low-k dielectric’ refers to a material having a k lower than silicon oxide. The terms ‘substantially’, ‘near’, ‘approximately’, ‘nearly’, and ‘about’ refer to values ​​generally within + / - 20% of a target value, e.g., within + / - 5% or within + / - 2%, based on the context of a specific value as described herein or known in the art. Similarly, terms indicating the orientation of various elements, e.g., 'coplanar', 'perpendicular', 'orthogonal', 'parallel', or any other angle between elements, generally refer to being within + / - 20% of a target value, e.g., within + / - 5% or within + / - 2%, based on the context of a specific value as described in this specification or known in the art.

[0012] As used herein, terms such as “over,” “below,” “between,” and “on” refer to the relative position of one material layer or component with respect to another layer or component. For example, a layer placed above or below another layer may be in direct contact with the other layer, or there may be one or more intermediate layers. Furthermore, a layer placed between two layers may be in direct contact with these two layers, or there may be one or more intermediate layers. In contrast, a first layer “above” a second layer is in direct contact with the second layer. Similarly, unless explicitly stated otherwise, a feature placed between two features may be in direct contact with an adjacent feature, or there may be one or more intermediate layers.

[0013] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B) or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, C). Where the term “between” is used in relation to a measurement range, it includes the end of the measurement range. As used herein, the notation “A / B / C” means (A), (B) and / or (C).

[0014] Even if a specific element is referred to in the singular in this document, this element may comprise multiple sub-elements. For example, an "insulating material" may comprise one or more insulating materials. Unless otherwise specified, the term "insulating" and its derivatives (e.g., "insulative" or "insulator") mean "electrically insulating," and the term "conducting" and its derivatives (e.g., "conductive" or "conductor") mean "electrically conducting." For example, the term "insulating material" may refer to a solid material that is substantially electrically non-conductive (and / or a liquid material that solidifies after processing as described herein). These may include, as examples rather than limitations, organic polymers and plastics, and inorganic materials such as ionic crystals, magnets, glass, silicon and alumina, or combinations thereof. These may include dielectric materials, highly polarized materials, and / or piezoelectric materials. Without departing from the scope of the present disclosure, they may be transparent or opaque. With respect to optical signals and / or devices, components, and elements operating using optical signals, the term 'conductive / conductive' may mean 'optically conductive / conductive'.

[0015] This description uses the phrases “in the examples” or “in the examples,” each of which may refer to one or more of the same or different examples. Furthermore, terms such as “comprising,” “including,” and “having” as used in relation to the examples of this disclosure are synonyms. This disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed examples. The accompanying drawings are not necessarily drawn to scale. Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates that different instances of similar objects are being referenced and does not imply that the objects thus described must be in a given order, chronologically, spatially, sequentially, or in any other way.

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of this description, and the drawings illustrate exemplary embodiments that may be implemented. It should be understood that other embodiments may be used, and that structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be taken as a limiting reference. To avoid complicating the drawings, if multiple instances of a specific element are depicted, reference numerals may be assigned only to some of the elements. Multiple drawings with different letters under the same number may be referred to by the letters, for example, FIGS. 3a through 3e may be referred to as 'Fig. 3'.

[0017] In the drawings, while some schematic diagrams of exemplary structures of the various devices and assemblies described herein may be drawn with accurate right angles and straight lines, it should be understood that these schematic diagrams may not reflect real-world processing limitations, which may cause features to appear less 'ideal' when any structure described herein is inspected, for example, using scanning electron microscope (SEM) or transmission electron microscope (TEM) images. In these images of actual structures, possible processing defects may also be visible, such as, for example, non-perfectly straight edges of the material, tapered vias or other openings, unintended rounding of corners or variations in the thickness of different material layers, intermittent screws, edge or combination dislocations within crystal regions, and / or intermittent dislocation defects of single atoms or clusters of atoms. Other defects common in the field of device manufacturing, although not listed herein, may be present. For example, the presence of an IC structure having nanoribbon transistors and S / D contacts on both sides of a nanoribbon can be determined by examining layout and mask data for reconstructing the circuit using an optical microscope, TEM, or SEM, and by examining reverse engineering of device components, and / or by examining cross-sections of devices to detect the shape and location of various device elements described herein using, for example, Physical Failure Analysis (PFA).

[0018] FIG. 1 provides a perspective view of an exemplary IC structure (100) implementing a nanoribbon transistor (110) according to some embodiments. FIG. 1 is a perspective view, and for illustrative purposes, an exemplary coordinate system (105) (xyz coordinate system) is shown in FIG. 1. Other drawings showing various axes (e.g., FIG. 3a and FIG. 3e) refer to the axes of the coordinate system (105).

[0019] Looking at the details of FIG. 1, the IC structure (100) may include one or more semiconductor materials formed as a nanoribbon (104) (i.e., a long semiconductor structure) extending substantially parallel to the substrate (102). The transistor (110) may be formed based on the nanoribbon (104) in such a way that it provides a gate stack (112) that at least partially wraps a portion of the nanoribbon called the 'channel portion', and provides S / D regions illustrated in FIG. 1 as a first S / D region (114) and a second S / D region (116) on both sides of the gate stack (112). FIG. 1 also illustrates a first S / D contact (124), a second S / D contact (126), and a dummy second S / D contact (126'). The first S / D contact (124) can make conductive contact with the first S / D region (114) from the front of the nanoribbon (104) (i.e., electrically connected, e.g., directly electrically connected). The second S / D contact (126) can make conductive contact with the second S / D region (116) from the rear of the nanoribbon (104) (i.e., electrically connected, e.g., directly electrically connected). As described with reference to FIGS. 3a through 3e, since the actual functional contact for the S / D region (116) is provided from the rear of the nanoribbon (104) to the second S / D contact (126), the dummy second S / D contact (126') is shown as a dotted line object in FIG. 1 to indicate that it may be a non-functional contact for the S / D region (116) (hence referred to as a 'dummy' contact). In another embodiment, the dummy second S / D contact (126') may not be present in the IC structure (100). In some embodiments, a layer of oxide material (130) may be provided between the substrate (102) and the gate stack (112) and / or the nanoribbon (104), and in other embodiments, the oxide material (130) may not be present in the IC structure (100).Although only one nanoribbon (104) is illustrated in FIG. 1, in some embodiments, the IC structure (100) may include a stack of nanoribbons (104), wherein a plurality of nanoribbons (104) may be stacked perpendicularly to one another as is known in the art. In such embodiments, the gate stack (112) may at least partially enclose a portion of a plurality (e.g., all) of the nanoribbons (104) of the stack, and a first S / D region (114) and a second S / D region (116) may each extend continuously across the entire stack, thus forming a single transistor (110) having a channel portion in a plurality of nanoribbons (104) of the stack. An exemplary embodiment of a transistor comprising a stack of nanoribbons (104) is illustrated in FIG. 3a through 3e.

[0020] The IC structure (100) illustrated in FIG. 1, as well as the IC structure / device illustrated in other drawings of the present disclosure, are intended to show the relative arrangement of some components therein, and the IC structure / device or part thereof illustrated herein may include other components not illustrated. For example, additional layers such as a spacer layer around the gate stack (112) of a transistor (110) are not illustrated in FIG. 1. As another example, although not specifically illustrated in FIG. 1, dielectric spacers may be provided between the first S / D contact (124) and the gate stack (112), between the second S / D contact (126) and the gate stack (112), and optionally between the dummy second S / D contact (126') and the gate stack (112) to provide electrical insulation between the source, gate, and drain contacts (for the sake of not complicating the drawings, these dielectric spacers are not illustrated in FIG. 1 but are illustrated as gate spacers (348) in FIG. 3a through 3e). Generally, the 'contacts' described herein may also be referred to as 'electrodes'. As another example, although not specifically illustrated in FIG. 1, at least a portion of the transistor (110) may be surrounded by an insulating material, such as any suitable interlayer insulating (ILD) material. In some embodiments, this insulating material may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organic silicates such as silsesquioxane, siloxane, or organic silicate glass. In other embodiments, the insulating material surrounding a portion of the transistor (110) may be a high-k dielectric containing elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.Examples of high-k materials that can be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0021] Embodiments of the present disclosure may be formed or implemented on any suitable substrate (102), such as a substrate, die, wafer, or chip. The substrate (102) may be, for example, the wafer (2000) of FIG. 4 discussed below, or a die, for example, the singulated die (2002) of FIG. 4 discussed below, or may be contained therein. The substrate (102) may be a semiconductor substrate composed of a semiconductor material system, for example, an N-type or P-type material system. In one embodiment, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In other embodiments, the semiconductor substrate may be formed using an alternative material (which may or may not be combined with silicon), and this alternative material includes, but is not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, indium aluminum nitride or gallium antimonide, or other combinations of Group III-V materials (i.e., materials from Group III and V of the periodic table), Group II-VI materials (i.e., materials from Group II and VI of the periodic table), or Group IV materials (i.e., materials from Group IV of the periodic table). In some embodiments, the substrate may be amorphous. In some embodiments, the substrate (102) may be a printed circuit board (PCB) substrate. While some examples of materials on which the substrate (102) may be formed are described herein, any material capable of functioning as a base on which an IC structure having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon can be constructed falls within the spirit and scope of the present disclosure.

[0022] The nanoribbon (104) may take the form of, for example, a nanowire or a nanoribbon. In some embodiments, the area of ​​the cross section of the nanoribbon (104) (i.e., the area in the yz plane of the coordinate system (105)) is between about 25 and 10,000 square nanometers, including all values ​​and ranges within it (e.g., between about 25 and 1,000 square nanometers, or between about 25 and 500 square nanometers). The cross section of the nanoribbon (104) may be a cross section along a plane perpendicular to the longitudinal axis (120) of the nanoribbon (104), where the longitudinal axis (120) may follow, for example, the x-axis of the coordinate system (105) and is shown as a dashed line in FIG. 1. In some embodiments, the width of the nanoribbon (104) (i.e., a dimension measured along the y-axis of the coordinate system (105), for example, in a direction perpendicular to the longitudinal axis (120) in a plane parallel to the substrate (102)) may be at least about 3 times larger than the thickness (or 'height') of the nanoribbon (104) (i.e., a dimension measured along the z-axis of the coordinate system (105), for example, in a plane perpendicular to the substrate (102)), which includes all values ​​and ranges therein (e.g., at least about 4 times larger, or at least about 5 times larger).

[0023] The nanoribbon (104) shown in FIG. 1 is depicted as having a square cross-section, or more generally, a rectangular cross-section, but the nanoribbon (104) may instead have a cross-section with rounded corners or otherwise irregular shape, and the gate stack (112) may correspond to the shape of the nanoribbon (104). The terms ‘front’ and ‘back’ of the nanoribbon may refer to a surface / plane of the semiconductor material of the nanoribbon (104) that is substantially parallel to the substrate (102), and the term ‘sidewall’ (or ‘side’ or simply ‘side’) of the nanoribbon may refer to an opposing surface of the nanoribbon (104) that is substantially perpendicular to the substrate (102) and extends in the direction of the longitudinal axis (120) of the nanoribbon (104), whereas the term ‘end’ of the nanoribbon may refer to an opposing surface of the nanoribbon (104) that is substantially perpendicular to the longitudinal axis (120) of the nanoribbon (104).

[0024] The nanoribbon (104) may be formed from one or more semiconductor materials, which are collectively referred to as ‘channel materials’. Generally, the channel material of the transistor (110) may be composed of a semiconductor material system, for example, including an N-type or P-type material system. In some embodiments, the nanoribbon (104) may include high-mobility oxide semiconductor materials such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon (104) may include a combination of semiconductor materials. In some embodiments, the nanoribbon (104) may include a single-crystal semiconductor such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon (104) may comprise a compound semiconductor having a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from group V of the periodic table (e.g., P, As, Sb).

[0025] In some exemplary N-type transistor embodiments (i.e., embodiments where the transistor (110) is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of the nanoribbon (104) may comprise a III-V material having relatively high electron mobility, including (but not limited to) InGaAs, InP, InSb, and InAs. In some of these embodiments, the channel material of the nanoribbon (104) may be a ternary III-V alloy such as InGaAs, GaAsSb, InAsP, or InPSb. Some In x Ga 1-x In the case of the As fin example, the In content (x) may be between 0.6 and 0.9, and preferably at least 0.7 (e.g., In 0.7 Ga 0.3As). In some exemplary P-type transistor embodiments (i.e., in the case where the transistor (110) is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of the nanoribbon (104) may preferably be a Group IV material having high hole mobility, including (but not limited to) Ge or a Ge-rich SiGe alloy. In some exemplary embodiments, the channel material of the nanoribbon (104) may have a Ge content between 0.6 and 0.9, and preferably at least 0.7.

[0026] In some embodiments, the channel material of the nanoribbon (104) may be a thin film material such as a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, when the transistor formed on the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon (104) may include at least one of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may include gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, It may be doped with at least one of tungsten and magnesium. In some embodiments, the channel material of the nanoribbon (104) may have a thickness between about 5 and 75 nanometers (including all values ​​and ranges therein). In some embodiments, the thin film channel material may be deposited at a relatively low temperature, which makes it possible to deposit the channel material within the thermal budget imposed on back-end manufacturing, for example, to avoid damage to other components such as front-end components such as logic devices.

[0027] As mentioned above, the channel material may include IGZO. IGZO-based devices possess several desirable electrical and fabrication characteristics. IGZO has high electron mobility ranging from 20 to 50 times higher than other semiconductors, for example, amorphous silicon. Additionally, amorphous IGZO (a-IGZO) transistors generally feature a high band gap, low-temperature processing compatibility, and low manufacturing costs compared to other semiconductors. IGZO can be deposited as a uniform amorphous phase while maintaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different compositions of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One specific form of IGZO has the chemical formula InGaO3(ZnO)5. Another exemplary form of IGZO has an indium:gallium:zinc ratio of 1:2:1. As various other examples, IGZO may have a gallium-to-indium ratio of 1:1, a gallium-to-indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium-to-indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO may also contain a third dopant, such as aluminum or nitrogen.

[0028] As described above, in some embodiments, the transistor (110) may be a TFT. A TFT is a special type of FET made by depositing an active semiconductor material on a substrate (e.g., the substrate (102) described above) which may be a non-conductive base. Some of these materials may be deposited at a relatively low temperature, which enables them to be deposited within the thermal budget allocated to the back-end manufacturing process to prevent damage to front-end components, such as logic devices of an IC device in which the transistor may be included. Accordingly, in some embodiments, the channel material of the transistor (110) may be a semiconductor material deposited at a relatively low temperature and may include any thin film material, such as the high-mobility oxide semiconductor material described above.

[0029] In another embodiment, the channel material of the transistor (110) may be epitaxially grown in a process involving a relatively high temperature, instead of being deposited at a relatively low temperature as described above with reference to the TFT. In this embodiment, the channel material may include any semiconductor material described above, including oxide semiconductor materials. In some of these embodiments, the channel material may be epitaxially grown directly onto a semiconductor layer of a substrate on which the transistor is to be manufactured in a process known as 'monolithic integration'. In other of these embodiments, the channel material of the transistor (110) may be epitaxially grown onto a semiconductor layer of another substrate, and then the epitaxially grown layer of the channel material may be transferred to a substrate (e.g., substrate (102)) on which the transistor is to be placed in a process known as 'layer transfer', in which case the latter substrate may include, but does not necessarily include, a semiconductor layer prior to layer transfer. Layer transfer preferably enables the formation of non-planar transistors, such as nanoribbon transistors, on a base or on a layer that does not contain semiconductor material (e.g., the back end of an IC device). Layer transfer also preferably enables the formation of transistors of any architecture (e.g., non-planar or planar transistors) without adverse effects of a relatively high-temperature epitaxial growth process on a device that may already exist on the base.

[0030] Channel materials deposited at relatively low temperatures are generally polycrystalline, polymorphic, or amorphous semiconductors, or any combination thereof. Epitaxially grown channel materials are generally highly crystalline (e.g., single-crystal or single-crystalline) materials. Therefore, whether the channel material of the transistor (110) was deposited at a relatively low temperature or was epitaxially grown can be identified by examining the crystal grain size of the active portion of the channel material (e.g., the portion of the channel material forming the channel of the transistor). If the average crystal grain size of the channel material of the transistor (110) is between about 0.5 and 1 nanometer (in which case the material may be polycrystalline) or smaller than about 0.5 nanometers (in which case the material may be polymorphic or amorphous), it may indicate that the channel material has been deposited (e.g., in which case the transistor containing such channel material is a TFT). On the other hand, the average crystal grain size of the channel material of the transistor (110) being about 1 nanometer or larger (in this case, the material may be a single-crystal material) may indicate that the channel material was epitaxially grown by monolithic integration or layer transfer and incorporated into the final device.

[0031] In some embodiments, the channel material of the transistor (110) may comprise a two-dimensional (2D) semiconductor material, i.e., a semiconductor material having a thickness of several nanometers or less, and electrons within the semiconductor material may move freely in the 2D plane, but their movement in a third direction is restricted, which is governed by quantum mechanics. In some of these embodiments, the channel material may comprise a single atomic monolayer of the 2D semiconductor material, whereas in other of these embodiments, the channel material may comprise five or more atomic monolayers of the 2D semiconductor material. Examples of 2D materials that may be used to implement the channel material of any transistor described herein include, but are not limited to, graphene, hexagonal boron nitride, or transition metal chalcogenides.

[0032] A gate stack (112) comprising a gate electrode material (108) and optionally a gate insulator (106) can completely or nearly completely wrap a portion of the nanoribbon (104) as shown in FIG. 1, and the channel portion of the transistor (110) is an active region (channel region) of the channel material within the portion of the nanoribbon (104) wrapped by the gate stack (112). As shown in FIG. 1, the gate insulator (106) can wrap a cross-section / transverse portion of the nanoribbon (104), and the gate electrode material (108) can wrap the gate insulator (106).

[0033] The gate electrode material (108) may include at least one P-type work function (PWF) metal or N-type work function (NWF) metal depending on whether the transistor (110) is a PMOS transistor or an NMOS transistor. The PWF metal may be used as the gate electrode material (108) when the transistor (110) is a PMOS transistor, and the NWF metal may be used as the gate electrode material (108) when the transistor (110) is an NMOS transistor. In the case of a PMOS transistor, the gate electrode material that may be used in different parts of the gate electrode material (108) includes, but is not limited to, tungsten, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide) and conductive metal nitrides (e.g., titanium nitride). In the case of an NMOS transistor, the gate electrode material that may be used in different parts of the gate electrode material (108) includes, but is not limited to, tungsten, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, titanium aluminum carbide). In one example in which both the NMOS transistor and the PMOS transistor include a gate electrode material including tungsten, the gate electrode material including tungsten for the NMOS transistor may include fluorine, and the gate electrode material including tungsten for the PMOS transistor may be fluorine-free (e.g., the gate electrode material including tungsten for the PMOS transistor may substantially not include fluorine). In some embodiments, the gate electrode material (108) may comprise a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a filling metal layer.For other purposes, such as functioning as a diffusion barrier layer and / or an adhesive layer, an additional layer may be included next to the gate electrode material (108).

[0034] In some embodiments, the gate insulator (106) may comprise one or more high-k dielectrics comprising any of the materials described above with reference to an ILD that can surround a portion of the transistor (110). In some embodiments, the high-k dielectric may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used for the gate insulator (106) may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate insulator (106) to improve the quality of the gate insulator (106) during the manufacture of the transistor (110). The gate insulator (106) may have a thickness that is between about 0.5 nanometers and 3 nanometers in some embodiments, which includes all values ​​and ranges within it (e.g., between about 1 nanometer and 3 nanometers, or between about 1 nanometer and 2 nanometers), and in other embodiments, the thickness of the gate insulator (106) may be greater than 3 nanometers. In some embodiments, the gate stack (112) may be surrounded by a gate spacer not shown in FIG. 1. Such a gate spacer will be configured to provide separation between the gate stack (112) and the S / D contacts (124, 126) of the transistor (110) (e.g., the gate spacer (348) of FIG. 3a through 3e described below), and may be made of a low-k dielectric material, some examples of which have been described above.The gate spacer may include pores or air gaps to further reduce the dielectric constant.

[0035] Moving on to the S / D regions (114, 116) of the transistor (110), in some embodiments, the S / D regions are preferably formed to form respective S / D contacts and ohmic contacts, for example, at least about 10 20 or at least about 10 21 cm -3 Although they may be highly doped with a dopant concentration, these regions may have a lower dopant concentration and, in some embodiments, may form Schottky contacts. Regardless of the exact doping level, the S / D region of the transistor may be a region having a higher dopant concentration than other regions, for example, a region having a higher dopant concentration than the dopant concentration in the channel portion (i.e., within the channel material extending between the first S / D region (114) and the second S / D region (116)), and thus may be referred to as a 'highly doped' (HD) region. The channel portion of the transistor (110) may have a significantly lower doping concentration than the doping concentration of the S / D regions (114, 116), for example, 10 18 cm -3 Less than or 10 17 cm -3 It may include semiconductor materials having a doping concentration of less than [amount].

[0036] The S / D regions (114, 116) of the transistor (110) can generally be formed using an implantation / diffusion process or an etching / deposition process. In the former process, a dopant such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the nanoribbon (104) to form source and drain regions. An annealing process that activates the dopant and further diffuses it into the nanoribbon (104) can follow the ion implantation process. In the latter process, a portion of the nanoribbon (104) can be etched first to form a recess at the location where the S / D regions (114, 116) will be formed. Then, an epitaxial deposition process can be performed to fill the recess with the material used to manufacture the S / D regions (114, 116). In some embodiments, the S / D regions (114, 116) may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In additional embodiments, the S / D regions (114, 116) may be formed using one or more alternative semiconductor materials such as germanium or a Group III-V material or alloy. And in additional embodiments, one or more metal and / or metal alloy layers may be used to form the S / D regions (114, 116). In some embodiments, the distance between the first S / D region (114) and the second S / D region (116) (i.e., the dimension measured along the longitudinal axis (120) of the nanoribbon (104)) may be between about 5 nanometers and 40 nanometers, which includes all values ​​and ranges within it (e.g., between about 22 nanometers and 35 nanometers, or between about 20 nanometers and 30 nanometers).

[0037] FIG. 2 is a flowchart of an S / D contact metallization method (200) for manufacturing an IC structure having a nanoribbon transistor and S / D contacts on both sides of one or more nanoribbons of the nanoribbon transistor, according to some embodiments. FIGS. 3a through 3e are side cross-sectional views illustrating exemplary IC structures after various processes of the method of FIG. 2 according to some embodiments. FIGS. 3a through 3e each illustrates an IC structure comprising a nanoribbon transistor having a stack of nanoribbons. For example, the nanoribbon transistor of the IC structure of FIGS. 3a through 3e may be implemented as the transistor (110) of FIG. 1, wherein FIGS. 3a through 3e illustrates a side cross-sectional view (i.e., a cross-section along the nanoribbon (104)) along a plane substantially perpendicular to the substrate (102) and including the longitudinal axis (120) shown in FIG. 1. Accordingly, FIGS. 3a through 3e each represent a side cross-sectional view along the xz plane of the coordinate system (105) of FIG. 1. Although FIGS. 3a through 3e illustrate a specific number (e.g., 4) of nanoribbons (334) in a stack of nanoribbons for the transistors shown in these figures, this is merely for ease of explanation, and an IC structure having a nanoribbon transistor having S / D contacts on both sides of the nanoribbons described herein may include more or fewer nanoribbons (334) in a stack of nanoribbons for a given transistor. Some elements shown in FIGS. 3a through 3e are referred to herein by reference numerals shown in different patterns in these figures, and a legend showing the correspondence between the reference numerals and the patterns is provided at the bottom of each figure page of FIGS. 3a through 3e. For example, FIGS. 3a through 3e represent nanoribbons (334), insulating materials (340), electrically conductive materials (346), etc. using various patterns.

[0038] Although the operations of the manufacturing method illustrated in FIG. 2 are each depicted individually and in a specific order, these operations may be performed in any appropriate order and repeated as many times as necessary. For example, the exemplary manufacturing method illustrated in FIG. 2 may include other operations not specifically depicted in the drawings, such as various cleaning or planarization operations as known in the art. For example, in some embodiments, the substrate on which the IC structure is provided, as well as layers of various other materials subsequently deposited on this substrate, are cleaned before, after, or during any process of the manufacturing method illustrated in FIG. 2 to remove, for example, oxides, surface-bonded organic and metal contaminants, as well as subsurface contaminants. In some embodiments, cleaning may be performed, for example, by using a chemical solution (e.g., peroxide) and / or ultraviolet (UV) radiation combined with ozone, and / or by removing oxides after oxidizing the surface (e.g., using thermal oxidation) (e.g., using hydrofluoric acid (HF)). As another example, the array / device described herein may be planarized before, after, or during any process of the manufacturing method illustrated in FIG. 2 described herein to remove, for example, top deposits or excess material. In some embodiments, planarization may be performed using a wet or dry planarization process, for example, the planarization may be chemical mechanical planarization (CMP), which can be understood as a process using surface polishing, abrasives, and slurries to remove top deposits and planarize the surface.

[0039] This method (200) begins with process 202, which includes providing a transistor on the front surface of a substrate and providing a front S / D contact in the first S / D area of ​​the transistor. The IC structure (302) shown in FIG. 3a represents an exemplary result of process 202. As shown in FIG. 3a, the IC structure (302) includes a transistor (110) built on the basis of a nanoribbon stack of multiple nanoribbons (334) rather than a single nanoribbon (104) as shown in FIG. 1, wherein each nanoribbon (334) can be implemented as a nanoribbon (104). Although the nanoribbon stack of the IC structure (302) is shown as containing four nanoribbons (334), other embodiments may include fewer nanoribbons (334) or more nanoribbons (334).

[0040] FIG. 3a further illustrates a sub-pin (336) of a semiconductor material (338) located beneath a stack of nanoribbons (334). In some embodiments, the semiconductor material (338) may comprise any semiconductor material described above for nanoribbons (104), but in some embodiments, at least a portion of the nanoribbons (334) and the sub-pin (336) may comprise semiconductor materials of different material compositions.

[0041] As illustrated in FIG. 3a, a gate stack (112) having a gate insulator (106) and a gate electrode material (108) may wrap around the channel portion of the nanoribbon (334). FIG. 3a further illustrates a first S / D region (114) and a second S / D region (116) that extend beyond the stack of the nanoribbon (334) and are electrically insulated / separated from the gate electrode material (108) and the semiconductor material (338) of the sub-pin (336) by an insulator material (340). In some embodiments, as part of manufacturing the transistor (110), so-called dimples (342) may be formed to separate the S / D regions (114, 116) from the gate electrode material (108). As illustrated in FIG. 3a, the dimple (342) may be filled with an insulating material (340), and thus the insulating material (340) may be referred to as a 'dimple spacer'. The insulating material (340) may include any insulating material described herein, for example, any ILD material described above.

[0042] In FIG. 3a, a gate contact (344) is shown on top of a stack of nanoribbons (334) (i.e., on the front surface of the nanoribbons (334)), as well as a first S / D contact (124) and a dummy second S / D contact (126') on both sides of the gate contact (344). The gate contact (344) may include an electrically conductive material (346) that electrically conductively contacts the gate electrode material (108). In various embodiments, the material composition of the electrically conductive material (346) and the gate electrode material (108) may be substantially the same or different. As further illustrated in FIG. 3a, the sidewalls of the first S / D contact (124) and the dummy second S / D contact (126') may be lined with a gate spacer (348). The gate spacer (348) can electrically insulate the electrically conductive material of the first S / D contact (124) and the dummy second S / D contact (126') from the gate electrode material (108) and the electrically conductive material (346) of the gate contact (344). The gate spacer (348) may include one or more spacer materials, diffusion prevention materials, adhesive materials, etc., as known in the art for forming contacts on various components of the IC structure. In some embodiments, the gate spacer (348) may include the low-k dielectric and / or any ILD material described above.

[0043] In some embodiments, as illustrated in FIG. 3a, the first S / D contact (124) may comprise a conductive filler material (364) and the dummy second S / D contact (126') may comprise an insulating material (366). In various embodiments, the conductive filler material (364) may comprise any suitable metal (e.g., tungsten, titanium, tantalum, copper, ruthenium, palladium, platinum, cobalt, nickel, etc.), a metal alloy, or a carbide or nitride of one or more metals, while the insulating material (366) may comprise any insulating material described herein, for example, any low-k dielectric material described herein. In other embodiments, the dummy second S / D contact (126') may comprise a conductive filler material such as the conductive filler material (364) instead of the insulating material (366) (not illustrated in FIG. 3a). In this embodiment, the conductive filling material within the dummy second S / D contact (126') can be electrically floating (i.e., not electrically connected to any signal path, power path, or ground path).

[0044] As also illustrated in FIG. 3a, in some embodiments, optionally, the first S / D contact (124) and the dummy second S / D contact (126') may include an interface liner (350) at the bottom and possibly also on the sidewall. The interface liner (350) may include any material capable of improving the electrical contact between the S / D regions (114, 116) and the electrically conductive filler material (364) of the first S / D contact (124) and the dummy second S / D contact (126'). In some embodiments, the interface liner (350) may include a metal such as titanium or be a metal, which, once deposited, is mixed with the material of the S / D region (114, 116), e.g., silicon, to form an interface compound (352) (e.g., titanium silicide or any other compound including the metal of the conductive filler material (364) and the semiconductor of the S / D region (114, 116), which may help reduce the contact resistance of the S / D contact (124). As illustrated in FIG. 3a, in some embodiments, the interface liner (350) may be recessed on the sidewalls of the first S / D contact (124) and the dummy second S / D contact (126'). In some embodiments, the thickness of the interface liner (350) may be between about 2 nanometers and about 20 nanometers, e.g., between about 2 and 15 nanometers, or between about 2 and 10 nanometers. Although not specifically illustrated in FIG. 3a, in some embodiments, optionally, the first S / D contact (124) and the dummy second S / D contact (126') may also be lined with one or more additional liners, which include, but are not limited to, a material containing silicon and nitrogen (e.g., silicon nitride), a material containing silicon and oxygen (e.g., silicon oxide), a material containing silicon and carbon (e.g., silicon carbide), and / or a composite material thereof.

[0045] Method (200) may subsequently proceed to process 204, which includes providing an insulating layer on the back of a stack of nanoribbons (334) of an IC structure (302) and forming a first opening in the insulating layer to expose the back of a second S / D region (116) of a transistor (110). The IC structure (304) illustrated in FIG. 3b represents an exemplary result of process 204. As illustrated in FIG. 3b, in some embodiments, process 204 may include substantially removing the substrate (102) by thinning the substrate (102), for example, starting from the back of the IC structure (100), and replacing it with a layer of insulating material (368). The insulating material (368) may include any insulating material described herein, for example, any low-k dielectric material described herein. FIG. 3b further illustrates an opening (326) formed in an insulating material (368) and extending from the rear surface of the IC structure (304) toward and into the second S / D region (116). Thus, the opening (326) exposes the rear surface of the second S / D region (116). Because the opening (326) extends into the second S / D region (116), the exposed portion of the second S / D region (116) may have a concave shape, or, in other words, the shape of the opening (326) may be convex in the portion where the opening (326) extends into the second S / D region (116).

[0046] Any suitable deposition technique, such as spin-coating, dip-coating, physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, electron beam deposition), chemical vapor deposition (CVD), or atomic layer deposition (ALD), may be used to deposit the insulating material (368) in process 204. Subsequently, any suitable etching technique may be used to form an opening (326) in the insulating material (368). In some embodiments, anisotropic etching may be used to form the opening (326). In some embodiments, the anisotropic etching of process 204 may include etching using an etching solution in the form of a chemically active ionized gas (i.e., plasma), for example, using chemicals of the bromine (Br) and chloride (Cl) series. In some embodiments, during the etching of process 204, the IC structure may be heated to an elevated temperature, for example, between room temperature and 200 degrees Celsius (including all values ​​and ranges therein), so that the etching byproducts can be removed from the surface. In some embodiments, the anisotropic etching of process 204 may include dry etching such as RF reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE. In various embodiments, any suitable patterning technique, such as photolithography or electron-beam (e-beam) patterning (but not limited thereto), may be used to define the location and dimensions of the opening (326) in process 204, in combination with the use of one or more masks if possible.

[0047] Next, the method (200) may include process 206, which includes providing a rear S / D contact in a second S / D region (116) within an opening formed in process 204. The IC structure (306) illustrated in FIG. 3c represents an exemplary result of process 206. As illustrated in FIG. 3c, the IC structure (306) includes a second S / D contact (126) formed in an opening (326) of the IC structure (304). Since the second S / D contact (126) is formed in an insulating material (368) on the rear side of the IC structure, it is a rear S / D contact. The composition of the material included in the second S / D contact (126) may vary depending on the specific design. At least, the second S / D contact (126) of the IC structure (306) comprises a conductive material that at least partially fills the volume of the opening (326) of the IC structure (304). Although this conductive material is illustrated as a conductive filling material (364) in FIG. 3c, in some embodiments, the material composition of the conductive filling material (364) in the second S / D contact (126) and the first S / D contact (124) may differ from each other. As further illustrated in FIG. 3c, in some embodiments, the second S / D contact (126) may comprise an interface liner (350) and an interface compound (352) similar to those in the first S / D contact (124). As described above, since the shape of the opening (326) may be convex in the portion where the opening (326) extends into the second S / D region (116), the shape of one or more corresponding portions of the conductive filling material (364), interface liner (350), and interface compound (352) of the second S / D contact (126) provided in the portion of the opening (326) closest to the second S / D region (116) may also be convex in the direction toward the second S / D region (116).The interface compound (352) in the second S / D contact (126) may include a metal of the conductive material of the second S / D contact (126) (e.g., a metal of the conductive filler material (364)) and a semiconductor of the second S / D region (116), e.g., titanium and silicon.

[0048] As also illustrated in FIG. 3c, in some embodiments, the second S / D contact (126) may further include an additional liner (376) on at least a portion of one or more sidewalls of the second S / D contact (126). In some embodiments, the additional liner (376) may include nitrogen, e.g., nitrogen and silicon in combination with the semiconductor material. In some embodiments, the additional liner (376) may include an etching stop material. In some embodiments, the additional liner (376) may be an insulating material. In some embodiments, the thickness of the additional liner (376) may be between about 2 nanometers and about 20 nanometers, e.g., between about 2 and 15 nanometers, or between about 2 and 10 nanometers.

[0049] Any suitable deposition technique, such as PVD, CVD, or ALD, may be used to deposit various parts of the second S / D contact (126) in process 206. In some embodiments, a conformal deposition technique, such as ALD, may be used to deposit the interface liner (350), the interface compound (352), and the additional liner (376) in process 206. In additional embodiments, any one or more of the interface liner (350), the interface compound (352), and the additional liner (376) may not be present on the second S / D contact (126) of the IC structure (306) and the subsequent IC structure manufactured using method (200).

[0050] The method (200) may subsequently proceed to process 208, which includes forming a second opening in the insulating layer provided in process 204 to expose the back surface of the first S / D region (114) of the transistor (110). The IC structure (308) illustrated in FIG. 3d illustrates an exemplary result of process 208, which shows an opening (324) formed in the insulating material (368) extending from the back surface of the IC structure (304) toward and into the first S / D region (114). Thus, the opening (324) exposes the back surface of the first S / D region (114). Because the opening (324) extends into the first S / D area (114), the exposed portion of the first S / D area (114) may have a concave shape, or, in other words, the shape of the opening (324) may be convex in the portion where the opening (324) extends into the first S / D area (114). The opening (324) may be formed using the process described for the opening (326).

[0051] Finally, the method (200) may include process 210, which includes providing an insulator structure in contact with a first S / D region (114) within an opening formed in process 208. The IC structure (310) illustrated in FIG. 3e represents an exemplary result of process 210. As illustrated in FIG. 3e, the IC structure (310) includes an insulator structure (354) formed in an opening (324) of the IC structure (308). Since the insulator structure (354) is formed in an insulating material (368) on the back of the IC structure, it is a back insulator structure. Since this includes an insulating material such as an insulating material (366) that fills the insulating structure (354) and contacts the first S / D region (114), the insulating structure (354) can be considered as a dummy rear S / D contact similar to the dummy S / D contact (126') but located on the rear side. The composition of the material included in the insulating structure (354) may vary depending on the specific design. At least, the insulating structure (354) of the IC structure (310) includes an insulating material that at least partially fills the volume of the opening (324) of the IC structure (308). Although this insulating material is illustrated as the insulating material (366) in FIG. 3e, in some embodiments, the material composition of the insulating material (366) in the insulating structure (354) and the dummy S / D contact (126') may differ from each other. As also illustrated in FIG. 3e, in some embodiments, the insulator structure (354) may include a liner (374) on at least a portion of one or more sidewalls of the insulator structure (354). In some embodiments, the liner (374) may include nitrogen, e.g., nitrogen and silicon, in combination with a semiconductor material. In some embodiments, the liner (374) may include an etching stop material. In some embodiments, the liner (374) may be an insulator material.In some embodiments, the thickness of the liner (374) may be between about 2 nanometers and about 20 nanometers, for example between about 2 and 15 nanometers, or between about 2 and 10 nanometers.

[0052] Any suitable deposition technique, such as PVD, CVD, or ALD, may be used to deposit various parts of the insulator structure (354) in process 210. In some embodiments, a conformal deposition technique, such as ALD, may be used to deposit the liner (374) in process 210. In additional embodiments, the liner (374) may not be present in the insulator structure (354) of the IC structure (310).

[0053] An IC structure having S / D contacts on both sides of a nanoribbon transistor and a nanoribbon, for example, any embodiment described with reference to FIGS. 1 to 3, or any combination of such embodiments, having S / D contacts (124, 126) on both sides of a nanoribbon transistor (110) and a nanoribbon (334), may be included in any suitable electronic device. FIGS. 4 to 9 show various examples of a device that may include one or more IC structures having S / D contacts on both sides of a nanoribbon transistor and a nanoribbon (for example, any embodiment of the IC structure (100) described herein or any embodiment of the IC structure (310)).

[0054] FIG. 4 illustrates a plan view of a wafer and a die that may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon, according to some embodiments. The wafer (2000) may be composed of a semiconductor material and may include one or more dies (2002) having an IC structure formed on the surface of the wafer (2000). Each die (2002) may be a repeating unit of a semiconductor product having any suitable IC structure (e.g., any IC structure described with reference to FIG. 1 through 3). After the manufacture of the semiconductor product is completed (e.g., after the manufacture of one or more IC structures described herein), the wafer (2000) may undergo a singulation process in which each die (2002) is separated from one another to provide individual 'chips' of the semiconductor product. In particular, a device comprising one or more IC structures as disclosed herein may take the form of a wafer (2000) (e.g., not modularized) or a die (2002) (e.g., modularized). The die (2002) may include one or more nanoribbon transistors and S / D contacts on both sides of the nanoribbon as described herein, and / or any other IC components as well as support circuits for routing electrical signals to the S / D contacts (124, 126) on both sides of the transistor (110) and the nanoribbon (334). In some embodiments, the wafer (2000) or the die (2002) may include a memory device (e.g., a memory device having one or more nanoribbon transistors (110) and S / D contacts (124, 126) on both sides of the nanoribbon (334)), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Many of these devices can be combined on a single die (2002).For example, a memory array formed by a plurality of memory devices may be formed on the same die (2002) as other logic configured to store information in a processing device (e.g., the processing device (2500) of FIG. 9) or a memory device, or to execute instructions stored in the memory array.

[0055] FIG. 5 is a side cross-sectional view of an IC device (2100) that may include one or more IC structures having S / D contacts on both sides of a nanoribbon transistor and a nanoribbon, as described herein, according to some embodiments. For example, any transistor (2140) of the IC device (2100) may be implemented as any nanoribbon transistor (110) having S / D contacts (124, 126) on both sides of a nanoribbon (334), as described herein. As another example, one or more IC devices (2100) may be included in one or more dies (2002) of FIG. 4. The IC device (2100) may be formed on a substrate (2102) (e.g., a wafer (2000) of FIG. 4) and may be included in a die (e.g., a die (2002) of FIG. 4). The substrate (2102) may take any form of the substrate (102) described above.

[0056] The IC device (2100) may include one or more device layers (2104) disposed on a substrate (2102). The device layer (2104) may include features of one or more transistors (2140) (e.g., MOSFETs) formed on the substrate (2102). The device layer (2104) may include, for example, one or more S / D regions (2120), a gate (2122) for controlling current flow within the transistor (2140) between the S / D regions (2120), and one or more S / D contacts (2124) for routing electrical signals between the S / D regions (2120). The transistor (2140) may include additional features, such as device isolation regions, gate contacts, etc., which are not illustrated for clarity. The transistor (2140) is not limited to the type and configuration illustrated in FIG. 5 and may include a wide range of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or GAA transistors, such as nanoribbon and nanowire transistors.

[0057] Each transistor (2140) may include a gate (2122) formed of at least two layers of a gate insulator and a gate electrode. The gate insulator of the transistor (2140) may be implemented as the gate insulator (106) described above, and the gate electrode of the transistor (2140) may be implemented as the gate electrode material (108) described above.

[0058] The S / D region (2120) may be formed adjacent to the gate (2122) of each transistor (2140) within the substrate (2102). The S / D region (2120) of the transistor (2140) may be implemented as the S / D region (114 and 116) described above.

[0059] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from a device (e.g., a transistor (2140)) of the device layer (2104) through one or more interconnect layers (illustrated in FIG. 5 as interconnect layers (2106, 2108, 2110)) disposed on the device layer (2104). For example, conductive features of the device layer (2104) (e.g., a gate (2122) and an S / D contact (2124)) may be electrically connected to an interconnect structure (2128) of the interconnect layers (2106, 2108, 2110). One or more interconnect layers (2106, 2108, 2110) may form a metallized stack (also referred to as an 'ILD stack') (2119) of the IC device (2100).

[0060] The interconnect structure (2128) may be arranged within the interconnect layers (2106, 2108, 2110) to route electrical signals according to a wide range of designs (in particular, this arrangement is not limited to the specific configuration of the interconnect structure (2128) shown in FIG. 5). Although FIG. 5 shows a specific number of interconnect layers (2106, 2108, 2110), embodiments of the present disclosure include IC devices having more or fewer interconnect layers than shown.

[0061] In some embodiments, the interconnect structure (2128) may include a conductive line (2128a) and / or a conductive via (2128b) filled with an electrically conductive material such as metal. The conductive line (2128a) may be arranged to route an electrical signal in a direction in a plane substantially parallel to the surface of the substrate (2102) on which the device layer (2104) is formed. For example, the conductive line (2128a) may route an electrical signal in the forward and backward directions of this page at the time of FIG. 5. The conductive via (2128b) may be arranged to route an electrical signal in a direction in a plane substantially perpendicular to the surface of the substrate (2102) on which the device layer (2104) is formed. In some embodiments, the conductive via (2128b) may electrically connect the conductive lines (2128a) of different interconnect layers (2106, 2108, 2110) together.

[0062] The interconnection layers (2106, 2108, 2110) may include an insulating material (2126) disposed between interconnection structures (2128) as illustrated in FIG. 5. In some embodiments, the insulating material (2126) disposed between interconnection structures (2128) in different interconnection layers (2106, 2108, 2110) may have different compositions, and in other embodiments, the composition between the insulating materials (2126) of different interconnection layers (2106, 2108, 2110) may be the same.

[0063] A first interconnect layer (2106) may be formed on top of the device layer (2104). In some embodiments, the first interconnect layer (2106) may include a conductive line (2128a) and / or a conductive via (2128b) as illustrated. The conductive line (2128a) of the first interconnect layer (2106) may be connected to a contact (e.g., an S / D contact (2124)) of the device layer (2104).

[0064] A second interconnect layer (2108) may be formed on top of the first interconnect layer (2106). In some embodiments, the second interconnect layer (2108) may include a conductive via (2128b) for connecting a conductive line (2128a) of the second interconnect layer (2108) to a conductive line (2128a) of the first interconnect layer (2106). Although the conductive line (2128a) and the conductive via (2128b) are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer (2108)) for clarity, in some embodiments, the conductive line (2128a) and the conductive via (2128b) may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0065] A third interconnect layer (2110) (and additional interconnect layers if required) may be formed continuously on the second interconnect layer (2108) according to a technique and configuration similar to that described in relation to the second interconnect layer (2108) or the first interconnect layer (2106). In some embodiments, the interconnect layer 'higher' (i.e. further away from the device layer (2104)) in the metallization stack (2119) within the IC device (2100) may be thicker.

[0066] The IC device (2100) may include a solder resist material (2134) (e.g., polyimide or a similar material) formed on an interconnection layer (2106, 2108, 2110) and one or more conductive contacts (2136). In FIG. 5, the conductive contacts (2136) are shown to take the form of bond pads. The conductive contacts (2136) may be electrically connected to an interconnection structure (2128) and configured to route electrical signals of transistor(s) (2140) to another external device. For example, a solder bond may be formed on one or more conductive contacts (2136) to mechanically and / or electrically connect a chip containing the IC device (2100) to another component (e.g., a circuit board). The IC device (2100) may include additional structures or alternative structures for routing electrical signals from interconnection layers (2106, 2108, 2110), and, for example, may include other similar features (e.g., posts) for routing electrical signals to external components, such as conductive contacts (2136).

[0067] FIG. 6 is a side cross-sectional view of an exemplary IC package (2200) that may include one or more IC structures having S / D contacts on both sides of a nanoribbon transistor and a nanoribbon, as described herein, according to some embodiments. For example, any die (2202) of the IC package (2200) may be implemented as the die (2002) of FIG. 4. As another example, any die (2202) may include any embodiment of the IC device (2100) of FIG. 5. In an embodiment where the IC package (2200) includes a plurality of dies (2202), the IC package (2200) may be referred to as a multi-chip package (MCP). The dies (2202) may include circuits for performing any desired function. For example, one or more of the dies (2202) may be logic dies (e.g., silicon-based dies), and one or more of the dies (2202) may be memory dies (e.g., high-bandwidth memory). In some embodiments, the IC package (2200) may be a system-in-package (SiP). In some embodiments, the IC package (2200) may include a photonics IC (PIC) packaged together with the IC package. In some embodiments, the IC package (2200) may include a fully integrated electronic photonics IC (EPIC).

[0068] The IC package (2200) may include a package substrate (2204) that can be formed from a dielectric material (e.g., ceramic, build-up film, epoxy film having filler particles inside, glass, organic material, inorganic material, combination of organic and inorganic materials, embedded portion formed from different materials, etc.) and may have conductive paths extending through the dielectric material between planes (2206) and planes (2208), or between different locations on planes (2206) and / or between different locations on planes (2208). These conductive paths may take the form of any interconnect structure (2128) discussed above with reference to FIG. 5.

[0069] The package substrate (2204) may include a conductive contact (2210) connected to a conductive path (not shown) through the package substrate (2204), thereby allowing a circuit within the die (2202) and / or interposer (2212) to be electrically connected to various conductive contacts (2214) (or other devices (not shown) included in the package substrate (2204).

[0070] The IC package (2200) may include an interposer (2212) connected to a package substrate (2204) through a conductive contact (2216) of the interposer (2212), a first level interconnect (2218), and a conductive contact (2210) of the package substrate (2204). The first level interconnect (2218) shown in FIG. 6 is a solder bump, but any suitable first level interconnect (2218) may be used. In some embodiments, the IC package (2200) may not include an interposer (2212), and instead, the die (2202) may be directly connected to the conductive contact (2210) on the surface (2206) by the first level interconnect (2218). Generally, one or more dies (2202) can be connected to a package substrate (2204) through any suitable structure (e.g., silicon bridge, organic bridge, one or more waveguides, one or more interposers, wire bond, etc.).

[0071] The IC package (2200) may include one or more dies (2202) connected to the interposer (2212) through a conductive contact (2220) of the die (2202), a first level interconnect (2222), and a conductive contact (2224) of the interposer (2212). The conductive contact (2224) may be connected to a conductive path (not shown) through the interposer (2212), thereby allowing a circuit within the die (2202) to be electrically connected to various conductive contacts (2216) (or to other devices (not shown) included in the interposer (2212). The first level interconnect (2222) shown in FIG. 6 is a solder bump, but any suitable first level interconnect (2222) may be used. For example, the first level interconnect (2222) may include a hybrid bonding interconnect. As used herein, 'conductive contact' may refer to a part of a conductive material (e.g., metal) that functions as an interface between different components, and the conductive contact may be recessed from the surface of the component, flush with the surface, or extending away from the surface, and may have any suitable shape (e.g., conductive pad or socket).

[0072] In some embodiments, the underfill material (2226) may be placed between the package substrate (2204) and the interposer (2212) around the first level interconnect (2218), and the mold compound (2228) may be placed around the die (2202) and the interposer (2212) and in contact with the package substrate (2204). In some embodiments, the underfill material (2226) may be the same as the mold compound (2228). Exemplary materials that may be used for the underfill material (2226) and the mold compound (2228) may be suitable materials such as epoxy molding compound (EMC). The second level interconnect (2230) may be connected to the conductive contact (2214). The second level interconnect (2230) illustrated in FIG. 6 is a solder ball (e.g., in the case of a ball grid array arrangement), but any suitable second level interconnect (2230) may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). The second level interconnect (2230) may be used to connect the IC package (2200) to a circuit board (e.g., a motherboard), an interposer, or other components such as other IC packages, as is known in the art and as discussed below with reference to FIG. 7.

[0073] The IC package (2200) illustrated in FIG. 6 is a flip-chip package, but other package architectures may be used. For example, the IC package (2200) may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. As another example, the IC package (2200) may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies (2202) are illustrated in the IC package (2200) of FIG. 6, the IC package (2200) may include any predetermined number of dies (2202). The IC package (2200) may include additional passive components, such as surface-mount resistors, capacitors, and inductors, placed on the first side (2206) or the second side (2208) of the package substrate (2204), or on any side of the interposer (2212). More generally, the IC package (2200) may include any other active or passive components known in the art.

[0074] FIG. 7 is a side cross-sectional view of an IC device assembly (2300) that may include one or more IC packages or other electronic components (e.g., dies) comprising one or more IC structures having nanoribbon transistors and S / D contacts on both sides of the nanoribbon as described herein, according to some embodiments. The IC device assembly (2300) includes a plurality of components disposed on a circuit board (2302) (e.g., a motherboard). The IC device assembly (2300) includes components disposed on a first surface (2340) of the circuit board (2302) and an opposing second surface (2342) of the circuit board (2302), and generally, the components may be disposed on one or both surfaces (2340 and 2342). Any IC package discussed below in relation to the IC device assembly (2300) may take the form of any embodiment of the IC package (2200) discussed above with reference to FIG. 6.

[0075] In some embodiments, the circuit board (2302) may be a PCB comprising a plurality of metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed into a desired circuit pattern to route electrical signals (optionally combined with other metal layers) between components connected to the circuit board (2302). In other embodiments, the circuit board (2302) may be a non-PCB substrate.

[0076] The IC device assembly (2300) illustrated in FIG. 7 includes a package-on-interposer structure (2336) connected to a first side (2340) of a circuit board (2302) by a connection component (2316). The connection component (2316) can electrically and mechanically connect the package-on-interposer structure (2336) to the circuit board (2302) and may include a solder ball, a male and female part of a socket (as illustrated in FIG. 7), an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical connection structure.

[0077] The package-on-interposer structure (2336) may include an IC package (2320) connected to the package interposer (2304) by a connecting component (2318). The connecting component (2318) may take any suitable application form, such as the form discussed above with reference to the connecting component (2316). Although a single IC package (2320) is shown in FIG. 7, multiple IC packages may be connected to the package interposer (2304), and additional interposers may actually be connected to the package interposer (2304). The package interposer (2304) may provide an intervening substrate used to bridge the circuit board (2302) and the IC package (2320). The IC package (2320) may be, for example, a die (die (2002) in FIG. 4), an IC device (e.g., IC device (2100) in FIG. 5), or any other suitable component, or may include such. Generally, the package interposer (2304) may spread the connections to a wider pitch or reroute one connection to another. For example, the package interposer (2304) may connect the IC package (2320) (e.g., a die) to a set of BGA conductive contacts of a connection component (2316) to connect the IC package (2320) to the circuit board (2302). In the embodiment illustrated in FIG. 7, the IC package (2320) and the circuit board (2302) are attached to both sides of the package interposer (2304), but in other embodiments, the IC package (2320) and the circuit board (2302) may be attached to the same side of the package interposer (2304). In some embodiments, three or more components may be interconnected through a package interposer (2304). In some embodiments, the IC package (2320) may include one or more IC structures having a nanoribbon transistor and S / D contacts on both sides of the nanoribbon as described herein.

[0078] In some embodiments, the package interposer (2304) may be formed as a PCB comprising a plurality of metal layers separated from one another by a layer of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer (2304) may be formed from a polymer material such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin having inorganic fillers, ceramic material, or polyimide. In some embodiments, the package interposer (2304) may be formed from an alternative rigid or flexible material that may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer (2304) may include metal lines (2310) and vias (2308), including (but not limited to) through-substrate vias (TSVs) (2306). The package interposer (2304) may further include embedded devices (2314) including both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the package interposer (2304). The package-on-interposer structure (2336) may take the form of any package-on-interposer structure known in the art.

[0079] The IC device assembly (2300) may include an IC package (2324) connected to a first side (2340) of the circuit board (2302) by a connection component (2322). The connection component (2322) may take any form of the embodiment discussed above with reference to the connection component (2316), and the IC package (2324) may take any form of the embodiment discussed above with reference to the IC package (2320).

[0080] The IC device assembly (2300) illustrated in FIG. 7 includes a package-on-package structure (2334) connected to a second side (2342) of a circuit board (2302) by a connecting component (2328). The package-on-package structure (2334) includes an IC package (2326) and an IC package (2332) connected together by a connecting component (2330), such that the IC package (2326) is positioned between the circuit board (2302) and the IC package (2332). The connecting component (2328, 2330) may take any form of an embodiment of the connecting component (2316) discussed above, and the IC package (2326, 2332) may take any form of an embodiment of the IC package (2320) discussed above. The package-on-package structure (2334) can be configured according to any board (2302) and package-on-package structure known in the art.

[0081] FIG. 8 is a block diagram of an exemplary computing device (2400) that may include one or more components, including a nanoribbon transistor and one or more IC structures having S / D contacts on both sides of the nanoribbon, as described herein according to some embodiments. For example, any suitable component of the computing device (2400) may include a die (e.g., die (2002) of FIG. 4) having one or more IC structures having S / D contacts (124, 126) on both sides of the nanoribbon transistor (110) and the nanoribbon (334), as described herein. Any one or more of the components of the computing device (2400) may include the IC device (2100) of FIG. 5, the IC package (2200) of FIG. 6, or the IC device assembly (2300) of FIG. 7.

[0082] Although FIG. 8 illustrates a computing device (2400) that includes a plurality of components, any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the computing device (2400) may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0083] Furthermore, in various embodiments, the computing device (2400) may not include one or more of the components illustrated in FIG. 8, and the computing device (2400) may include an interface circuit for connecting to one or more components. For example, the computing device (2400) may not include a display device (2412) and may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device (2412) can be connected. In another set of examples, the computing device (2400) may not include an audio input device (2416) or an audio output device (2414) and may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device (2416) or an audio output device (2414) can be connected.

[0084] The computing device (2400) may include a processing device (2402) (e.g., one or more processing devices). As used herein, the terms ‘processing device’ or ‘processor’ may refer to any device or part of a device that processes electronic data from registers and / or memory and converts said electronic data into other electronic data that can be stored in registers and / or memory. The processing device (2402) may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. In some embodiments, the processing device (2402) may include one or more IC structures having nanoribbon transistors and S / D contacts on both sides of the nanoribbon as described herein.

[0085] The computing device (2400) may include memory (2404), which itself may include one or more memory devices such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory (2404) may include memory that shares a die with the processing device (2402). This memory may be used as a cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic random access memory (MRAM). In some embodiments, the memory (2404) may include one or more IC structures having nanoribbon transistors and S / D contacts on both sides of the nanoribbon as described herein.

[0086] In some embodiments, the computing device (2400) may include a communication chip (2406) (e.g., one or more communication chips). For example, the communication chip (2406) may be configured to manage wireless communication for the transmission of data between the computing device (2400) and the device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of communicating data using electromagnetic radiation modulated through a non-solid medium. This term does not imply that the associated device does not include wires, although it may not in some embodiments.

[0087] The communication chip (2406) can implement any number of wireless standards or protocols, including (but not limited to) the Institute of Electrical and Electronics Engineers (IEEE) standards, such as Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 revision), and any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultramobile Broadband (UMB) project (also referred to as '3GPP2'), etc.) and the Long-Term Evolution (LTE) project. An IEEE 1402.16 compliant Broadband Wireless Access (BWA) network is commonly referred to as a WiMAX network, which is an acronym for the World Standard Interoperability for Microwave Access and is a certification mark for products that have passed conformity and interoperability tests for the IEEE 1402.16 standard. The communication chip (2406) can operate according to GSM (Global System for Mobile Communication), GPRS (General Packet Radio Service), UMTS (Universal Mobile Telecommunications System), HSPA (High Speed ​​Packet Access), E-HSPA (Evolved HSPA), or LTE networks. The communication chip (2406) can operate according to EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network), or E-UTRAN (Evolved UTRAN).The communication chip (2406) may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocol specified in 3G, 4G, 5G, and above. In other embodiments, the communication chip (2406) may operate according to other wireless protocols. The computing device (2400) may include an antenna (2408) to facilitate wireless communication and / or receive other wireless communication (such as AM or FM radio transmission).

[0088] In some embodiments, the communication chip (2406) may manage wired communication such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As mentioned above, the communication chip (2406) may include a number of communication chips. For example, the first communication chip (2406) may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and the second communication chip (2406) may be dedicated to long-range wireless communication such as GPS (global positioning system), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip (2406) may be dedicated to wireless communication, and the second communication chip (2406) may be dedicated to wired communication.

[0089] The computing device (2400) may include a battery / power circuit (2410). The battery / power circuit (2410) may include one or more energy storage devices (e.g., a battery or a capacitor) and / or a circuit for connecting a component of the computing device (2400) to an energy source (e.g., AC line power) separate from the computing device (2400).

[0090] The computing device (2400) may include a display device (2412) (or, as discussed above, a corresponding interface circuit). The display device (2412) may include any visual indicator, such as, for example, a head-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0091] The computing device (2400) may include an audio output device (2414) (or, as discussed above, a corresponding interface circuit). The audio output device (2414) may include any device that generates an audible indicator, such as, for example, a speaker, a headset, or earbuds.

[0092] The computing device (2400) may include an audio input device (2416) (or, as discussed above, a corresponding interface circuit). The audio input device (2416) may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device having a Musical Device Digital Interface (MIDI) output).

[0093] The computing device (2400) may include other output devices (2418) (or corresponding interface circuits as discussed above). Examples of other output devices (2418) may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0094] The computing device (2400) may include other input devices (2418) (or corresponding interface circuits as discussed above). Examples of other input devices (2420) may include an accelerometer, a gyroscope, a compass, an image capture device, a cursor control device such as a keyboard, a mouse, a stylus, or a touchpad, a barcode reader, a QR (Quick Response) code reader, any sensor, or an RFID (radio frequency identification) reader.

[0095] The computing device (2400) may include a GPS device (2422) (or, as discussed above, a corresponding interface circuit). The GPS device (2422) can communicate with a satellite-based system and receive the location of the computing device (2400) as is known in the art.

[0096] The computing device (2400) may include a security interface device (2424). The security interface device (2424) may include any device that provides security features for the computing device (2400) or for any individual component within it (e.g., for the processing device (2402) or for the memory (2404). Examples of security features may include authorization, access to digital certificates, access to items in a keychain, etc. Examples of the security interface device (2424) may include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.

[0097] In some embodiments, the computing device (2400) may include a temperature detection device (2426) and a temperature control device (2428).

[0098] The temperature detection device (2426) may include any device capable of determining the temperature of any individual component of or within the computing device (2400) (e.g., the temperature of the processing device (2402) or the memory (2404)). In various embodiments, the temperature detection device (2426) may be configured to determine the temperature of an object (e.g., the computing device (2400), a component of the computing device (2400), a device connected to the computing device, etc.), an environment (e.g., a data center containing, controlled by, or associated with the computing device (2400)), etc. The temperature detection device (2426) may include one or more temperature sensors. Each temperature sensor of the temperature detection device (2426) may have different locations inside and around the computing device (2400). The temperature sensor generates data (e.g., digital data) representing the detected temperature and may provide this data to other devices, such as a temperature control device (2428), a processing device (2402), a memory (2404), etc. In some embodiments, the temperature sensor of the temperature detection device (2426) may be turned on or off by, for example, the processing device (2402) or an external system. The temperature sensor detects the temperature when it is turned on and does not detect the temperature when it is turned off. In other embodiments, the temperature sensor of the temperature detection device (2426) may detect the temperature continuously and automatically, or detect the temperature at a predefined time or at a time triggered by an event associated with the computing device (2400) or any component therein.

[0099] The temperature control device (2428) may include any device configured to change (e.g., decrease) the temperature based on one or more target temperatures and / or based on temperature measurements performed by the temperature detection device (2426). The target temperature may be a preferred temperature. The target temperature may vary depending on the setting in which the computing device (2400) operates. In some embodiments, the target temperature may be 200 Kelvin or lower. In some embodiments, the target temperature may be 20 Kelvin or lower or 5 Kelvin or lower. The target temperature for different objects and different environments of or associated with the computing device (2400) may be different. In some embodiments, the cooling provided by the temperature control device (2428) may be a multi-stage process having a temperature ranging from room temperature to 4K or lower.

[0100] In some embodiments, the temperature control device (2428) may include one or more cooling devices. Each cooling device may have different locations inside and around the computing device (2400). The cooling device of the temperature control device (2428) may be associated with one or more temperature sensors of the temperature detection device (2426) and may be configured to operate based on the temperature detected by the temperature sensors. For example, the cooling device may be configured to determine whether the detected ambient temperature is above the target temperature or whether the detected ambient temperature is higher than the target temperature by a certain value, or to determine whether any other temperature-related condition related to the temperature of the computing device (2400) is satisfied. In response to determining that one or more temperature-related conditions related to the temperature of the computing device (2400) are satisfied (e.g., in response to determining that the detected ambient temperature has exceeded the target temperature), the cooling device may trigger its cooling mechanism to begin reducing the ambient temperature. Otherwise, the cooling device does not trigger any cooling. The cooling device of the temperature control device (2428) may operate with various cooling mechanisms such as evaporation cooling, radiation cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. The cooling device of the temperature control device (2428) may include a cooling agent, such as water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature control device (2428) may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.In some embodiments, the temperature control device (2428) or any part thereof (e.g., one or more of the individual cooling devices) may be connected in close proximity (e.g., less than 1 meter) to the computing device (2400) and may be provided in a separate enclosure where a dedicated heat exchanger (e.g., a compressor, a heating, ventilation and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may be present.

[0101] By maintaining a target temperature, the energy consumption of the computing device (2400) (or its components) can be reduced, while computing efficiency can be improved. For example, if the computing device (2400) (or its components) operates at a lower temperature, energy dissipation (e.g., heat dissipation) can be reduced. Additionally, the energy consumed by the semiconductor components (e.g., the energy required to switch the transistors of any component of the computing device (2400)) can also be reduced. Various semiconductor materials may have lower resistivity and / or higher mobility at lower temperatures. Thus, by lowering the temperature, the current per unit supply voltage can be increased. Conversely, for the same required current, the supply voltage can be lowered by lowering the temperature. Since energy is correlated with the supply voltage, the energy consumption of the semiconductor components can also be lowered. In some embodiments, energy savings achieved by reducing heat dissipation and by reducing energy consumed by semiconductor components of a computing device or its components may outweigh (sometimes significantly outweigh) the costs associated with the energy required for cooling.

[0102] The computing device (2400) may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop computing device, a server or other network computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device (2400) may be any other electronic device that processes data.

[0103] FIG. 9 is a block diagram of an exemplary processing device (2500) that may include one or more IC structures having S / D contacts on both sides of a nanoribbon transistor disclosed herein. For example, any suitable component of the processing device (2500) may include a die (e.g., die (2002) of FIG. 4) having one or more IC structures having S / D contacts on both sides of a nanoribbon transistor as described herein. Any one or more of the components of the processing device (2500) may include the IC device (2100) of FIG. 5, the IC package (2200) of FIG. 6, or the IC device assembly (2300) of FIG. 7. Any one or more of the components of the processing device (2500) may include or be included in the computing device (2400) of FIG. 8, for example, the processing device (2500) may be the processing device (2402) of the computing device (2400).

[0104] Although FIG. 9 illustrates that the processing device (2500) includes a plurality of components, any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the processing device (2500) may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SoC die or connected to a single base, e.g., a single carrier substrate.

[0105] Furthermore, in various embodiments, the processing device (2500) may not include one or more of the components shown in FIG. 9, and the processing device (2500) may include an interface circuit for connecting to one or more components. For example, the processing device (2500) may not include a memory (2504) and may include a display device interface circuit (e.g., a connector and driver circuit) to which the memory (2504) can be connected.

[0106] The processing device (2500) may include a logic circuit (2502) (e.g., one or more circuits configured to implement logic / computing functions). Examples of such circuits include ICs that implement one or more input / output (I / O) functions, arithmetic operations, data pipelining, etc.

[0107] In some embodiments, the logic circuit (2502) may include one or more circuits responsible for reading / writing data stored in the memory (2504). To this end, the logic circuit (2502) may include one or more I / O ICs configured to control access to the data stored in the memory (2504).

[0108] In some embodiments, the logic circuit (2502) may include one or more high-performance computing dies configured to perform various operations on data stored in memory (2504) (e.g., arithmetic and logical operations, pipelining of data from one or more memory dies of memory (2504) and also possible data from external devices / chips). In some embodiments, the logic circuit (2502) may be configured to control only input / output access to data and not perform any operations on the data. In some embodiments, the logic circuit (2502) may implement an IC, etc., configured to implement I / O control of data stored in memory (2504) and to combine data from memory (2504) for transfer to a device / chip inside or outside the processing device (2500) (e.g., transfer via a central bus). In some embodiments, the logic circuit (2502) may be configured not to perform any operations on the data other than assembling for I / O and transfer to memory (2504).

[0109] The processing device (2500) may include a memory (2504) configured to include one or more ICs configured to implement memory circuits (e.g., a memory device, a memory array, an IC implementing one or more of control logic configured to control the memory device and the array). In some embodiments, the memory (2504) may be implemented as described above with reference to the memory (2404) (Fig. 8). In some embodiments, the memory (2504) may be a designated device configured to provide storage functions to a component of the processing device (2500) (e.g., local), whereas the memory (2404) may be configured to provide system-level storage functions to the entire computing device (2400) (e.g., global). In some embodiments, the memory (2504) may include a memory that shares a die with the logic circuit (2502).

[0110] The processing device (2500) may include a communication device (2506) that can be implemented substantially as the communication chip (2406) described above with reference to FIG. 8. In some embodiments, the communication device (2506) may be a designated device configured to provide communication functions to a component of the processing device (2500) (e.g., local), whereas the communication device (2506) may be configured to provide system-level communication functions to the entire computing device (2400) (e.g., global).

[0111] The processing device (2500) may include an interconnection portion (2508), which may include any element or device comprising an electrically conductive material for providing electrical connection to one or more components of the processing device (2500) or to one or more associated components and / or between these various components. Examples of the interconnection portion (2508) include a conductive line / wire (also referred to as a 'line' or 'metal line' or 'trench') and a conductive via (also referred to as a 'via' or 'metal via'). In some embodiments, the interconnection portion (2508) may be implemented as the interconnection structure (2128) of FIG. 5 described above.

[0112] The processing device (2500) may substantially be implemented as described above with reference to the temperature detection device (2426) of FIG. 8, but may include a temperature detection device (2510) configured to determine the temperature of the processing device (2500) or its components, for example, on a more local scale. In some embodiments, the temperature detection device (2510) may be a designated device configured to provide a temperature detection function to a component of the processing device (2500) (e.g., local), whereas the temperature detection device (2510) may be configured to provide a system-level temperature detection function to the entire computing device (2400) (e.g., global).

[0113] The processing device (2500) may substantially be implemented as described above with reference to the temperature control device (2428) of FIG. 8, but may include a temperature control device (2512) configured to control the temperature of the processing device (2500) or its components, for example, on a more local scale. In some embodiments, the temperature control device (2512) may be a designated device configured to provide temperature control functions to a component of the processing device (2500) (e.g., local), whereas the temperature control device (2428) may be configured to provide system-level temperature control functions to the entire computing device (2400) (e.g., global).

[0114] The processing device (2500) may include a battery / power circuit (2514) which can be implemented as described above with reference substantially to the battery / power circuit (2410) of FIG. 8. In some embodiments, the battery / power circuit (2514) may be a designated device configured to provide battery / power functionality to a component of the processing device (2500) (e.g., local), whereas the battery / power circuit (2410) may be configured to provide system-level battery / power functionality to the entire computing device (2400) (e.g., global).

[0115] The processing device (2500) may include a hardware security device (2516) that can be implemented as described above with reference to the security interface device (2424) of FIG. 8. In some embodiments, the hardware security device (2516) may be a physical computing device configured to protect and manage digital keys, and to perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, the hardware security device (2516) may include one or more security cryptoprocessor chips.

[0116] The following paragraph provides various examples of the embodiments disclosed herein.

[0117] Example 1 provides an integrated circuit (IC) structure comprising a nanoribbon containing a semiconductor material, and a transistor comprising a channel portion, a first region and a second region—the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon and has a front and a back surface, the first region and the second region are located at both ends of the channel portion, one of the first region and the second region is the source region of the transistor, and the other of the first region and the second region is the drain region of the transistor—and a first conductive contact conductively in contact with the first region (e.g., directly electrically connected to the first region)—the first conductive contact is located on the front surface of the channel portion—and a second conductive contact conductively in contact with the second region (e.g., directly electrically connected to the second region)—the second conductive contact is located on the back surface of the channel portion—and an insulator structure in contact with the first region (e.g., directly physically in contact)—the insulator structure is located on the back surface of the channel portion, and in a side cross-sectional view of the IC structure, with respect to the first region in the insulator structure The shape at the interface includes convexity (e.g., in the direction toward the first region).

[0118] Example 2 provides an IC structure according to Example 1, wherein the nanoribbon is one of a plurality of nanoribbons stacked perpendicularly to each other, and the insulator structure extends to a first region up to the level of the nanoribbon closest to the insulator structure among at least the plurality of nanoribbons.

[0119] Example 3 provides an IC structure according to Example 1 or 2, wherein the insulator structure includes a low-k dielectric.

[0120] Example 4 provides an IC structure according to Example 1 or 2, wherein the insulator structure comprises a liner on at least a portion of the sidewalls of the insulator structure and a filling material that fills at least partially the remaining volume of the insulator structure, the filling material is an insulator material, and the material composition of the filling material is different from the material composition of the liner.

[0121] Example 5 provides an IC structure according to Example 4, wherein the liner comprises silicon and nitrogen.

[0122] Example 6 provides an IC structure according to Example 4 or 5, wherein the filling material includes a low-k dielectric material.

[0123] Example 7 provides an IC structure according to any one of Examples 1 to 6, and in a side cross-sectional view of the IC structure, the shape at the interface with the second region at the second conductive contact is convex (e.g., in the direction toward the second region).

[0124] Example 8 provides an IC structure according to any one of Examples 1 to 7, wherein the second conductive contact comprises a conductive material and an interface liner between the conductive material and the second region.

[0125] Example 9 provides an IC structure according to Example 8, and in a side cross-sectional view of the IC structure, the shape at the interface with the second region in the interface liner is convex (e.g., in the direction toward the second region).

[0126] Example 10 provides an IC structure according to Example 8 or 9, wherein the interface liner comprises titanium.

[0127] Example 11 provides an IC structure according to any one of Examples 8 to 10, and further includes an interface compound at the interface between the interface liner and the second region.

[0128] Example 12 provides an IC structure according to Example 11, and in a side cross-sectional view of the IC structure, the shape at the interface with the second region in the interface compound is convex (e.g., in the direction toward the second region).

[0129] Example 13 provides an IC structure according to Example 11 or 12, wherein the interface compound comprises a metal of a conductive material and a semiconductor of a second region.

[0130] Example 14 provides an IC structure according to any one of Examples 11 to 13, wherein the interface compound comprises titanium and silicon.

[0131] Example 15 provides an IC structure according to any one of Examples 8 to 14, wherein the second conductive contact further includes an additional liner on at least a portion of the sidewall of the first conductive contact.

[0132] Example 16 provides an IC structure according to Example 15, wherein the additional liner comprises silicon and nitrogen.

[0133] Example 17 provides an integrated circuit (IC) structure comprising: a stack of nanoribbons containing semiconductor material—the stack has a front and a back—and a transistor comprising a channel portion, a first region and a second region—the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon stack, the first region and the second region are located at both ends of the channel portion, one of the first region and the second region is the source region of the transistor, and the other of the first region and the second region is the drain region of the transistor—and a first conductive contact conductively in contact with the first region (e.g., directly electrically connected to the first region)—the first conductive contact is on the front of the nanoribbon stack—and a second conductive contact conductively in contact with the second region (e.g., directly electrically connected to the second region)—the second conductive contact is on the back of the nanoribbon stack—and an insulator structure conductively in contact with the first region (e.g., directly physically in contact)—the insulator structure is on the back of the nanoribbon stack The insulating structure is included, and extends to a first region up to the level of the nanoribbon closest to the insulating structure among the stacks of nanoribbons.

[0134] Example 18 provides an IC structure according to Example 17, wherein in a side cross-sectional view of the IC structure, the shape at the interface with the first region in the insulator structure is convex (e.g., in the direction toward the first region).

[0135] Example 19 provides an IC structure according to any one of Examples 1 through 18, wherein the IC structure includes or is part of a central processing unit.

[0136] Example 20 provides an IC structure according to any one of Examples 1 through 19, wherein the IC structure includes or is part of a memory structure.

[0137] Example 21 provides an IC structure according to any one of Examples 1 through 20, wherein the IC structure includes or is part of a logic circuit.

[0138] Example 22 provides an IC structure according to any one of Examples 1 to 21, wherein the IC structure includes or is part of an input / output circuit.

[0139] Example 23 provides an IC structure according to any one of Examples 1 to 22, wherein the IC structure includes or is part of a field-programmable gate array transceiver.

[0140] Example 24 provides an IC structure according to any one of Examples 1 through 23, wherein the IC structure includes or is part of field-programmable gate array logic.

[0141] Example 25 provides an IC structure according to any one of Examples 1 through 24, wherein the IC structure includes or is part of a power transfer circuit.

[0142] Example 26 provides an integrated circuit (IC) package, which comprises an IC die containing an IC structure and additional IC components connected to the IC die, wherein the IC die comprises a stack of nanoribbons containing semiconductor material—the stack has a front and a back—and a transistor comprising a channel portion, a source region and a drain region—the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon stack, and the channel portion is located between the source region and the drain region—and a first conductive contact conductively in contact with the drain region (e.g., directly electrically connected to the drain region)—the first conductive contact is located on the front of the nanoribbon stack—and a second conductive contact conductively in contact with the source region (e.g., directly electrically connected to the source region)—the second conductive contact is located on the back of the nanoribbon stack—and an insulator structure in contact with the drain region (e.g., by direct physical contact)—the insulator structure is located on the back of the nanoribbon stack, and in a side cross-sectional view of the IC structure, the drain region and in the insulator structure The shape at the interface includes convexity (e.g., in the direction toward the drain region).

[0143] Example 27 provides an IC structure according to Example 25, wherein the insulator structure comprises a liner on at least a portion of the sidewalls of the insulator structure and a filling material that fills at least partially the remaining volume of the insulator structure, the filling material is an insulator material, and the material composition of the filling material is different from the material composition of the liner.

[0144] Example 28 provides an IC package according to Example 26 or 27, which further includes an insulating material that at least partially surrounds the IC die and additional IC components.

[0145] Example 29 provides an IC structure according to any one of Examples 26 to 28, wherein additional IC components include a package substrate.

[0146] Example 30 provides an IC structure according to any one of Examples 26 to 28, wherein additional IC components include an interposer.

[0147] Example 31 provides an IC structure according to any one of Examples 26 to 28, wherein the additional IC component includes an additional IC die.

[0148] Example 32 provides a computing device comprising a carrier substrate and an IC structure connected to the carrier substrate, wherein the IC structure is an IC structure according to any one of Examples 1 to 25, or the IC structure is included in an IC package according to any one of Examples 26 to 31.

[0149] Example 33 provides a computing device according to Example 32, wherein the computing device is a wearable or handheld computing device.

[0150] Example 34 provides a computing device according to Example 32 or 33, wherein the computing device further includes one or more communication chips.

[0151] Example 35 provides a computing device according to any one of Examples 32 to 34, wherein the computing device further includes an antenna.

[0152] Example 36 provides a computing device according to any one of Examples 32 to 35, wherein the carrier substrate is a motherboard.

[0153] Example 37 provides a method for manufacturing an IC structure, the method comprising the steps of: providing a nanoribbon comprising a semiconductor material; providing a transistor comprising a channel portion, a first region and a second region, wherein the channel portion of the transistor comprises a portion of the semiconductor material of the nanoribbon and has a front and a back surface, and the first region and the second region are at both ends of the channel portion, one of the first region and the second region is the source region of the transistor, and the other of the first region and the second region is the drain region of the transistor; and a first conductive contact that is conductively in contact with the first region (e.g., directly electrically connected to the first region) - the first conductive contact is on the front surface of the channel portion; and a second conductive contact that is conductively in contact with the second region (e.g., directly electrically connected to the second region) - the second conductive contact is on the back surface of the channel portion; and an insulator structure that is in contact with the first region (e.g., directly physically in contact) - the insulator structure is on the back surface of the channel portion, and the IC structure In the side cross-sectional view, the shape at the interface with the first region in the insulating structure includes convexity (e.g., in the direction toward the first region).

[0154] Example 38 provides a method according to Example 37, and the method further includes a process of providing an IC structure according to any one of Examples 2 to 25, an IC package according to any one of Examples 26 to 31, or a computing device according to any one of Examples 32 to 36.

[0155] Descriptions of illustrated embodiments of the present disclosure, including those described in the summary, are not exclusive or limit the present disclosure to the exact form disclosed. While specific embodiments and examples of the present disclosure are described herein for illustrative purposes, those skilled in the art will understand that various equivalent modifications are possible within the scope of the present disclosure. Such modifications to the present disclosure may be made in light of the detailed description.

Claims

Claim 1 As an integrated circuit (IC) structure, a transistor comprising a nanoribbon containing a semiconductor material, a channel portion, a first region, and a second region The channel portion of the above transistor includes the portion of the semiconductor material of the nanoribbon and has a front side and a back side, The first region and the second region are located at both ends of the channel portion, and One of the first region and the second region is the source region of the transistor, and An IC structure comprising: one of the first region and the other of the second region is a drain region of the transistor; a first conductive contact conductively contacting the first region; the first conductive contact being on the front surface of the channel portion; a second conductive contact conductively contacting the second region; the second conductive contact being on the rear surface of the channel portion; and an insulator structure contacting the first region; the insulator structure being on the rear surface of the channel portion, and in a side cross-sectional view of the IC structure, the shape at the interface with the first region of the insulator structure is convex. Claim 2 In claim 1, the nanoribbon is one of a plurality of nanoribbons stacked perpendicularly to one another, and the insulator structure extends to the first region up to the level of the nanoribbon closest to the insulator structure among the plurality of nanoribbons, an IC structure. Claim 3 In claim 1, the insulator structure comprises an IC structure including a low-k dielectric. Claim 4 In claim 1, the insulator structure comprises a liner on at least a portion of the sidewall of the insulator structure and a filling material that at least partially fills the remaining volume of the insulator structure, wherein the filling material is an insulator material and the material composition of the filling material is different from the material composition of the liner, an IC structure. Claim 5 In paragraph 4, the liner is an IC structure comprising silicon and nitrogen. Claim 6 In paragraph 4, the above-mentioned filling material comprises an IC structure including a low-k dielectric material. Claim 7 An IC structure according to any one of claims 1 to 6, wherein in the side cross-sectional view of the IC structure, the shape at the interface with the second region at the second conductive contact is convex. Claim 8 An IC structure according to any one of claims 1 to 6, wherein the second conductive contact comprises a conductive material and an interface liner between the conductive material and the second region. Claim 9 In claim 8, in the side cross-sectional view of the IC structure, the shape at the interface with the second region in the interface liner is convex, IC structure. Claim 10 In claim 8, the above interface liner is an IC structure comprising titanium. Claim 11 In claim 8, an IC structure further comprising an interface compound at the interface between the interface liner and the second region. Claim 12 In claim 11, in the side cross-sectional view of the IC structure, the shape at the interface with the second region in the interface compound is convex, IC structure. Claim 13 In claim 11, the above interface compound comprises an IC structure including a metal of the conductive material and a semiconductor of the second region. Claim 14 In claim 11, the above interface compound is an IC structure comprising titanium and silicon. Claim 15 In claim 8, the IC structure, wherein the second conductive contact further comprises an additional liner on at least a portion of the sidewall of the first conductive contact. Claim 16 In paragraph 15, the additional liner is an IC structure comprising silicon and nitrogen. Claim 17 As an integrated circuit (IC) structure, a stack of nanoribbons comprising a semiconductor material - said stack has a front side and a back side - and a transistor comprising a channel portion, a first region and a second region - The channel portion of the above transistor includes the portion of the semiconductor material of the stack of the above nanoribbon, and The first region and the second region are located at both ends of the channel portion, and One of the first region and the second region is the source region of the transistor, and An IC structure comprising: one of the first region and the other of the second region is a drain region of the transistor; a first conductive contact conductively in contact with the first region; the first conductive contact is on the front surface of the stack of the nanoribbons; a second conductive contact conductively in contact with the second region; the second conductive contact is on the rear surface of the stack of the nanoribbons; and an insulator structure in contact with the first region; the insulator structure is on the rear surface of the stack of the nanoribbons, and the insulator structure extends into the first region at least to the level of the nanoribbon closest to the insulator structure among the stack of the nanoribbons. Claim 18 In claim 17, in the side cross-sectional view of the IC structure, the shape at the interface with the first region in the insulator structure is convex, IC structure. Claim 19 An integrated circuit (IC) package comprising an IC die including an IC structure and additional IC components connected to the IC die, wherein the IC die comprises: a stack of nanoribbons including a semiconductor material - said stack has a front surface and a back surface - and a transistor including a channel portion, a source region and a drain region - said channel portion of the transistor includes a portion of said semiconductor material of said nanoribbon stack, said channel portion is between said source region and said drain region - and a first conductive contact conductively contacting the drain region - said first conductive contact is on said front surface of said nanoribbon stack - and a second conductive contact conductively contacting the source region - said second conductive contact is on said back surface of said nanoribbon stack - and an insulator structure contacting the drain region - said insulator structure is on said back surface of said nanoribbon stack, and in a side cross-sectional view of said IC structure, the shape at the interface with said drain region in said insulator structure is convex. Claim 20 In claim 19, the insulator structure comprises a liner on at least a portion of the sidewall of the insulator structure and a filling material that fills at least partially the remaining volume of the insulator structure, wherein the filling material is an insulator material and the material composition of the filling material is different from the material composition of the liner, IC package.

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